A dual-rail power supply control method and power management chip

Abstract

This application provides a dual-rail power supply control method and power management chip, including: receiving a first signal sent by a system chip (SOC); determining the receiving order corresponding to the first signal based on the first signal and historical received information; determining whether the receiving order corresponding to the first signal meets a preset priority order; if the receiving order corresponding to the first signal meets the preset priority order, controlling the CPU or the SRAM to hibernate or wake up based on the first signal and a preset correspondence; if the receiving order corresponding to the first signal does not meet the preset priority order, continuing to monitor for a first preset duration to obtain a second signal; first controlling the CPU or the SRAM to hibernate or wake up based on the second signal, and then controlling the CPU or the SRAM to hibernate or wake up based on the first signal. This application can improve the battery life of electronic devices.

Description

Technical Field

[0001] This application relates to the field of power gating technology, and in particular to a dual-rail power supply control method and power management chip. Background Technology

[0002] Currently, with the development of technology, the penetration rate of electronic devices has become increasingly widespread. Especially mobile phones, laptops, and other electronic devices have become essential items in people's work and daily lives. At the same time, as the performance of electronic devices improves, the power consumption of functional modules such as processors is also increasing, putting greater pressure on the battery life of these devices. Meanwhile, a System-on-Chip (SoC), as a dedicated integrated circuit, contains a complete system and all embedded software. By identifying and processing signals through the SoC, the operating status of the system and functional modules can be determined, facilitating further energy-saving adjustments. Therefore, how to reduce the power consumption of functional modules such as processors and improve the battery life of electronic devices through SoCs has become an urgent problem to be solved. Summary of the Invention

[0003] The purpose of this application is to provide a dual-rail power supply control method and a power management chip to solve the problem of how to reduce the power consumption of functional modules such as processors. The specific technical solution is as follows:

[0004] A first aspect of this application provides a dual-rail power supply control method applied to a power management chip (PMIC), the method comprising:

[0005] Receive a first signal sent by the system chip SOC, wherein the first signal includes one of the following: system hibernation SYS_SLP power-on signal, SYS_SLP power-off signal, core power domain control CORE_PD power-off signal, and CORE_PD power-on signal;

[0006] Based on the first signal and historical reception information, the reception order corresponding to the first signal is determined, wherein the historical reception information includes: the historical reception information of each signal among the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on signal;

[0007] Determine whether the receiving order corresponding to the first signal satisfies a preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-on signal takes precedence over the CORE_PD power-on signal;

[0008] If the receiving order corresponding to the first signal satisfies the preset priority order, the CPU or the static random access memory (SRAM) is controlled to hibernate or wake up according to the first signal and the preset correspondence. The preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to hibernate in response to the SYS_SLP power-off signal, and controlling the CPU to hibernate in response to the CORE_PD power-off signal.

[0009] If the receiving order corresponding to the first signal does not meet the preset priority order, continue monitoring for a first preset duration to obtain the second signal; first, control the CPU or control the SRAM according to the second signal to perform sleep or wake-up, and then control the CPU or control the SRAM according to the first signal to perform sleep or wake-up.

[0010] In one possible implementation, determining the reception order corresponding to the first signal based on the first signal and historical reception information includes:

[0011] If the first signal is the SYS_SLP power-off signal, based on the historical reception information, it is determined whether the CORE_PD power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-off signal priority; if no, the reception order corresponding to the first signal is SYS_SLP power-off signal priority.

[0012] If the first signal is a CORE_PD power-on signal, based on the historical reception information, it is determined whether a SYS_SLP power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-on signal priority; if no, the reception order corresponding to the first signal is CORE_PD power-on signal priority.

[0013] If the first signal is a CORE_PD power-off signal, based on the historical reception information, it is determined whether a SYS_SLP power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-off signal priority; if no, the reception order corresponding to the first signal is CORE_PD power-off signal priority.

[0014] If the first signal is the SYS_SLP power-on signal, based on the historical reception information, it is determined whether the CORE_PD power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-on signal priority; if no, the reception order corresponding to the first signal is SYS_SLP power-on signal priority.

[0015] In one possible implementation, determining whether the receiving order corresponding to the first signal satisfies a preset priority order includes:

[0016] If the first signal is a CORE_PD power-down signal, and the receiving order of the first signal is CORE_PD power-down signal first, then the condition is satisfied; if the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is SYS_SLP power-on signal first, then the condition is satisfied; if the first signal is a SYS_SLP power-on signal, and the receiving order of the first signal is SYS_SLP power-on signal first, then the condition is satisfied; if the first signal is a SYS_SLP power-down signal, and the receiving order of the first signal is CORE_PD power-down signal first, then the condition is satisfied.

[0017] If the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is CORE_PD power-on signal first, then the condition is not met; if the first signal is a SYS_SLP power-off signal, and the receiving order of the first signal is SYS_SLP power-off signal first, then the condition is not met.

[0018] In one possible implementation, the second signal is a SYS_SLP power-on signal or a CORE_PD power-off signal, and the first signal is a SYS_SLP power-off signal or a CORE_PD power-on signal; the step of first controlling the CPU or SRAM to hibernate or wake up according to the second signal, and then controlling the CPU or SRAM to hibernate or wake up according to the first signal, includes:

[0019] When the first signal is the CORE_PD power-on signal, and the receiving order of the first signal is CORE_PD power-on signal first, and the second signal is the SYS_SLP power-on signal, the SRAM is first woken up according to the SYS_SLP power-on signal, and then the CPU is woken up according to the CORE_PD power-on signal.

[0020] When the first signal is the SYS_SLP power-down signal, and the receiving order of the first signal is SYS_SLP power-down signal first, and the second signal is the CORE_PD power-down signal, the CPU is first controlled to enter sleep mode according to the CORE_PD power-down signal, and then the SRAM is controlled to enter sleep mode according to the SYS_SLP power-down signal.

[0021] In one possible implementation, if the receiving order corresponding to the first signal satisfies the preset priority order, the CPU or SRAM is controlled to enter a sleep or wake-up state based on the first signal and the preset correspondence, including:

[0022] If the first signal is a CORE_PD power-off signal, and the receiving order of the first signal is CORE_PD power-off signal first, then the CPU is controlled to go into sleep mode according to the CORE_PD power-off signal.

[0023] If the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is SYS_SLP power-on signal first, then the CPU is controlled to wake up according to the CORE_PD power-off signal.

[0024] If the first signal is the SYS_SLP power-on signal, and the receiving order corresponding to the first signal is SYS_SLP power-on signal first, then the SRAM is controlled to be woken up according to the SYS_SLP power-on signal.

[0025] If the first signal is the SYS_SLP power-down signal, and the receiving order corresponding to the first signal is CORE_PD power-down signal first, then the SRAM is controlled to be woken up according to the SYS_SLP power-on signal.

[0026] A second aspect of this application provides a power management chip, the chip comprising:

[0027] The first signal receiving module is used to receive a first signal sent by the system chip SOC, wherein the first signal includes one of the following: system hibernation SYS_SLP power-on signal, SYS_SLP power-off signal, core power domain control CORE_PD power-off signal, and CORE_PD power-on signal;

[0028] The sequence determination module is used to determine the reception order corresponding to the first signal based on the first signal and historical reception information, wherein the historical reception information includes: the historical reception information of each signal among the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on signal;

[0029] The priority determination module is used to determine whether the receiving order corresponding to the first signal meets the preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-on signal takes precedence over the CORE_PD power-on signal;

[0030] A response control module is configured to, when the reception order corresponding to the first signal satisfies the preset priority order, control the CPU or the SRAM to hibernate or wake up according to the first signal and a preset correspondence, wherein the preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to hibernate in response to the SYS_SLP power-off signal, and controlling the CPU to hibernate in response to the CORE_PD power-off signal; when the reception order corresponding to the first signal does not satisfy the preset priority order, continue monitoring for a first preset duration to obtain a second signal; first control the CPU or the SRAM to hibernate or wake up according to the second signal, and then control the CPU or the SRAM to hibernate or wake up according to the first signal.

[0031] In one possible implementation, the sequence determination module is specifically configured to, when the first signal is a SYS_SLP power-off signal, determine, based on the historical reception information, whether a CORE_PD power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-off signal priority; otherwise, the reception order corresponding to the first signal is SYS_SLP power-off signal priority; when the first signal is a CORE_PD power-on signal, determine, based on the historical reception information, whether a SYS_SLP power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-on signal priority; otherwise, the reception order corresponding to the first signal is CORE_PD power-on signal priority. The ORE_PD power-on signal takes priority; if the first signal is the CORE_PD power-off signal, based on the historical reception information, it is determined whether the SYS_SLP power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-off signal priority, otherwise, the reception order corresponding to the first signal is CORE_PD power-off signal priority; if the first signal is the SYS_SLP power-on signal, based on the historical reception information, it is determined whether the CORE_PD power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-on signal priority, otherwise, the reception order corresponding to the first signal is SYS_SLP power-on signal priority.

[0032] In one possible implementation, the priority determination module is specifically configured to: if the receiving order of the first signal is CORE_PD power-down signal (where CORE_PD power-down takes precedence), then the condition is satisfied; if the first signal is CORE_PD power-on signal (where SYS_SLP power-on takes precedence), then the condition is satisfied; if the first signal is SYS_SLP power-on signal (where SYS_SLP power-on takes precedence), then the condition is satisfied; if the first signal is SYS_SLP power-down signal (where CORE_PD power-down takes precedence), then the condition is satisfied; if the first signal is CORE_PD power-on signal (where CORE_PD power-on takes precedence), then the condition is not satisfied; if the first signal is SYS_SLP power-down signal (where SYS_SLP power-down takes precedence), then the condition is not satisfied.

[0033] In one possible implementation, the response control module is specifically configured to, when the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is CORE_PD power-on signal priority, and the second signal is a SYS_SLP power-on signal, first control the SRAM to wake up according to the SYS_SLP power-on signal, and then control the CPU to wake up according to the CORE_PD power-on signal; when the first signal is a SYS_SLP power-off signal, and the receiving order of the first signal is SYS_SLP power-off signal priority, and the second signal is a CORE_PD power-off signal, first control the CPU to hibernate according to the CORE_PD power-off signal, and then control the SRAM to hibernate according to the SYS_SLP power-off signal.

[0034] In one possible implementation, the response control module is specifically configured to: when the first signal is a CORE_PD power-off signal, if the receiving order of the first signal is CORE_PD power-off signal first, control the CPU to enter sleep mode according to the CORE_PD power-off signal; when the first signal is a CORE_PD power-on signal, if the receiving order of the first signal is SYS_SLP power-on signal first, control the CPU to wake up according to the CORE_PD power-off signal; when the first signal is a SYS_SLP power-on signal, if the receiving order of the first signal is SYS_SLP power-on signal first, control the SRAM to wake up according to the SYS_SLP power-on signal; and when the first signal is a SYS_SLP power-off signal, if the receiving order of the first signal is CORE_PD power-off signal first, control the SRAM to wake up according to the SYS_SLP power-on signal.

[0035] In another aspect of the embodiments of this application, an electronic device is also provided, including: a PMIC, a SOC, a CPU, and an SRAM: the PMIC is electrically connected to the SOC, the CPU, and the SRAM respectively;

[0036] The PMIC is used to execute any of the dual-rail power supply control methods described above.

[0037] In another aspect of the embodiments of this application, a computer-readable storage medium is provided, which stores a computer program that, when executed by a processor, implements any of the dual-rail power supply control methods described above.

[0038] In another aspect of the embodiments of this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the dual-rail power supply control methods described above.

[0039] Beneficial effects of the embodiments in this application:

[0040] This application provides a dual-rail power supply control method and power management chip. The method includes: receiving a first signal sent by a system-on-chip (SOC), wherein the first signal includes one of a system sleep (SYS_SLP) power-on signal, a SYS_SLP power-off signal, a core power domain control (CORE_PD) power-off signal, and a CORE_PD power-on signal; determining the receiving order corresponding to the first signal based on the first signal and historical receiving information, wherein the historical receiving information includes historical receiving information of each of the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on signal; and determining whether the receiving order corresponding to the first signal satisfies a preset priority order, wherein the preset priority order includes: the CORE_PD power-off signal taking precedence over the SYS_SLP power-off signal, and the SYS_SLP power-off signal taking precedence over the SYS_SLP power-off signal. The S_SLP power-on signal takes precedence over the CORE_PD power-on signal. When the receiving order corresponding to the first signal satisfies the preset priority order, the CPU or SRAM is controlled to hibernate or wake up according to the first signal and a preset correspondence. The preset correspondence includes: controlling SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling SRAM to hibernate in response to the SYS_SLP power-off signal, and controlling the CPU to hibernate in response to the CORE_PD power-off signal. If the receiving order corresponding to the first signal does not satisfy the preset priority order, the system continues to monitor for a first preset duration to obtain a second signal. The CPU or SRAM is first controlled to hibernate or wake up according to the second signal, and then the CPU or SRAM is controlled to hibernate or wake up according to the first signal. The method of this application embodiment can determine the receiving order corresponding to the first signal based on the first signal and historical receiving information after receiving the first signal, and determine whether the receiving order corresponding to the first signal satisfies the preset priority order. If the receiving order corresponding to the first signal satisfies the preset priority order, the CPU or SRAM can be controlled to wake up or hibernate according to the first signal and the preset correspondence. In this way, by controlling the wake-up and hibernation of the CPU or SRAM, the power consumption of the CPU or SRAM can be reduced and the battery life of the electronic device can be improved.

[0041] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0043] Figure 1 This is a schematic flowchart of a dual-rail power supply control method according to an embodiment of this application;

[0044] Figure 2 This is another schematic flowchart of the dual-rail power supply control method according to an embodiment of this application;

[0045] Figure 3 A schematic diagram of the structure of a power management chip provided in an embodiment of this application;

[0046] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0048] The first aspect of this application provides a dual-rail power supply control method applied to a PMIC (Power Management Chip). See [link to relevant documentation]. Figure 1 , Figure 1 This is a flowchart illustrating a dual-rail power supply control method according to an embodiment of this application. The method includes:

[0049] Step S11: Receive a first signal sent by the system chip SOC, wherein the first signal includes one of the following: system hibernation SYS_SLP power-on signal, SYS_SLP power-off signal, core power domain control CORE_PD power-off signal, and CORE_PD power-on signal;

[0050] Step S12: Determine the receiving order corresponding to the first signal based on the first signal and the historical receiving information, wherein the historical receiving information includes: the historical receiving information of each signal in the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on signal;

[0051] Step S13: Determine whether the receiving order corresponding to the first signal satisfies the preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-on signal takes precedence over the CORE_PD power-on signal.

[0052] Step S14: If the receiving order corresponding to the first signal satisfies the preset priority order, control the CPU or the SRAM to hibernate or wake up according to the first signal and the preset correspondence. The preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to hibernate in response to the SYS_SLP power-off signal, and controlling the CPU to hibernate in response to the CORE_PD power-off signal. If the receiving order corresponding to the first signal does not satisfy the preset priority order, continue monitoring for a first preset duration to obtain a second signal. First, control the CPU or the SRAM to hibernate or wake up according to the second signal, and then control the CPU or the SRAM to hibernate or wake up according to the first signal.

[0053] Corresponding to step S11 above, the method of this embodiment is applied to a PMIC and can be executed by the PMIC. The PMIC can be electrically connected to the SOC, CPU, and SRAM. Specifically, the PMIC can obtain the SYS_SLP power-down signal or the CORE_PD power-on signal sent by the SOC through its electrical connection with the SOC. SYS_SLP is a sleep state control signal in power management, sent by the SOC; CORE_PD is the CPU core voltage enable signal, also sent by the SOC. SYS_SLP and CORE_PD can be used to characterize the working or stopping signals of the CPU or SRAM, thereby enabling or waking up the CPU and SRAM based on these signals. This ensures normal device operation while reducing power consumption, achieving energy saving and increased battery life. Specifically, the SYS_SLP power-on signal can be determined by detecting the falling edge of the SYS_SLP signal, the CORE_PD power-on signal can be determined by detecting the falling edge of the CORE_PD signal, the SYS_SLP power-down signal can be determined by detecting the rising edge of the SYS_SLP signal, and the CORE_PD power-down signal can be determined by detecting the rising edge of the CORE_PD signal. The first signal sent by the system chip SOC indicates that when one of the following signals is received: YS_SLP power-on signal, SYS_SLP power-off signal, CORE_PD power-off signal, or CORE_PD power-on signal, the received signal is identified as the first signal.

[0054] Corresponding to step S12 above, the historical reception information includes: historical reception information for each of the following signals: the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on signal. Specifically, the historical reception information may include whether one or more of the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on signal were received beforehand, and may include information such as the specific reception time. Based on the first signal and the historical reception information, the reception order corresponding to the first signal is determined, and it can be determined whether the received first signal was received earlier or later. For example, when the first information is a CORE_PD power-on signal, if the historical reception information indicates that a SYS_SLP power-on signal has been received, then the CORE_PD power-on signal is the signal received later, and the determined reception order corresponding to the first signal is SYS_SLP power-on signal priority; when the first information is a CORE_PD power-on signal, if the historical reception information indicates that a SYS_SLP power-on signal has not been received, then the CORE_PD power-on signal is the signal received earlier, and the reception order corresponding to the first signal is CORE_PD power-on signal priority; similarly, when the first information is a SYS_SLP power-off signal, if the historical reception information indicates that a CORE_PD power-off signal has been received, then the SYS_SLP power-off signal is the signal received later, and the reception order corresponding to the first signal is CORE_PD power-off signal priority; when the first information is a SYS_SLP power-off signal, if the historical reception information indicates that a CORE_PD power-off signal has not been received, then the SYS_SLP power-off signal is the signal received earlier, and the reception order corresponding to the first signal is SYS_SLP power-off signal priority. In practical use, this historical reception information can record only the reception information within a single time period, or it can record the reception information within a longer time period and then select a specific time period for identification. Specifically, this time period can be 1 second or other preset durations.

[0055] Corresponding to step S13 above, the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-on signal takes precedence over the CORE_PD power-on signal. Specifically, as explained in the previous paragraph, determining the receiving order corresponding to the first signal based on the first signal and historical reception information may include: SYS_SLP power-on signal priority, CORE_PD power-on signal priority, CORE_PD power-down signal priority, and SYS_SLP power-down signal priority. Then, to determine whether the receiving order corresponding to the first signal satisfies the preset priority order, the obtained receiving order corresponding to the first signal can be compared with the preset priority order. If they are the same, it is determined that the order satisfies the priority order; otherwise, it is determined that the order does not satisfy the priority order. That is, if the receiving order corresponding to the first signal is SYS_SLP power-on signal priority or CORE_PD power-down signal priority, it is determined that the order satisfies the priority order.

[0056] Corresponding to step S14 above, the preset correspondence includes: controlling SRAM wake-up in response to the SYS_SLP power-on signal, controlling CPU wake-up in response to the CORE_PD power-on signal, controlling SRAM sleep in response to the SYS_SLP power-off signal, and controlling CPU sleep in response to the CORE_PD power-off signal; if the receiving order corresponding to the first signal does not satisfy the preset priority order, continue monitoring for a first preset duration to obtain a second signal; first control the CPU or SRAM to sleep or wake up according to the second signal, and then control the CPU or SRAM to sleep or wake up according to the first signal. If the receiving order corresponding to the first signal satisfies the preset priority order, the CPU (processor) can be controlled to wake up or the SRAM (static random access memory) can be controlled to sleep according to the first signal and the preset correspondence. For example, when the first signal is the SYS_SLP power-on signal and the receiving order corresponding to the first signal is SYS_SLP power-on signal priority, the SRAM is controlled to wake up. When the first signal is the CORE_PD power-off signal and the receiving order corresponding to the first signal is CORE_PD power-off signal priority, the CPU is controlled to sleep. If the receiving order corresponding to the first signal does not meet the preset priority order, the system continues to monitor for a first preset duration to obtain a second signal. First, the CPU or SRAM is controlled to hibernate or wake up based on the second signal. Then, the CPU or SRAM is controlled to hibernate or wake up based on the first signal. For example, when the first signal is a CORE_PD power-on signal, and the receiving order corresponding to the first signal prioritizes the CORE_PD power-on signal, the system continues to monitor for a first preset duration to receive the second signal, SYS_SLP power-on signal. First, the SRAM is controlled to wake up based on the SYS_SLP power-on signal, and then the CPU is controlled to wake up based on the CORE_PD power-on signal. Similarly, when the first signal is a SYS_SLP power-off signal, and the receiving order corresponding to the first signal prioritizes the SYS_SLP power-off signal, the system continues to monitor for a first preset duration to receive the second signal, CORE_PD power-off signal. First, the CPU is controlled to hibernate based on the CORE_PD power-off signal, and then SYS_SLP is controlled to hibernate based on the CORE_PD power-on signal. In practical use, controlling the CPU to hibernate before SYS_SLP hibernation and the CPU to wake up after SYS_SLP wake-up ensures normal data storage and prevents data errors. Specifically, this second preset duration can be a pre-set duration, such as 50ms, 60ms, 80ms, etc.

[0057] As can be seen, the method of this application embodiment can determine the receiving order corresponding to the first signal after receiving the first signal, based on the first signal and historical receiving information, and determine whether the receiving order corresponding to the first signal satisfies the preset priority order. If the receiving order corresponding to the first signal satisfies the preset priority order, the CPU or SRAM can be controlled to wake up or hibernate according to the first signal and the preset correspondence. In this way, by controlling the wake-up and hibernation of the CPU or SRAM, the power consumption of the CPU or SRAM can be reduced and the battery life of the electronic device can be improved.

[0058] In one possible implementation, determining the reception order corresponding to the first signal based on the first signal and historical reception information includes:

[0059] If the first signal is the SYS_SLP power-off signal, based on the historical reception information, it is determined whether the CORE_PD power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-off signal priority; if no, the reception order corresponding to the first signal is SYS_SLP power-off signal priority.

[0060] If the first signal is a CORE_PD power-on signal, based on the historical reception information, it is determined whether a SYS_SLP power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-on signal priority; if no, the reception order corresponding to the first signal is CORE_PD power-on signal priority.

[0061] If the first signal is a CORE_PD power-off signal, based on the historical reception information, it is determined whether a SYS_SLP power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-off signal priority; if no, the reception order corresponding to the first signal is CORE_PD power-off signal priority.

[0062] If the first signal is the SYS_SLP power-on signal, based on the historical reception information, it is determined whether the CORE_PD power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-on signal priority; if no, the reception order corresponding to the first signal is SYS_SLP power-on signal priority.

[0063] In this embodiment, the receiving order of the first signal is determined based on the first signal and historical received information. The historical received information can be used to determine whether the first information is the priority received information. In actual use, if the system is in sleep mode, it will receive the CORE_PD power-down signal and the SYS_SLP power-down signal; if the system is awake, it will receive the CORE_PD power-on signal and the SYS_SLP power-on signal. Therefore, in this embodiment, when determining the receiving order of the first signal, only the CORE_PD power-down signal and the SYS_SLP power-down signal can be compared, and only the CORE_PD power-on signal and the SYS_SLP power-on signal can be compared. Specifically, when the first signal is a SYS_SLP power-down signal, it is determined whether a CORE_PD power-down signal exists in the historical received information. If so, the CORE_PD power-down signal takes priority; otherwise, the SYS_SLP power-down signal takes priority. When the first signal is a SYS_SLP power-on signal, it is determined whether a CORE_PD power-on signal exists in the historical received information. If so, the CORE_PD power-on signal takes priority; otherwise, the SYS_SLP power-on signal takes priority. When the first signal is a CORE_PD power-down signal, it is determined whether a SYS_SLP power-down signal exists in the historical received information. If so, the SYS_SLP power-down signal takes priority; otherwise, the CORE_PD power-down signal takes priority. When the first signal is a CORE_PD power-on signal, it is determined whether a SYS_SLP power-on signal exists in the historical received information. If so, the SYS_SLP power-on signal takes priority; otherwise, the CORE_PD power-on signal takes priority.

[0064] In one possible implementation, determining whether the receiving order corresponding to the first signal satisfies a preset priority order includes:

[0065] If the first signal is a CORE_PD power-down signal, and the receiving order of the first signal is CORE_PD power-down signal first, then the condition is satisfied; if the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is SYS_SLP power-on signal first, then the condition is satisfied; if the first signal is a SYS_SLP power-on signal, and the receiving order of the first signal is SYS_SLP power-on signal first, then the condition is satisfied; if the first signal is a SYS_SLP power-down signal, and the receiving order of the first signal is CORE_PD power-down signal first, then the condition is satisfied.

[0066] If the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is CORE_PD power-on signal first, then the condition is not met; if the first signal is a SYS_SLP power-off signal, and the receiving order of the first signal is SYS_SLP power-off signal first, then the condition is not met.

[0067] Specifically, in the previous step, the determined reception order corresponding to the first signal may include: when the first signal is a SYS_SLP power-down signal, the CORE_PD power-down signal or the SYS_SLP power-down signal takes priority; when the first signal is a SYS_SLP power-on signal, the CORE_PD power-on signal or the SYS_SLP power-on signal takes priority; when the first signal is a CORE_PD power-down signal, the SYS_SLP power-down signal or the CORE_PD power-down signal takes priority; when the first signal is a CORE_PD power-on signal, the SYS_SLP power-on signal or the CORE_PD power-on signal takes priority. The preset priority order includes: the CORE_PD power-down signal takes priority over the SYS_SLP power-down signal, and the SYS_SLP power-on signal takes priority over the CORE_PD power-on signal. If the receiving order of the first signal is CORE_PD power-down signal first, then the condition is satisfied; if the receiving order of the first signal is SYS_SLP power-on signal first, then the condition is satisfied; if the receiving order of the first signal is SYS_SLP power-on signal first, then the condition is satisfied; if the receiving order of the first signal is CORE_PD power-down signal first, then the condition is satisfied. If the receiving order of the first signal is CORE_PD power-on signal first, then the condition is not satisfied; if the receiving order of the first signal is SYS_SLP power-down signal first, then the condition is not satisfied.

[0068] In one possible implementation, if the receiving order corresponding to the first signal satisfies the preset priority order, the CPU or SRAM is controlled to enter a sleep or wake-up state based on the first signal and the preset correspondence, including:

[0069] If the first signal is a CORE_PD power-off signal, and the receiving order of the first signal is CORE_PD power-off signal first, then the CPU is controlled to go into sleep mode according to the CORE_PD power-off signal.

[0070] If the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is SYS_SLP power-on signal first, then the CPU is controlled to wake up according to the CORE_PD power-off signal.

[0071] If the first signal is the SYS_SLP power-on signal, and the receiving order corresponding to the first signal is SYS_SLP power-on signal first, then the SRAM is controlled to be woken up according to the SYS_SLP power-on signal.

[0072] If the first signal is the SYS_SLP power-down signal, and the receiving order corresponding to the first signal is CORE_PD power-down signal first, then the SRAM is controlled to be woken up according to the SYS_SLP power-on signal.

[0073] In this embodiment, the CPU can be controlled to hibernate or wake up in response to the CORE_PD power-down signal and the CORE_PD power-on signal. This can be achieved by the PMIC raising VDDCPU (CPU core voltage) to power down and controlling the CPU to wake up by the PMIC lowering VDDCPU. Similarly, the SRAM can be controlled to hibernate or wake up in response to the SYS_SLP power-on signal and the SYS_SLP power-down signal. This can be achieved by the PMIC raising VDDSRAM (SRAM core voltage) to power down and controlling the SRAM to wake up by the PMIC lowering VDDSRAM. As described above, in the following four cases: when the first signal is a CORE_PD power-down signal, if the receiving order of the first signal is CORE_PD power-down signal priority; when the first signal is a SYS_SLP power-on signal, if the receiving order of the first signal is SYS_SLP power-on signal priority; when the first signal is a SYS_SLP power-down signal, if the receiving order of the first signal is CORE_PD power-down signal priority; when the first signal is a CORE_PD power-down signal, if the receiving order of the first signal is CORE_PD power-down signal priority; when the first signal is a CORE_PD power-on signal, if the receiving order of the first signal is SYS_SLP power-on signal priority; if the corresponding order satisfies the preset priority order, then the CPU or SRAM can be directly controlled to hibernate or wake up.

[0074] In one possible implementation, the second signal is a SYS_SLP power-on signal or a CORE_PD power-off signal, and the first signal is a SYS_SLP power-off signal or a CORE_PD power-on signal; the step of first controlling the CPU or SRAM to hibernate or wake up according to the second signal, and then controlling the CPU or SRAM to hibernate or wake up according to the first signal, includes:

[0075] When the first signal is the CORE_PD power-on signal, and the receiving order of the first signal is CORE_PD power-on signal first, and the second signal is the SYS_SLP power-on signal, the SRAM is first woken up according to the SYS_SLP power-on signal, and then the CPU is woken up according to the CORE_PD power-on signal.

[0076] When the first signal is the SYS_SLP power-down signal, and the receiving order of the first signal is SYS_SLP power-down signal first, and the second signal is the CORE_PD power-down signal, the CPU is first controlled to enter sleep mode according to the CORE_PD power-down signal, and then the SRAM is controlled to enter sleep mode according to the SYS_SLP power-down signal.

[0077] In this embodiment, in the following two cases: when the first signal is a CORE_PD power-on signal, the receiving order of the first signal is CORE_PD power-on signal priority; when the first signal is a SYS_SLP power-off signal, the receiving order of the first signal is SYS_SLP power-off signal priority, and the preset priority order is not satisfied. In cases where the preset priority order is not satisfied, the second signal can continue to be acquired. Since the system receives both CORE_PD power-on signal and SYS_SLP power-on signal, or both CORE_PD power-off signal and SYS_SLP power-off signal, during system wake-up or sleep, the receiving order is as follows: when the first signal is a CORE_PD power-on signal, the receiving order of the first signal is CORE_PD power-on signal priority, and the second signal is generally a SYS_SLP power-on signal; when the first signal is a SYS_SLP power-off signal, the receiving order of the first signal is SYS_SLP power-off signal priority, and the second signal is generally a CORE_PD power-off signal. Therefore, when the second signal is the SYS_SLP power-on signal, the SRAM is first woken up according to the SYS_SLP power-on signal, and then the CPU is woken up according to the CORE_PD power-on signal; when the second signal is the CORE_PD power-off signal, the CPU is first put into hibernation according to the CORE_PD power-off signal, and then the SRAM is put into hibernation according to the SYS_SLP power-off signal, thereby achieving normal system startup or hibernation while satisfying the startup sequence.

[0078] To illustrate the method of the embodiments of this application, the following description is based on a specific example. (See attached image.) Figure 2 ,include:

[0079] 1. Control mode selection: Asynchronous control. In actual use, users can select asynchronous mode, in which the CPU and SRAM are respectively put into sleep and woken up. Specifically, the PMIC can support VDDSRAM and VDDCPU being controlled by SYS_SLP and CORE_PD respectively. SYS_SLP can be configured to control the power-on and power-off of VDDSRAM, and CORE_PD can be configured to control the power-on and power-off of VDDCPU.

[0080] 2. Setting detection priorities: For the sleep state, the power-down signal monitoring priorities for SYS_SLP and CORE_PD are set. Then, the real-time status of the power-down signals of SYS_SLP and CORE_PD is monitored, and a sequential judgment is performed. This application's solution supports setting the monitoring priority of the PMIC response to the power-down signals of SYS_SLP and CORE_PD. The CORE_PD signal response priority is set higher than SYS_SLP. That is, when the system CORE_PD goes high, VDDCPU powers down first, then SYS_SLP goes high and VDDSRAM powers down, conforming to the timing requirement that VDDCPU powers down before VDDSRAM. The response interval between CORE_PD and SYS_SLP can also be recorded. For exiting the sleep state, the power-on signal monitoring priorities for SYS_SLP and CORE_PD are set. Then, the real-time status of the power-on signals of SYS_SLP and CORE_PD is monitored, and a sequential judgment is performed. This application's solution supports setting the monitoring priority of the PMIC response to the power-on signals of SYS_SLP and CORE_PD. The SYS_SLP signal response priority is set higher than CORE_PD. That is, when the system SYS_SLP is pulled low, VDDSRAM powers on first, and then CORE_PD pulls low before VDDCPU powers on, which meets the timing requirement that VDDSRAM powers on before VDDCPU. The response interval between SYS_SLP and CORE_PD can also be recorded.

[0081] 3. For the sleep state, after power-down detection, it is determined whether the sequence is normal. If normal, the VDDSRAM / VDDCPU power-down timing follows normally, and then the sleep state is entered. If abnormal, the VDDSRAM / VDDCPU power-down timing follows normally after the normal timing is restored. Specifically, the solution of this application can support recording an anomaly and the response interval between SYS_SLP and CORE_PD when the system SYS_SLP goes high before CORE_PD goes high. At the same time, an anomaly timing recovery mechanism is activated, that is, when the SYS_SLP signal response precedes CORE_PD, a delay can be performed (the waiting time can be configured by the software), and VDDSRAM power-down will occur after CORE_PD goes high and VDDCPU is powered down, thereby ensuring the timing requirement that VDDCPU powers down before VDDSRAM. The same applies when the priority of the SYS_SLP signal response is set higher than that of CORE_PD. Regarding exiting sleep mode, after power-on detection, the sequence is checked for normality. If normal, the VDDSRAM / VDDCPU power-on timing is executed normally, and the system exits sleep mode. If abnormal, the VDDSRAM / VDDCPU power-on timing is executed normally after timing recovery. Specifically, the solution in this application supports recording anomalies and the response interval between CORE_PD and SYS_SLP when the system CORE_PD is pulled low before SYS_SLP. Simultaneously, an anomaly timing recovery mechanism is activated. That is, when the CORE_PD signal response precedes SYS_SLP, a delay (configurable by software) can be implemented before VDDCPU power-on occurs after SYS_SLP pulls low and VDDSRAM is powered on, thus ensuring the timing requirement of VDDSRAM powering on before VDDCPU. The same principle applies when the CORE_PD signal response priority is set higher than SYS_SLP.

[0082] A second aspect of this application provides a power management chip, see [link to relevant documentation]. Figure 3 , Figure 3 A schematic diagram of a power management chip provided in an embodiment of this application is shown. The chip includes:

[0083] The first signal receiving module 301 is used to receive a first signal sent by the system chip SOC, wherein the first signal includes one of the following: system hibernation SYS_SLP power-on signal, SYS_SLP power-off signal, core power domain control CORE_PD power-off signal, and CORE_PD power-on signal.

[0084] The sequence determination module 302 is used to determine the reception order corresponding to the first signal based on the first signal and the historical reception information, wherein the historical reception information includes: the historical reception information of each signal among the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on signal;

[0085] The priority determination module 303 is used to determine whether the receiving order corresponding to the first signal meets the preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-on signal takes precedence over the CORE_PD power-on signal;

[0086] The response control module 304 is configured to, when the reception order corresponding to the first signal satisfies the preset priority order, control the CPU or the SRAM to hibernate or wake up according to the first signal and a preset correspondence, wherein the preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to hibernate in response to the SYS_SLP power-off signal, and controlling the CPU to hibernate in response to the CORE_PD power-off signal; when the reception order corresponding to the first signal does not satisfy the preset priority order, continue monitoring for a first preset duration to obtain a second signal; first control the CPU or the SRAM to hibernate or wake up according to the second signal, and then control the CPU or the SRAM to hibernate or wake up according to the first signal.

[0087] In one possible implementation, the sequence determination module is specifically configured to, when the first signal is a SYS_SLP power-off signal, determine, based on the historical reception information, whether a CORE_PD power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-off signal priority; otherwise, the reception order corresponding to the first signal is SYS_SLP power-off signal priority; when the first signal is a CORE_PD power-on signal, determine, based on the historical reception information, whether a SYS_SLP power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-on signal priority; otherwise, the reception order corresponding to the first signal is CORE_PD power-on signal priority. The ORE_PD power-on signal takes priority; if the first signal is the CORE_PD power-off signal, based on the historical reception information, it is determined whether the SYS_SLP power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-off signal priority, otherwise, the reception order corresponding to the first signal is CORE_PD power-off signal priority; if the first signal is the SYS_SLP power-on signal, based on the historical reception information, it is determined whether the CORE_PD power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-on signal priority, otherwise, the reception order corresponding to the first signal is SYS_SLP power-on signal priority.

[0088] In one possible implementation, the priority determination module is specifically configured to: if the receiving order of the first signal is CORE_PD power-down signal (where CORE_PD power-down takes precedence), then the condition is satisfied; if the first signal is CORE_PD power-on signal (where SYS_SLP power-on takes precedence), then the condition is satisfied; if the first signal is SYS_SLP power-on signal (where SYS_SLP power-on takes precedence), then the condition is satisfied; if the first signal is SYS_SLP power-down signal (where CORE_PD power-down takes precedence), then the condition is satisfied; if the first signal is CORE_PD power-on signal (where CORE_PD power-on takes precedence), then the condition is not satisfied; if the first signal is SYS_SLP power-down signal (where SYS_SLP power-down takes precedence), then the condition is not satisfied.

[0089] In one possible implementation, the response control module is specifically configured to, when the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is CORE_PD power-on signal priority, and the second signal is a SYS_SLP power-on signal, first control the SRAM to wake up according to the SYS_SLP power-on signal, and then control the CPU to wake up according to the CORE_PD power-on signal; when the first signal is a SYS_SLP power-off signal, and the receiving order of the first signal is SYS_SLP power-off signal priority, and the second signal is a CORE_PD power-off signal, first control the CPU to hibernate according to the CORE_PD power-off signal, and then control the SRAM to hibernate according to the SYS_SLP power-off signal.

[0090] In one possible implementation, the response control module is specifically configured to: when the first signal is a CORE_PD power-off signal, if the receiving order of the first signal is CORE_PD power-off signal first, control the CPU to enter sleep mode according to the CORE_PD power-off signal; when the first signal is a CORE_PD power-on signal, if the receiving order of the first signal is SYS_SLP power-on signal first, control the CPU to wake up according to the CORE_PD power-off signal; when the first signal is a SYS_SLP power-on signal, if the receiving order of the first signal is SYS_SLP power-on signal first, control the SRAM to wake up according to the SYS_SLP power-on signal; and when the first signal is a SYS_SLP power-off signal, if the receiving order of the first signal is CORE_PD power-off signal first, control the SRAM to wake up according to the SYS_SLP power-on signal.

[0091] As can be seen, the chip in this application embodiment can, after receiving the first signal, determine the receiving order corresponding to the first signal based on the first signal and historical receiving information, and determine whether the receiving order corresponding to the first signal satisfies a preset priority order. If the receiving order corresponding to the first signal satisfies the preset priority order, the CPU or SRAM can be controlled to wake up or hibernate based on the first signal and a preset correspondence. This reduces the power consumption of the CPU or SRAM and improves the battery life of the electronic device by controlling the wake-up and hibernation of the CPU or SRAM.

[0092] In another aspect of the embodiments of this application, an electronic device is also provided, see [link to relevant documentation]. Figure 4 , Figure 4A schematic diagram of an electronic device provided in an embodiment of this application includes: a PMIC, a SOC, a CPU, and an SRAM; the PMIC is electrically connected to the SOC, CPU, and SRAM respectively.

[0093] The PMIC is used to execute any of the dual-rail power supply control methods described above.

[0094] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the steps of any of the above-described dual-rail power supply control methods.

[0095] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the dual-rail power supply control methods described in the above embodiments.

[0096] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a solid-state drive (SSD), etc.

[0097] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0098] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments for chips, electronic devices, and storage media are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0099] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A dual-rail power supply control method, characterized in that, The method, applied to a power management chip (PMIC), includes: Receive a first signal sent by the system chip SOC, wherein the first signal includes one of the following: system hibernation SYS_SLP power-on signal, SYS_SLP power-off signal, core power domain control CORE_PD power-off signal, and CORE_PD power-on signal; Based on the first signal and historical reception information, the reception order corresponding to the first signal is determined, wherein the historical reception information includes: the historical reception information of each signal among the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on signal; Determine whether the receiving order corresponding to the first signal satisfies a preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-on signal takes precedence over the CORE_PD power-on signal; If the receiving order corresponding to the first signal satisfies the preset priority order, the CPU or the static random access memory (SRAM) is controlled to hibernate or wake up according to the first signal and the preset correspondence. The preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to hibernate in response to the SYS_SLP power-off signal, and controlling the CPU to hibernate in response to the CORE_PD power-off signal. If the receiving order corresponding to the first signal does not meet the preset priority order, the system continues to monitor for a first preset duration to obtain the second signal; first, the CPU or SRAM is controlled according to the second signal to hibernate or wake up, and then the CPU or SRAM is controlled according to the first signal to hibernate or wake up, with the second signal having a higher priority than the first signal.

2. The method according to claim 1, characterized in that, The step of determining the reception order corresponding to the first signal based on the first signal and historical reception information includes: If the first signal is the SYS_SLP power-off signal, based on the historical reception information, it is determined whether the CORE_PD power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-off signal priority; if no, the reception order corresponding to the first signal is SYS_SLP power-off signal priority. If the first signal is a CORE_PD power-on signal, based on the historical reception information, it is determined whether a SYS_SLP power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-on signal priority; if no, the reception order corresponding to the first signal is CORE_PD power-on signal priority. If the first signal is a CORE_PD power-off signal, based on the historical reception information, it is determined whether a SYS_SLP power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-off signal priority; if no, the reception order corresponding to the first signal is CORE_PD power-off signal priority. If the first signal is the SYS_SLP power-on signal, based on the historical reception information, it is determined whether the CORE_PD power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-on signal priority; if no, the reception order corresponding to the first signal is SYS_SLP power-on signal priority.

3. The method according to claim 2, characterized in that, The step of determining whether the receiving order corresponding to the first signal satisfies the preset priority order includes: If the first signal is a CORE_PD power-down signal, and the receiving order of the first signal is CORE_PD power-down signal first, then the condition is satisfied; if the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is SYS_SLP power-on signal first, then the condition is satisfied; if the first signal is a SYS_SLP power-on signal, and the receiving order of the first signal is SYS_SLP power-on signal first, then the condition is satisfied; if the first signal is a SYS_SLP power-down signal, and the receiving order of the first signal is CORE_PD power-down signal first, then the condition is satisfied. If the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is CORE_PD power-on signal first, then the condition is not met; if the first signal is a SYS_SLP power-off signal, and the receiving order of the first signal is SYS_SLP power-off signal first, then the condition is not met.

4. The method according to claim 3, characterized in that, The step of first controlling the CPU or SRAM to hibernate or wake up according to the second signal, and then controlling the CPU or SRAM to hibernate or wake up according to the first signal, includes: When the first signal is the CORE_PD power-on signal, and the receiving order of the first signal is CORE_PD power-on signal first, and the second signal is the SYS_SLP power-on signal, the SRAM is first woken up according to the SYS_SLP power-on signal, and then the CPU is woken up according to the CORE_PD power-on signal. When the first signal is the SYS_SLP power-down signal, and the receiving order of the first signal is SYS_SLP power-down signal first, and the second signal is the CORE_PD power-down signal, the CPU is first controlled to enter sleep mode according to the CORE_PD power-down signal, and then the SRAM is controlled to enter sleep mode according to the SYS_SLP power-down signal.

5. The method according to claim 3, characterized in that, If the receiving order corresponding to the first signal satisfies the preset priority order, the processor CPU or the static random access memory (SRAM) is controlled to enter sleep or wake-up mode according to the first signal and the preset correspondence, including: If the first signal is a CORE_PD power-off signal, and the receiving order of the first signal is CORE_PD power-off signal first, then the CPU is controlled to go into sleep mode according to the CORE_PD power-off signal. If the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is SYS_SLP power-on signal first, then the CPU is controlled to wake up according to the CORE_PD power-off signal. If the first signal is the SYS_SLP power-on signal, and the receiving order corresponding to the first signal is SYS_SLP power-on signal first, then the SRAM is controlled to be woken up according to the SYS_SLP power-on signal. If the first signal is the SYS_SLP power-down signal, and the receiving order corresponding to the first signal is CORE_PD power-down signal first, then the SRAM is controlled to be woken up according to the SYS_SLP power-on signal.

6. A power management chip, characterized in that, The chip includes: The first signal receiving module is used to receive a first signal sent by the system chip SOC, wherein the first signal includes one of the following: system hibernation SYS_SLP power-on signal, SYS_SLP power-off signal, core power domain control CORE_PD power-off signal, and CORE_PD power-on signal; The sequence determination module is used to determine the reception order corresponding to the first signal based on the first signal and historical reception information, wherein the historical reception information includes: the historical reception information of each signal among the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on signal; The priority determination module is used to determine whether the receiving order corresponding to the first signal meets the preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-on signal takes precedence over the CORE_PD power-on signal; A response control module is configured to, when the reception order corresponding to the first signal satisfies the preset priority order, control the CPU or the SRAM to hibernate or wake up according to the first signal and a preset correspondence, wherein the preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to hibernate in response to the SYS_SLP power-off signal, and controlling the CPU to hibernate in response to the CORE_PD power-off signal; when the reception order corresponding to the first signal does not satisfy the preset priority order, continue monitoring for a first preset duration to obtain a second signal; first control the CPU or the SRAM to hibernate or wake up according to the second signal, and then control the CPU or the SRAM to hibernate or wake up according to the first signal, wherein the second signal has a higher priority than the first signal.

7. The chip according to claim 6, characterized in that, The sequence determination module is specifically used to, when the first signal is a SYS_SLP power-off signal, determine, based on the historical reception information, whether a CORE_PD power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-off signal priority; otherwise, the reception order corresponding to the first signal is SYS_SLP power-off signal priority; when the first signal is a CORE_PD power-on signal, determine, based on the historical reception information, whether a SYS_SLP power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-on signal priority; otherwise, the reception order corresponding to the first signal is CORE_PD. Power-on signal priority; when the first signal is a CORE_PD power-off signal, based on the historical reception information, determine whether a SYS_SLP power-off signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is SYS_SLP power-off signal priority, otherwise, the reception order corresponding to the first signal is CORE_PD power-off signal priority; when the first signal is a SYS_SLP power-on signal, based on the historical reception information, determine whether a CORE_PD power-on signal was received within the previous second preset time period; if yes, the reception order corresponding to the first signal is CORE_PD power-on signal priority, otherwise, the reception order corresponding to the first signal is SYS_SLP power-on signal priority.

8. The chip according to claim 6, characterized in that, The priority determination module is specifically configured to: If, when the first signal is a CORE_PD power-down signal, the receiving order of the first signal is CORE_PD power-down signal priority, then the condition is satisfied; if, when the first signal is a CORE_PD power-on signal, the receiving order of the first signal is SYS_SLP power-on signal priority, then the condition is satisfied; if, when the first signal is a SYS_SLP power-on signal, the receiving order of the first signal is SYS_SLP power-on signal priority, then the condition is satisfied; if, when the first signal is a SYS_SLP power-down signal, the receiving order of the first signal is SYS_PD power-up signal priority, then the condition is satisfied; if, when the first signal is a SYS_SLP power-down signal, the receiving order of the first signal is CORE_PD power-on signal priority, then the condition is not satisfied; if, when the first signal is a SYS_SLP power-down signal, the receiving order of the first signal is SYS_SLP power-down signal priority, then the condition is not satisfied.

9. The chip according to claim 8, characterized in that, The response control module is specifically configured to, when the first signal is a CORE_PD power-on signal, and the receiving order of the first signal is CORE_PD power-on signal first, and the second signal is a SYS_SLP power-on signal, first control the SRAM to wake up according to the SYS_SLP power-on signal, and then control the CPU to wake up according to the CORE_PD power-on signal; when the first signal is a SYS_SLP power-off signal, and the receiving order of the first signal is SYS_SLP power-off signal first, and the second signal is a CORE_PD power-off signal, first control the CPU to hibernate according to the CORE_PD power-off signal, and then control the SRAM to hibernate according to the SYS_SLP power-off signal.

10. An electronic device, characterized in that, include: PMIC, SOC, CPU, and SRAM: The PMIC is electrically connected to the SOC, CPU, and SRAM, respectively. The PMIC is used to perform the method described in any one of claims 1-5.

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