Data transmission method, server, readable storage medium and program product

Abstract

The application discloses a data transmission method, a server, a readable storage medium and a program product, relates to the technical field of data processing, and dynamically adjusts the frequency of a clock signal according to the processor load rate in a data transmission process, improves the data transmission rate through a higher clock signal frequency when the processor load is low and the clock signal quality is good, adopts a lower clock signal frequency when the processor load is high and the clock signal quality is poor, reduces signal fluctuation caused by the interference of the processor on the clock signal, and thus improves the stability of data transmission in the equipment upgrading process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular, relates to a data transmission method, a server, a readable storage medium and a program product. BACKGROUND

[0002] In a storage server, a Complex Programmable Logic Device (CPLD) is an important component, which is used to implement digital logic circuits, state monitoring and the like. A Baseboard Management Controller (BMC) in the storage server is responsible for managing and maintaining firmware of the CPLD, and writes the firmware of the CPLD into the CPLD to implement upgrading of the CPLD.

[0003] In the upgrading process, the BMC controls a high or low level analog clock signal and a data signal of a specified pin. The clock signal serves as a synchronization reference for data transmission, and the data signal needs to be stable at a rising edge or a falling edge of the clock signal, so as to ensure that the CPLD can correctly receive data carried by the data signal.

[0004] However, a load of a Central Processing Unit (CPU) of the BMC affects stability of the clock signal, and the higher the frequency of the clock signal is, the more obvious the influence is, thereby leading to poor stability of data transmission in the upgrading process. SUMMARY

[0005] The present application provides a data transmission method, a server, a readable storage medium and a program product, to at least solve the problem of poor stability of data transmission in the related art.

[0006] The present application provides a data transmission method, applied to a Baseboard Management Controller of a server, the Baseboard Management Controller comprising a processor and a clock generator, the server further comprising a device to be upgraded, the method comprising:

[0007] obtaining a target signal frequency corresponding to a load rate of the processor, the target signal frequency being negatively correlated with the load rate;

[0008] adjusting a signal generation frequency of the clock generator according to the target signal frequency, and controlling the clock generator to output a target clock signal corresponding to the target signal frequency according to the adjusted signal generation frequency;

[0009] performing data transmission based on the target clock signal, and writing an upgrading firmware corresponding to a device upgrading task into the device to be upgraded.

[0010] The application further provides a server, comprising a memory for storing a computer program, and a processor for executing the computer program to implement the steps of any of the data transmission methods.

[0011] The application further provides a computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of any of the data transmission methods.

[0012] The application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps of any of the data transmission methods.

[0013] Through the application, the frequency of the clock signal is dynamically adjusted according to the processor load rate in the data transmission process, the data transmission rate is improved by using a higher clock signal frequency when the processor load is low and the clock signal quality is good, and a lower clock signal frequency is used when the processor load is high and the clock signal quality is poor, so that the signal fluctuation caused by the interference of the processor on the clock signal is reduced, thereby improving the stability of data transmission in the device upgrading process. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0015] Figure 1 The data transmission method flowchart provided for the embodiments of the application;

[0016] Figure 2 The application scenario schematic diagram provided for the embodiments of the application;

[0017] Figure 3 The data transmission device structure schematic diagram provided for the embodiments of the application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, not all. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0019] It should be noted that in the description of the present application, the term "comprising", "containing" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or further includes elements inherent to such a process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0020] In order to enable those skilled in the art to better understand the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0021] The embodiment of the present application provides a data transmission method, and the method is described in detail in combination with the execution flow of the data transmission method.

[0022] Figure 1 The data transmission method flowchart provided by the embodiment of the present application. The method can be applied to Figure 2 The application scenario shown in the figure includes a server 21, for example, a storage server. The server 21 includes a baseboard management controller 211 and a device to be upgraded 212. The baseboard management controller 211 needs to periodically write upgrade firmware to the device to be upgraded 212 to complete the function update or vulnerability repair of the device to be upgraded 212. The baseboard management controller 211 includes a processor and a clock generator. The processor can be a central processing unit. The clock generator is used to generate a clock signal and provide a time reference for data transmission.

[0023] The data transmission method shown in Figure 2 The application scenario is introduced, and the data transmission method shown in Figure 1 The specific steps of the method are as follows:

[0024] S101, obtaining a target signal frequency corresponding to a load rate of a processor, the target signal frequency being negatively correlated with the load rate.

[0025] The load rate of the processor refers to the task busy degree of the processor in a unit of time, which is usually expressed in percentage and reflects the current resource occupation of the processor.

[0026] The target signal frequency is the frequency of the clock signal planned to be output by the clock generator of the baseboard management controller, which is the target rate reference of data transmission.

[0027] After the baseboard management controller obtains the load rate of the processor, the target signal frequency of the clock generator is determined according to the load rate. Since the load rate of the processor will affect the stability of the clock signal, the higher the load rate of the processor, the more serious the influence on the clock signal, and the poorer the quality of the clock signal, the lower target signal frequency is used to control the clock generator when the load rate of the processor is high, so as to reduce the number of signal edges in unit time and reduce the probability that data cannot be stable at the clock signal edge during data transmission; when the load rate of the processor is high, the higher target signal frequency is used to control the clock generator, so as to improve the efficiency of data transmission.

[0028] Specifically, the target signal frequency decreases with the increase of the load rate. For example, when the load rate of the processor is less than 50%, the target signal frequency is 10MHz; when the load rate of the processor is 50%-80%, the target signal frequency is 5MHz; when the load rate of the processor is greater than 80%, the target signal frequency is 1MHz.

[0029] Optionally, when the device upgrade is performed, the baseboard management controller monitors the processor occupancy rate of each thread through the real-time monitoring function pre-configured in the baseboard management controller, and calculates the sum of the processor occupancy rate of each thread, so as to obtain the load rate of the processor.

[0030] S102, the signal generation frequency of the clock generator is adjusted according to the target signal frequency, and the clock generator outputs the target clock signal corresponding to the target signal frequency according to the adjusted signal generation frequency.

[0031] The target clock signal is an electrical signal generated by the clock generator according to the target signal frequency, and the period of the high and low level alternation is the target signal frequency, which is used as the rate and timing reference of data transmission.

[0032] In the actual clock signal generation process, due to the influence of factors such as signal quality and processor load, even if the clock generator is controlled to generate a clock signal according to the target signal frequency, the actual measured signal frequency obtained finally may be quite different from the target signal frequency, or there may be signal fluctuation. In this step, the signal generation frequency of the clock generator is adjusted, so that the finally output clock signal is the target clock signal meeting the target signal frequency requirement. For example, the error between the finally output clock signal and the target clock signal is less than a preset error threshold.

[0033] S103, data transmission is performed based on the target clock signal, and the upgrade firmware corresponding to the device upgrade task is written into the device to be upgraded.

[0034] The upgrade firmware is a program file to be written, which contains upgrade information of the device to be upgraded. The execution process of the device upgrade task includes a writing process of the upgrade firmware, and the device upgrade task is completed after the upgrade firmware is completely and correctly written into the device to be upgraded.

[0035] During the device upgrade task, data transmission is performed between the baseboard management controller and the device to be upgraded. The baseboard management controller sends the upgrade firmware to the device to be upgraded, and the device to be upgraded returns response information to the baseboard management controller. That is, during the data transmission process, the data sending time and the receiving confirmation time need to be determined according to the edge of the target clock signal, so that the data can be stabilized at the edge of the target clock signal.

[0036] The embodiment of the application dynamically adjusts the frequency of the clock signal according to the processor load rate during the data transmission process. When the processor load is low and the quality of the clock signal is good, a higher clock signal frequency is used to improve the data transmission rate. When the processor load is high and the quality of the clock signal is poor, a lower clock signal frequency is used to reduce the signal fluctuation caused by the interference of the processor on the clock signal, thereby improving the stability of data transmission during the device upgrade process.

[0037] On the basis of the above embodiment, based on the target clock signal for data transmission, before the upgrade firmware corresponding to the device upgrade task is written into the device to be upgraded, the method further comprises: obtaining a target priority corresponding to the load rate, the priority of the target priority being positively correlated with the load rate; and adjusting the priority of the device upgrade task to the target priority, so that the device upgrade task is allocated system resources corresponding to the target priority.

[0038] Correspondingly, based on the target clock signal for data transmission, the upgrade firmware corresponding to the device upgrade task is written into the device to be upgraded, comprising: based on the system resources and the target clock signal for data transmission, the upgrade firmware corresponding to the device upgrade task is written into the device to be upgraded.

[0039] In the server, the baseboard management controller needs to process multiple tasks at the same time, including the upgrade task of the device to be upgraded and other tasks. When the load rate of the processor is high, if the upgrade task and other tasks use the same priority, the response of the upgrade task may be further delayed due to the preemption of system resources.

[0040] Therefore, the baseboard management controller dynamically adjusts the priority of the upgrade task according to the load rate of the processor. The higher the load rate of the processor is, the higher the target priority of the upgrade task is, so that the upgrade task can be allocated more system resources when the load rate of the processor is high.

[0041] For example, when the load rate of the processor reaches 80%, the priority of the upgrade task is set to 99, so that the upgrade task is in the first position in the priority order and can obtain sufficient system resources, thereby avoiding being preempted by other non-critical tasks.

[0042] When the load rate of the processor is at a normal level, there are sufficient idle system resources for the execution of the upgrade task, and the target priority of the upgrade task can be set to a normal priority accordingly, and the system resources are allocated to the upgrade task in a conventional manner.

[0043] The embodiments of the present application dynamically adjust the priority of the upgrade task according to the load rate of the processor, and give the upgrade task a higher priority when the load of the processor is high, so that the upgrade task can preempt system resources in a high-load scenario of the processor, ensure the process of the upgrade task to be scheduled preferentially, reduce the influence of the load rate of the processor on the clock signal in the upgrade process, and further improve the stability of data transmission.

[0044] In some embodiments, before obtaining the target signal frequency corresponding to the load rate of the processor, the method further comprises: determining a target detection frequency based on the historical load rate of the processor in the last detection period, the target detection frequency being positively correlated with the historical load rate; and detecting the load rate of the processor according to the target detection frequency.

[0045] The last detection period refers to the just-ended load detection period, and the historical load rate refers to the load rate of the processor calculated by a predetermined algorithm in the period.

[0046] The target detection frequency refers to the frequency of the upcoming load detection, that is, the number of detections per unit time. The higher the target detection frequency, the shorter the interval of load detection of the processor.

[0047] The target detection frequency is related to the real-time performance of load detection. The higher the target detection frequency, the higher the real-time performance of load detection of the processor, and the higher the frequency of adjusting the target signal frequency of the clock generator and / or the target priority of the upgrade task.

[0048] The embodiments of the present application dynamically adjust the detection frequency of the load rate of the processor at a subsequent time according to the load rate of the processor, increase the detection frequency when the load of the processor is high, shorten the detection period, thereby increasing the adjustment frequency of the target signal frequency and / or the target priority of the upgrade task, and make the adjusted target signal frequency and / or the target priority of the upgrade task more suitable for the current load state, avoid the load state lag caused by too low detection frequency, the target signal frequency and / or the target priority of the upgrade task failing to adapt to the real-time load state, and the high data transmission failure rate and error rate, and further improve the reliability of data transmission.

[0049] On the basis of any of the above embodiments, the processor load rate is calculated in the following manner: a historical load rate of the processor in a previous detection period and a real-time load rate at the start of the current detection period are obtained; the historical load rate and the real-time load rate are weighted and summed to obtain a load rate of the processor in the current detection period, the weight of the historical load rate being less than the weight of the real-time load rate.

[0050] The historical load rate of the previous detection period refers to the load rate obtained by the above calculation manner corresponding to the completed load detection period. The real-time load rate at the start of the current detection period represents the latest load state of the processor.

[0051] The process of weighted sum of the historical load rate and the real-time load rate is represented as:

[0052] .

[0053] wherein, is the load rate of the current detection period, is the historical load rate of the previous detection period, is the real-time load rate, and a and b represent the weights of the two, respectively.

[0054] Optionally, the weight of the historical load rate and the weight of the real-time load rate are 1.

[0055] It can be understood that the historical load rate is also obtained based on the above calculation manner, and the load rate of each detection period will be the historical load rate of the next detection period. Therefore, the historical load rate actually carries the load conditions of each detection period before the current detection period, and the load conditions of each detection period are weighted in the form of exponential decay according to the time interval from the current detection period. The load rate corresponding to the detection period with a longer time interval from the current detection period is weighted by b to the power of n, and the power is positively correlated with the time interval.

[0056] The embodiment of the application obtains the load rate of the current detection period by weighted sum of the historical load rate and the real-time load rate, which takes into account the stability of historical data and the timeliness of real-time data, avoids sudden changes in the clock signal frequency caused by sudden changes in the load rate, reduces the jitter of the clock signal under the premise of reasonable load rate calculation, and further improves the stability of data transmission based on the clock signal.

[0057] The adjustment and compensation process of the clock signal will be described in detail below.

[0058] In some embodiments, the signal generation frequency of the clock generator is adjusted according to the target signal frequency, and the clock generator is controlled to output a target clock signal corresponding to the target signal frequency at the adjusted signal generation frequency, including: controlling the clock generator to output a first clock signal at the target signal frequency; determining a signal jitter rate of the first clock signal based on a signal edge of the first clock signal and a preset signal edge corresponding to the target clock signal; calculating a frequency adjustment parameter according to a preset jitter rate and the signal jitter rate; and adjusting the signal generation frequency of the clock generator based on the frequency adjustment parameter, and controlling the clock generator to output the target clock signal corresponding to the target signal frequency at the adjusted signal generation frequency.

[0059] The output frequency of the clock generator can be adjusted by controlling relevant parameters such as the frequency division ratio. The first clock signal is a clock signal that the clock generator initially outputs at the target signal frequency, and may have a certain jitter since it has not yet been corrected for jitter.

[0060] The signal edge refers to the rising edge generated when the clock signal jumps from low to high or the falling edge generated when the clock signal jumps from high to low, and the preset signal edge is the ideal edge position calculated based on the target signal frequency. Due to the existence of signal jitter, there is a time domain deviation between the signal edge of the first clock signal and the preset signal edge, and the jitter rate of the first clock signal can be obtained based on the time domain deviation and the signal period of the first clock signal.

[0061] Specifically, the jitter rate of the first clock signal is calculated as follows: determining the time domain deviation between the signal edge of the first clock signal and the preset signal edge corresponding to the target clock signal; and calculating the ratio of the time domain deviation to the period of the first clock signal to obtain the signal jitter rate.

[0062] The time domain deviation represents the difference between the signal edge of the first clock signal and the preset signal edge, and the proportion of the time domain deviation in the clock period is the jitter rate of the first clock signal.

[0063] The preset jitter rate is a pre-set maximum jitter rate threshold that can be tolerated. For example, the preset jitter rate can be set to 2%. The frequency adjustment parameter is a value used to correct the signal frequency of the clock generator, and its size is positively correlated with the difference between the preset jitter rate and the measured jitter rate. When the difference between the preset jitter rate and the measured jitter rate is larger, it means that the jitter of the first clock signal is more serious, and a larger frequency adjustment parameter is needed to correct the jitter of the first clock signal as soon as possible; when the difference between the preset jitter rate and the measured jitter rate is smaller, it means that the jitter of the first clock signal is less serious, and a smaller frequency adjustment parameter is needed for fine tuning.

[0064] After the frequency adjustment parameter is obtained, frequency correction is performed by changing the control parameter (such as the frequency division ratio) of the clock generator, so that the frequency of the corrected clock signal conforms to the target signal frequency, and the jitter rate is less than the preset jitter rate.

[0065] The specific implementation manner of calculating the frequency adjustment parameter according to the preset jitter rate and the signal jitter rate is: calculating the difference between the preset jitter rate and the signal jitter rate to obtain a jitter error; and performing proportional-integral-derivative calculation on the jitter error based on preset coefficients to obtain the frequency adjustment parameter, wherein the preset coefficients include a proportional coefficient, an integral coefficient, and a differential coefficient.

[0066] The jitter error represents the degree to which the signal jitter rate exceeds the preset jitter rate, and the calculation process is represented as:

[0067]

[0068] wherein, represents the jitter error at time t, represents the signal jitter rate, represents the preset jitter rate.

[0069] Optionally, when the jitter error obtained by continuous multiple detections exceeds a preset jitter error tolerance value, the target signal frequency is set to a preset minimum frequency, and a baseboard management controller interrupt is triggered to record an error log.

[0070] Further, the proportional-integral-derivative formula is used to calculate the frequency adjustment parameter corresponding to the jitter error. The calculation process of the frequency adjustment parameter is represented as:

[0071]

[0072] wherein, is a proportional coefficient, is a proportional term, which is used for immediate response to the current error for rapid correction; is an integral coefficient, is an integral term, which is used for eliminating steady-state error and compensating for long-term error; is a differential coefficient, is a differential term, which is used for suppressing oscillation, predicting the trend of change, for example, slowing down the frequency increase rate in advance when the load rapidly decreases.

[0073] The proportional coefficient, the integral coefficient, and the differential coefficient can be set based on expert experience or determined by the Ziegler-Nichols method, which is not limited in the present application.

[0074] Optionally, in the process of adjusting the signal generation frequency of the clock generator based on the frequency adjustment parameter, when the frequency variation rate corresponding to the frequency adjustment parameter is greater than the preset frequency variation rate, the signal generation frequency of the clock generator is adjusted according to the preset frequency variation rate.

[0075] The size of the frequency adjustment parameter determines the frequency variation rate of the clock signal when the signal generation frequency is adjusted. The greater the frequency adjustment parameter, the greater the frequency of the clock signal, which is more likely to cause the clock signal to fluctuate greatly due to the sudden change of the signal frequency. Therefore, when the frequency variation rate corresponding to the frequency adjustment parameter is greater than the preset frequency variation rate, adjusting according to the frequency adjustment parameter is likely to cause the clock signal to fluctuate greatly.

[0076] Therefore, the preset frequency variation rate is set as the maximum frequency variation rate that can be accepted during the adjustment process. Even when the frequency variation rate corresponding to the frequency adjustment parameter is greater than the preset frequency variation rate, the signal generation frequency of the clock generator is adjusted according to the preset frequency variation rate to avoid the clock signal from fluctuating greatly due to the sudden change of the frequency, thereby reducing the impact of the change of the clock signal frequency on data transmission and further improving the stability of data transmission.

[0077] On the basis of the above embodiment, after determining the signal jitter rate of the clock signal based on the signal edge of the first clock signal and the preset signal edge corresponding to the target clock signal, the method further comprises: when the signal jitter rate is greater than a first preset threshold, determining the length of the delay signal according to the signal jitter rate; and inserting the delay signal into the first clock signal to reduce the time domain deviation between the next signal edge of the first clock signal and the preset signal edge.

[0078] The first preset threshold is a preset jitter rate threshold. The signal jitter below the threshold has less impact on data transmission and can be gradually adjusted by the method in the above embodiment. The signal jitter above the threshold has greater impact on data transmission and needs to be actively compensated by inserting the delay signal.

[0079] The insertion of the delay signal means adding a fixed time delay in the high or low phase of the current clock signal to make the position of the next signal edge close to the preset signal edge.

[0080] Specifically, when the signal jitter rate is greater than the first preset threshold, determining the length of the delay signal according to the signal jitter rate comprises: when the signal jitter rate is greater than the first preset threshold and less than a second preset threshold, determining the length of the delay signal as a first preset length, the first preset length being a product of the time domain deviation and a first preset proportion; when the signal jitter rate is greater than or equal to the second preset threshold, determining the length of the delay signal as a difference between the time domain deviation and a second preset length, the second preset length being a product of a signal period corresponding to the signal generation frequency and a second preset proportion, the first preset proportion being greater than the second preset proportion.

[0081] Optionally, the first preset threshold is 10%, and the second preset threshold is 30%.

[0082] When the signal jitter rate is greater than the first preset threshold and less than the second preset threshold, determining that the current signal jitter is small-amplitude jitter, and taking the time domain deviation multiplied by the first preset proportion as the compensation value. For example, the first preset proportion is 50%. In this way, the signal jitter can be quickly corrected.

[0083] When the signal jitter rate is greater than or equal to the second preset threshold, determining that the current signal jitter is large-amplitude jitter, and taking the difference between the time domain deviation and the second preset length as the compensation value, wherein the second preset length is a product of a signal period corresponding to the signal generation frequency and a second preset proportion, and the first preset proportion is greater than the second preset proportion. For example, the second preset proportion is 10%. In this way, the large-amplitude jitter can be quickly corrected, and signal fluctuations caused by too fast correction can be avoided.

[0084] The embodiments of the present application correct the signal jitter with different strategies according to the amplitude of the signal jitter, quickly correct the small-amplitude jitter, quickly correct the large-amplitude jitter while controlling the correction rate, avoid signal fluctuations caused by too fast correction or over-correction, improve the adaptability to complex environments such as high voltage and strong electromagnetism, and further improve the stability and reliability of data transmission.

[0085] On the basis of the above-mentioned embodiments, data transmission is performed based on a target clock signal, and a device upgrade task is performed by writing an upgrade firmware corresponding to the device upgrade task into a device to be upgraded, which comprises: obtaining a first data block in the upgrade firmware; and sending the first data block to the device to be upgraded based on the target clock signal.

[0086] After the first data block is sent to the device to be upgraded, in response to receiving write success information sent by the device to be upgraded, a second data block in the upgrade firmware is obtained; and the second data block is sent to the device to be upgraded based on the target clock signal, the second data block being a next data block of the first data block.

[0087] Alternatively, in response to receiving the write failure information sent by the device to be upgraded and / or not receiving information from the device to be upgraded within a preset waiting time, the first data block is re-sent to the device to be upgraded.

[0088] The firmware to be upgraded is a program file to be transmitted, and the first data block is a first continuous data segment obtained by performing data block segmentation on the firmware to be upgraded.

[0089] Since the device to be upgraded samples data at the signal edge of the clock signal, the first data block needs to be sent to the device to be upgraded based on the target clock signal, so that the device to be upgraded can sample at the signal edge of the target clock signal to obtain the first data block, and the timing synchronization between the baseboard management controller and the device to be upgraded is ensured.

[0090] The write success information is an acknowledgement signal returned by the device to be upgraded after correctly receiving and verifying the data block, and informs the baseboard management controller that the current data block transmission is completed and error-free.

[0091] The second data block is a next segment of data in the firmware to be upgraded and continuous with the first data block. After receiving the write success information of the device to be upgraded, the baseboard management controller sends the next data block to the device to be upgraded.

[0092] When the baseboard management controller does not receive the write success information of the first data block, for example, receives the write failure information sent by the device to be upgraded and / or does not receive information from the device to be upgraded within a preset waiting time, it is determined that the first data block fails to write, and the first data block is re-sent to the device to be upgraded.

[0093] The embodiment of the application determines that the previous data block is successfully written in the device to be upgraded, and then sends the next data block, and re-sends the data block when the data block fails to write, so as to ensure that each data block is successfully written in the device to be upgraded in sequence, which not only ensures the integrity of the firmware transmission, but also avoids the need to re-transmit the entire firmware when the overall verification fails after all data is written, thereby improving the upgrading efficiency.

[0094] Optionally, the size of the next data block is determined according to the write condition of the data block. For example, when a continuous preset number of data blocks are successfully written, the size of the next data block is determined as n times the size of the last sent data block; or when a data block fails to write, the size of the next data block is determined as 1 / n times the size of the data block that fails to write, wherein n is a positive integer.

[0095] The n can be 2.

[0096] After multiple consecutive data blocks have been successfully written, it indicates that the current data transmission quality is high. Appropriately increasing the size of individual data blocks can improve data transmission efficiency. For example, if the last sent data block was 128 bytes, the size of the next data block should be set to 256 bytes.

[0097] When a write failure requires retransmission, it indicates that the current data transmission has been disrupted. In this case, reducing the size of individual data blocks and the amount of data transmitted in a single transmission reduces the probability of disruption. For example, if the size of the failed data block is 256 bytes, the size of the next data block should be 128 bytes.

[0098] This application embodiment increases the amount of data transmitted in a single transmission by increasing the size of the next data block after multiple consecutive data blocks are successfully written; and decreases the size of the next data block when a data block fails to be written, thereby reducing the amount of data transmitted in a single transmission and lowering the probability of interference. This allows the size of the data block to be matched with the data transmission quality in real time, balancing the efficiency and reliability of data transmission.

[0099] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0100] Embodiments of this application also provide a data transmission device. Figure 3 This is a schematic diagram of the data transmission device structure provided in an embodiment of this application. Figure 3 As shown, the data transmission device 30 includes a first acquisition module 31, a control module 32, and a transmission module 33. The first acquisition module 31 is used to acquire the target signal frequency corresponding to the processor's load rate, and the target signal frequency is negatively correlated with the load rate. The control module 32 is used to adjust the signal generation frequency of the clock generator according to the target signal frequency, and control the clock generator to output the target clock signal corresponding to the target signal frequency according to the adjusted signal generation frequency. The transmission module 33 is used to perform data transmission based on the target clock signal and write the upgrade firmware corresponding to the device upgrade task into the device to be upgraded.

[0101] Optionally, the data transmission device 30 comprises a second acquisition module, configured to acquire a target priority corresponding to the load rate before the data transmission based on the target clock signal and before the upgrade firmware corresponding to the device upgrade task is written into the device to be upgraded, the priority of the target priority being positively correlated with the load rate; adjust the priority of the device upgrade task to the target priority corresponding to the load rate, so that the device upgrade task is allocated the system resource corresponding to the target priority; correspondingly, the transmission module 33 is configured to perform the data transmission based on the system resource and the target clock signal, and write the upgrade firmware corresponding to the device upgrade task into the device to be upgraded.

[0102] Optionally, the data transmission device 30 comprises a detection module, configured to determine a target detection frequency based on the historical load rate of the processor in the last detection period before acquiring the target signal frequency corresponding to the load rate of the processor, the target detection frequency being positively correlated with the historical load rate; and detect the load rate of the processor according to the target detection frequency.

[0103] Optionally, the detection module is further configured to acquire the historical load rate of the processor in the last detection period and the real-time load rate at the starting moment of the current detection period; and perform weighted summation on the historical load rate and the real-time load rate to obtain the load rate of the processor in the current detection period, the weight of the historical load rate being less than the weight of the real-time load rate.

[0104] Optionally, the control module 32 comprises a control unit, a determination unit, a calculation unit and an adjustment unit; the control unit is configured to control the clock generator to output the first clock signal at the target signal frequency; the determination unit is configured to determine the signal jitter rate of the first clock signal based on the signal edge of the first clock signal and the preset signal edge corresponding to the target clock signal; the calculation unit is configured to calculate the frequency adjustment parameter according to the preset jitter rate and the signal jitter rate; and the adjustment unit is configured to adjust the signal generation frequency of the clock generator based on the frequency adjustment parameter, and control the clock generator to output the target clock signal corresponding to the target signal frequency at the adjusted signal generation frequency.

[0105] Optionally, the determination unit is configured to determine the time domain deviation of the signal edge of the first clock signal and the preset signal edge corresponding to the target clock signal; and calculate the ratio of the time domain deviation and the period of the first clock signal to obtain the signal jitter rate.

[0106] Optionally, the calculation unit is configured to calculate the difference between the preset jitter rate and the signal jitter rate to obtain a jitter error; and perform proportional-integral-differential calculation on the jitter error based on a preset coefficient to obtain the frequency adjustment parameter, the preset coefficient comprising a proportional coefficient, an integral coefficient and a differential coefficient.

[0107] Optionally, the adjusting unit is configured to adjust the signal generation frequency of the clock generator according to the preset frequency variation rate when the frequency variation rate corresponding to the frequency adjustment parameter is greater than the preset frequency variation rate.

[0108] Optionally, the adjusting unit is further configured to determine the length of the delay signal according to the signal jitter rate when the signal jitter rate is greater than the first preset threshold; and insert the delay signal into the first clock signal to reduce the time domain deviation of the next signal edge of the first clock signal from the preset signal edge.

[0109] Optionally, the adjusting unit is further configured to determine the length of the delay signal as a first preset length when the signal jitter rate is greater than the first preset threshold and less than a second preset threshold, the first preset threshold being less than the second preset threshold, and the first preset length being a product of the time domain deviation and a first preset proportion; and determine the length of the delay signal as a difference between the time domain deviation and a second preset length when the signal jitter rate is greater than or equal to the second preset threshold, the second preset length being a product of a signal period corresponding to the signal generation frequency and a second preset proportion, and the first preset proportion being greater than the second preset proportion.

[0110] Optionally, the transmission module 33 is configured to acquire a first data block in the upgrade firmware; send the first data block to the device to be upgraded based on the target clock signal; acquire a second data block in the upgrade firmware in response to receiving write success information sent by the device to be upgraded; and send the second data block to the device to be upgraded based on the target clock signal, the second data block being a next data block of the first data block.

[0111] Optionally, the transmission module 33 is further configured to re-send the first data block to the device to be upgraded in response to receiving write failure information sent by the device to be upgraded and / or not receiving information from the device to be upgraded for a preset waiting time.

[0112] The features of the embodiments of the data transmission device can be referred to the related descriptions of the embodiments of the data transmission method, which will not be repeated here.

[0113] The embodiments of the present application also provide a server, comprising a memory and a processor, the memory storing a computer program, and the processor being configured to run the computer program to perform the steps in any of the above-mentioned data transmission method embodiments.

[0114] The embodiments of the present application also provide a computer readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above-mentioned data transmission method embodiments when running.

[0115] In an example embodiment, the computer readable storage medium described above can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0116] Embodiments of the present application also provide a computer program product, which comprises a computer program. The computer program is executed by a processor to implement the steps in any of the data transmission method embodiments described above.

[0117] Embodiments of the present application also provide another computer program product, which comprises a non-volatile computer readable storage medium. The non-volatile computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the steps in any of the data transmission method embodiments described above.

[0118] The skilled in the art can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0119] The above describes in detail a data transmission method, a server, a readable storage medium and a program product provided by the present application. The principles and implementation modes of the present application are described by applying specific examples. The above description of the examples is only applicable to help understand the method and core idea of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application. These improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A data transmission method, characterized by, The method is applied to a baseboard management controller of a server, the baseboard management controller comprising a processor and a clock generator, the server further comprising a device to be upgraded, and the method comprises: determining a target detection frequency based on a historical load rate of the processor in a previous detection period, the target detection frequency being positively correlated with the historical load rate; detecting a load rate of the processor according to the target detection frequency; obtaining a real-time load rate of the processor at a starting moment of a current detection period; performing weighted summation on the historical load rate and the real-time load rate to obtain a load rate of the processor in the current detection period, the weight of the historical load rate being less than the weight of the real-time load rate; obtaining a target signal frequency corresponding to the load rate of the processor, the target signal frequency being negatively correlated with the load rate; adjusting a signal generation frequency of the clock generator according to the target signal frequency, and controlling the clock generator to output a target clock signal corresponding to the target signal frequency at the adjusted signal generation frequency; performing data transmission based on the target clock signal, and writing an upgrade firmware corresponding to a device upgrade task into the device to be upgraded.

2. The data transmission method of claim 1, wherein, Before the data transmission based on the target clock signal and the writing of the upgrade firmware corresponding to the device upgrade task into the device to be upgraded, the method further comprises: obtaining a target priority corresponding to the load rate, the priority of the target priority being positively correlated with the load rate; adjusting a priority of the device upgrade task to the target priority, so that the device upgrade task is allocated system resources corresponding to the target priority; correspondingly, the data transmission based on the target clock signal and the writing of the upgrade firmware corresponding to the device upgrade task into the device to be upgraded comprise: performing data transmission based on the system resources and the target clock signal, and writing the upgrade firmware corresponding to the device upgrade task into the device to be upgraded.

3. The data transmission method of claim 1, wherein, The adjustment of the signal generation frequency of the clock generator according to the target signal frequency and the control of the clock generator to output the target clock signal corresponding to the target signal frequency at the adjusted signal generation frequency comprise: controlling the clock generator to output a first clock signal at the target signal frequency; determining a signal jitter rate of the first clock signal based on a signal edge of the first clock signal and a preset signal edge corresponding to the target clock signal; calculating a frequency adjustment parameter according to a preset jitter rate and the signal jitter rate; adjusting the signal generation frequency of the clock generator based on the frequency adjustment parameter, and controlling the clock generator to output the target clock signal corresponding to the target signal frequency at the adjusted signal generation frequency.

4. The data transmission method of claim 3, wherein, The determination of the signal jitter rate of the first clock signal based on the signal edge of the first clock signal and the preset signal edge corresponding to the target clock signal comprises: determining a time domain deviation of the signal edge of the first clock signal and the preset signal edge corresponding to the target clock signal; calculating a ratio of the time domain deviation to a period of the first clock signal to obtain the signal jitter rate.

5. The data transmission method of claim 3, wherein, The frequency adjustment parameter is calculated according to the preset jitter rate and the signal jitter rate, and the calculation frequency adjustment parameter comprises: The difference between the preset jitter rate and the signal jitter rate is calculated to obtain a jitter error; The jitter error is calculated by proportional-integral-derivative based on a preset coefficient to obtain the frequency adjustment parameter, and the preset coefficient includes a proportional coefficient, an integral coefficient, and a differential coefficient.

6. The data transmission method of claim 3, wherein, The signal generation frequency of the clock generator is adjusted based on the frequency adjustment parameter, and the adjustment comprises: When the frequency change rate corresponding to the frequency adjustment parameter is greater than a preset frequency change rate, the signal generation frequency of the clock generator is adjusted according to the preset frequency change rate.

7. The data transmission method of claim 3, wherein, After determining the signal jitter rate of the first clock signal based on the signal edge of the first clock signal and the preset signal edge corresponding to the target clock signal, the method further comprises: When the signal jitter rate is greater than a first preset threshold, the length of the delay signal is determined according to the signal jitter rate; The delay signal is inserted into the first clock signal to reduce the time domain deviation between the next signal edge of the first clock signal and the preset signal edge.

8. The data transmission method of claim 7, wherein, When the signal jitter rate is greater than a first preset threshold and less than a second preset threshold, the length of the delay signal is determined as a first preset length, the first preset threshold is less than the second preset threshold, and the first preset length is a product of the time domain deviation and a first preset proportion. When the signal jitter rate is greater than or equal to the second preset threshold, the length of the delay signal is determined as a difference between the time domain deviation and a second preset length, the second preset length is a product of the signal period of the first clock signal and a second preset proportion, and the first preset proportion is greater than the second preset proportion. The data transmission based on the target clock signal writes the upgrade firmware corresponding to the device upgrade task into the device to be upgraded, and comprises:

9. The data transmission method of claim 1, wherein, Obtaining a first data block in the upgrade firmware; Sending the first data block to the device to be upgraded based on the target clock signal; In response to receiving the write success information sent by the device to be upgraded, obtaining a second data block in the upgrade firmware; Sending the second data block to the device to be upgraded based on the target clock signal, and the second data block is the next data block of the first data block. After sending the first data block to the device to be upgraded based on the target clock signal, the method further comprises:

10. The data transmission method of claim 9, wherein, In response to receiving the write failure information sent by the device to be upgraded, and / or, after a preset waiting time, no information is received from the device to be upgraded, the first data block is re-sent to the device to be upgraded. Comprise:

11. An electronic device, comprising: Memory for storing computer programs; The processor is used to execute the computer program to realize the steps of the data transmission method in any one of claims 1 to 10. The computer program is stored in the computer readable storage medium, and the computer program is executed by the processor to realize the steps of the data transmission method in any one of claims 1 to 10.

12. A computer-readable storage medium, characterized in that, ​ 13. A computer program product comprising a computer program, characterized in that, The computer program, which is executed by a processor, implements the steps of the data transmission method according to any one of claims 1 to 10.

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