Error rate determination method, data recovery method, apparatus, device, and medium

Abstract

The application discloses a bit error rate determination method, a data recovery method, a device, equipment and a medium, and relates to the technical field of flash memories. Based on a mark mapping relationship, target initial mark data corresponding to a target mark address is determined. Then, based on the target initial mark data and to-be-compared mark data, a mark bit error rate of the mark data is calculated. Since the bit error conditions in the physical page are uniformly distributed, the mark bit error rate between the target initial mark data and the to-be-compared mark data can be used as the bit error rate of the physical page. The mark bit error rate can be used to determine whether the read voltage meets the requirements in the data recovery process, thereby assisting the data recovery process. Moreover, the mark bit error rate is obtained by comparing the target initial mark data with the to-be-compared mark data. Compared with the traditional technology of calculating the bit error rate by using all the data of the physical page, the application has the advantages of fast calculation speed and high efficiency, thereby reducing the time length of the data recovery process and improving the efficiency of data recovery.

Description

Technical Field

[0001] This application relates to the field of flash memory technology, and in particular to a method for determining bit error rate, a data recovery method, an apparatus, a device, and a medium. Background Technology

[0002] Flash memory chips are widely used storage products today, possessing excellent characteristics such as high speed and non-volatility. Internally, they represent data in the form of stored electrical charge. In actual use, changes in various internal and external conditions can cause variations in the amount of stored charge. If this variation accumulates to a certain extent, accessing the flash memory using the default read operation may not retrieve the correct data.

[0003] When a read operation fails, a data recovery process is executed to re-determine the read voltage of the flash memory. During data recovery, the flash memory chip manufacturer typically provides a reread table. This table is traversed to recover data, attempting to read using the voltage specified in the table. The bit error rate (BER) is calculated after each read until it meets the requirements. In related technologies, the BER is usually calculated by comparing all the data stored in the physical pages of the flash memory with the original data. This process is time-consuming and inefficient, resulting in a lengthy and inefficient data recovery process. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a bit error rate determination method, a data recovery method, an apparatus, a device, and a medium, which can quickly determine the bit error rate of flash memory with high efficiency, thereby reducing the time required for the data recovery process and improving the efficiency of data recovery.

[0005] The bit error rate determination method according to a first aspect of this application, applied to flash memory, includes:

[0006] In response to the detection that the first read operation for the flash memory has failed, the reread voltage and the operation address in the first read operation are obtained;

[0007] Based on a pre-generated tag mapping relationship, a target tag address corresponding to the operation address in the first read operation is determined; wherein, the tag mapping relationship records the correspondence between multiple operation addresses and multiple tag addresses;

[0008] A second read operation is performed on the flash memory based on the target tag address and the reread voltage to obtain the tag data to be compared from the physical page of the flash memory;

[0009] Based on the tag mapping relationship, target initial tag data corresponding to the target tag address is determined; wherein, the tag mapping relationship also records the correspondence between multiple initial tag data and multiple tag addresses;

[0010] Based on the initial target label data and the target label data, the label error rate of the label data is calculated.

[0011] The bit error rate determination method according to the embodiments of this application has at least the following beneficial effects: When the first read operation for flash memory fails, it indicates that the data in flash memory cannot be read normally using the default voltage of flash memory. Therefore, the reread voltage and the operation address in the first read operation are obtained. Based on a pre-generated tag mapping relationship, a target tag address corresponding to the operation address in the first read operation is determined. A second read operation is performed on flash memory based on the target tag address and the reread voltage to obtain the tag data to be compared from the physical page of flash memory. Based on the tag mapping relationship, the target initial tag data corresponding to the target tag address is determined. Then, the tag bit error rate of the tag data is calculated based on the target initial tag data and the tag data to be compared. Since the bit error rate within a physical page is uniformly distributed, the tag bit error rate between the target initial tag data and the tag data to be compared can be used as the bit error rate of the physical page. The tag bit error rate can be used to determine whether the reread voltage meets the requirements during the data recovery process, thereby assisting the data recovery process. Furthermore, the bit error rate is obtained by comparing the target initial labeled data with the labeled data to be compared. Compared with the traditional technology that calculates the bit error rate using all the data in the physical page, the bit error rate calculation speed of this application is faster and more efficient, thereby reducing the time of the data recovery process and improving the efficiency of data recovery.

[0012] According to some embodiments of this application, before obtaining the reread voltage and the operation address in the first read operation in response to detecting that the first read operation for the flash memory has failed, the method further includes:

[0013] In response to detecting a write operation to the flash memory, the operation address of the write operation is obtained;

[0014] The marker address is calculated based on the operation address of the write operation;

[0015] Generate the initial tag data;

[0016] Establish the mapping relationship between the initial tag data, the operation address of the write operation, and the tag address to obtain the tag mapping relationship;

[0017] The initial tag data is written to the tag address of the flash memory.

[0018] According to some embodiments of this application, the step of calculating the tag address based on the operation address of the write operation includes:

[0019] The offset address is calculated based on the address calculation formula. The marker address is then obtained based on the operation address of the write operation and the offset address. The address calculation formula is:

[0020] L=(chip_no*pages_per_chip+block_no*pages_per_block+page_no)*Large_prime%page_length;

[0021] Where L is the offset address, chip_no is the flash memory number, pages_per_chip is the total number of physical pages in the flash memory, block_no is the physical block number in the write operation address, pages_per_block is the total number of physical pages in the physical block, page_no is the physical page number in the write operation address, Large_prime is a preset prime number, and page_length is the length of the physical page.

[0022] According to some embodiments of this application, obtaining the reread voltage includes:

[0023] Obtain the read voltage of the first read operation;

[0024] The reread voltage is obtained from a preset reread voltage table based on the read voltage, wherein the reread voltage is greater than or less than the read voltage of the first read operation.

[0025] According to some embodiments of this application, the step of calculating the tag address based on the operation address of the write operation includes:

[0026] The physical page to be written is determined based on the operation address of the write operation;

[0027] The marked address is randomly generated based on the physical page to be written; wherein the marked address is located within the physical page to be written.

[0028] A second aspect of this application provides a data recovery method applied to flash memory, the method including the bit error rate determination method as described in any one of the first aspect embodiments;

[0029] Also includes:

[0030] Detect the bit error rate of the marker;

[0031] If the bit error rate of the marker is detected to be less than the preset bit error threshold, the reread voltage is used as the target read voltage of the flash memory, and the first read operation is re-executed on the flash memory based on the target read voltage to obtain the first target recovery data;

[0032] The error correction code module corrects the first target recovery data to obtain the second target recovery data.

[0033] According to some embodiments of this application, after detecting the bit error rate of the marker, the method further includes:

[0034] If the bit error rate of the marker is detected to be greater than or equal to the preset bit error threshold, the reread voltage is updated, and the process jumps to perform a second read operation on the flash memory based on the marker address and the reread voltage to obtain the target marker data from the physical page of the flash memory.

[0035] A third aspect of this application provides a bit error rate determination apparatus applied to flash memory, the apparatus comprising:

[0036] The first acquisition module is configured to acquire the reread voltage and the operation address in the first read operation in response to detecting that the first read operation for the flash memory has failed.

[0037] The first determining module is used to determine the target tag address corresponding to the operation address in the first read operation based on a pre-generated tag mapping relationship; wherein the tag mapping relationship records the correspondence between multiple operation addresses and multiple tag addresses;

[0038] The second acquisition module is used to perform a second read operation on the flash memory based on the target tag address and the reread voltage, so as to obtain the tag data to be compared from the physical page of the flash memory;

[0039] The second determining module is used to determine the target initial tag data corresponding to the target tag address based on the tag mapping relationship; wherein, the tag mapping relationship also records the correspondence between multiple initial tag data and multiple tag addresses;

[0040] The calculation module is used to calculate the bit error rate of the labeled data based on the target initial labeled data and the labeled data to be compared.

[0041] A fourth aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the bit error rate determination method according to any one of the first aspect embodiments, or the data recovery method according to any one of the second aspect embodiments.

[0042] A fifth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the bit error rate determination method according to any one of the first aspect embodiments, or the data recovery method according to any one of the second aspect embodiments.

[0043] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0044] The present application will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0045] Figure 1 This is a flowchart illustrating the steps of the bit error rate determination method according to an embodiment of this application.

[0046] Figure 2 This is a flowchart illustrating a step before step S110 in the bit error rate determination method of this application embodiment;

[0047] Figure 3 This is a schematic diagram of a sub-process of the data recovery method according to an embodiment of this application;

[0048] Figure 4 This is a schematic diagram of a specific process of the data recovery method according to an embodiment of this application;

[0049] Figure 5 This is a block diagram of the bit error rate determination device according to an embodiment of this application;

[0050] Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0051] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0052] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0053] In the description of this application, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0054] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0055] In the description of this application, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0056] NAND flash memory chips are widely used storage products today, possessing excellent characteristics such as high speed and non-volatility. Internally, they represent data in the form of stored electrical charges. During actual use, changes in various internal and external conditions can cause variations in the amount of stored charge. If this variation accumulates to a certain extent, accessing the flash memory using the default read operation may not retrieve the correct data. Generally, NAND flash manufacturers allow adjustments to the read voltage used to determine the cell state. By adjusting the read voltage, the data can be correctly recovered; this process is usually called data recovery (readretry) or rereading. During the use of NAND flash products, the number of electrons in the cell changes due to the influence of internal and external environmental conditions, leading to the inability to retrieve correct data using the default read voltage. Manufacturers typically provide multiple readretry methods to adjust the read voltage and recover data.

[0057] When a read operation fails, a data recovery process is executed to re-determine the read voltage of the flash memory. During this process, the flash memory chip manufacturer typically provides a reread table. This table is traversed to recover data, attempting to read it using the voltage specified in the table. The bit error rate (BER) is calculated after each read until it meets the required level. In related technologies, the BER is usually calculated by comparing all the data stored in the physical pages of the flash memory with the original data. This process is time-consuming and inefficient, resulting in a long data recovery process and very high latency in data reading.

[0058] Based on this, this application provides a bit error rate determination method, a data recovery method, an apparatus, a device, and a medium, which can quickly determine the bit error rate of flash memory with high efficiency, thereby reducing the time of the data recovery process, improving the efficiency of data recovery, and thus reducing the latency of data reading from flash memory.

[0059] The first aspect of this application provides a method for determining bit error rate. This method can be applied to a terminal or a server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, etc.; the server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application implementing the bit error rate determination method, etc., but is not limited to the above forms.

[0060] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0061] Reference Figure 1 , Figure 1 This is a flowchart illustrating the steps of a bit error rate determination method according to an embodiment of this application. The bit error rate determination method of this application is applied to flash memory. The bit error rate determination method of this application includes, but is not limited to, steps S110 to S150.

[0062] Step S110: In response to detecting that the first read operation for the flash memory failed, obtain the reread voltage and the operation address in the first read operation;

[0063] It's important to note that the operation address in the first read operation refers to the data read address, which indicates the specific location of the data to be read. The physical page of the data to be read can be determined through the operation address in the first read operation. For example, the operation address in the first read operation includes the flash memory number, physical page number, and physical block number.

[0064] It should be noted that the flash memory or flash application system is equipped with an error correction code module (ECC). When the first read operation is performed, the flash memory is read based on the operation address in the first read operation to obtain the read data. Then the error correction code module performs error correction verification on the read data. If the error correction code module determines that the read data cannot pass the error correction verification, that is, the verification fails, then the first read operation is considered to have failed.

[0065] It should be noted that the Error Correction Code (ECC) module is the core reliability engine of the NAND Flash storage system. Its function is to detect and correct bit errors caused by physical mechanisms (charge leakage, read / write interference, noise, etc.) in real time by adding redundant verification information to the data.

[0066] Step S120: Based on the pre-generated tag mapping relationship, determine the target tag address corresponding to the operation address in the first read operation; wherein, the tag mapping relationship records the correspondence between multiple operation addresses and multiple tag addresses;

[0067] In some embodiments, the tag mapping relationship records the correspondence between each physical page and a tag address. When the operation address in the first read operation is obtained, the physical page corresponding to the first read operation is determined, and then the tag address corresponding to that physical page is determined from the tag mapping relationship as the target tag address, thereby obtaining the target tag address.

[0068] Step S130: Perform a second read operation on the flash memory based on the target tag address and the reread voltage to obtain the tag data to be compared from the physical page of the flash memory;

[0069] It should be noted that the tag data is pre-stored in the tag address corresponding to the physical page. Therefore, in step S130, by performing a second read operation on the flash memory based on the target tag address and the reread voltage, the tag data to be compared can be obtained from the physical page indicated by the operation address of the first read operation.

[0070] Step S140: Based on the tag mapping relationship, determine the target initial tag data corresponding to the target tag address; wherein, the tag mapping relationship also records the correspondence between multiple initial tag data and multiple tag addresses;

[0071] Step S150: Calculate the bit error rate of the labeled data based on the initial target labeled data and the labeled data to be compared.

[0072] Specifically, the target initial labeled data is compared one by one with the labeled data to be compared, thereby obtaining the label error rate. For example, the target initial labeled data is compared one by one with the labeled data to be compared, the number of erroneous bits in the labeled data to be compared is obtained, and the number of erroneous bits is divided by the total number of bits in the target initial labeled data to obtain the label error rate.

[0073] It is worth noting that the bit error rate determination method in this embodiment, through steps S110 to S150, when a first read operation on the flash memory fails, it indicates that the data in the flash memory cannot be read normally using the default voltage of the flash memory. Therefore, the reread voltage and the operation address in the first read operation are obtained. Based on the pre-generated tag mapping relationship, the target tag address corresponding to the operation address in the first read operation is determined. Based on the target tag address and the reread voltage, a second read operation is performed on the flash memory to obtain the tag data to be compared from the physical page of the flash memory. Based on the tag mapping relationship, the target initial tag data corresponding to the target tag address is determined. Then, based on the target initial tag data and the tag data to be compared, the tag error rate of the tag data is calculated. Since the bit error rate within the physical page is uniformly distributed, the tag error rate between the target initial tag data and the tag data to be compared can be used as the bit error rate of the physical page. The tag error rate can be used to determine whether the reread voltage meets the requirements during the data recovery process, thereby assisting the data recovery process. Furthermore, the bit error rate (BER) is obtained by comparing the target initial labeled data with the labeled data to be compared. Compared with traditional techniques that calculate the BER using all the data in a physical page, the BER calculation method in this application is faster and more efficient. Reducing the decoding time of invalid error correction code modules further shortens the data recovery process, improves data recovery efficiency, and consequently reduces the latency of data reading from flash memory.

[0074] In some embodiments, refer to Figure 2 , Figure 2 This is a schematic flowchart illustrating a step before step S110 in the bit error rate determination method according to an embodiment of this application. Steps S210 to S250 may also be included before step S110.

[0075] Step S210: In response to detecting a write operation to the flash memory, obtain the operation address of the write operation;

[0076] It's important to note that write operations are used to write data to be stored into flash memory. The address of a write operation includes the flash memory number, physical page number, and physical block number. The flash memory number refers to the serial number of the flash memory chip.

[0077] Step S220: Calculate the tag address based on the operation address of the write operation;

[0078] In some embodiments, step S220 specifically includes steps S221 and S222.

[0079] Step S221: Determine the physical page to be written based on the operation address of the write operation;

[0080] Step S222: Randomly generate a marker address based on the physical page to be written; wherein the marker address is located within the physical page to be written.

[0081] For example, the physical page to which the data to be stored is written is determined by the physical block number and physical page number in the write operation address, and then a marker address is determined on that physical page. For instance, after writing the data, the remaining storage space of the physical page to which the data is written can be determined, and an address matching a preset length can be randomly selected from the remaining storage space as the marker address. It is worth noting that the preset length is less than the length of the data to be stored.

[0082] Step S230: Generate initial labeled data;

[0083] It is worth noting that the initial tag data can be a randomly generated sequence, and the length of the initial tag data is equal to the preset length. This allows for writing different tag data to each physical page, ensuring the randomness of the tag data within a physical block. In some embodiments, the preset length is 200 bits.

[0084] Step S240: Establish the mapping relationship between the initial tag data, the operation address of the write operation, and the tag address to obtain the tag mapping relationship;

[0085] In some embodiments, the correspondence between initial tag data, the operation address of the write operation, and the tag address is recorded to obtain a tag mapping relationship. In other embodiments, the correspondence between initial tag data, the physical page indicated by the operation address of the write operation, and the tag address is recorded as a tag mapping relationship. Generating a tag mapping relationship facilitates the determination of the target tag address corresponding to the operation address in the first read operation in step S120, and also facilitates the determination of the target initial tag data corresponding to the target tag address in step S140.

[0086] Step S250: Write the initial tag data to the tag address of the flash memory.

[0087] It is worth noting that, in the bit error rate determination method of this application embodiment, through steps S210 to S250, when performing a write operation, not only is the data to be stored written to the physical page of the flash memory, but initial tag data is also written to the physical page, and a mapping relationship is established between the initial tag data, the operation address of the write operation and the tag address to obtain the tag mapping relationship, so that when the data recovery process needs to be performed, the bit error rate of the physical page can be quickly evaluated based on the initial tag data.

[0088] In some embodiments, step S220 specifically includes:

[0089] The offset address is calculated based on the address calculation formula. The marker address is then obtained based on the write operation address and the offset address. The address calculation formula is:

[0090] L=(chip_no*pages_per_chip+block_no*pages_per_block+page_no)*Large_prime%page_length;

[0091] Where L is the offset address, chip_no is the flash memory number in the write operation address, pages_per_chip is the total number of physical pages in the flash memory, block_no is the physical block number in the write operation address, pages_per_block is the total number of physical pages in the physical block, page_no is the physical page number in the write operation address, Large_prime is the preset prime number, and page_length is the length of the physical page.

[0092] It is worth noting that the offset address is calculated using the address calculation formula, and then the tag address is obtained based on the write operation address and the offset address. For example, the write operation address and the offset address are added together to obtain the tag address. This ensures that the tag address corresponding to each physical page is unique, preventing data distribution within physical blocks from failing to meet randomization requirements. In other embodiments, the same purpose can be achieved by writing different tag data to each physical page. Alternatively, a similar purpose can be achieved by splitting the tag data into smaller sequences and writing them to different offset addresses within the physical page.

[0093] It should be noted that the length of the marked data is shorter than the length of the corresponding data to be stored. Due to the characteristics of flash memory, the bit error rate within a page is basically uniformly distributed, so the bit error rate of the entire physical page can be evaluated by checking the bit error rate of the marked data.

[0094] In some embodiments, obtaining the reread voltage in step S110 may include steps S111 and S112.

[0095] Step S111: Obtain the read voltage of the first read operation;

[0096] Step S112: Obtain the reread voltage from a preset reread voltage table based on the read voltage, wherein the reread voltage is greater than or less than the read voltage of the first read operation.

[0097] It is worth noting that each flash memory chip has a pre-set reread voltage table. The read voltage for the first read operation is generally the default read voltage of the flash memory chip. If the first read operation fails, it means that the read voltage of the first read operation cannot read data, so it is necessary to change the read voltage by obtaining the reread voltage from the pre-set reread voltage table. The reread voltage is not the same as the read voltage. It should be noted that the reread voltage table records multiple voltages. The reread voltage table may be pre-set by the flash memory chip manufacturer or pre-set by someone skilled in the art based on the actual situation.

[0098] A second aspect of this application provides a data recovery method. The data recovery method is applied to flash memory and includes the bit error rate determination method of the first aspect embodiment. (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of a sub-process of the data recovery method according to an embodiment of this application. Figure 3 The illustrated process includes steps S310 to S330.

[0099] Step S310: Detect the bit error rate of the marker;

[0100] Step S320: If the bit error rate of the marker is detected to be less than the preset bit error threshold, the reread voltage is used as the target read voltage of the flash memory, and the first read operation is re-executed on the flash memory based on the target read voltage to obtain the first target recovery data;

[0101] It should be noted that the preset error threshold can be set by the error correction code module. If the marking error rate is less than the preset error threshold, the error correction code module can correct the data. When the marking error rate is greater than or equal to the preset error threshold, the error correction code module cannot correct the data.

[0102] Step S330: Correct the first target recovery data using the error correction code module to obtain the second target recovery data.

[0103] In some embodiments, refer to Figure 4 , Figure 4 This is a schematic diagram of a specific process of the data recovery method according to an embodiment of this application. Figure 4The illustrated process includes steps S110 to S150, and also steps S310 to S330. Specifically, steps S110 to S150 first calculate the bit error rate (BER), and then steps S310 to S330 obtain the second target recovery data, thereby realizing the data recovery process. In this process, the BER is obtained by comparing the target initial BER with the BER to be compared. Compared with traditional techniques that calculate the BER using all data in a physical page, the BER calculation speed of this application is faster and more efficient, thus reducing the time required for the data recovery process and improving the efficiency of data recovery.

[0104] In some embodiments, after detecting the bit error rate of the marker in step S310, the method further includes:

[0105] If the bit error rate of the marker is detected to be greater than or equal to the preset bit error threshold, the reread voltage is updated and the process jumps to step S130, where a second read operation is performed on the flash memory based on the marker address and the reread voltage to obtain the marker data to be compared from the physical page of the flash memory.

[0106] Specifically, if the bit error rate (BER) is greater than or equal to a preset BER threshold, it indicates that the current reread voltage does not meet the requirements, and therefore the reread voltage needs to be updated. For example, a new voltage is selected from the reread voltage table as the new reread voltage, and the process jumps to step S130. This process is repeated for each reread voltage table, selecting a new voltage each time, until the BER is less than the preset BER threshold. When every voltage in the reread voltage table has been selected and the BER is still greater than or equal to the preset BER threshold, an error alarm is generated and sent to the relevant terminal.

[0107] It should be noted that since the data recovery method of the second aspect embodiment includes the bit error rate determination method of the first aspect embodiment, the specific implementation method and beneficial effects of the bit error rate determination method of the first aspect embodiment are applicable to the data recovery method of the second aspect embodiment.

[0108] A third aspect of this application provides a bit error rate determination apparatus, which is applied to flash memory. (Refer to...) Figure 5 , Figure 5 This is a block diagram of a bit error rate determination device according to an embodiment of this application. The bit error rate determination device includes:

[0109] The first acquisition module 510 is used to acquire the reread voltage and the operation address in the first read operation in response to detecting that the first read operation for the flash memory has failed.

[0110] The first determining module 520 is used to determine the target tag address corresponding to the operation address in the first read operation based on a pre-generated tag mapping relationship; wherein, the tag mapping relationship records the correspondence between multiple operation addresses and multiple tag addresses;

[0111] The second acquisition module 530 is used to perform a second read operation on the flash memory based on the target tag address and the reread voltage, so as to obtain the tag data to be compared from the physical page of the flash memory;

[0112] The second determining module 540 is used to determine the target initial tag data corresponding to the target tag address based on the tag mapping relationship; wherein, the tag mapping relationship also records the correspondence between multiple initial tag data and multiple tag addresses;

[0113] The calculation module 550 is used to calculate the bit error rate of the target initial labeled data and the labeled data to be compared.

[0114] The bit error rate determination apparatus of the third aspect embodiment of this application is used to execute the bit error rate determination method of the first aspect embodiment. When executing the method, if a first read operation against the flash memory fails, it indicates that the data in the flash memory cannot be read normally using the flash memory's default voltage. Therefore, the reread voltage and the operation address in the first read operation are obtained. Based on a pre-generated tag mapping relationship, a target tag address corresponding to the operation address in the first read operation is determined. A second read operation is performed on the flash memory based on the target tag address and the reread voltage to obtain the tag data to be compared from the physical pages of the flash memory. Based on the tag mapping relationship, target initial tag data corresponding to the target tag address is determined. Then, based on the target initial tag data and the tag data to be compared, the tag error rate of the tag data is calculated. Since the bit error rate within a physical page is uniformly distributed, the tag error rate between the target initial tag data and the tag data to be compared can be used as the bit error rate of the physical page. The tag error rate can be used during data recovery to determine whether the reread voltage meets the requirements, thereby assisting the data recovery process. Furthermore, the bit error rate is obtained by comparing the target initial labeled data with the labeled data to be compared. Compared with the traditional technology that calculates the bit error rate using all the data in the physical page, the bit error rate calculation speed of this application is faster and more efficient, thereby reducing the time of the data recovery process and improving the efficiency of data recovery.

[0115] It should be noted that the specific implementation of the bit error rate determination device is basically the same as the specific implementation of the bit error rate determination method in the above embodiments, and will not be repeated here. Under the premise of meeting the requirements of the embodiments of this application, the bit error rate determination device may also be provided with other functional modules to realize the bit error rate determination method in the above embodiments.

[0116] A fourth aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the bit error rate determination method of the above embodiments. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0117] In one embodiment, reference is made to Figure 6 , Figure 6 The hardware structure of an electronic device according to an embodiment of this application is illustrated. The electronic device includes:

[0118] The processor 601 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0119] The memory 602 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 602 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 602 and is invoked by the processor 601 to execute the bit error rate determination method of the first aspect embodiment of this application or the data recovery method of the second aspect embodiment of this application.

[0120] The input / output interface 603 is used to implement information input and output;

[0121] The communication interface 604 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0122] Bus 605 transmits information between various components of the device (e.g., processor 601, memory 602, input / output interface 603, and communication interface 604);

[0123] The processor 601, memory 602, input / output interface 603, and communication interface 604 are connected to each other within the device via bus 605.

[0124] According to a fifth aspect of this application, a computer-readable storage medium stores a computer program that, when executed by a processor, implements the bit error rate determination method of the first aspect embodiment or the data recovery method of the second aspect embodiment.

[0125] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0126] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0127] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0128] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0129] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0130] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0131] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0132] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0133] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0134] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0135] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0136] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for determining bit error rate, characterized in that, Applied to flash memory, the method includes: In response to the detection that the first read operation for the flash memory has failed, the reread voltage and the operation address in the first read operation are obtained; Based on a pre-generated tag mapping relationship, a target tag address corresponding to the operation address in the first read operation is determined; wherein, the tag mapping relationship records the correspondence between multiple operation addresses and multiple tag addresses; A second read operation is performed on the flash memory based on the target tag address and the reread voltage to obtain the tag data to be compared from the physical page of the flash memory; Based on the tag mapping relationship, target initial tag data corresponding to the target tag address is determined; wherein, the tag mapping relationship also records the correspondence between multiple initial tag data and multiple tag addresses; Based on the target initial labeled data and the labeled data to be compared, the labeling error rate of the labeled data is calculated; Before obtaining the reread voltage and the operation address in the first read operation in response to detecting a failure of the first read operation on the flash memory, the method further includes: In response to detecting a write operation to the flash memory, the operation address of the write operation is obtained; The marker address is calculated based on the operation address of the write operation; Generate the initial tag data; Establish a mapping relationship between the initial tag data, the operation address of the write operation, and the tag address to obtain the tag mapping relationship; The initial tag data is written to the tag address of the flash memory.

2. The bit error rate determination method according to claim 1, characterized in that, The calculation of the marker address based on the operation address of the write operation includes: The offset address is calculated based on the address calculation formula. The marker address is then obtained based on the operation address of the write operation and the offset address. The address calculation formula is: L=(chip_no*pages_per_chip+block_no*pages_per_block+page_no)*Large_prime%page_length; Where L is the offset address, chip_no is the flash memory number, pages_per_chip is the total number of physical pages in the flash memory, block_no is the physical block number in the write operation address, pages_per_block is the total number of physical pages in the physical block, page_no is the physical page number in the write operation address, Large_prime is a preset prime number, and page_length is the length of the physical page.

3. The bit error rate determination method according to claim 1, characterized in that, The acquisition of the reread voltage includes: Obtain the read voltage of the first read operation; The reread voltage is obtained from a preset reread voltage table based on the read voltage, wherein the reread voltage is greater than or less than the read voltage of the first read operation.

4. The bit error rate determination method according to claim 1, characterized in that, The calculation of the marker address based on the operation address of the write operation includes: The physical page to be written is determined based on the operation address of the write operation; The marked address is randomly generated based on the physical page to be written; wherein the marked address is located within the physical page to be written.

5. A data recovery method, characterized in that, Applied to flash memory, the method includes the bit error rate determination method as described in any one of claims 1 to 4; Also includes: Detect the bit error rate of the marker; If the bit error rate of the marker is detected to be less than a preset bit error threshold, the reread voltage is used as the target read voltage of the flash memory, and the first read operation is re-executed on the flash memory based on the target read voltage to obtain the first target recovery data; The error correction code module corrects the first target recovery data to obtain the second target recovery data.

6. The data recovery method according to claim 5, characterized in that, After detecting the bit error rate of the marker, the method further includes: If the bit error rate of the marker is detected to be greater than or equal to the preset bit error threshold, the reread voltage is updated, and the process jumps to perform a second read operation on the flash memory based on the marker address and the reread voltage to obtain the marker data to be compared from the physical page of the flash memory.

7. A bit error rate determination device, characterized in that, Applied to flash memory, the device includes: The first acquisition module is configured to acquire the reread voltage and the operation address in the first read operation in response to detecting that the first read operation for the flash memory has failed. The first determining module is used to determine the target tag address corresponding to the operation address in the first read operation based on a pre-generated tag mapping relationship; wherein the tag mapping relationship records the correspondence between multiple operation addresses and multiple tag addresses; The second acquisition module is used to perform a second read operation on the flash memory based on the target tag address and the reread voltage, so as to obtain the tag data to be compared from the physical page of the flash memory; The second determining module is used to determine the target initial tag data corresponding to the target tag address based on the tag mapping relationship; wherein, the tag mapping relationship also records the correspondence between multiple initial tag data and multiple tag addresses; The calculation module is used to calculate the bit error rate of the labeled data based on the target initial labeled data and the labeled data to be compared; Before obtaining the reread voltage and the operation address in the first read operation in response to detecting a failure of the first read operation on the flash memory, the method further includes: In response to detecting a write operation to the flash memory, the operation address of the write operation is obtained; The marker address is calculated based on the operation address of the write operation; Generate the initial tag data; Establish a mapping relationship between the initial tag data, the operation address of the write operation, and the tag address to obtain the tag mapping relationship; The initial tag data is written to the tag address of the flash memory.

8. An electronic device, characterized in that, The electronic device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the bit error rate determination method according to any one of claims 1 to 4, or the data recovery method according to any one of claims 5 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the bit error rate determination method according to any one of claims 1 to 4, or the data recovery method according to any one of claims 5 to 6.

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