Prefetcher control method, apparatus, and processor

Abstract

The embodiment of the application provides a prefetcher control method, device and processor, relates to the technical field of data storage, and the method comprises the following steps: firstly, monitoring the memory access address predicted by a first prefetcher and the memory access address predicted by a second prefetcher; the preset priority of the first prefetcher is lower than the preset priority of the second prefetcher; then, updating the redundancy index associated with the first prefetcher according to the monitoring result; finally, controlling the function state of the first prefetcher based on the redundancy index associated with the first prefetcher. Through the technical scheme, the redundancy rate between different prefetchers can be reduced, and the control mode of the first prefetcher is determined through the redundancy index, so that the robustness of the whole scheme can be improved.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a prefetcher control method, apparatus and processor. Background Technology

[0002] A prefetcher is a hardware or software mechanism in computer architecture that can perform prefetch training by monitoring memory access patterns to achieve data prefetching. That is, it predicts the data that the program may access in the future and loads it into the internal cache in advance, thereby reducing the performance latency caused by the processor waiting for data.

[0003] To efficiently predict and preload potentially accessed data, processors deploy multiple prefetchers simultaneously for different data access patterns. However, when different prefetchers repeatedly request the same address, it can lead to resource conflicts and reduced efficiency.

[0004] Specifically, in practical applications, different programs have diverse data access patterns, including, for example, the fixed-step pattern and the streaming pattern. The fixed-step pattern can be, for example, accessing data at fixed intervals (A[0], A[2], A[4]...). The streaming pattern can be, for example, accessing data sequentially (A[0], A[1], A[2]...). Since a single prefetcher cannot cover all scenarios, the processor, in order to efficiently predict and preload data that may be accessed in the future, will deploy multiple prefetchers simultaneously for different data access patterns.

[0005] However, when different prefetchers repeatedly initiate prefetch requests for the same address, it can lead to resource conflicts and efficiency degradation. Specifically, assuming that different prefetchers predict the same memory access address based on different data access patterns, then different prefetchers will initiate prefetch requests for the same memory access address. In this case, the same data at the same address will be prefetched multiple times. On the one hand, repeated operations increase power consumption; on the other hand, too many prefetch requests may block normal memory access, causing performance degradation and excessive occupation of the cache interface. Summary of the Invention

[0006] In view of this, embodiments of this application provide a prefetcher control method, apparatus, and processor to at least partially solve the above-mentioned problems.

[0007] According to a first aspect of the embodiments of this application, a prefetcher control method is provided, comprising: monitoring memory access addresses predicted by a first prefetcher and memory access addresses predicted by a second prefetcher; wherein the preset priority of the first prefetcher is lower than the preset priority of the second prefetcher; updating a redundancy index associated with the first prefetcher based on the monitoring results; and controlling the functional state of the first prefetcher based on the redundancy index associated with the first prefetcher.

[0008] According to a second aspect of the embodiments of this application, a prefetcher control device is provided, comprising: a monitoring module for monitoring memory access addresses predicted by a first prefetcher and memory access addresses predicted by a second prefetcher; wherein the preset priority of the first prefetcher is lower than the preset priority of the second prefetcher; an update module for updating a redundancy index associated with the first prefetcher based on the monitoring results; and an execution module for controlling the functional state of the first prefetcher based on the redundancy index associated with the first prefetcher.

[0009] According to a third aspect of the embodiments of this application, a prefetching device is provided, including: a first prefetcher, a second prefetcher, and a prefetcher control device as described in the second aspect.

[0010] According to a fourth aspect of the embodiments of this application, a processor is provided, including the prefetching device as described in the third aspect.

[0011] In the above technical solution, the redundancy index of the lower-priority prefetcher can be updated by monitoring the memory access addresses predicted by prefetchers of different priorities, and the control method for the lower-priority prefetcher can be determined based on the redundancy index. Through the technical solution of this application embodiment, the redundancy rate between different prefetchers can be reduced. Furthermore, the redundancy index set for the low-priority prefetcher in this application embodiment can describe the accumulation of multiple prefetch address prediction results. By indicating the control method for the first prefetcher through this redundancy index, the overall robustness of the solution can be improved. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0013] Figure 1 This is a schematic diagram of a prefetcher structure;

[0014] Figure 2 A schematic flowchart of a prefetcher control method provided in an embodiment of this application;

[0015] Figure 3 Another flowchart illustrating the prefetcher control method provided in this application embodiment;

[0016] Figure 4 A schematic diagram of the pre-fetcher control device provided in the embodiments of this application;

[0017] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0019] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0020] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0021] It should also be noted that the terms "first, second, and third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, and third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0022] Furthermore, in the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0023] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies of the embodiments of this application are described below. The following relevant technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and they all fall within the protection scope of the embodiments of this application.

[0024] To facilitate understanding, the above technical issues will be further explained below with reference to the accompanying drawings.

[0025] Figure 1 A schematic diagram of a prefetcher structure is given, such as... Figure 1 As shown, a prefetcher may include, for example, a fixed-stride prefetcher and a streaming prefetcher.

[0026] The fixed-stride prefetcher can include multiple stride streams, which are memory access sequences with a fixed stride. Each stride stream corresponds to a program counter (PC). For a stride stream of the same PC, the difference between the addresses of two adjacent accesses can be calculated, and this difference is used as the prefetch stride for the stride stream corresponding to that PC. Based on this prefetch stride, the prefetch address is generated. For example, the prefetch address = current address + n × stride, where n represents the prefetch depth. For instance, when n = 1, it means prefetching the next data item; when n = 2, it means prefetching the next two data items. Each PC independently maintains its own stride and address state to avoid interference between access patterns of different instructions.

[0027] Streaming sequential prefetchers are based on consecutive address access patterns. They typically perform streaming checks by address region. A streaming sequential prefetch is triggered when the address of each cache line or multiple consecutive cache lines within the same address region is accessed. The prefetch address for a streaming sequential prefetch can be calculated, for example, by adding N to the current address. N can be a non-zero positive integer.

[0028] Based on the prefetcher structure described above, the compiler uses loop unrolling to improve execution efficiency, allowing multiple program counters (PCs) of the fixed-step prefetcher to each activate a stride stream and access contiguous addresses in parallel. Simultaneously, streaming contiguous prefetchers also trigger streaming prefetching. This can lead to multiple prefetchers simultaneously triggering prefetching of the same address, resulting in wasted power and performance degradation.

[0029] This application is submitted to address the aforementioned issues.

[0030] Figure 2This is a schematic flowchart of a prefetcher control method provided in an embodiment of this application. (Reference) Figure 2 The flow of the prefetcher control method provided in this application embodiment may include:

[0031] Step 101: Monitor the memory access address predicted by the first prefetcher and the memory access address predicted by the second prefetcher.

[0032] In this embodiment of the application, priorities can be pre-set for each different prefetcher based on specific setting principles.

[0033] In one possible implementation, different priorities can be set for each prefetcher based on its prefetching training difficulty. For example, prefetchers with high prefetching training difficulty can be given higher priorities, while those with low prefetching training difficulty can be given lower priorities. For instance, if the prefetching training difficulty of a fixed-step prefetcher is lower than that of a streaming continuous prefetcher, then the priority of the fixed-step prefetcher can be set lower than that of the streaming continuous prefetcher.

[0034] In another possible implementation, different priorities can be set for each prefetcher based on their prefetch training accuracy. For example, a higher priority can be set for prefetchers with high prefetch training accuracy, and a lower priority can be set for prefetchers with low prefetch training accuracy.

[0035] In another possible implementation, different priorities can be randomly assigned to different prefetchers.

[0036] Based on the above priority settings, in this embodiment of the application, the memory access addresses predicted by the high-priority prefetcher and the low-priority prefetcher can be monitored simultaneously, and the state control of the low-priority prefetcher can be performed based on their respective memory access addresses.

[0037] For ease of understanding and description, the implementation flow of the prefetcher control method provided in this application embodiment is described below using a first prefetcher and a second prefetcher as examples. The preset priority of the first prefetcher is lower than that of the second prefetcher. This application embodiment does not limit the specific types of the first and second prefetchers. As an example, the first prefetcher may include any one or more fixed-step prefetchers, and the second prefetcher may include any one or more streaming continuous prefetchers.

[0038] Step 102: Update the redundancy index associated with the first prefetcher based on the monitoring results.

[0039] In this embodiment of the application, the first prefetcher (i.e. the low-priority prefetcher) may be associated with a redundancy index. The redundancy index can be used to characterize the redundancy of the first prefetcher. The higher the redundancy index, the higher the redundancy of the first prefetcher, and the more it should be turned off so that it stops initiating data prefetching.

[0040] The redundancy index associated with the first prefetcher can be updated based on the monitoring results of the memory access addresses predicted by the first prefetcher and the memory access addresses predicted by the second prefetcher.

[0041] Specifically, if, based on the monitoring results above, it is determined that the memory access address predicted by the first prefetcher is also predicted by the second prefetcher, it indicates that the first and second prefetchers predicted the same memory access address, and the first prefetcher has performed redundant prediction. In this case, the redundancy index associated with the first prefetcher can be increased. If it is determined that the memory access address predicted by the first prefetcher is not predicted by the second prefetcher, it indicates that the first and second prefetchers predicted different memory access addresses, and the first prefetcher has not performed redundant prediction. In this case, the redundancy index associated with the first prefetcher can be decreased.

[0042] In one possible implementation, the second prefetcher obtains the memory access address predicted by the first prefetcher. Then, the second prefetcher compares the memory access address predicted by the first prefetcher with its own predicted memory access address. If they match, it means the memory access address predicted by the first prefetcher has been predicted by the second prefetcher, and the second prefetcher can control the increase of the redundancy index associated with the first prefetcher. If they do not match, it means the memory access address predicted by the first prefetcher has not been predicted by the second prefetcher, and the second prefetcher can control the decrease of the redundancy index associated with the first prefetcher.

[0043] Step 103: Based on the redundancy index associated with the first prefetcher, control the prefetch request sending function of the first prefetcher.

[0044] Based on the update principle of the redundancy index associated with the first prefetcher in step 102 above, when the redundancy index associated with the first prefetcher exceeds the first threshold, the first prefetcher can be controlled to stop sending prefetch requests. In this way, on the one hand, the first prefetcher can continue to perform prefetch training, including continuing to monitor the program's memory access patterns (such as address sequences, step sizes, PC correlations, etc.), updating its internal state (such as step size calculation, flow detection), and generating predicted prefetch addresses. On the other hand, the first prefetcher will not initiate prefetch requests based on the generated prefetch addresses. Based on this implementation, redundant prefetch conflicts can be prevented, and the prefetch training process of the first prefetcher can be unaffected. Therefore, when the first prefetcher resumes its prefetch requests, relatively accurate address prediction can still be achieved without relearning the address memory access patterns.

[0045] Accordingly, when the redundancy index associated with the first prefetcher falls below the second threshold, the first prefetcher can be controlled to send prefetch requests normally. In this embodiment, the redundancy index associated with the first prefetcher falling below the second threshold can mean that it is always below the second threshold. That is, after the execution of this method flow begins, the redundancy index associated with the first prefetcher never exceeds the first threshold, and the function of the first prefetcher sending prefetch requests is never disabled. In this case, it is sufficient to keep the function of the first prefetcher initiating prefetcher requests enabled. The redundancy index associated with the first prefetcher falling below the second threshold can also mean that after it exceeds the first threshold, it returns to falling below the second threshold. That is, after the execution of this method flow begins, the redundancy index associated with the first prefetcher has exceeded the first threshold, and the function of the first prefetcher sending prefetch requests has been disabled. In this case, the first prefetcher can be controlled to resume sending prefetch requests.

[0046] Regarding the scenario described above where the first prefetcher resumes sending prefetch requests, specifically, after the first prefetcher's prefetch requests are controlled to stop sending, since the first prefetcher is still performing prefetch training and generating prefetch addresses, the redundancy index associated with the first prefetcher can continue to be updated based on the method described above. When the redundancy index associated with the first prefetcher falls below the second threshold, the first prefetcher can be controlled to resume sending prefetch requests.

[0047] The actual values ​​of the first threshold and the second threshold can be flexibly set according to requirements. The first threshold can be equal to the second threshold, or the first threshold can be greater than the second threshold; this embodiment does not impose any restrictions on this.

[0048] In this embodiment, the redundancy index can be recorded using a counter. The redundancy index associated with the first prefetcher can have an initial value. The initial value of the redundancy index of the first prefetcher, the first threshold, and the second threshold can be set according to the number of bits in the counter. For example, assuming the counter used has 4 bits, the maximum redundancy index that can be recorded is 15. Based on this, for example, the initial value of the redundancy index can be set to 1, and the first threshold and the second threshold can be equal, both set to 6. Based on the monitoring results obtained in step 101 above, the redundancy index associated with the first prefetcher can be updated on the basis of this initial value. Each update can be an increase or decrease of a set gradient value, which can be, for example, 1. For example, when it is detected that the memory access address predicted by the first prefetcher is also predicted by the second prefetcher, the redundancy index can be increased by 1; when it is detected that the memory access address predicted by the first prefetcher is not predicted by the second prefetcher, the redundancy index can be decreased by 1. Therefore, when the redundancy index associated with the first prefetcher is detected to be higher than 6, the first prefetcher can be controlled to stop sending prefetch requests. When the redundancy index associated with the first prefetcher is detected to be lower than 6 again, the first prefetcher can be controlled to resume sending prefetch requests. It should be understood that the above numerical descriptions are only examples and should not be construed as limiting the embodiments of this application. In other implementations, counters with different bit lengths can be used, and different initial values ​​of the redundancy index, the first threshold, and the second threshold can be selected.

[0049] In one possible implementation, a second prefetcher can monitor changes in the redundancy index associated with the first prefetcher. If the redundancy index is determined to be greater than the first threshold, the second prefetcher can control the first prefetcher to stop sending prefetch requests. If the redundancy index is determined to be less than the second threshold, the second prefetcher can control the first prefetcher to send prefetch requests.

[0050] Alternatively, the aforementioned update operation of the redundancy index of the first prefetcher and the control operation of whether the first prefetcher sends a prefetch request can be performed by the first prefetcher itself, or by the processor. This application embodiment does not limit this.

[0051] By employing the above technical solution, when the redundancy index of a low-priority prefetcher exceeds a threshold, the low-priority prefetcher can be controlled to stop sending prefetch requests. This reduces the redundancy rate between different prefetchers and prevents it from affecting the subsequent prefetch training accuracy of the low-priority prefetcher. Furthermore, the redundancy index set for the low-priority prefetcher in this embodiment describes the accumulation of multiple prefetch address prediction results. By using this redundancy index to indicate the control method for the first prefetcher, the overall robustness of the solution can be improved.

[0052] Figure 3 This is another schematic flowchart illustrating the prefetcher control method provided in an embodiment of this application. (See reference...) Figure 3 The flow of the prefetcher control method provided in this application embodiment may include:

[0053] Step 201: Monitor the memory access address predicted by the first prefetcher and the memory access address predicted by the second prefetcher.

[0054] Step 202: Update the redundancy index associated with the first prefetcher based on the monitoring results.

[0055] Step 203: Control the prefetch training function of the first prefetcher based on the redundancy index associated with the first prefetcher.

[0056] Unlike the previous embodiments, in this embodiment, the prefetching training function of the low-priority prefetcher can be controlled based on the redundancy index of the low-priority prefetcher.

[0057] Specifically, if the redundancy index associated with the first prefetcher is lower than the second threshold, the first prefetcher can be controlled to perform prefetch training normally. If the redundancy index associated with the first prefetcher is higher than the first threshold, the first prefetcher can be controlled to stop prefetch training. In this way, when the redundancy index of the first prefetcher exceeds the set threshold, the first prefetcher can stop monitoring or analyzing the program's memory access mode, stop generating any prefetch addresses, and stop initiating prefetch requests.

[0058] The implementation method of this application embodiment can avoid the prefetch training overhead of the first prefetcher when the first prefetcher is redundant.

[0059] In the implementation of this application embodiment, when the first prefetcher stops prefetch training, the prefetch training of the first prefetcher can also be resumed.

[0060] For example, after controlling the first prefetcher to stop prefetching training, the duration of the stoppage can be timed. If it is determined that the duration of the stoppage exceeds a set threshold, the first prefetcher can be controlled to resume prefetching training. Alternatively, after controlling the first prefetcher to stop prefetching training, a user-sent instruction can be received, and based on the instruction, it can be determined whether to resume prefetching training.

[0061] Similar to the aforementioned embodiments, in this embodiment, the second prefetcher can also monitor the changes in the redundancy index associated with the first prefetcher. The second prefetcher can control the first prefetcher to stop prefetching training after detecting that the redundancy index is higher than a first threshold, and the second prefetcher can control the first prefetcher to perform prefetching training normally after detecting that the redundancy index is lower than a second threshold.

[0062] The above implementation scheme can also prevent different prefetchers from prefetching data to the same address. Furthermore, by controlling the prefetch training of redundant prefetchers to stop, the scheme can avoid the prefetch training overhead of redundant prefetchers.

[0063] In another embodiment of this application, a target cache region can be pre-set, which can be used to cache memory access addresses predicted by each prefetcher. Then, when any prefetcher predicts a target memory access address, it can be compared with each memory access address already cached in the target cache region. If the target memory access address already exists among the memory access addresses cached in the target cache region, it means that another prefetcher has already initiated a prefetch request for that target memory access address. Therefore, to prevent redundant prefetching, this prefetcher can be controlled not to send a prefetch request. If the target memory access address does not exist among the memory access addresses cached in the target cache region, it means that no other prefetcher has initiated a prefetch request for that target memory access address. Therefore, this prefetcher can be controlled to send a prefetch request.

[0064] The above implementation scheme can also prevent multiple prefetchers from initiating prefetch requests for the same memory access address. Furthermore, the above implementation scheme can make targeted judgments on the memory access address predicted by each prefetcher each time, and can achieve precise control over each prefetch request of each prefetcher.

[0065] Figure 4 A schematic diagram of a pre-fetcher control device provided in an embodiment of this application. (Reference) Figure 4 The prefetcher control device provided in this application embodiment may include: a monitoring module 401, an update module 402, and an execution module 403.

[0066] The monitoring module 401 is used to monitor the memory access address predicted by the first prefetcher and the memory access address predicted by the second prefetcher; the preset priority of the first prefetcher is lower than the preset priority of the second prefetcher.

[0067] The update module 402 is used to update the redundancy index associated with the first prefetcher based on the monitoring results.

[0068] The execution module 403 is used to control the functional state of the first prefetcher based on the redundancy index associated with the first prefetcher.

[0069] In one specific implementation, the update module 402 is specifically used to increase the redundancy index of the first prefetcher when the memory access address predicted by the first prefetcher is also predicted by the second prefetcher; and to decrease the redundancy index of the first prefetcher when the memory access address predicted by the first prefetcher is not predicted by the second prefetcher.

[0070] In one specific implementation, the execution module 403 is specifically used to control the prefetch request sending function of the first prefetcher based on the redundancy index associated with the first prefetcher.

[0071] In one specific implementation, the execution module 403 is specifically used to control the first prefetcher to stop sending prefetch requests when the redundancy index associated with the first prefetcher is higher than a first threshold; and to control the first prefetcher to send prefetch requests normally when the redundancy index associated with the first prefetcher is lower than a second threshold.

[0072] In one specific implementation, the execution module 403 is specifically used to control the prefetch training function of the first prefetcher based on the redundancy index associated with the first prefetcher.

[0073] In one specific implementation, the execution module 403 is specifically used to control the first prefetcher to stop performing prefetch training when the redundancy index associated with the first prefetcher is higher than a first threshold; and to control the first prefetcher to perform prefetch training normally when the redundancy index associated with the first prefetcher is lower than a second threshold.

[0074] In one specific implementation, the execution module 403 is further configured to pre-set the priority of different prefetchers according to the prefetch training difficulty of different prefetchers.

[0075] In the above technical solution, the redundancy index of the lower-priority prefetcher can be updated by monitoring the memory access addresses predicted by prefetchers of different priorities, and the control method for the lower-priority prefetcher can be determined based on the redundancy index. Through the technical solution of this application embodiment, the redundancy rate between different prefetchers can be reduced. Furthermore, the redundancy index set for the low-priority prefetcher in this application embodiment can describe the accumulation of multiple prefetch address prediction results. By indicating the control method for the first prefetcher through this redundancy index, the overall robustness of the solution can be improved.

[0076] In another embodiment of this application, a prefetching device may be provided, which may include a first prefetcher, a second prefetcher, and a prefetcher control device, wherein the prefetcher control device can be used to control the first prefetcher and the second prefetcher. Specific functional implementations can be found in the descriptions of the foregoing method embodiments, and will not be repeated here.

[0077] In another embodiment of this application, a processor may be provided, which may include the prefetching device described above. The processor may be configured in any electronic device so that the electronic device can implement the prefetcher control method provided in this application.

[0078] Figure 5A schematic diagram of an electronic device according to an embodiment of this application is shown. The electronic device can be used to execute the prefetcher control method provided in the embodiment of this application. The specific implementation of the electronic device is not limited by the specific embodiments of this application.

[0079] like Figure 5 As shown, the electronic device may include: a processor 502, a communications interface 504, a memory 506, and a communications bus 508.

[0080] The processor 502, communication interface 504, and memory 506 communicate with each other via communication bus 508. Communication interface 504 is used to communicate with other electronic devices or servers. The processor 502 may include a prefetching device, which can be used to execute program 510, specifically performing the relevant steps in the above-described prefetcher control method embodiment.

[0081] Specifically, program 510 may include program code that includes computer operation instructions.

[0082] Processor 502 may be a CPU, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The smart device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0083] Memory 506 is used to store program 510. Memory 506 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0084] Specifically, program 510 can be used to cause processor 502 to perform the following operations: In an optional implementation, program 510 is further used to cause processor 502 to perform the following operations. The specific implementation of each step in program 510 can be found in the corresponding steps and system descriptions in the above-described prefetcher control method embodiments, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0085] This application also provides a computer program product, including computer instructions that instruct a computing device to perform an operation corresponding to any of the prefetcher control methods in the above-described plurality of method embodiments. It should be noted that, depending on implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0086] This application also provides a computer-readable storage medium in which the methods described in this application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as ASIC or FPGA) for such software processing. It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the prefetcher control method described herein. Furthermore, when a general-purpose computer accesses code for implementing the prefetcher control method shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the prefetcher control method shown herein.

[0087] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0088] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0089] Furthermore, it should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Moreover, the collection, use and processing of related data must comply with relevant laws, regulations and standards, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0090] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0091] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0092] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0093] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0094] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A prefetcher control method, characterized in that, include: The memory access addresses predicted by the first prefetcher and the memory access addresses predicted by the second prefetcher are monitored. The preset priority of the first prefetcher is lower than the preset priority of the second prefetcher; Based on the consistency between the memory access addresses predicted by the first prefetcher and the memory access addresses predicted by the second prefetcher, the redundancy index associated with the first prefetcher is updated; the redundancy index is used to characterize the redundancy of the first prefetcher. The functional state of the first prefetcher is controlled based on the redundancy index associated with it.

2. The method according to claim 1, characterized in that, The step of updating the redundancy index associated with the first prefetcher based on the consistency between the memory access addresses predicted by the first prefetcher and the memory access addresses predicted by the second prefetcher includes: If the memory access address predicted by the first prefetcher is also predicted by the second prefetcher, increase the redundancy index of the first prefetcher. If the memory access address predicted by the first prefetcher is not predicted by the second prefetcher, the redundancy index of the first prefetcher is reduced.

3. The method according to claim 1, characterized in that, The control of the functional state of the first prefetcher based on the redundancy index associated with the first prefetcher includes: Based on the redundancy index associated with the first prefetcher, the prefetch request sending function of the first prefetcher is controlled.

4. The method according to claim 1, characterized in that, The control of the functional state of the first prefetcher based on the redundancy index associated with the first prefetcher includes: If the redundancy index associated with the first prefetcher is higher than a first threshold, control the first prefetcher to stop sending prefetch requests; If the redundancy index associated with the first prefetcher is lower than the second threshold, the first prefetcher is controlled to send prefetch requests normally.

5. The method according to claim 1, characterized in that, The control of the functional state of the first prefetcher based on the redundancy index associated with the first prefetcher includes: The prefetching training function of the first prefetcher is controlled based on the redundancy index associated with the first prefetcher.

6. The method according to claim 5, characterized in that, The control of the prefetch training function of the first prefetcher based on the redundancy index associated with the first prefetcher includes: If the redundancy index associated with the first prefetcher is higher than a first threshold, control the first prefetcher to stop performing prefetch training; If the redundancy index associated with the first prefetcher is lower than the second threshold, the first prefetcher is controlled to perform prefetch training normally.

7. The method according to claim 1, characterized in that, The method further includes: Based on the prefetching training difficulty of different prefetchers, the priorities of different prefetchers are pre-set.

8. A pre-fetcher control device, characterized in that, include: The monitoring module is used to monitor the memory access addresses predicted by the first prefetcher and the memory access addresses predicted by the second prefetcher. The preset priority of the first prefetcher is lower than the preset priority of the second prefetcher; An update module is used to update the redundancy index associated with the first prefetcher based on the consistency between the memory access address predicted by the first prefetcher and the memory access address predicted by the second prefetcher; the redundancy index is used to characterize the redundancy degree of the first prefetcher. The execution module is used to control the functional state of the first prefetcher based on the redundancy index associated with the first prefetcher.

9. A pre-fetching device, characterized in that, include: The first pre-fetcher, the second pre-fetcher, and the pre-fetcher control device as described in claim 8.

10. A processor, characterized in that, include: The prefetching device as described in claim 9.

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