A circuit and implementation method for sorting sequence index values in bit-reverse order

Abstract

This invention discloses a circuit and implementation method for sorting sequences bit-by-bit according to index values, relating to the field of digital signal processing technology. It solves the problems of high hardware requirements, complex design, and unpredictable processing delay in existing processor-based bit-by-bit sorting by index values. Key features of the solution include: multiple reversal processing layers, the number of which is determined by the length of the input sequence; the input terminal with the smallest layer number receives the input sequence, and the output terminal with the largest layer number sends the output sequence; each reversal processing layer includes multiple reversal units, the number of which is the same as the layer number; the input terminal with the largest number serves as the input terminal of the layer, and the output terminal with the smallest number serves as the output terminal of the layer; wherein, the number... j The reversing unit is used to process the input sequence with a length of , dividing the sequence into 4 equal segments according to the input order, keeping the first and last segments unchanged, and swapping the middle two segments; the above problem is solved by performing hierarchical reversing processing through a simple circuit structure.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and more specifically, to a circuit and implementation method for sorting sequences in reverse order by index value. Background Technology

[0002] The Fast Fourier Transform (FFT) is one of the most important algorithms in digital signal processing, widely used in fields such as communication, audio processing, and image processing. The FFT core is the hardware circuit module that implements the FFT algorithm, and its design directly affects the system's performance, power consumption, and resource utilization. In hardware implementation, the FFT core typically uses fixed-point data, based on classic Cooley-Tukey, Sande-Tukey, and improved algorithms. Pipeline-architecture FFT circuits are widely used in real-time signal processing due to their good balance between data throughput and hardware resource consumption. However, in the pipelined architecture of FFT, time-decimation FFT algorithms, represented by Cooley-Tukey, require the sequence input to be reversed bit-by-bit according to the sequence element index values ​​before the butterfly operation, and the circuit outputs the FFT operation results in the normal order. Conversely, frequency-decimation FFT algorithms, represented by Sande-Tukey, receive the sequence input in sequence for the butterfly operation, but the circuit outputs the FFT operation results in the order of the sequence element index values ​​after bit-by-bit reversal. To correctly execute FFT or process FFT operation results, it is sometimes necessary to reverse the sequential input sequence or restore the reversed output sequence to the normal order. Currently available solutions for reversing output are mostly based on processors such as CPUs and MCUs. Performing the reversing process on the CPU or MCU places high hardware requirements, is complex in design, and makes the processing latency difficult to determine.

[0003] Therefore, this application provides a circuit and implementation method for sorting sequences in reverse order by index value, thereby solving the above problems. Summary of the Invention

[0004] The purpose of this application is to provide a circuit and implementation method for sorting sequences bit by bit according to index values, which solves the problems of high hardware requirements, complex design, and difficult-to-determine processing delay in existing processor-based bit-by-bit sorting by index values. This application performs layered sorting through a simple circuit structure, which can support pipelined processing, has a simple implementation structure, low hardware requirements, and can calculate the processing delay based on the length of the input sequence.

[0005] This application first provides a circuit for sorting a sequence in reverse order by index value, comprising:

[0006] Multiple reverse processing layers. The number of reverse processing layers is determined by the length of the input sequence; for a length of... The input sequence has the following reverse processing layer number: , The integer is greater than 1. The multiple reverse processing layers are connected in order according to their layer numbers. The input terminal of the reverse processing layer with the smallest layer number receives the sequentially input input sequence, and the output terminal of the reverse processing layer with the largest layer number outputs the output sequence after being reversed bit by bit according to the index value.

[0007] Each reverse order processing layer consists of multiple reverse order units, the number of which is the same as the layer number. These units are connected in numerical order, with the input of the unit with the highest number serving as the input of its respective reverse order processing layer, and the output of the unit with the lowest number serving as the output of its respective reverse order processing layer. The reverse unit is used to... The input sequence is processed by dividing it into equal parts of length 1 according to the input order. The 4th paragraph Given a positive integer, keep the positions of the first and last segments unchanged, and swap the positions of the middle two segments.

[0008] In one possible implementation, the reversing unit includes: two condition selectors and a shift register; the length of the shift register is... , This is the number of the reverse processing unit; the condition selector is used to select based on the control signal: connect the input of the shift register to the output of the shift register, and connect the input of the reverse processing unit to the output of the reverse processing unit; or connect the input of the shift register to the input of the reverse processing unit, and connect the output of the shift register to the output of the reverse processing unit; the control signal is determined by the index value of the input sequence.

[0009] In one possible implementation, the control signal is the bit of the input sequence index value, counted from low to high, starting from 0. and When the control signal is 2'b10, connect the input of the shift register to the output of the shift register, and connect the input of the reverse processing unit to the output of the reverse processing unit; when the control signal is not 2'b10, connect the input of the shift register to the input of the reverse processing unit, and connect the output of the shift register to the output of the reverse processing unit.

[0010] In one possible implementation, the reversal unit includes: When the value exceeds the threshold, RAM resources are used to replace shift register resources, and logic resources are used to replace the condition selector.

[0011] In one possible implementation, the circuit's processing delay is: Shoot, among them The layer number is for reverse processing. The length of the input sequence is a power of 2.

[0012] In one possible implementation, the reversing unit of each reversing processing layer is encapsulated as a module, which has an input and an output.

[0013] This application also provides a method for sorting a sequence in reverse order by index value, based on the circuit described above. The method includes: obtaining an input sequence, the length of which is... , The input sequence is an integer greater than 1; the input sequence is connected in order of layer number. The reverse order processing layer takes the input sequence into the layer with the lowest layer number and outputs it from the layer with the highest layer number. Within each reverse order processing layer, the input sequence is fed into multiple reverse units connected in numerical order. The number of reverse units is the same as the layer number. The input sequence starts from the reverse unit with the highest layer number and outputs from the reverse unit with the lowest layer number. Specifically, in the layer numbering... In the reverse unit, the input sequence is... Given an input sequence of length , the sequence is divided into equal parts of length in the input order. The 4th paragraph Given a positive integer, keep the positions of the first and last segments unchanged, and swap the positions of the middle two segments.

[0014] In one possible implementation, in numbering In the reverse unit, the input sequence is... Given an input sequence of length , the sequence is divided into equal parts of length in the input order. The 4th paragraph Given positive integers, keep the first and last segments of the sequence unchanged, and swap the positions of the middle two segments. This is achieved through the following steps: extract the control signal from the index values ​​of the input sequence; select the appropriate element based on the control signal: directly use the elements of the input sequence as the output of the reverse unit, and adjust the length to... The output of the shift register is used as input; or, the elements of the input sequence are fed into the length register. The shift register is used to take the output of the shift register as the output of the reverse unit.

[0015] In one possible implementation, the control signal is extracted from the index value of the input sequence; this includes: extracting the first control signal, counting from low to high (starting from 0), from the index value bits of the input sequence. and This bit serves as the control signal.

[0016] In one possible implementation, when the control signal is 2'b10, the elements of the input sequence are directly used as the output of the reversal unit, and the length is adjusted to... The output of the shift register is used as input; when the control signal is not 2'b10, the elements of the input sequence are sent to the input register of length . The shift register is used to take the output of the shift register as the output of the reverse unit.

[0017] Compared with existing technologies, this application has the following advantages: 1. Supports pipelined processing: This application achieves bit-by-bit reversal operation through hierarchical and sequential processing, supporting pipelined operation and eliminating blocking signals; 2. Simple interface structure: This application includes only one input port and one output port. The input port receives the input sequence input in index value order, and the output port outputs the output sequence bit-by-bit according to the index value. Compared with CPU / MCU-based implementation schemes, the interface is greatly simplified, which can greatly improve design flexibility; 3. Flexible design: This application can select the integrated encapsulated reversal processing layer module to build a layered architecture according to the length of the input sequence, and flexibly adjust the layered architecture according to the change in the length of the input sequence, improving design flexibility; 4. Low hardware resource consumption: This application only involves shift register cache, condition selector, or RAM resources and logic resources, and the control signal is only two bits, which significantly reduces the hardware resources consumed compared with CPU / MCU-based implementation schemes; 5. Fixed processing delay: The processing delay of this application has a fixed one-to-one correspondence with the sequence length, which facilitates timing design. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0019] Figure 1 A schematic diagram of a circuit for sorting a sequence in reverse order by index value, provided in an embodiment of this application;

[0020] Figure 2 Numbers provided for embodiments of this application The schematic diagram of the reverse unit;

[0021] Figure 3 This is a flowchart illustrating a method for sorting a sequence in reverse order by index value, as provided in an embodiment of this application. Detailed Implementation

[0022] In the following, the terms “comprising” or “may include” as used in the various embodiments of this application indicate the presence of the claimed function, operation, or element, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in the various embodiments of this application, the terms “comprising,” “having,” and their cognates are intended only to indicate a specific feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing, or the possibility of adding one or more combinations of the foregoing.

[0023] In various embodiments of this application, the expression "or" or "at least one of B and / or C" includes any combination or all combinations of the words listed simultaneously. For example, the expression "B or C" or "at least one of B and / or C" may include B, may include C, or may include both B and C.

[0024] The terms used in the various embodiments of this application (such as "first," "second," etc.) may modify various constituent elements in the various embodiments, but do not limit the corresponding constituent elements. For example, the above terms do not limit the order and / or importance of the elements. The above terms are only used for the purpose of distinguishing one element from other elements. For example, a first user device and a second user device refer to different user devices, although both are user devices. For example, without departing from the scope of the various embodiments of this application, a first element may be referred to as a second element, and similarly, a second element may also be referred to as a first element.

[0025] It should be noted that if a description refers to "connecting" a component to another component or "connecting" it to another component, then the first component can be directly connected to the second component, and a third component can be "connected" between the first and second components. Conversely, when a component is "directly connected" to another component or "directly connected" to another component, it can be understood that there is no third component between the first and second components.

[0026] The terminology used in the various embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the various embodiments of this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in a generally used dictionary) are to be interpreted as having the same meaning as in the context of the relevant technical field and are not to be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this application are only for explaining this application and are not intended to limit this application.

[0028] Please see Figure 1 As shown, Figure 1 This is a schematic diagram of a circuit for sorting a sequence bit-by-bit according to its index value, provided in an embodiment of this application. The circuit for sorting a sequence bit-by-bit according to its index value includes: multiple reverse order processing layers, the number of which is determined by the length of the input sequence, where the length of the input sequence is... The number of reverse processing layers is , For integers greater than 1, multiple reverse processing layers are connected sequentially according to their layer numbers. The input terminal of the reverse processing layer with the smallest layer number receives the sequentially input input sequence, and the output terminal of the reverse processing layer with the largest layer number outputs the output sequence after being reversed bit by bit according to the index value. Each reverse processing layer includes multiple reverse units, the number of which is the same as the layer number of the reverse processing layer. The multiple reverse units are connected sequentially according to their numbers. The input terminal of the reverse unit with the largest number serves as the input terminal of its respective reverse processing layer, and the output terminal of the reverse unit with the smallest number serves as the output terminal of its respective reverse processing layer. Wherein, the number... The reverse unit is used to... The input sequence is processed by dividing it into equal parts of length 1 according to the input order. The 4th paragraph Given a positive integer, keep the positions of the first and last segments unchanged, and swap the positions of the middle two segments.

[0029] Specifically, the circuit for sorting a sequence bit-by-bit according to its index value performs the following function: receiving an input sequence, reversing the input sequence bit-by-bit according to its index value, and outputting a reordered sequence. This circuit performs bit-by-bit reversal processing based on the index value for input sequences of length being integer powers of 2. This circuit adopts a hierarchical structure, handling sequential input sequences of length... The input sequence, the circuit is divided into Each layer of the reverse processing layer performs bitwise reverse processing, and each reverse processing layer consists of several sequentially connected reverse units. The input sequence starts from the first... The input to the reverse processing layer is from the first layer. The output of the layer reversal processing layer outputs the reversed result, where the first... layer( In the reverse processing layer, including a total of A series of consecutive reverse-order units, the reverse-order processing units are numbered from... Sort up to 1. Each reversing unit receives the input sequence according to the processing length, divides the input sequence into four equal segments in the input order, keeps the first and last segments unchanged, and swaps the positions of the middle two segments. For the 1st... In the reverse order processing layer, the first ( ) reverse processing units, The length of the input sequence is processed, and the length is... The sequence is divided into equal parts of length according to the input order. Given four subsequences, keep the first and last subsequences in their original positions and swap the positions of the two middle subsequences. The input sequence undergoes multiple layers of reverse processing, ultimately outputting a sequence ordered positionally by index, satisfying the requirements of classic Cooley-Tukey, Sande-Tukey, and improved algorithms for ordering sequence elements positionally by index.

[0030] The improvement of this application lies in providing a circuit that supports pipelined processing, has a simple structure, flexible design, and fixed processing delay, and sorts sequences bit-by-bit according to their index values. Specifically, the circuit of this application adopts a multi-level reverse processing architecture, realizing bit-by-bit reverse operation through hierarchical processing. Each layer consists of multiple sequentially connected reverse units, refining the hierarchical processing process. The circuit supports pipelined operation, and there are no blocking signals in the entire circuit design, thereby ensuring that bit-by-bit reverse operation and sequence output can continue when receiving continuous sequence inputs, guaranteeing the stability and continuity of pipelined processing. The circuit of this application has only one input terminal and one output terminal externally, and each reverse processing layer internally has one input terminal and one output terminal. Compared with CPU / MCU-based implementation schemes, the interface structure of this application is simpler and easier to use. The circuit of this application sets the number of reverse processing layers according to the length of the input sequence, and the reverse processing layers can be expanded / reduced at any time according to the change in the length of the input sequence, improving design flexibility. The circuit of this application realizes hierarchical bit-by-bit reverse operation through multiple sequentially connected reverse units, and the processing delay of the circuit can be calculated according to the length of the input sequence, which facilitates timing design.

[0031] Please see Figure 2 As shown, Figure 2 Numbers provided for embodiments of this application The schematic diagram of the reversing unit. In one possible implementation, the reversing unit includes: two condition selectors and a shift register; the length of the shift register is... , This is the number of the reverse processing unit; the condition selector is used to select based on the control signal: connect the input of the shift register to the output of the shift register, and connect the input of the reverse processing unit to the output of the reverse processing unit; or connect the input of the shift register to the input of the reverse processing unit, and connect the output of the shift register to the output of the reverse processing unit; the control signal is determined by the index value of the input sequence.

[0032] Furthermore, the control signal is the first bit of the input sequence index value, counted from low to high, starting from 0. and When the control signal is 2'b10, the input of the shift register is connected to the output of the shift register, and the input of the reverse processing unit is connected to the output of the reverse processing unit; when the control signal is not 2'b10, the input of the shift register is connected to the input of the reverse processing unit, and the output of the shift register is connected to the output of the reverse processing unit.

[0033] Specifically, the sequence position swapping function of the reversing unit is implemented based on the index value of the input sequence of that unit, combined with a condition selector and a shift register. For example... Figure 2As shown, in the input sequence, the input element and its index value idx are synchronously input to the reverse processing unit, with the first element being processed in the reverse order. Taking the reverse order processing unit as an example, it takes the first bit from the received index value idx, counting from 0 to the highest. and The bit is used as a control signal when the first bit... and When the bits are high and low (using HDL hardware description language, idx[j:j-1]=2'b10, where 2'b10 indicates that the control signal is a two-bit binary signal, specifically a binary 10), the length is... The input of the shift register selects its own output, and the output of the reverse unit selects its own input; in this case, the input element is directly used as the output element. and When the level value of a bit does not meet the aforementioned conditions, the input terminal of the shift register selects the input terminal of the reversing unit, and the output terminal of the reversing unit selects the output terminal of the shift register. At this time, the input element enters the shift register, and the output element is obtained from the shift register.

[0034] In one possible implementation, the reversal unit includes: When the value exceeds the threshold, RAM resources are used to replace shift register resources, and logic resources are used to replace the condition selector.

[0035] Specifically, when the input sequence is too long, i.e. When the size is too large, the delay caused by continuing to use shift registers and condition selectors to form the reversal unit is too high. Therefore, RAM resources and logic resources are used to implement the function of the reversal unit.

[0036] It is understood that the circuit in this application only involves shift registers and condition selectors. When the input sequence is long, it only involves RAM resources and logic resources, and uses two control signals, consuming only one LUT (lookup table) resource. The input sequence, when reversed, only requires consuming One LUT resource. Compared to CPU / MCU-based implementations, the hardware resources consumed are significantly reduced.

[0037] In one possible implementation, the circuit's processing delay is: Shoot, among them The layer number is for reverse processing. The length of the input sequence is a power of 2.

[0038] Specifically, for the first Layer reverse processing layer The delay of the condition selector at the input of the shift register in the reverse order unit is not included in the data processing delay of the reverse order unit because it does not affect the data output delay. However, the delay of the condition selector at the output of the reverse order unit is included in the data processing delay because it is a necessary path for the output data. Considering the data travels through a length of... The shift register cache introduces latency. Shoot, therefore the first The processing latency of each reverse unit is shoot.

[0039] Accordingly, the first The processing latency of the layer reverse order processing layer is The total processing delay of the circuit that sorts the sequence bit-by-bit according to its index is [time value]. shoot.

[0040] It is understandable that there is a fixed one-to-one correspondence between the length of the input sequence and the processing delay, which facilitates timing design.

[0041] In one possible implementation, the reversing unit of each reversing processing layer is encapsulated as a module, which has an input and an output.

[0042] Understandably, a standardized reverse processing layer can be implemented through encapsulation. When designing the number of reverse processing layers based on the power of the input sequence, the encapsulated reverse processing layers can be connected sequentially to form a circuit that sorts the sequence bit by bit according to the index value. This can adapt to the requirement of reversing the input sequence bit by bit according to the index, and does not require large-scale design adjustments to the circuit structure, thus having great design and application flexibility.

[0043] Please see Figure 3 As shown, Figure 3 The flowchart illustrates a method for sorting a sequence in reverse order by index value according to an embodiment of this application. This method is based on the circuit described above and includes: acquiring an input sequence, the length of which is... , The input sequence is an integer greater than 1; the input sequence is connected in order of layer number. The reverse order processing layer takes the input sequence into the layer with the lowest layer number and outputs it from the layer with the highest layer number. Within each reverse order processing layer, the input sequence is fed into multiple reverse units connected in numerical order. The number of reverse units is the same as the layer number. The input sequence starts from the reverse unit with the highest layer number and outputs from the reverse unit with the lowest layer number. Specifically, in the layer numbering... In the reverse unit, the input sequence is... Given an input sequence of length , the sequence is divided into equal parts of length in the input order. The 4th paragraph Given a positive integer, keep the positions of the first and last segments unchanged, and swap the positions of the middle two segments.

[0044] In one possible implementation, in numbering In the reverse unit, the input sequence is... Given an input sequence of length , the sequence is divided into equal parts of length in the input order. The 4th paragraph Given positive integers, keep the first and last segments of the sequence unchanged, and swap the positions of the middle two segments. This is achieved through the following steps: extract the control signal from the index values ​​of the input sequence; select the appropriate element based on the control signal: directly use the elements of the input sequence as the output of the reverse unit, and adjust the length to... The output of the shift register is used as input; or, the elements of the input sequence are fed into a shift register of length [length missing]. The shift register is used to take the output of the shift register as the output of the reverse unit.

[0045] In one possible implementation, the control signal is extracted from the index value of the input sequence; this includes: extracting the first control signal, counting from low to high (starting from 0), from the index value bits of the input sequence. and This bit serves as the control signal.

[0046] Furthermore, when the control signal is 2'b10, the elements of the input sequence are directly used as the output of the reverse unit, and the length is adjusted to... The output of the shift register is used as input; when the control signal is not 2'b10, the elements of the input sequence are sent to the input register of length . The shift register is used to take the output of the shift register as the output of the reverse unit.

[0047] It is understood that the circuit and implementation method for sorting sequences bit-by-bit according to index values ​​provided in this application have the following advantages: 1. Supports pipelined processing: This application achieves bit-by-bit reversal operation through hierarchical and sequential processing, supporting pipelined operation and eliminating blocking signals; 2. Simple interface structure: This application includes only one input port and one output port. The input port receives the input sequence input in index value order, and the output port outputs the output sequence after bit-by-bit reversal according to index values. Compared with CPU / MCU-based implementation schemes, the interface is greatly simplified, which can greatly improve design flexibility; 3. Flexible design: This application can select the integrated encapsulated reversal processing layer module to build a layered architecture according to the length of the input sequence, and flexibly adjust the layered architecture according to the changes in the length of the input sequence, improving design flexibility; 4. Low hardware resource consumption: This application only involves shift register buffers, condition selectors, or RAM resources and logic resources, and the control signals are only two bits, which significantly reduces the hardware resources consumed compared with CPU / MCU-based implementation schemes; 5. Fixed processing delay: The processing delay of this application has a fixed one-to-one correspondence with the sequence length, which facilitates timing design.

[0048] Please refer to Tables 1-4. This application also provides specific application examples to detail the entire process of implementing the circuit and method provided in this application to sort the input sequence in reverse order according to the index value.

[0049] Assume the length of the input sequence to be processed is 8 = 2 3 That is, N=3, the circuit includes N-1=2 reverse processing layers, numbered one and two. The input terminal of the first reverse processing layer serves as the input terminal of the entire circuit, and the output terminal of the second reverse processing layer serves as the output terminal of the entire circuit. The number of reverse units in each reverse processing layer is consistent with the layer number. The input terminal of the reverse unit with the largest number in each layer serves as the input terminal of this layer, and the output terminal of the reverse unit with the smallest number serves as the output terminal of this layer. The input sequence to be processed is input from the reverse unit numbered 1 in the first layer, and the output sequence is output from the reverse unit numbered 1 in the second layer. The structural design of the reverse processing layer is shown in Table 1.

[0050] Table 1. Structural Design of the Reverse Processing Layer

[0051]

[0052] The correspondence between the reverse unit number and the internal structure of the reverse unit is shown in Table 2. Reverse units with the same number in different reverse processing layers have the same internal structure, so they will not be described separately for each layer.

[0053] Table 2. Correspondence between Reverse Unit Numbering and Reverse Unit Internal Structure

[0054]

[0055] Where idx represents the index value.

[0056] Each reversing unit uses two condition selectors and one shift register to divide the input sequence into four equal segments according to the length of the sequence it processes, and then swaps the positions of the two middle segments before outputting the result. Table 3 shows the processing results of an input sequence of length 8 through each reversing processing layer.

[0057] Table 3 shows the processing results of an input sequence of length 8 after each reverse processing layer.

[0058]

[0059] Table 4 provides examples of the numbering. j The data states of the input, shift register, and output of the =2 reversal unit at different clock cycles. Here, X represents the state when there is no valid data, and the output of the shift register is delayed by one clock cycle compared to its internal state.

[0060] Table 4 j =2 Reverse sequence unit's status table under different clock cycles

[0061]

[0062] In this application example, in terms of processing delay, the processing delay of the condition selector is 1 clock cycle, and the number of clock cycles of sequence delay caused by the shift register buffer is the same as the length of the shift register.

[0063] The circuit contains two reverse processing layers. The first layer contains one reverse unit and the second layer contains two reverse units. Each reverse unit contains two condition selectors, so the entire circuit contains six condition selectors.

[0064] In the entire circuit, the condition selector generates a total delay of 3 clock cycles, and the shift register buffer generates a total delay of 4 clock cycles, so the total delay of the circuit is 4 + 3 = 7 clock cycles. In terms of resource consumption, 6 condition selectors are used and 4 memory units are used for the shift register, resulting in minimal resource consumption.

[0065] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A circuit for sorting a sequence in reverse order by index value, characterized in that, include: A multi-layer reverse order processing layer, wherein the number of layers is determined by the length of the input sequence, and the length of the input sequence is 2. N The number of layers in the reverse processing layer is N-1, where N is an integer greater than 1. The multiple reverse processing layers are connected in order according to the layer number. The input end of the reverse processing layer with the smallest layer number receives the sequentially input input sequence, and the output end of the reverse processing layer with the largest layer number outputs the output sequence after being reversed bit by bit according to the index value. Each reverse order processing layer includes: multiple reverse order units, the number of which is the same as the layer number of the reverse order processing layer. The multiple reverse order units are connected in order of number, with the input of the reverse order unit with the largest number serving as the input of the reverse order processing layer and the output of the reverse order unit with the smallest number serving as the output of the reverse order processing layer. Wherein, the reverse unit numbered j is used to start with 2 j+1 The input sequence is processed by dividing it into equal parts of length 2 according to the input order. j-1 Given four segments, where j is a positive integer, keep the first and last segments unchanged and swap the positions of the middle two segments.

2. The circuit for sorting a sequence in reverse order by index value according to claim 1, characterized in that, The reverse order unit includes: two condition selectors and a shift register; The length of the shift register is 2. j-1 j is the number of the reversed unit; The condition selector is used to select, according to the control signal: connecting the input of the shift register to the output of the shift register, and connecting the input of the reversing unit to the output of the reversing unit; or connecting the input of the shift register to the input of the reversing unit, and connecting the output of the shift register to the output of the reversing unit. The control signal is determined by the index value of the input sequence.

3. The circuit for sorting a sequence in reverse order by index value according to claim 2, characterized in that, The control signal is the j-th and j-1-th bits of the input sequence index value, counted from low to high starting from 0. When the control signal is 2'b10, the input and output of the shift register are connected, and the input and output of the reversing unit are connected. When the control signal is not 2'b10, the input and output of the shift register are connected, and the output of the shift register is connected. Here, 2'b10 indicates that the control signal is a two-bit binary signal, specifically a binary value of 10.

4. The circuit for sorting a sequence in reverse order by index value according to claim 2, characterized in that, The reverse order unit includes: when N is greater than the threshold, replacing the shift register resource with RAM resources and replacing the condition selector with logic resources.

5. The circuit for sorting a sequence in reverse order by index value according to claim 1, characterized in that, The processing delay of the circuit is: Let i be the layer number of the reverse processing layer, and N be the length of the input sequence raised to the power of 2.

6. The circuit for sorting a sequence in reverse order by index value according to claim 1, characterized in that, The reversing unit of each reversing processing layer is encapsulated as a module, which has an input and an output.

7. A method for sorting a sequence in reverse order by index value, characterized in that, The method is executed based on the implementation circuit as described in any one of claims 1 to 6, and includes: Obtain the input sequence, the length of which is 2. N N is an integer greater than 1; The input sequence is fed into N-1 reverse processing layers connected in order of layer number. The input sequence is input from the reverse processing layer with the smallest layer number and is transformed into the output sequence from the reverse processing layer with the largest layer number. In each reverse processing layer, the input sequence is input to multiple reverse units connected in numerical order. The number of reverse units is the same as the layer number of the reverse processing layer. The input sequence is input from the reverse unit with the largest number and output from the reverse unit with the smallest number. In the reversed unit numbered j, the input sequence begins with 2... j+1 Given an input sequence of length 2, the sequence is divided into equal parts of length 2 according to the input order. j-1 Given four segments, where j is a positive integer, keep the first and last segments unchanged and swap the positions of the middle two segments.

8. The method for sorting a sequence in reverse order by index value according to claim 7, characterized in that, In the reversed unit numbered j, the input sequence begins with 2... j+1 Given an input sequence of length 2, the sequence is divided into equal parts of length 2 according to the input order. j-1 Given four segments, where j is a positive integer, keep the first and last segments unchanged and swap the positions of the middle two segments; this can be achieved through the following steps: Extract control signals from the index values ​​of the input sequence; Based on the control signal selection: the elements of the input sequence are directly used as the output of the reverse unit, and the length is adjusted to 2. j-1 The output of the shift register is used as input; or, the elements of the input sequence are fed into a shift register of length 2. j-1 The shift register is used to take the output of the shift register as the output of the reverse unit.

9. A method for sorting a sequence in reverse order by index value according to claim 8, characterized in that, Extract control signals from the index values ​​of the input sequence; including: The control signal is obtained by extracting the j-th and j-1-th bits from the index value bits of the input sequence, starting from 0.

10. A method for sorting a sequence in reverse order by index value according to claim 9, characterized in that, When the control signal is 2'b10, the elements of the input sequence are directly used as the output of the reverse unit, and the length is adjusted to 2. j-1 The output of the shift register is used as input; when the control signal is not 2'b10, the elements of the input sequence are sent to a shift register of length 2. j -1 The shift register is used to take the output of the shift register as the output of the reverse unit; where 2'b10 indicates that the control signal is a two-bit binary signal, and its specific value is binary 10.

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