FPGA parallel computing unit scheduling method and device for image processing

Abstract

The embodiment of the application provides a kind of FPGA parallel computing unit scheduling method and device for image processing, through the innovative design data security transmission mechanism, through physical continuous memory allocation and descriptor queue management, realize the safe isolation and access control of data.Construct the data block encryption strategy based on timestamp, combined with dynamic buffer adjustment and state monitoring, establish reliable data protection system.Introduce processing delay monitoring mechanism, through real-time performance evaluation and resource scheduling, ensure the privacy of data processing process.The method effectively solves the deficiencies of traditional technology in data security, access control and privacy protection and other aspects on the basis of data encryption transmission, significantly improves the security and reliability of FPGA parallel computing.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data processing, specifically to an FPGA parallel computing unit scheduling method and device for image processing. BACKGROUND

[0002] The existing FPGA parallel computing unit scheduling method has obvious deficiencies. Traditional systems lack optimization in data block processing and fail to dynamically adjust data block size according to actual image resolution, affecting processing efficiency.

[0003] In addition, the existing technology has bottlenecks in data transmission and cache management. Most systems lack perfect PCIe transmission mechanisms and buffer dynamic adjustment strategies, resulting in insufficient parallel computing efficiency.

[0004] The existing system has technical shortcomings in state monitoring. It lacks real-time monitoring capability for processing delay, making it difficult to achieve efficient resource scheduling through state tracking, affecting the overall performance of the system. Solving these problems is of great significance to improving the performance of FPGA parallel computing. SUMMARY

[0005] To solve the problems in the prior art, the present application provides an FPGA parallel computing unit scheduling method and device for image processing, which can effectively solve the deficiencies of traditional technology in data security, access control and privacy protection, and significantly improve the security and reliability of FPGA parallel computing.

[0006] In order to solve at least one of the above problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides an FPGA parallel computing unit scheduling method for image processing, comprising:

[0008] A data transmission channel is established between the host and the field programmable gate array through the PCIe interface, a physically continuous memory area is allocated as a direct memory access buffer, a descriptor queue is created in the shared memory to record the source and target address information of data transmission, the descriptor queue is mapped to the user space, the burst transmission length and address alignment mode are configured, the optimal size of the data block is calculated according to the image resolution and the overlap area is set;

[0009] The image data is converted to gray value and divided into multiple data blocks according to the optimal size, boundary pixels are added to each data block and a timestamp containing data block number and processing time is set, the data block is written into the direct memory access buffer, the doorbell register is triggered to send a task signal to the field programmable gate array, the field programmable gate array prefetches descriptors from the descriptor queue and writes the data block into the dynamic random access memory;

[0010] A two-dimensional cache array is constructed and data blocks completed by processing are written to corresponding positions according to the timestamps, processing delays are monitored and buffer sizes are dynamically adjusted, the field programmable gate array writes data block states to a state register and triggers an interrupt signal, absence and repetition of the data blocks are detected by a state tracker, the host reads the data blocks from the dynamic random access memory according to contents of the state register, and the host sends a data read completion signal to the field programmable gate array.

[0011] Further, the host loads a PCIe device driver and enables an interrupt response mechanism, a physically continuous memory region is allocated by a kernel module and registered as a direct memory access buffer, the direct memory access buffer is mapped to a user space address, a PCIe link is configured to a third generation specification and a link width is set, and a bus master is started to connect the PCIe interface to a advanced extensible interface bus.

[0012] The field programmable gate array loads IP core configuration parameters of PCIe, configures an advanced extensible interface memory mapping protocol and an advanced extensible interface reduced interface protocol, creates a descriptor queue in shared memory to record source address and target address information of data transmission, sets sizes of direct memory access receiving and sending buffers according to system requirements, configures burst transmission length and address alignment mode, and establishes an interrupt vector table to bind task identification and an interrupt processing function.

[0013] Further, the physical address space of the descriptor queue is mapped to a process virtual address space by a memory mapping function, a base address register space is configured to realize access to control and state registers, a direct memory access burst transmission length is set to an integer multiple of a basic transmission unit, an address boundary alignment mode is configured to ensure data access efficiency, and read-write pointer update information of the descriptor queue is written to a doorbell register.

[0014] Optimal sizes of individual data blocks are calculated based on widths and heights of input images, the data block sizes are set to integer multiples of processing unit calculation capabilities, overlapping region mapping relationships are established between adjacent data blocks, pixel widths of the overlapping regions are calculated to ensure boundary pixel continuity, the data block sizes and overlapping region parameters are written to configuration registers, and a data block index table is generated to record block correlation information.

[0015] Further, the method further comprises: converting an RGB color space of the input image into a grayscale image; dividing the grayscale image data into a plurality of data blocks based on the optimal size; adding boundary pixels around each of the data blocks to form extended data blocks; calculating position information of the extended data blocks in a global coordinate system; generating data block descriptors containing a start address and an end address; and assigning a globally unique data block number to each of the data blocks.

[0016] A timestamp management unit records a processing state of the data blocks, the timestamp contains two time attribute fields of a data block number and a data block processing time, a timestamp mapping table is established to store time sequence information of the data blocks, the data blocks and corresponding timestamp information are written into a specified position of the direct memory access buffer, and a data block state register is updated to record a transmission completion flag.

[0017] Further, the method further comprises: writing task information into a specified offset address of a base address register space; triggering a doorbell register to generate an interrupt request signal; configuring an interrupt mask bit of an interrupt status register; activating an interrupt controller to enable an interrupt response; reading an interrupt vector table to obtain an interrupt service program entry address; sending a task start signal to the FPGA; and updating a task state register to record a task execution state.

[0018] The FPGA reads descriptor information from the descriptor queue to a prefetch buffer, parses the descriptor to obtain a source address and a target address of the data block, configures a transmission parameter of a direct memory access controller, establishes a burst transmission channel to write the data block into a specified storage unit of the DRAM, updates a read pointer of the descriptor queue, and writes a data block transmission completion flag into a state register.

[0019] Further, the method further comprises: calculating a number of rows and columns of a two-dimensional cache array according to an image resolution and the data block size, assigning a fixed size of storage space to each cache unit, reading the timestamp information to determine a write position of the data block, establishing a cache address mapping table to record a storage position of the data block in the two-dimensional cache array, writing the processed data block into a corresponding cache unit, and updating a cache state table to record a storage state of the data block.

[0020] The method further comprises: reading a processing time field in the timestamp to calculate a processing delay of the data block, adjusting a buffer size according to a statistical value of the processing delay, configuring a buffer threshold to control a read-write rate of the data block, writing a processing state of the data block into a specified bit field of a state register by the FPGA, generating an interrupt request signal to notify a processing completion event, and updating an interrupt flag bit of an interrupt status register.

[0021] Further, the state tracker reads the cache state table of the two-dimensional cache array, checks the continuity of the data blocks according to the data block number, establishes a data block state mapping table to record the missing and repeated data block information, writes the data block state mapping table to a specific field of the state register, updates the detection counter of the state tracker, and generates a data block state detection report to record the position information of the abnormal data block.

[0022] The host reads the state register to obtain the processing state of the data block, configures the read parameter of the direct memory access controller, reads the processed data block from the dynamic random access memory to the system memory, updates the read state flag of the data block, writes the read completion flag to the field programmable gate array, clears the corresponding interrupt state bit, and releases the storage space occupied by the read data block.

[0023] In a second aspect, the application provides an FPGA parallel computing unit scheduling device for image processing, comprising: an image processing module, configured to establish a data transmission channel between a host and a field programmable gate array through a PCIe interface, allocate a physically continuous memory region as a direct memory access buffer, create a descriptor queue in a shared memory to record the source address and target address information of data transmission, map the descriptor queue to a user space, configure the burst transmission length and address alignment mode, calculate the optimal size of a data block according to the image resolution and set an overlap region;

[0024] a data writing module, configured to convert image data into grayscale values and divide the image data into a plurality of data blocks according to the optimal size, add boundary pixels to each data block and set a timestamp containing the data block number and processing time, write the data blocks into the direct memory access buffer, trigger a doorbell register to send a task signal to the field programmable gate array, and the field programmable gate array prefetches a descriptor from the descriptor queue and writes the data blocks into a dynamic random access memory;

[0025] In a third aspect, the application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the FPGA parallel computing unit scheduling method for image processing when executing the program.

[0026] In a fourth aspect, the application provides a computer readable storage medium having a computer program stored thereon, wherein the computer program is executable by a processor to implement the steps of the FPGA parallel computing unit scheduling method for image processing.

[0027] In a fifth aspect, the present application provides a computer program product comprising computer programs / instructions which, when executed by a processor, implement the steps of the image processing-oriented FPGA parallel computing unit scheduling method.

[0028] From the above technical solution, the present application provides an image processing-oriented FPGA parallel computing unit scheduling method and device. By innovatively designing a data security transmission mechanism, through physical continuous memory allocation and descriptor queue management, data security isolation and access control are achieved. A timestamp-based data block encryption strategy is constructed, combined with dynamic buffer adjustment and state monitoring, to establish a reliable data protection system. A processing delay monitoring mechanism is introduced to ensure the privacy of the data processing process through real-time performance evaluation and resource scheduling. Based on data encryption transmission, this method effectively solves the shortcomings of traditional technologies in data security, access control and privacy protection, significantly improving the security and reliability of FPGA parallel computing. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0030] Figure 1 The flowchart of the image processing-oriented FPGA parallel computing unit scheduling method in the embodiments of the present application;

[0031] Figure 2 The structure diagram of the image processing-oriented FPGA parallel computing unit scheduling device in the embodiments of the present application;

[0032] Figure 3 The structure diagram of the electronic device in the embodiments of the present application.

[0033] Reference signs:

[0034] Electronic device 9600, central processor 9100, memory 9140, communication module 9110, input unit 9120, audio processor 9130, display 9160, power supply 9170, buffer memory 9141, application / function storage unit 9142, data storage unit 9143, driver program storage unit 9144, antenna 9111, speaker 9131, microphone 9132. DETAILED DESCRIPTION

[0035] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0036] The acquisition, storage, use, processing and the like of data in the technical solutions of the present application comply with relevant provisions of national laws and regulations.

[0037] In view of the problems in the prior art, the present application provides an FPGA parallel computing unit scheduling method and device for image processing, which innovatively designs a data security transmission mechanism, realizes data security isolation and access control through physical continuous memory allocation and descriptor queue management, constructs a timestamp-based data block encryption strategy, combines dynamic buffer adjustment and state monitoring to establish a reliable data protection system, and introduces a processing delay monitoring mechanism to ensure the privacy of the data processing process through real-time performance evaluation and resource scheduling. Based on data encryption transmission, the method effectively solves the deficiencies of traditional technologies in data security, access control and privacy protection, and significantly improves the security and reliability of FPGA parallel computing.

[0038] In order to effectively solve the deficiencies of traditional technologies in data security, access control and privacy protection, and significantly improve the security and reliability of FPGA parallel computing, the present application provides an embodiment of an FPGA parallel computing unit scheduling method for image processing, as shown in Figure 1 , which specifically includes the following contents:

[0039] Step S101: establishing a data transmission channel between a host and a field programmable gate array through a PCIe interface, allocating a physically continuous memory region as a direct memory access buffer, creating a descriptor queue in the shared memory to record the source address and target address information of data transmission, mapping the descriptor queue to the user space, configuring the burst transmission length and address alignment mode, calculating the optimal size of the data block according to the image resolution and setting the overlap region;

[0040] Optionally, the embodiment is directed to the problems of low PCIe transmission bandwidth utilization, poor memory management efficiency and unreasonable data block division in traditional FPGA image processing systems, and innovatively designs a data transmission optimization scheme based on intelligent scheduling. In terms of PCIe transmission efficiency evaluation, the embodiment designs a transmission efficiency score formula: Transfer_Score = α × (Bandwidth_Utilization) + β × (DMA_Efficiency) + γ × (Memory_Coherency), where α, β, γ are weight coefficients, respectively representing bandwidth utilization, DMA transmission efficiency and memory consistency. At the same time, the data block optimization score formula: Block_Score = (Processing_Units × Block_Size) / (Overlap_Size + Transfer_Overhead) is introduced to evaluate the rationality of data block division.

[0041] The embodiment first realizes efficient data transmission through deeply optimized PCIe interface configuration. In the PCIe channel establishment process, the system adopts a hierarchical configuration strategy to complete the parameter settings of the physical layer, the data link layer and the transaction layer in turn. In the physical layer configuration, the system selects the appropriate PCIe generation number and channel width according to the actual bandwidth requirement, such as for high-resolution image processing, the PCIe Gen3 x8 configuration is preferred to provide sufficient transmission bandwidth. In the data link layer configuration, the system improves the reliability of data transmission by optimizing the flow control parameters and retransmission strategy. In the transaction layer configuration, the system realizes request priority management to ensure that critical data transmission requests can be processed preferentially. In order to improve the transmission efficiency, the system sets the maximum load size and the maximum read request size in the PCIe configuration space, which is aligned with the processor cache line size, reducing the fragmentation overhead in the data transmission process. This multi-level PCIe optimization mechanism provides efficient and reliable channel protection for subsequent data transmission.

[0042] The embodiment innovatively realizes a continuous physical memory allocation mechanism. When allocating a DMA buffer, the system adopts a reserved memory region to ensure the continuity of the allocated physical memory space. In the specific implementation, the system reduces the number of page table entries and improves address translation efficiency through the large page table mechanism of the memory management unit. At the same time, the system establishes a buffer management table to record the usage status and access authority of each memory block. In order to improve memory access efficiency, the system considers the NUMA architecture characteristics when allocating memory and preferentially selects a memory region local to the processor node. In the descriptor queue creation process, the system adopts a ring buffer design and realizes efficient descriptor access through read-write pointer management. The queue size is dynamically adjusted according to actual processing requirements to avoid resource waste. This optimized memory management mechanism significantly improves data transmission efficiency.

[0043] The embodiment realizes efficient user space access through an optimized mapping mechanism. When mapping the descriptor queue to the user space, the system adopts a zero-copy technology to avoid data copy overhead between the kernel space and the user space. During the mapping process, the system realizes fine-grained access control through page table entry settings to ensure data access security. At the same time, the system implements a mapping address cache mechanism to reduce the overhead of repeated mapping operations. In terms of burst transmission configuration, the system selects the optimal burst transmission length according to PCIe channel characteristics and memory access mode. Address alignment requirements are realized through hardware masking to ensure that all transmission operations are performed on legal address boundaries. This fine configuration mechanism provides stable performance guarantee for data transmission.

[0044] The embodiment establishes an intelligent data block division mechanism. When calculating the optimal data block size, the system considers multiple factors, including the parallelism of the FPGA processing unit, PCIe transmission efficiency, and memory access characteristics. By establishing a performance model, the system can predict the processing efficiency under different block sizes, thereby selecting the optimal configuration. When setting the overlap region, the system determines the appropriate number of overlapping pixels according to the characteristics of the image processing algorithm to ensure the accuracy of boundary processing. In order to improve processing efficiency, the system implements a data block prefetching mechanism to preload the next data block while processing the current block. This optimized division mechanism significantly improves parallel processing efficiency.

[0045] The embodiment provides a complete data management solution. Through multi-level optimization design, the system realizes whole-process optimization from PCIe transmission to data block processing, significantly improving the overall performance of the FPGA image processing system. This deep optimization management mechanism provides reliable technical support for practical applications.

[0046] Step S102: converting the image data into gray scale values and dividing the image data into a plurality of data blocks according to the optimal size, adding boundary pixels to each of the data blocks and setting a timestamp containing a data block number and a processing time, writing the data blocks into the DMA buffer, triggering a doorbell register to send a task signal to the FPGA, and the FPGA pre-fetches descriptors from the descriptor queue and writes the data blocks into the DRAM;

[0047] Optionally, the embodiment is directed to the problems of low data preprocessing efficiency, discontinuous inter-block boundary processing, and complex data transmission synchronization in traditional FPGA image processing. A data preprocessing and transmission scheme based on timestamps is designed. In terms of data preprocessing evaluation, a preprocessing efficiency score formula is designed: Process_Score = α × (Color_Convert / Base_Time) + β × (Block_Efficiency) + γ × (Border_Quality), where α, β, and γ are weight coefficients representing color conversion speed ratio, data block division efficiency, and boundary processing quality, respectively. A transmission efficiency score formula is also introduced: Transfer_Score = (Block_Size × Queue_Depth) / (Setup_Time + Transfer_Delay), which is used to evaluate data transmission performance. These two score indicators comprehensively reflect the performance characteristics of the preprocessing and transmission process.

[0048] The embodiment first realizes high-quality grayscale conversion through a deeply optimized color conversion mechanism. For input images of different formats, an adaptive channel extraction algorithm is used to separate RGB data. During grayscale conversion, the system dynamically adjusts the conversion weights based on image content characteristics. For example, for areas containing a large amount of details, the weight of the green channel is increased to retain more texture information; for high-light areas, the weight is appropriately reduced to avoid information loss. The converted grayscale data is accessed quickly through a multi-level cache mechanism, and continuous pixel data is processed in a pipeline manner. Especially when processing high-resolution images, the system simultaneously converts multiple pixel data through parallel processing, significantly improving processing efficiency. During data block division, the system uses an adaptive block strategy based on the previously determined optimal size parameters. Considering the parallel processing capability and storage resource limitations of the FPGA, the selection of block size needs to balance processing efficiency and resource utilization. Through the establishment of a data block management table, the system realizes efficient block-level management, including block creation, positioning, and state tracking functions.

[0049] The embodiment adopts an innovative boundary processing mechanism to ensure data continuity. When adding boundary pixels to data blocks, the system adopts different filling strategies according to the spatial position of the blocks. For data blocks at the edge of the image, boundary pixels are generated by mirroring filling or boundary extension; for internal data blocks, real overlapping pixels are extracted from adjacent blocks. This intelligent boundary processing mechanism effectively avoids discontinuity in block processing. The timestamp design adopts a double-field structure, with a data block number field ensuring global uniqueness and a processing time field used for task scheduling and state tracking. The system maintains the timing relationship of data blocks through a timestamp mapping table, supporting block-level synchronization and sequential control based on timestamps. This complete preprocessing mechanism significantly improves the quality and efficiency of data preparation.

[0050] The embodiment implements an efficient data transmission mechanism. When data blocks are written to the DMA buffer, the system adopts a batch transmission strategy to achieve continuous storage of data through pre-allocated buffers. The triggering of the doorbell register adopts an edge-triggered mode to ensure reliable signal transmission. The FPGA side reads descriptor information in advance through a prefetch mechanism, establishes a transmission request queue, and implements pipeline operation in the transmission process. When data is written to dynamic random access memory, the system quickly locates the storage location through an address mapping table and uses burst transmission mode to improve data throughput. This optimized transmission mechanism significantly reduces data transmission overhead.

[0051] The embodiment provides a reliable preprocessing and transmission solution. Through optimized color conversion, data blocking, and transmission control, the system implements an efficient data preparation process. This reliable processing mechanism provides high-quality data support for subsequent FPGA parallel computing. The innovation of the embodiment lies in the deep optimization of the data preprocessing and transmission process, which significantly improves the processing efficiency of the system through reasonable resource scheduling and fine process control. In particular, when processing large-scale image data, the optimization effect is more obvious. At the same time, the design of the scheme fully considers the actual application requirements and has good scalability and adaptability.

[0052] Step S103: Construct a two-dimensional cache array and write the processed data blocks to the corresponding positions according to the timestamps, monitor the processing delay and dynamically adjust the buffer size, the FPGA writes the data block state to the state register and triggers an interrupt signal, the state tracker detects the absence and repetition of the data blocks, the host reads the data blocks from the DRAM according to the content of the state register, and the host sends a data read completion signal to the FPGA.

[0053] Optionally, the embodiment is directed to the problem of two-dimensional data organization confusion, low cache management efficiency and unreliable state synchronization in FPGA image processing, and a set of adaptive cache-based data management scheme is innovatively designed. In the aspect of cache performance evaluation, the embodiment designs a cache efficiency score formula: Cache_Score = a x (Access_Speed / Base_Speed) + β x (Space_Utilization) + γ x (Hit_Rate), wherein a, β, γ are weight coefficients, respectively representing access speed ratio, space utilization and hit rate. At the same time, the delay evaluation formula: Delay_Score = (Processing_Time x Block_Count) / (Buffer_Size + Sync_Overhead) is introduced, which is used to evaluate the relationship between processing delay and buffer configuration. These two score indicators comprehensively reflect the data management performance.

[0054] The embodiment first realizes efficient data management through a deeply optimized cache organization mechanism. The construction of the two-dimensional cache array adopts hierarchical design, including data storage layer, address mapping layer and state management layer. In the data storage layer, the system organizes data using block storage structure according to the internal storage resource characteristics of FPGA. The size of each storage unit is optimized according to the data block size to ensure efficient use of storage space. The address mapping layer realizes fast conversion from timestamp to storage location, and supports efficient data positioning by establishing a multi-level mapping table. The state management layer maintains the usage state of each storage unit, including idle, writing, occupied and other state information. Especially when processing large-scale data, this hierarchical management mechanism significantly improves data access efficiency. In order to handle data write conflicts, the system implements a timestamp-based arbitration mechanism to ensure that data is written to the cache in the correct order. At the same time, by establishing a write queue, the system can cache multiple data blocks to be written, reducing write waiting time.

[0055] The embodiment innovatively realizes an adaptive buffer management mechanism. In monitoring the processing delay, the system uses a sliding window to count the processing time of data blocks, and by analyzing the trend of processing time, it predicts the future processing load. The adjustment of buffer size adopts a gradual strategy to avoid frequent and large adjustments that cause system instability. When detecting that the processing delay continues to increase, the system will appropriately increase the buffer size to provide more data cache space; when the processing delay decreases, the buffer size is correspondingly reduced to avoid resource waste. This dynamic adjustment mechanism can optimize resource allocation according to the actual processing load, improving the adaptability of the system. At the same time, the system implements a buffer data prefetching mechanism, which loads the data to be processed in advance according to the timestamp of the data block, reducing data waiting time.

[0056] The embodiment realizes reliable data tracking through an optimized state synchronization mechanism. The state register adopts a bit field design, and different bit fields respectively record the processing state, error flag and control information of the data block. The generation of the interrupt signal adopts an edge trigger mode, ensuring reliable transmission of the signal. The state tracker detects the absence and repetition of the data block by scanning the timestamp sequence, updates the error flag bit immediately when an anomaly is found, and starts the corresponding recovery mechanism. For example, for the absent data block, the system attempts to re-request the data; for the repeated data block, the newer version of the timestamp is retained. This complete state management mechanism significantly improves the reliability of data processing.

[0057] The embodiment establishes an efficient data readback mechanism. After receiving the interrupt signal, the host quickly locates the data block to be processed by reading the state register. The data reading process adopts a batch transmission mode, and efficient data transfer is achieved through the DMA controller. After reading is completed, the system notifies the FPGA through a special completion signal, triggering the release operation of the related resources. This optimized readback mechanism significantly reduces the data transmission overhead. The innovation of the embodiment lies in the all-round optimization of the data management process, which significantly improves the processing efficiency of the system through adaptive resource scheduling and reliable state synchronization. In particular, when processing complex image data, the optimization effect is more obvious. At the same time, the design of the scheme fully considers the actual application requirements, and has good scalability and robustness.

[0058] From the above description, it can be seen that the FPGA parallel computing unit scheduling method for image processing provided by the embodiment of the application can realize safe isolation and access control of data through innovative design of a data safe transmission mechanism, through physical continuous memory allocation and descriptor queue management. A data block encryption strategy based on timestamps is constructed, combined with dynamic buffer adjustment and state monitoring, to establish a reliable data protection system. A processing delay monitoring mechanism is introduced to ensure the privacy of the data processing process through real-time performance evaluation and resource scheduling. On the basis of data encryption transmission, the method effectively solves the deficiencies of traditional technologies in data security, access control and privacy protection, and significantly improves the security and reliability of FPGA parallel computing.

[0059] In an embodiment of the FPGA parallel computing unit scheduling method for image processing of the application, the following contents can be specifically included:

[0060] Step S201: The host end loads the PCIe device driver program and enables the interrupt response mechanism, allocates a physical continuous memory area through a kernel module and registers it as a direct memory access buffer, maps the direct memory access buffer to a user space address, configures the PCIe link to the third generation specification and sets the link width, starts the bus master to connect the PCIe interface to the advanced extensible interface bus;

[0061] Step S202: The field programmable gate array loads the PCIe IP core configuration parameters, configures the advanced extensible interface memory mapping protocol and the advanced extensible interface reduced interface protocol, creates a descriptor queue in the shared memory to record the source address and target address information of data transmission, sets the size of the direct memory access receiving buffer and the sending buffer according to the system requirements, configures the burst transmission length and the address alignment mode, and establishes an interrupt vector table to bind the task identification and the interrupt processing function.

[0062] Optionally, the embodiment innovatively designs an interface initialization scheme based on double-end cooperation to solve the problems of complex PCIe interface configuration, low memory management efficiency and difficult data transmission synchronization in the FPGA system. In terms of PCIe performance evaluation, the embodiment designs a link efficiency scoring formula: Link_Score = α × (Link_Width × Link_Speed) + β × (DMA_Efficiency) + γ × (Interrupt_Response), wherein α, β and γ are weight coefficients, respectively representing the link bandwidth, the DMA transmission efficiency and the interrupt response speed. Meanwhile, a protocol adaptation scoring formula: Protocol_Score = (Transaction_Rate × Buffer_Utilization) / (Setup_Overhead + Sync_Delay) is introduced to evaluate the adaptation effect of the interface protocol.

[0063] The embodiment first realizes reliable device initialization through a deeply optimized driver loading mechanism. During the host driver program loading process, the system adopts a layered initialization strategy to complete device identification, resource allocation and function configuration in turn. The driver program reads the device identification information through the PCI configuration space to ensure correct matching with the FPGA device. The interrupt response mechanism adopts the MSI-X mode to support multi-queue interrupt distribution, significantly improving the interrupt processing efficiency. Especially in processing high-concurrency data transmission, the system binds the interrupt request to a specific processor core through interrupt affinity configuration to reduce interrupt processing delay. During the memory allocation process, the system applies physically continuous memory pages through the kernel memory management interface to avoid memory fragmentation problems. In order to improve the memory access efficiency, the system considers the processor cache line size when allocating the DMA buffer to ensure data access alignment. This optimized initialization mechanism provides a stable hardware foundation for subsequent data transmission.

[0064] The embodiment innovatively realizes the PCIe link configuration mechanism. The PCIe link configuration adopts an adaptive adjustment strategy, and selects optimal link parameters according to actual bandwidth requirements. The system is preferentially configured as a PCIe Gen3 specification, and supports higher transmission rates. The selection of the link width considers FPGA resource constraints and actual bandwidth requirements, and the optimal configuration is determined through a performance evaluation model. In the link training process, the system adjusts the electrical parameters in a fine-grained manner to ensure signal quality. The startup of the bus master adopts a progressive strategy, first completes basic initialization, and then gradually enables advanced functions. The connection with the advanced extensible interface bus is realized through a bridge controller, supporting address space mapping and transmission protocol conversion. This fine link configuration mechanism significantly improves the reliability of data transmission.

[0065] The embodiment realizes efficient protocol adaptation through optimized IP core configuration. The configuration of the PCIe IP core on the FPGA side adopts parameterized design, supporting flexible function customization. When configuring the advanced extensible interface protocol, the system simultaneously supports both memory mapping and slim interface modes, meeting the transmission requirements of different scenarios. The creation of the descriptor queue adopts a ring buffer structure, and efficient descriptor access is realized through read-write pointer management. The buffer size is set based on actual processing requirements, and the optimal configuration is predicted through a performance model. The selection of burst transmission parameters considers memory access characteristics to ensure transmission efficiency. The interrupt vector table is established in a scatter-gather manner, supporting a flexible interrupt handling mechanism. This complete protocol configuration mechanism provides reliable protocol support for data transmission.

[0066] The embodiment establishes a comprehensive resource management framework. From driver loading to protocol configuration, each link is deeply optimized to ensure efficient use of resources. The management of DMA buffers adopts a multi-level cache strategy, supporting fast data access. By establishing a complete interrupt handling framework, the system realizes an efficient task synchronization mechanism. This optimized resource management mechanism significantly improves the overall performance of the system.

[0067] The embodiment provides an innovative solution for PCIe interface configuration. Through a double-end collaborative configuration mechanism, the system realizes full-stack optimization from hardware to software. This reliable configuration mechanism provides an efficient data transmission channel for FPGA image processing systems. The technical solution of the embodiment has good scalability and can adapt to different scales of data processing requirements, providing reliable technical support for FPGA application development.

[0068] In an embodiment of the image processing-oriented FPGA parallel computing unit scheduling method of the present application, the following content can also be specifically included:

[0069] Step S301: mapping the physical address space of the descriptor queue to the process virtual address space through a memory mapping function, configuring a base address register space to enable access to control registers and status registers, setting a direct memory access burst transfer length to an integer multiple of a basic transfer unit, configuring an address boundary alignment mode to ensure data access efficiency, and writing read-write pointer update information of the descriptor queue into a doorbell register;

[0070] Step S302: calculating the optimal size of a single data block based on the width and height of an input image, setting the data block size to an integer multiple of the processing unit computing capacity, establishing an overlap region mapping relationship between adjacent data blocks, calculating the pixel width of the overlap region to ensure boundary pixel continuity, writing the data block size and overlap region parameters into a configuration register, and generating a data block index table to record block correlation information.

[0071] Optionally, the embodiment innovatively designs a data organization scheme based on intelligent mapping to address the problems of complex address mapping, unreasonable data block division, and low boundary processing efficiency in FPGA image processing. In terms of address mapping evaluation, the embodiment designs a mapping efficiency score formula: Map_Score = α × (Translation_Speed / Base_Speed) + β × (Space_Efficiency) + γ × (Access_Latency), where α, β, and γ are weight coefficients representing address translation speed ratio, space utilization rate, and access latency, respectively. Meanwhile, a data block optimization score formula: Block_Score = (Processing_Units × Block_Size) / (Overlap_Cost + Communication_Overhead) is introduced to evaluate the rationality of data block division.

[0072] The embodiment first realizes efficient storage access through a deeply optimized address mapping mechanism. In the address mapping process of the descriptor queue, the system adopts a hierarchical mapping strategy to segment the physical address space and map it to the virtual address space. The implementation of the mapping function considers the memory access mode and uses a page table hierarchical mechanism to reduce address translation overhead. To improve access efficiency, the system precomputes page table entries during the mapping process and caches hot page table entries in the TLB. In particular, for frequently accessed descriptor regions, the system reduces the page table level through a large page table mechanism, significantly reducing address translation latency. In the configuration of the base address register space, the system adopts a region division strategy to map control registers and status registers to different address intervals, facilitating independent access and management. This optimized mapping mechanism provides efficient address translation support for data access.

[0073] The embodiment innovatively realizes the transmission parameter configuration mechanism. The setting of the DMA burst transmission length is based on the data block characteristics and the bus characteristics, and the optimal transmission unit is calculated through a performance model. The system configures the burst length as an integer multiple of the basic transmission unit, and ensures the transmission efficiency. The address alignment requirement is realized through a hardware mask, and all transmission operations are performed on the legal address boundary. The read and write pointers of the descriptor queue are updated by using atomic operations, and the processing unit is notified in real time through the doorbell register. This fine parameter configuration mechanism significantly improves the data transmission efficiency. The implementation of the doorbell mechanism adopts an edge trigger mode, which ensures the reliable transmission of the update signal. At the same time, the system establishes a pointer state table to track the usage of the queue in real time, and supports dynamic queue management.

[0074] The embodiment realizes efficient image processing through an optimized data block division mechanism. When calculating the optimal size of the data block, the system considers multiple factors: first, based on the resolution characteristics of the input image, the basic data block size is calculated; then, according to the parallelism and computing capacity of the FPGA processing unit, the block size is adjusted to meet the hardware processing efficiency requirement; finally, considering the storage resource limitation, the data block can be effectively used on-chip. The final size of the data block is set to be an integer multiple of the processing unit computing capacity, and this alignment mechanism ensures that the processing unit can be fully utilized. When establishing the overlap region, the system analyzes the characteristics of the image processing algorithm to determine the minimum necessary number of overlapping pixels. The mapping of the overlap region uses a shared memory method to support data sharing between adjacent blocks. This optimized division mechanism significantly improves the processing efficiency.

[0075] The embodiment establishes a complete data management framework. The design of the configuration register adopts a multi-field structure, which not only stores the data block parameters, but also contains processing control information. The implementation of the data block index table adopts a multi-level index structure to support fast inter-block relationship query. Through the establishment of a complete parameter management mechanism, the system realizes efficient organization and access of data blocks. This optimized management mechanism provides reliable data support for image processing.

[0076] The embodiment provides an innovative solution for data organization. Through optimized address mapping and data block management, the system realizes full-process optimization from storage access to data organization. This reliable organization mechanism provides efficient data support for FPGA image processing. The technical solution of the embodiment has good scalability and can adapt to different scales and types of image processing requirements, providing reliable technical support for FPGA application development. Especially when processing large-scale image data, the optimization effect is more obvious.

[0077] In an embodiment of the image processing oriented FPGA parallel computing unit scheduling method of the present application, the following contents can also be specifically included:

[0078] Step S401: converting the RGB color space of the input image into a grayscale image, dividing the grayscale image data into a plurality of data blocks based on the optimal size, adding boundary pixels around each of the data blocks to form extended data blocks, calculating position information of the extended data blocks in a global coordinate system, generating data block descriptors containing start addresses and end addresses, and assigning globally unique data block numbers to each of the data blocks;

[0079] Step S402: creating a timestamp management unit to record processing states of the data blocks, the timestamp containing two time attribute fields of data block number and data block processing time, establishing a timestamp mapping table to store timing information of the data blocks, writing the data blocks and their corresponding timestamp information into designated positions of the direct memory access buffer, and updating a data block state register to record a transmission completion flag.

[0080] Optionally, the embodiment innovatively designs a data preprocessing scheme based on timestamps to solve the problems of inaccurate color conversion, chaotic data block management, and unreliable timing control in FPGA image processing. In terms of color conversion evaluation, the embodiment designs a conversion quality score formula: Color_Score = α × (Detail_Preserve) + β × (Edge_Clarity) + γ × (Noise_Suppress), where α, β, and γ are weight coefficients representing detail preservation, edge clarity, and noise suppression, respectively. Meanwhile, a timing management score formula: Timing_Score = (Processing_Speed × Block_Count) / (Timestamp_Overhead + Sync_Delay) is introduced to evaluate the timing control effect.

[0081] The embodiment first realizes high-quality grayscale conversion through a deeply optimized color conversion mechanism. When processing RGB images, the system uses an adaptive weight method for channel synthesis, dynamically adjusting the contribution of each channel by analyzing the image content characteristics. For high-light areas, the system appropriately reduces the green channel weight to avoid information oversaturation; for dark areas, it increases the red channel weight to retain more detail information. When calculating the weight, the system considers the human eye's visual characteristics, making the converted grayscale image more consistent with human eye perception. Especially when processing images with rich textures, the system enhances detail performance through a local contrast enhancement algorithm. The conversion process uses a pipeline design, supporting parallel processing of multiple pixels, significantly improving conversion efficiency. During data block division, the system uses an adaptive block strategy based on the previously determined optimal size. The size of each data block not only considers the processing capacity of the FPGA, but also takes into account the principle of data access locality, ensuring processing efficiency. This optimized conversion mechanism provides high-quality input data for subsequent processing.

[0082] The embodiment innovatively realizes a boundary expansion mechanism. When adding boundary pixels to data blocks, the system uses different filling strategies based on the block's position. For data blocks inside the image, the system extracts actual pixel values from adjacent blocks as boundary pixels; for data blocks at the image edge, it uses an intelligent filling algorithm. For example, for areas containing obvious edge features, the system generates boundary pixels through edge extension; for texture areas, it fills the boundary using a texture synthesis algorithm. The position calculation of the expanded data block uses a hierarchical mapping method, first determining the block's reference position in the global coordinate system, and then calculating the actual range after expanding the boundary. During descriptor generation, the system not only records address information but also includes block attribute markers, facilitating subsequent processing control. The allocation of data block numbers uses a partition encoding method to ensure the uniqueness and continuity of the numbers. This complete data organization mechanism significantly improves the reliability of data management.

[0083] The embodiment realizes reliable timing control through optimized timestamp management. The timestamp management unit uses a hierarchical design, including three functional modules: timestamp generation, mapping management, and state tracking. The timestamp design uses a double-field structure, with the data block number field used to uniquely identify data blocks and the processing time field recording the expected processing time window. This design not only supports timestamp-based data synchronization but also can be used for load balancing and anomaly detection. The timestamp mapping table uses a multi-level index structure to support fast timing information query and update. During data writing, the system uses atomic operations to ensure the consistency of timestamp information. The state register update uses a bit field design, with different bit fields recording transmission status, processing status, and error flags. This fine timing management mechanism significantly improves the controllability of data processing.

[0084] The embodiment establishes a complete data management framework. From color conversion to timing control, each link is optimized in depth to ensure the quality and efficiency of data processing. Especially when processing large-scale image data, the system significantly improves the processing speed through parallel processing and pipeline operation. The introduction of the timestamp mechanism not only solves the data synchronization problem, but also provides reliable state tracking capability for the system. The innovation of this embodiment lies in the all-round optimization of the data preprocessing process. Through reasonable resource scheduling and fine process control, the processing efficiency of the system is significantly improved. This optimization effect is outstanding in practical application, especially in processing image processing tasks that require accurate timing control, the system shows superior performance and reliability.

[0085] In an embodiment of the FPGA parallel computing unit scheduling method for image processing of the present application, the following contents can also be specifically included:

[0086] Step S501: write task information to the specified offset address of the base address register space, trigger the doorbell register to generate an interrupt request signal, configure the interrupt mask bit of the interrupt status register, activate the interrupt controller to enable interrupt response, read the interrupt vector table to obtain the interrupt service program entry address, send a task start signal to the FPGA, and update the task state register to record the task execution state;

[0087] Step S502: the FPGA reads the descriptor information from the descriptor queue to the pre-fetch buffer area, parses the descriptor to obtain the source address and target address of the data block, configures the transmission parameters of the DMA controller, establishes a burst transmission channel to write the data block to the specified storage unit of the DRAM, updates the read pointer of the descriptor queue, and writes the data block transmission completion flag to the status register.

[0088] Optionally, the embodiment innovatively designs a task control scheme based on intelligent interrupts to address the problems of unreliable task triggering, delayed interrupt response, and low data transmission efficiency in FPGA systems. In terms of task control evaluation, the embodiment designs an interrupt efficiency scoring formula: Interrupt_Score = α×(Response_Time / Base_Time) +β×(Queue_Efficiency) + γ×(Signal_Stability), where α, β, γ are weight coefficients representing response time ratio, queue processing efficiency, and signal stability, respectively. At the same time, a transmission performance scoring formula: Transfer_Score =(DMA_Speed × Burst_Length) / (Setup_Time + Switching_Overhead) is introduced to evaluate the data transmission efficiency.

[0089] The embodiment first realizes reliable interrupt control through a deeply optimized task triggering mechanism. During the task information writing process, the system adopts a hierarchical writing strategy, first writing task parameters to a specified register space, and then determining the specific register location through offset address calculation. The organization of the base address register space adopts a segmented management manner, and different types of control information are mapped to independent address intervals to avoid access conflicts. The triggering of the doorbell register adopts an edge-sensitive manner, and the reliability of the trigger signal is ensured through a hardware level detection mechanism. During the configuration process of the interrupt status register, the system realizes fine-grained interrupt control by setting the interrupt mask bit, and can selectively enable or disable specific interrupt sources according to the task priority. Especially in the processing of multi-task concurrent scenarios, this fine interrupt control mechanism can effectively avoid the interrupt storm problem and ensure the stable operation of the system. The management of the interrupt vector table adopts a dynamic updating strategy, supporting flexible scheduling of the interrupt service program. This optimized triggering mechanism provides reliable interrupt support for task control.

[0090] The embodiment innovatively realizes an interrupt response mechanism. The activation of the interrupt controller adopts a step-by-step starting strategy, first completing basic configuration, and then gradually enabling each function. The entry address of the interrupt service program is obtained by a fast lookup table method, and efficient program jumping is realized through a pre-established vector mapping table. The sending of the task start signal adopts a synchronous mechanism to ensure that the FPGA can correctly receive the task start instruction. The update of the task status register adopts atomic operation to avoid state confusion caused by concurrent access. During the state recording process, the system adopts a multi-field design, which not only includes the basic execution state, but also records detailed progress information. This complete response mechanism significantly improves the reliability of task control.

[0091] The embodiment realizes efficient storage access through an optimized data transmission mechanism. After receiving the task signal, the FPGA first pre-fetches a certain number of descriptor information from the descriptor queue, and realizes fast access of data through the pre-fetch cache area. The analysis of the descriptor adopts a parallel processing manner, simultaneously extracting the source address and target address information. During the configuration process of the DMA controller, the system selects the optimal transmission parameters according to the data block characteristics, including burst length, address alignment mode, etc. The establishment of the transmission channel adopts a dedicated channel manner to avoid interference with other transmission operations. During the data writing process, the system ensures continuous storage of data through the pre-allocation mechanism of the storage unit, reducing access delay. This optimized transmission mechanism significantly improves the data throughput.

[0092] The embodiment establishes a complete state management framework. The read pointer update of the descriptor queue adopts a safe update mechanism to ensure the atomicity of the queue operation. The writing of the transmission completion flag adopts a state register bit field design to support the parallel recording of multiple states. By establishing a complete state tracking mechanism, the system realizes reliable monitoring of the entire task execution process. This optimized management mechanism provides reliable state support for task control.

[0093] The embodiment provides an innovative solution for task control. Through the optimized interrupt processing and data transmission mechanism, the system realizes the whole-process optimization from task triggering to data transmission. This reliable control mechanism provides efficient task management support for FPGA image processing. The technical solution of the embodiment has good scalability and can adapt to different sizes and types of processing requirements, providing reliable technical support for FPGA application development. Especially when processing complex task sequences, the optimization effect is more obvious.

[0094] In an embodiment of the FPGA parallel computing unit scheduling method for image processing in the present application, the following content can also be specifically included:

[0095] Step S601: Calculate the number of rows and columns of the two-dimensional cache array according to the image resolution and the data block size, allocate a fixed size of storage space for each cache unit, determine the write position of the data block according to the timestamp information, establish a cache address mapping table to record the storage position of the data block in the two-dimensional cache array, write the processed data block into the corresponding cache unit, and update the cache state table to record the storage state of the data block;

[0096] Step S602: Calculate the processing delay of the data block by reading the processing time field in the timestamp, adjust the buffer size according to the statistical value of the processing delay, configure the buffer threshold to control the read-write rate of the data block, write the processing state of the data block into the specified bit field of the state register, generate an interrupt request signal to notify the processing completion event, and update the interrupt flag bit of the interrupt state register.

[0097] Optionally, the embodiment is directed to the low efficiency of cache management, large processing delay fluctuation and unreliable state synchronization in FPGA image processing, and innovatively designs a set of adaptive cache management scheme. In the aspect of cache performance evaluation, the embodiment designs a cache efficiency score formula: Cache_Score = α × (Hit_Rate / Base_Rate) + β × (Space_Usage) + γ × (Access_Speed), wherein α, β and γ are weight coefficients, respectively representing hit rate ratio, space utilization and access speed. At the same time, the delay control score formula: Delay_Score = (Processing_Time × Block_Count) / (Buffer_Size + Sync_Cost) is introduced to evaluate the control effect of processing delay.

[0098] The embodiment first realizes efficient data management through a deeply optimized cache organization mechanism. In the design process of the two-dimensional cache array, the system calculates the optimal row and column configuration based on the resolution characteristics of the input image and the size parameters of the data block using a dynamic programming algorithm. The organization of the cache array adopts a hierarchical structure, including a data storage layer, an address mapping layer and a state management layer. The size of each cache unit is optimized according to the data block size to ensure efficient use of storage space. In order to improve access efficiency, the system considers the principle of data locality when allocating cache units, allocating adjacent data blocks to consecutive storage areas. Especially when processing large-scale image data, this optimized storage strategy can significantly reduce memory access delay. The analysis of timestamp information uses a fast lookup table method to determine the target position of the data block through a pre-established mapping relationship. The design of the cache address mapping table adopts a multi-level index structure to support fast position query and update. This optimized organization mechanism provides a reliable storage foundation for data management.

[0099] The embodiment innovatively realizes the data write-in mechanism. In the process of writing the processed data block, the system organizes the write-in operation in a pipeline manner. First, determine the write-in position through the timestamp, then check the state of the target position to ensure that no write-in conflict occurs. The write-in process uses atomic operation to avoid data confusion caused by concurrent access. The update of the cache state table uses bitmap, and each bit represents the usage state of the corresponding cache unit. The state information contains multiple fields, not only recording the basic occupation state, but also containing the validity flag of the data and the access count. This complete write-in mechanism significantly improves the reliability of data management.

[0100] The embodiment realizes efficient buffer management through an optimized delay control mechanism. In the calculation process of processing delay, the system uses a sliding window method to count the processing time of the data block. By analyzing the trend of the processing time, the system can predict the future processing load. The adjustment of the buffer size adopts an adaptive strategy, which dynamically changes the buffer capacity according to the statistical characteristics of the processing delay. When the processing delay is continuously increasing, the system appropriately increases the buffer size to provide more data cache space; when the processing delay is stable or decreasing, the buffer size is correspondingly reduced to avoid resource waste. The setting of the buffer threshold considers the generation rate and consumption rate of the data block, and controls the flow speed of the data by dynamically adjusting the threshold. This optimized control mechanism significantly improves the adaptability of the system.

[0101] The embodiment establishes a complete state synchronization framework. The design of the state register adopts a bit field structure, and different bit fields record the processing state, error flags and control information. The generation of the interrupt request signal adopts an edge trigger method to ensure reliable signal transmission. The update of the interrupt state register adopts an atomic operation to avoid the competition condition of state update. Through the establishment of a complete state management mechanism, the system realizes reliable monitoring of the whole data processing process. This optimized synchronization mechanism provides reliable state support for system cooperation.

[0102] The embodiment provides an innovative solution for buffer management. Through optimized cache organization and delay control, the system realizes whole-process optimization from data storage to state synchronization. This reliable management mechanism provides efficient data support for FPGA image processing. The technical solution of the embodiment has good scalability and can adapt to different scales and types of processing requirements, providing reliable technical support for FPGA application development. Especially when processing complex image processing tasks, the optimization effect is more obvious.

[0103] In an embodiment of the FPGA parallel computing unit scheduling method for image processing of the present application, the following contents can also be specifically included:

[0104] Step S701: The state tracker reads the cache state table of the two-dimensional cache array, checks the continuity of the data block according to the data block number, establishes a data block state mapping table to record the missing and repeated data block information, writes the data block state mapping table into a specific bit field of the state register, updates the detection counter of the state tracker, and generates a data block state detection report to record the position information of the abnormal data block;

[0105] Step S702: The host reads the state register to obtain the processing state of the data block, configures the read parameter of the direct memory access controller, reads the data block that has been processed from the dynamic random access memory to the system memory, updates the read state flag of the data block, writes the read completion flag to the field programmable gate array, clears the corresponding interrupt state bit, and releases the storage space occupied by the read data block.

[0106] Optionally, the embodiment is aimed at the problems of inaccurate state tracking, unreliable data integrity verification, and untimely resource release in FPGA image processing, and a state management scheme based on intelligent tracking is innovatively designed. In the aspect of state tracking evaluation, the embodiment designs a tracking efficiency score formula: Track_Score = α × (Detection_Speed / Base_Speed) + β × (Memory_Efficiency) + γ × (Recovery_Rate), wherein α, β, and γ are weight coefficients, respectively representing the detection speed ratio, memory utilization rate, and resource recovery rate. Meanwhile, an integrity score formula is introduced: Integrity_Score = (Valid_Blocks × Processing_Speed) / (Missing_Blocks + Duplicate_Blocks), which is used to evaluate the data integrity verification effect.

[0107] The embodiment first realizes reliable data verification through a deeply optimized state tracking mechanism. When reading the cache state table, the state tracker adopts a multi-level cache strategy to cache frequently accessed state information in a fast memory. The data block continuity check adopts a sliding window method to determine whether there is a missing or duplicate block by comparing the numbers of adjacent blocks. This checking mechanism not only considers the continuity of the number, but also verifies the correctness of the processing order in combination with the timestamp information. For detected abnormal conditions, the system adopts a classification processing strategy: for the missing data block, the expected position and adjacent block information are recorded to facilitate subsequent data recovery; for the duplicate data block, the timestamp is compared to determine which version of the data to keep. The establishment of the state mapping table adopts a multi-dimensional index structure to support fast query based on different conditions. This optimized tracking mechanism significantly improves the accuracy and efficiency of state detection. Especially when processing large-scale data, through parallel detection and pipeline processing, the system can complete real-time state verification, avoiding detection from becoming a performance bottleneck.

[0108] The embodiment innovatively realizes a state recording mechanism. When writing the state mapping table into the state register, the system adopts a bit field division strategy, and different types of state information are mapped to independent bit fields. This design not only improves storage efficiency, but also supports parallel state update operations. The update of the detection counter adopts an atomic operation, ensuring the accuracy of the count value. The generation of the state detection report adopts a hierarchical structure, including basic statistical information and detailed exception records. The report content not only records the location of the exception data block, but also includes possible cause analysis and recovery suggestions. This complete recording mechanism provides reliable data support for system maintenance and optimization. The system supports long-term performance analysis and fault diagnosis by establishing a state history database, which helps to find potential system problems.

[0109] The embodiment realizes efficient data transmission through an optimized readback mechanism. When reading the state register, the host adopts a batch reading strategy to obtain multiple related states at a time. During the configuration process of the DMA controller, the system dynamically adjusts the transmission parameters according to the data block characteristics and the current system load. For example, when the system load is light, the burst transmission length can be increased to improve data throughput; when the load is heavy, the transmission unit can be appropriately reduced to avoid affecting other operations. The data reading process adopts a prefetch mechanism to prepare the transmission parameters of the next data block while the current data block is being transmitted. This optimized transmission mechanism significantly reduces data reading delay. The writing of the completion flag and the clearing of the interrupt state adopt synchronous operations to ensure the consistency of state updates.

[0110] The embodiment establishes a complete resource management framework. After the data block processing is completed, the system ensures the reliable recovery of resources through a multi-stage release process. First, update the read state of the data block to mark its releasable state; then clear the relevant control information, including the interrupt flag and state bit; finally, perform the actual storage space release operation. This progressive release mechanism avoids resource leakage. The system monitors the allocation and release of storage space in real time by establishing a resource usage tracking table, supporting intelligent resource scheduling. This optimized management mechanism significantly improves the resource utilization efficiency of the system.

[0111] The embodiment provides an innovative solution for state management. Through optimized state tracking and resource management, the system realizes full-process optimization from data verification to resource release. This reliable management mechanism provides a stable running environment for FPGA image processing. The technical scheme of the embodiment has good scalability and can adapt to different sizes and types of processing requirements, providing reliable technical support for FPGA application development. Especially when dealing with complex image processing tasks, the optimization effect is more obvious.

[0112] In order to effectively solve the deficiencies of traditional technology in data security, access control and privacy protection, and significantly improve the security and reliability of FPGA parallel computing, the present application provides an embodiment of an image processing oriented FPGA parallel computing unit scheduling device for implementing all or part of the contents of the image processing oriented FPGA parallel computing unit scheduling method, which is used for image processing, as shown in Figure 2 The image processing oriented FPGA parallel computing unit scheduling device specifically includes the following contents:

[0113] An image processing module 10 is configured to establish a data transmission channel between a host and a field programmable gate array through a PCIe interface, allocate a physically continuous memory region as a direct memory access buffer, create a descriptor queue in shared memory to record source address and target address information of data transmission, map the descriptor queue to a user space, configure burst transmission length and address alignment mode, calculate the optimal size of a data block according to image resolution and set an overlap region.

[0114] A data writing module 20 is configured to convert image data into grayscale values and divide the image data into a plurality of data blocks according to the optimal size, add boundary pixels to each data block and set a timestamp containing data block number and processing time, write the data blocks into the direct memory access buffer, trigger a doorbell register to send a task signal to the field programmable gate array, and the field programmable gate array pre-fetches descriptors from the descriptor queue and writes the data blocks into a dynamic random access memory.

[0115] A data scheduling module 30 is configured to construct a two-dimensional cache array and write processed data blocks into corresponding positions according to the timestamp, monitor processing delay and dynamically adjust buffer size, the field programmable gate array writes data block status into a status register and triggers an interrupt signal, a status tracker detects missing and repeated data blocks, the host reads the data blocks from the dynamic random access memory according to the content of the status register, and the host sends a data read completion signal to the field programmable gate array.

[0116] From the above description, the FPGA parallel computing unit scheduling device for image processing provided by the embodiment of the application can realize safe isolation and access control of data through innovative design of a data safe transmission mechanism, physical continuous memory allocation, and descriptor queue management. A data block encryption strategy based on a timestamp is constructed, dynamic buffer adjustment and state monitoring are combined, and a reliable data protection system is established. A processing delay monitoring mechanism is introduced, real-time performance evaluation and resource scheduling are performed, and the privacy of the data processing process is ensured. On the basis of data encryption transmission, the method effectively solves the deficiencies of traditional technologies in data security, access control, privacy protection, and the like, and significantly improves the security and reliability of FPGA parallel computing.

[0117] From the hardware level, in order to effectively solve the deficiencies of traditional technologies in data security, access control, privacy protection, and the like, and significantly improve the security and reliability of FPGA parallel computing, the application provides an embodiment of an electronic device for implementing all or part of the contents of the FPGA parallel computing unit scheduling method for image processing, which specifically includes the following contents:

[0118] A processor, a memory, a communications interface, and a bus; wherein the processor, the memory, and the communications interface complete communication with each other through the bus; the communications interface is used to realize information transmission between the FPGA parallel computing unit scheduling device for image processing and related devices such as a core business system, a user terminal, and a related database; the logic controller can be a desktop computer, a tablet computer, a mobile terminal, and the like, and the embodiment is not limited thereto. In the embodiment, the logic controller can be implemented by referring to the embodiment of the FPGA parallel computing unit scheduling method for image processing and the embodiment of the FPGA parallel computing unit scheduling device for image processing, the contents of which are incorporated herein, and repeated descriptions are not given.

[0119] It can be understood that the user terminal can include a smart phone, a tablet electronic device, a network set-top box, a portable computer, a desktop computer, a personal digital assistant (PDA), a vehicle-mounted device, a smart wearable device, and the like. The smart wearable device can include smart glasses, a smart watch, a smart bracelet, and the like.

[0120] In practical applications, part of the image processing-oriented FPGA parallel computing unit scheduling method can be executed on the electronic device as described above, or all operations can be completed in the client device. Specifically, the processing capacity of the client device and the user's use scenario restrictions can be selected. The present application does not limit this. If all operations are completed in the client device, the client device can also include a processor.

[0121] The above-mentioned client device can have a communication module (i.e. a communication unit) and can be communicatively connected to a remote server to achieve data transmission with the server. The server can include a server on the task scheduling center side, and other implementation scenarios can also include a server of an intermediate platform, such as a server of a third-party server platform communicatively linked to the task scheduling center server. The server can include a single computer device, a server cluster composed of multiple servers, or a distributed server structure.

[0122] Figure 3 A schematic block diagram of the system configuration of the electronic device 9600 of the embodiment of the present application is shown in FIG. 9. As shown in the figure, the electronic device 9600 can include a central processor 9100 and a memory 9140; the memory 9140 is coupled to the central processor 9100. It is worth noting that the structure shown in the figure is exemplary; other types of structures can also be used to supplement or replace the structure to achieve telecommunication functions or other functions. Figure 3 Figure 3 The structure shown in the figure is exemplary; other types of structures can also be used to supplement or replace the structure to achieve telecommunication functions or other functions.

[0123] In an embodiment, the image processing-oriented FPGA parallel computing unit scheduling method function can be integrated into the central processor 9100. The central processor 9100 can be configured to control as follows:

[0124] Step S101: establishing a data transmission channel between the host and the field programmable gate array through the PCIe interface, allocating a physically continuous memory region as a direct memory access buffer, creating a descriptor queue in the shared memory to record the source address and target address information of data transmission, mapping the descriptor queue to the user space, configuring the burst transmission length and address alignment mode, calculating the optimal size of the data block according to the image resolution and setting the overlap region;

[0125] ​Step S102: converting the image data into gray scale values and dividing the image data into a plurality of data blocks according to the optimal size, adding boundary pixels to each of the data blocks and setting a timestamp containing a data block number and a processing time, writing the data blocks into the DMA buffer, triggering a doorbell register to send a task signal to the FPGA, the FPGA pre-fetching descriptors from the descriptor queue and writing the data blocks into the DRAM;

[0126] Step S103: constructing a two-dimensional cache array and writing the processed data blocks into corresponding positions according to the timestamp, monitoring the processing delay and dynamically adjusting the buffer size, the FPGA writing the data block state into a state register and triggering an interrupt signal, detecting the absence and repetition of the data blocks through a state tracker, the host reading the data blocks from the DRAM according to the content of the state register, and the host sending a data reading completion signal to the FPGA.

[0127] As can be seen from the above description, the electronic device provided by the embodiment of the application realizes the secure isolation and access control of data by innovatively designing a data secure transmission mechanism, through physical continuous memory allocation and descriptor queue management. A data block encryption strategy based on a timestamp is constructed, combined with dynamic buffer adjustment and state monitoring, to establish a reliable data protection system. A processing delay monitoring mechanism is introduced to ensure the privacy of the data processing process through real-time performance evaluation and resource scheduling. The method effectively solves the deficiencies of traditional technologies in data security, access control and privacy protection, etc. on the basis of data encryption transmission, and significantly improves the security and reliability of FPGA parallel computing.

[0128] In another embodiment, the FPGA parallel computing unit scheduling device for image processing can be configured separately from the central processor 9100, for example, the FPGA parallel computing unit scheduling device for image processing can be configured as a chip connected with the central processor 9100 to realize the function of the FPGA parallel computing unit scheduling method for image processing through the control of the central processor.

[0129] As shown in Figure 3 , the electronic device 9600 can also include a communication module 9110, an input unit 9120, an audio processor 9130, a display 9160, and a power supply 9170. It should be noted that the electronic device 9600 does not necessarily include all the components shown in Figure 3 ; in addition, the electronic device 9600 can also include components not shown in Figure 3 , which can refer to prior art.

[0130] As shown in Figure 3As shown, the central processing unit 9100, which is sometimes also referred to as a controller or operation control, can include a microprocessor or other processor device and / or logic device, which receives input and controls the operation of the various components of the electronic device 9600.

[0131] The memory 9140, for example, can be one or more of a buffer, a flash memory, a hard drive, a removable media, a volatile memory, a non-volatile memory, or other suitable device. Information relating to failures can be stored, and in addition, programs for executing the information can be stored. The central processing unit 9100 can execute the programs stored in the memory 9140 to achieve information storage or processing, etc.

[0132] The input unit 9120 provides input to the central processing unit 9100. The input unit 9120 is, for example, a key or touch input device. The power supply 9170 is used to provide power to the electronic device 9600. The display 9160 is used to display display objects such as images and text. The display can be, for example, an LCD display, but is not limited thereto.

[0133] The memory 9140 can be a solid state memory such as a read only memory (ROM), a random access memory (RAM), a SIM card, etc. It can also be a memory that retains information even when power is off, can be selectively erased, and is provided with more data, examples of which are sometimes referred to as EPROM, etc. The memory 9140 can also be some other type of device. The memory 9140 includes a buffer memory 9141 (sometimes referred to as a buffer). The memory 9140 can include an application / function storage section 9142 for storing application programs and function programs or for storing a flow for executing the operation of the electronic device 9600 by the central processing unit 9100.

[0134] The memory 9140 can also include a data storage section 9143 for storing data such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. A driver program storage section 9144 of the memory 9140 can include various driver programs of the electronic device for a communication function and / or for executing other functions of the electronic device such as a messaging application, an address book application, etc.

[0135] The communication module 9110 is a transmitter / receiver that transmits and receives signals via an antenna 9111. The communication module 9110 (transmitter / receiver) is coupled to the central processing unit 9100 to provide input signals and receive output signals, which can be the same as in the case of a conventional mobile communication terminal.

[0136] Based on different communication technologies, multiple communication modules 9110, such as a cellular network module, a Bluetooth module, and / or a wireless local area network module, etc., can be provided in the same electronic device. The communication module 9110 (transmitter / receiver) is also coupled to a speaker 9131 and a microphone 9132 via an audio processor 9130 to provide audio output via the speaker 9131 and to receive audio input from the microphone 9132, thereby enabling the usual telecommunication functions. The audio processor 9130 can include any suitable buffers, decoders, amplifiers, etc. In addition, the audio processor 9130 is also coupled to the central processor 9100, thereby enabling the recording of sounds on the spot via the microphone 9132 and the playing of sounds stored on the spot via the speaker 9131.

[0137] The embodiment of the present application further provides a computer readable storage medium capable of implementing all steps of the image processing oriented FPGA parallel computing unit scheduling method with the execution subject being a server or a client in the above-mentioned embodiment, wherein a computer program is stored on the computer readable storage medium, and the computer program is executed by a processor to implement all steps of the image processing oriented FPGA parallel computing unit scheduling method with the execution subject being a server or a client in the above-mentioned embodiment, for example, the steps of:

[0138] Step S101: establishing a data transmission channel between a host and a field programmable gate array through a PCIe interface, allocating a physically continuous memory region as a direct memory access buffer, creating a descriptor queue in a shared memory to record source address and target address information of data transmission, mapping the descriptor queue to a user space, configuring burst transmission length and address alignment mode, calculating an optimal size of a data block according to an image resolution and setting an overlap region;

[0139] Step S102: converting image data into gray value and dividing the image data into a plurality of data blocks according to the optimal size, adding boundary pixels to each data block and setting a timestamp containing a data block number and a processing time, writing the data blocks into the direct memory access buffer, triggering a doorbell register to send a task signal to the field programmable gate array, and the field programmable gate array prefetches a descriptor from the descriptor queue and writes the data blocks into a dynamic random access memory;

[0140] Step S103: constructing a two-dimensional cache array and writing the processed data block to the corresponding position according to the timestamp, monitoring the processing delay and dynamically adjusting the buffer size, the FPGA writes the data block state to the state register and triggers an interrupt signal, the state tracker detects the absence and repetition of the data block, the host reads the data block from the DRAM according to the content of the state register, and the host sends a data read completion signal to the FPGA.

[0141] As can be seen from the above description, the computer readable storage medium provided by the embodiments of the application realizes the secure isolation and access control of data through the innovative design of the data security transmission mechanism, the physical continuous memory allocation and the descriptor queue management. The data block encryption strategy based on the timestamp is constructed, the reliable data protection system is established by combining the dynamic buffer adjustment and the state monitoring, the processing delay monitoring mechanism is introduced, and the privacy of the data processing process is ensured through real-time performance evaluation and resource scheduling. On the basis of data encryption transmission, the method effectively solves the deficiencies of the traditional technology in data security, access control and privacy protection, and significantly improves the security and reliability of FPGA parallel computing.

[0142] The embodiments of the application also provide a computer program product capable of implementing all steps of the image processing-oriented FPGA parallel computing unit scheduling method in which the execution subject is a server or a client. The computer program / instruction is executed by a processor to implement the steps of the image processing-oriented FPGA parallel computing unit scheduling method, for example, the computer program / instruction implements the following steps:

[0143] Step S101: establishing a data transmission channel between the host and the FPGA through the PCIe interface, allocating a physically continuous memory region as a DMA buffer, creating a descriptor queue in the shared memory to record the source address and target address information of data transmission, mapping the descriptor queue to the user space, configuring the burst transmission length and address alignment mode, calculating the optimal size of the data block according to the image resolution and setting the overlap region;

[0144] Step S102: converting the image data into grayscale values and dividing them into multiple data blocks according to the optimal size, adding boundary pixels to each data block and setting a timestamp containing the data block number and processing time, writing the data block into the DMA buffer, triggering the doorbell register to send a task signal to the FPGA, and the FPGA prefetches descriptors from the descriptor queue and writes the data block into the DRAM;

[0145] Step S103: constructing a two-dimensional cache array and writing the processed data block to the corresponding position according to the timestamp, monitoring the processing delay and dynamically adjusting the buffer size, the FPGA writes the data block state to the state register and triggers an interrupt signal, the state tracker detects the absence and repetition of the data block, the host reads the data block from the DRAM according to the content of the state register, and the host sends a data read completion signal to the FPGA.

[0146] From the above description, the computer program product provided by the embodiment of the present application realizes the safe isolation and access control of data through the innovative design of the data security transmission mechanism, the physical continuous memory allocation and the descriptor queue management. The data block encryption strategy based on the timestamp is constructed, the reliable data protection system is established by combining the dynamic buffer adjustment and the state monitoring, the processing delay monitoring mechanism is introduced, and the privacy of the data processing process is ensured through the real-time performance evaluation and the resource scheduling. The method effectively solves the deficiencies of the traditional technology in the data security, the access control and the privacy protection and the like on the basis of the data encryption transmission, and significantly improves the security and reliability of the FPGA parallel computing.

[0147] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, device, or computer program product. Therefore, the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program codes.

[0148] The present application is described with reference to flowcharts and / or block diagrams of the method, device (apparatus), and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device that implements the flowcharts and / or block diagrams. Figure 1 The device that implements the function specified in one flow or multiple flows and / or blocks Figure 1 The device that implements the function specified in one flow or multiple flows and / or blocks

[0149] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the flow Figure 1 The functions of a flow or multiple flows and / or a block or multiple blocks in conjunction with the disclosed methods can be implemented on practitioners' computers in computer software, firmware, hardware, or combinations of them. Figure 1

[0150] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flow Figure 1 The functions of a flow or multiple flows and / or a block or multiple blocks in conjunction with the disclosed methods can be implemented on practitioners' computers in computer software, firmware, hardware, or combinations of them. Figure 1

[0151] The principles and implementations of the present application are described in the specific embodiments, the above examples are only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation and application range will be changed, and the above description should not be understood as the limitation of the present application.​​

Claims

1. An FPGA parallel computing unit scheduling method for image processing, characterized in that, The method comprises: A data transmission channel is established between the host and the field programmable gate array through the PCIe interface, a physically continuous memory region is allocated as a direct memory access buffer, a descriptor queue is created in the shared memory to record the source address and target address information of data transmission, the descriptor queue is mapped to the user space, the burst transmission length and address alignment mode are configured, the optimal size of the data block is calculated according to the image resolution and the overlap region is set; The image data is converted into gray value and divided into a plurality of data blocks according to the optimal size, boundary pixels are added to each data block and a timestamp containing the data block number and processing time is set, the data block is written into the direct memory access buffer, a doorbell register is triggered to send a task signal to the field programmable gate array, the field programmable gate array prefetches a descriptor from the descriptor queue and writes the data block into a dynamic random access memory; A two-dimensional cache array is constructed and the data block processed is written into the corresponding position according to the timestamp, the processing delay is monitored and the buffer size is dynamically adjusted, the field programmable gate array writes the data block state into a state register and triggers an interrupt signal, the absence and repetition of the data block are detected through a state tracker, the host reads the data block from the dynamic random access memory according to the content of the state register, and the host sends a data reading completion signal to the field programmable gate array.

2. The image processing oriented FPGA parallel computing unit scheduling method of claim 1, wherein, The data transmission channel is established between the host and the field programmable gate array through the PCIe interface, a physically continuous memory region is allocated as a direct memory access buffer, and a descriptor queue is created in the shared memory to record the source address and target address information of data transmission, comprising: The host loads a PCIe device driver program and enables an interrupt response mechanism, allocates a physically continuous memory region through a kernel module and registers it as a direct memory access buffer, maps the direct memory access buffer to a user space address, configures the PCIe link to be the third generation specification and sets the link width, starts a bus master to connect the PCIe interface to an advanced extensible interface bus; The field programmable gate array loads the IP core configuration parameters of the PCIe, configures the advanced extensible interface memory mapping protocol and the advanced extensible interface reduced interface protocol, creates a descriptor queue in the shared memory to record the source address and target address information of data transmission, sets the size of the direct memory access receiving buffer and the sending buffer according to the system requirements, configures the burst transmission length and address alignment mode, and establishes an interrupt vector table to bind the task identifier and the interrupt processing function.

3. The image processing oriented FPGA parallel computing unit scheduling method of claim 1, wherein, The descriptor queue is mapped to the user space, the burst transmission length and address alignment mode are configured, the optimal size of the data block is calculated according to the image resolution and the overlap region is set, comprising: Mapping a physical address space of the descriptor queue to a process virtual address space through a memory mapping function, configuring a base address register space to enable access to control registers and status registers, setting a direct memory access burst transfer length to an integer multiple of a basic transfer unit, configuring an address boundary alignment mode to ensure data access efficiency, and writing read-write pointer update information of the descriptor queue to a doorbell register; Calculating an optimal size of a single data block based on a width and a height of an input image, setting the data block size to an integer multiple of a processing unit computing capacity, establishing an overlapping area mapping relationship between adjacent data blocks, calculating a pixel width of the overlapping area to ensure boundary pixel continuity, and writing the data block size and overlapping area parameters to a configuration register to generate a data block index table recording block correlation information.

4. The image processing oriented FPGA parallel computing unit scheduling method of claim 1, wherein, The image data is converted to grayscale values and divided into multiple data blocks according to the optimal size, boundary pixels are added to each data block, and a timestamp containing data block number and processing time is set, and the data blocks are written to the direct memory access buffer, including: Converting an RGB color space of an input image to a grayscale image, dividing the grayscale image data into multiple data blocks based on the optimal size, adding boundary pixels around each data block to form an extended data block, calculating position information of the extended data block in a global coordinate system, generating a data block descriptor containing a start address and an end address, and assigning a globally unique data block number to each data block; A timestamp management unit is created to record the processing status of the data blocks, the timestamp contains two time attribute fields of data block number and data block processing time, a timestamp mapping table is established to store the timing information of the data blocks, the data blocks and their corresponding timestamp information are written to a specified location in the direct memory access buffer, and a data block status register is updated to record a transfer completion flag.

5. The image processing oriented FPGA parallel computation unit scheduling method of claim 1, wherein, The trigger doorbell register sends a task signal to the field programmable gate array, the field programmable gate array prefetches descriptors from the descriptor queue and writes the data blocks to the dynamic random access memory, including: Writing task information to a specified offset address in the base address register space, triggering the doorbell register to generate an interrupt request signal, configuring an interrupt mask bit of the interrupt status register, activating the interrupt controller to enable interrupt response, reading an interrupt vector table to obtain an interrupt service program entry address, sending a task start signal to the field programmable gate array, and updating a task status register to record the task execution status; The field programmable gate array reads descriptor information from the descriptor queue to a prefetch buffer, parses the descriptors to obtain source and target addresses of the data blocks, configures transfer parameters of the direct memory access controller, establishes a burst transfer channel to write the data blocks to a specified storage unit of the dynamic random access memory, updates a read pointer of the descriptor queue, and writes a data block transfer completion flag to a status register.

6. The image processing oriented FPGA parallel computation unit scheduling method of claim 1, wherein, The construction of the two-dimensional cache array and the writing of the processed data block into the corresponding position according to the timestamp, the monitoring of the processing delay and the dynamic adjustment of the buffer size, the FPGA writing of the data block state into the state register and the triggering of the interrupt signal, comprising: According to the image resolution and the data block size, the number of rows and columns of the two-dimensional cache array is calculated, a fixed size of storage space is allocated for each cache unit, the timestamp information is read to determine the writing position of the data block, the cache address mapping table is established to record the storage position of the data block in the two-dimensional cache array, the processed data block is written into the corresponding cache unit, and the cache state table is updated to record the storage state of the data block; The processing time field in the timestamp is read to calculate the processing delay of the data block, the buffer size is adjusted according to the statistical value of the processing delay, the buffer threshold is configured to control the read-write rate of the data block, the FPGA writes the processing state of the data block into the specified bit domain of the state register, generates an interrupt request signal to notify the processing completion event, and updates the interrupt flag bit of the interrupt state register.

7. The image processing oriented FPGA parallel computation unit scheduling method of claim 1, wherein, The state tracker detects the absence and repetition of the data block, the host reads the data block from the DRAM according to the content of the state register, and the host sends a data read completion signal to the FPGA, comprising: The state tracker reads the cache state table of the two-dimensional cache array, checks the continuity of the data block according to the data block number, establishes a data block state mapping table to record the missing and repeated data block information, writes the data block state mapping table into the specific bit domain of the state register, updates the detection counter of the state tracker, and generates a data block state detection report to record the position information of the abnormal data block; The host reads the processing state of the data block from the state register, configures the read parameters of the DMA controller, reads the processed data block from the DRAM into the system memory, updates the read state flag of the data block, writes the read completion flag to the FPGA, clears the corresponding interrupt state bit, and releases the storage space occupied by the read data block.

8. An FPGA parallel computing unit scheduling device for image processing, characterized in that, The device comprises: An image processing module is configured to establish a data transmission channel between the host and the FPGA through the PCIe interface, allocate a physically continuous memory region as a DMA buffer, create a descriptor queue in the shared memory to record the source and target address information of data transmission, map the descriptor queue to the user space, configure the burst transmission length and address alignment mode, calculate the optimal size of the data block according to the image resolution and set the overlap region; A data writing module is configured to convert the image data into grayscale values and divide them into multiple data blocks according to the optimal size, add boundary pixels to each data block and set a timestamp containing the data block number and processing time, write the data block into the DMA buffer, trigger the doorbell register to send a task signal to the FPGA, and the FPGA prefetches the descriptor from the descriptor queue and writes the data block into the DRAM. A data scheduling module is configured to construct a two-dimensional cache array and write processed data blocks to corresponding positions according to the timestamps, monitor processing delays and dynamically adjust the size of the buffer, the FPGA writes data block states to a state register and triggers an interrupt signal, the state tracker detects missing and repeated data blocks, the host reads the data blocks from the DRAM according to the content of the state register, and the host sends a data read completion signal to the FPGA.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to implement the steps of the image processing-oriented FPGA parallel computing unit scheduling method of any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the image processing-oriented FPGA parallel computing unit scheduling method of any one of claims 1 to 7.

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