Parameter design method for satellite MOSFET surge suppression circuit

Abstract

The invention provides a satellite MOSFET surge suppression circuit parameter design method, which comprises the steps of adding a capacitor C1 between a grid electrode and a source electrode of an MOSEFT device, and adding a current-limiting resistor R5 at a grid electrode input end of the MOSEFT device; according to the Kirchhoff theorem and the relation formula of the voltage and the current of the capacitor, a voltage expression at the two ends of the capacitor C1 is obtained, and a time mathematical model from the grid voltage to MOSEFT conduction is established; estimating the duration of the surge current according to the maximum value of the surge current, the load bus voltage and the filter capacitance; calculating a divider resistance parameter of the satellite MOSFET gate drive circuit; and calculating the parameter of the capacitor C1. The method has the advantages that the MOSEFT surge suppression circuit is simple and effective in design, and the surge current suppression effect is well achieved.

Description

Technical Field

[0001] The present application relates to the field of aerospace payload circuit design, and specifically to a method for designing parameters of a MOSFET surge suppression circuit for satellites. Background Art

[0002] Because satellite-borne payloads utilize DC-DC power supplies and filtering modules, a short-duration, high-peak surge current is generated the moment the bus power supply is powered on. This can cause the payload equipment to malfunction or even be damaged. Adding a surge suppression circuit between the load bus terminal and the filtering module not only increases the transient time of the surge current but also suppresses the peak value of the surge current, allowing the load to function properly. Therefore, surge suppression circuit design is an essential component of the payload power supply. Traditional methods utilize large inductors in series with capacitors or SCRs with resistors to suppress surge current. This not only increases the size and weight of the power supply, but also reduces power conversion efficiency due to the series resistor. Therefore, it is of great significance to study the analysis and parameter design methods of MOS-EFT (Metal-Oxide-Semiconductor Field-Effect Transistor) surge suppression circuits. Summary of the Invention

[0003] The purpose of this application is to overcome the problem that surge current occurs at the moment of power-on of the satellite-borne load busbar, which can cause serious damage to the load.

[0004] In order to achieve the above-mentioned purpose, the present application proposes a parameter design method for a star MOSFET surge suppression circuit, wherein the MOSFET surge suppression circuit includes a MOSFET device and four voltage divider resistors R1, R2, R3 and R4; wherein,

[0005] The voltage-dividing resistors R1 and R2 are connected in parallel, connected to the source and gate of the MOSFET device respectively; the voltage-dividing resistors R3 and R4 are connected in parallel, connected to the gate of the MOSFET device and the negative pole of the satellite bus voltage respectively;

[0006] The method comprises:

[0007] Add capacitor C1 between the gate and source of the MOSFET device, and add current limiting resistor R5 at the gate input of the MOSFET device;

[0008] According to Kirchhoff's theorem and the relationship between capacitor voltage and current, the voltage expression of capacitor C1 is obtained, and the mathematical model of the time from gate voltage to MOSFET conduction is established;

[0009] Estimate the duration of the inrush current based on the maximum inrush current, load bus voltage, and filter capacitance;

[0010] Calculate the voltage divider resistor parameters of the star MOSFET gate drive circuit;

[0011] Calculate the parameters of capacitor C1.

[0012] As an improvement to the above method, the resistance range of the current limiting resistor R5 is 10K to 1000K ohms.

[0013] As an improvement to the above method, the voltage U across the capacitor C1 is C1 The expression is:

[0014]

[0015] Where E is the load bus voltage; t is time; τ1 is the charging time constant of capacitor C1:

[0016]

[0017] Among them, R1, R2, R3 and R4 are the voltage divider resistors of the MOSFET gate drive circuit.

[0018] As an improvement to the above method, the mathematical model of the time from gate voltage to MOSFET conduction is:

[0019]

[0020] Among them, t s is the charging time of capacitor C1; E is the load bus voltage; R1, R2, R3 and R4 are the voltage divider resistors of the MOSFET gate drive circuit; U GS is the MOSFET gate voltage.

[0021] As an improvement to the above method, the duration of the surge current T s0 The estimation method is:

[0022]

[0023] Where E is the load bus voltage; I inrush_max is the maximum value of the surge current; C filter For the filter capacitor.

[0024] As an improvement to the above method, the voltage divider resistance of the star MOSFET gate drive circuit is calculated using the following formula:

[0025]

[0026] Among them, U GSTH is the on-state voltage of MOSFET;

[0027] At the same time, R1, R2, R3 and R4 satisfy: R1 = R2, R3 = R4; and the resistance value is between 10K and 1000K ohms.

[0028] As an improvement to the above method, the capacitance C1 is calculated as follows:

[0029]

[0030] Where E is the load bus voltage; I inrush_max is the maximum value of the surge current; C filter is the filter capacitor; R1, R2, R3 and R4 are the voltage divider resistors of the MOSFET gate drive circuit; U M is the Miller plateau voltage.

[0031] Compared with the prior art, the advantages of this application are:

[0032] This paper discloses a method for designing parameters for a satellite-based MOSFET surge suppression circuit. It proposes a novel equivalent method for estimating the duration of a surge current and provides a detailed parameter design method for the surge suppression circuit. This method addresses the problem of suppressing the severe damage to the load caused by the surge current that occurs when the satellite's load bus is powered on. This method simplifies and effectively designs the MOSFET surge suppression circuit and effectively achieves surge current suppression. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Shown is the MOSEFT surge suppression circuit diagram;

[0034] Figure 2 The figure shows the surge current waveform.

[0035] Figure 3 Shown is a schematic diagram for estimating the duration of inrush current;

[0036] Figure 4 The figure shows the flow chart of the parameter design method of the MOSFET surge suppression circuit for star applications. DETAILED DESCRIPTION

[0037] The technical solution of this application is described in detail below with reference to the accompanying drawings.

[0038] like Figure 1 As shown, E is the satellite bus voltage, C filterThe load-side filter capacitor is a MOSFET surge suppression circuit. The satellite-based MOSFET is an existing technology and primarily includes: 1) a MOSFET device; 2) four resistors, R1, R2, R3, and R4, that form a MOSFET gate drive circuit. R1, R2, R3, and R4 are voltage divider resistors in the MOSFET gate drive circuit. R1 and R2 are connected in parallel, connecting the MOSFET device's source and gate, respectively; and R3 and R4 are connected in parallel, connecting the MOSFET device's gate and the negative pole of the satellite's onboard bus voltage, respectively.

[0039] The star MOSFET surge suppression circuit parameter design method provided in this application transforms the MOSFET surge suppression circuit by adding a capacitor C1 between the gate and source of the MOSFET device and adding a current limiting resistor R5 at the gate input end of the MOSFET device.

[0040] like Figure 4 As shown in FIG, the parameter design method of the MOS EFT surge suppression circuit for star use includes the following steps:

[0041] Step 1: Load bus voltage E and MOSFET gate voltage U GS Take samples;

[0042] Step 2: Analyze the conduction process of MOSSEFT, which is mainly divided into the following four stages:

[0043] The first stage is the MOSFET gate voltage U GS From zero to the on-state voltage U GSTH , at this stage the gate current is the parasitic capacitance C between the MOSFET gate and source gs Charging, MOSEFT is in cut-off state;

[0044] The second stage is the MOSFET gate voltage U GS From the on-state voltage U GSTH Increase to Miller platform voltage U M In this stage, the gate current is not only the parasitic capacitance C between the gate and source of MOSFET gs Charge and return the parasitic capacitance C of the MOSFET gate and drain gd During charging, MOSFET works in the variable resistance region, and the drain current ID of MOSFET increases from zero.

[0045] The third stage is the MOSFET gate voltage U GS The voltage U increases to the Miller platform and remains approximately unchanged. At this stage, the gate current gives the parasitic capacitance C of the MOSFET gate and drain. gd Charging, MOSFET works in the saturation region, the drain current I D Approximately remains unchanged, MOSFET is fully turned on;

[0046] The fourth stage is the MOSFET gate voltage U GS From the platform voltage U M Increased to the voltage provided by the driving circuit, at this stage the gate current to the capacitor C gs and C gd Charging, MOSFET is fully turned on.

[0047] like Figure 2 As shown in the figure, the four stages of MOSSEFT operation are analyzed. The duration of MOSSEFT in the second and third stages is very short. However, high-speed switching is not required when MOSSEFT is used in surge suppression circuits. For this purpose, a suitable capacitor C1 (C1>>C gs ) to increase the working time of MOSFET in the second stage, so that the filter capacitor C filter The charging time is increased by the current i flowing through the capacitor Cfilter Equal to the capacitance value C filter The product of the rate of change of the voltage across the capacitor with time is i Cfilter =C filter (du Cfilter / dt), where the rate of change of the voltage across the capacitor with time is du Cfilter / dt, it can be seen that when the numerator on the right side of the equal sign remains unchanged and the denominator increases, the value on the right side of the equal sign decreases. Therefore, it can be considered that the duration of the MOSFET surge suppression circuit will affect the current value. Therefore, this application proposes that the duration of the MOSFET in the second stage needs to be greater than the duration of the pre-calculated surge current, T s2 It can be roughly considered as the working time of MOSEFT in the second stage, T s0 is the duration of the surge current, T s2 Greater than T s0 This can suppress the inrush current;

[0048] Step 3: Based on Kirchhoff's theorem and the relationship between capacitor voltage and current, derive the voltage expression across capacitor C1 and establish a mathematical model of the time from gate voltage to MOSFET conduction. The process is as follows:

[0049] The gate voltage is the voltage across capacitor C1. To establish a time model for C1 charging, first solve the charging time constant τ1 of capacitor C1:

[0050] τ1=[(R1 / / R2) / / (R3 / / R4)]C1 (1)

[0051] Among them, R1, R2, R3, and R4 are the voltage divider resistors of the MOSFET gate drive circuit; / / is the parallel symbol.

[0052] Arrange formula (1) to obtain:

[0053]

[0054] Voltage U across capacitor C1 C1 for:

[0055]

[0056] Where, E is the load bus voltage; t is time.

[0057] Voltage U across capacitor C1 C1 Gate voltage U GS Equal, from equations (2) and (3), the mathematical model of MOSFET gate voltage and C1 charging time can be obtained as follows:

[0058]

[0059] Among them, U GS is the MOSFET gate voltage.

[0060] Step 4: In the MOS EFT surge suppression circuit, it is necessary to precalculate the duration of the surge current T s0 , this application proposes a new equivalent method to estimate the duration of surge current T s0 Filter capacitor C filter The amount of charge Q in the circuit is equal to the surge current i flowing through the circuit inrush and time t, but since the current is constantly changing, the value of Q should be:

[0061]

[0062] like Figure 3 As shown, due to the surge current i inrush The function of (t) is unknown, and the charge cannot be calculated by formula (5). However, the maximum value of the expected surge current can be calculated by the rated current of the load. Generally, the maximum value of the expected surge current I inrush_max Less than twice the rated current I rated , and the surge current waveform at the load bus terminal is "slope-shaped peak" so Q is i inrush The area enclosed by (t) and the time axis can be equivalently approximated as:

[0063]

[0064] Output filter capacitor C filter The charge calculation formula is:

[0065] Q=E·C filter(7)

[0066] The duration T of the pre-calculated surge current can be obtained from equations (6) and (7): s0 The values ​​are:

[0067]

[0068] Step 5: Calculate the resistance parameters in the MOSFET gate power supply circuit; design the MOSFET gate drive circuit resistance parameters. The values ​​of R1, R2, R3, and R4 in the charging circuit of the MOSFET gate and source capacitor C1 should meet the following requirements:

[0069]

[0070] Where U GSTH is the on-state voltage of MOSFET.

[0071] In the circuit, the design of arranging R1, R2, R3, and R4 in parallel and then in series can match more accurate resistance values, reduce random errors of resistance, and improve circuit reliability. Therefore, during design, R1 = R2 and R3 = R4 can be made. At the same time, in order to reduce the power loss of the circuit, the resistance values ​​of R1, R2, R3, and R4 can be selected from tens of K to hundreds of K ohms (10K to 1000K ohms). At the same time, the parameter values ​​of R1, R2, R3, and R4 can be calculated by satisfying formula (9).

[0072] Step 6: Design the MOSFET gate drive circuit capacitance parameters. The process is as follows:

[0073] In order to suppress the surge current, it is necessary to add a suitable capacitor C1 to the gate and source of the MOSFET to increase the working time T of the MOSFET in the second stage. s2 , T s2 It can be calculated with the mathematical model of capacitor C1 charging time, T s2 It can be roughly considered as the duration of the MOSFET surge suppression circuit, T s2 The duration T of the surge current must be greater than s0 In order to effectively suppress the surge current, the capacitance range of the parallel capacitor C1 between the MOSFET gate and source can be calculated; when the voltage across C1 is U M At this moment, the charging time is T s2 :

[0074]

[0075] At this time, T s2 It can be roughly considered as the duration of the MOSFET surge suppression circuit, T s2The duration T of the surge current must be greater than s0 In order to effectively suppress the surge current, it is necessary to meet the following requirements:

[0076] T s2 >T s0 (11)

[0077] From equations (8), (10) and (11), it can be concluded that the value of capacitor C1 should satisfy:

[0078]

[0079] Step 7: Arrange the parameters in steps 5 and 6 to complete the design of the MOSSEFT surge suppression circuit and effectively suppress the surge current; R1, R2, R3, and R4 in the surge suppression circuit should satisfy equation (9), and the gate and source of the MOSSEFT plus a suitable capacitor C1 should satisfy equation (12). A current limiting resistor R5 needs to be added to the gate input of the MOSSEFT to ensure circuit safety. Its resistance can be from tens to hundreds of ohms. At this point, the design of the MOSSEFT surge suppression circuit is completed.

[0080] Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of this application and are not intended to limit the scope of the present invention. Although this application has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions to the technical solutions of this application do not depart from the spirit and scope of the technical solutions of this application and should be encompassed by the claims of this application.

Claims

1. A parameter design method for a MOSFET surge suppression circuit for satellites, wherein the MOSFET surge suppression circuit includes a MOSFET device and four voltage divider resistors R1, R2, R3 and R4; wherein, The voltage-dividing resistors R1 and R2 are connected in parallel, connected to the source and gate of the MOSFET device respectively; the voltage-dividing resistors R3 and R4 are connected in parallel, connected to the gate of the MOSFET device and the negative pole of the satellite bus voltage respectively; The method comprises: Add capacitor C1 between the gate and source of the MOSFET device, and add current limiting resistor R5 at the gate input of the MOSFET device; According to Kirchhoff's theorem and the relationship between capacitor voltage and current, the voltage expression of capacitor C1 is obtained, and the mathematical model of the time from gate voltage to MOSFET conduction is established; Estimate the duration of the inrush current based on the maximum inrush current, load bus voltage, and filter capacitance; Calculate the voltage divider resistor parameters of the star MOSFET gate drive circuit; Calculate the parameters of capacitor C1.

2. The method for designing parameters of a satellite MOSFET surge suppression circuit according to claim 1, characterized in that: The resistance range of the current limiting resistor R5 is 10K to 1000K ohms.

3. The satellite MOSFET surge suppression circuit parameter design method according to claim 1, characterized in that: The voltage U across the capacitor C1 C1 The expression is: Where E is the load bus voltage; t is time; τ1 is the charging time constant of capacitor C1: Among them, R1, R2, R3 and R4 are the voltage divider resistors of the MOSFET gate drive circuit.

4. The satellite MOSFET surge suppression circuit parameter design method according to claim 1, characterized in that: The mathematical model of the time from gate voltage to MOSFET conduction is: Among them, t s is the charging time of capacitor C1; E is the load bus voltage; R1, R2, R3 and R4 are the voltage divider resistors of the MOSFET gate drive circuit; U GS is the MOSFET gate voltage.

5. The satellite MOSFET surge suppression circuit parameter design method according to claim 1, characterized in that: The duration of the surge current T s0 The estimation method is: Where E is the load bus voltage; I inrush_max is the maximum value of the surge current; C filter For the filter capacitor.

6. The method for designing parameters of a satellite MOSFET surge suppression circuit according to claim 1, characterized in that: The voltage divider resistance of the star MOSFET gate drive circuit is calculated using the following formula: Among them, U GSTH is the on-state voltage of MOSFET; At the same time, R1, R2, R3 and R4 satisfy: R1 = R2, R3 = R4; and the resistance value is between 10K and 1000K ohms.

7. The method for designing parameters of a satellite MOSFET surge suppression circuit according to claim 1, characterized in that: The calculation method of the capacitor C1 is: Where E is the load bus voltage; I inrush_max is the maximum value of the surge current; C filter is the filter capacitor; R1, R2, R3 and R4 are the voltage divider resistors of the MOSFET gate drive circuit; U M is the Miller plateau voltage.

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