Chip patterning process bad point detection model training method, product and equipment

Abstract

The application provides a chip patterning process defect detection model training method, product and equipment. The method comprises the following steps: obtaining basic layout data used for training and basic scanning electron microscope images measured after the basic layout data undergoes a patterning process; a basic defect detection model is established according to the basic layout data and the corresponding basic scanning electron microscope images; simulation training data is generated through the basic defect detection model; and the simulation training data and actual measurement data are input into a preset neural network architecture for training to obtain an artificial intelligence defect detection model. Through this method, simulation data is generated by using a basic model to make up for the lack of actual measurement data, and the accuracy of the artificial intelligence defect detection model is ensured by combining the actual measurement data, which improves the accuracy of the defect detection model for actual measurement SEM on one hand, and replaces the traditional modeling system with an AI model, further improving the simulation speed of the model.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a bad point detection model training method, product and equipment in a chip patterning process. BACKGROUND

[0002] In the current field of semiconductor technology, the most core step in semiconductor chip manufacturing is to transfer the design pattern of the chip to the wafer, wherein the patterning process (such as photolithography and etching) is the core link of converting the design layout into the actual pattern of the wafer, and the process quality directly determines the yield and performance of the chip. However, due to factors such as equipment precision, material properties and process fluctuations, bad points are prone to occur after the patterning process, and if not detected and corrected in time, it will lead to functional failure of the chip. Therefore, efficient and accurate bad point detection technology is the key to ensuring product quality in semiconductor manufacturing.

[0003] The current deep learning-based artificial intelligence (AI) model is introduced into bad point detection, but this scheme relies heavily on high-quality actual training data: and in semiconductor manufacturing, it is extremely costly to obtain scanning electron microscope (SEM) images containing various types of bad points, and bad point samples are scarce, and the generalization ability of the artificial intelligence model trained only on actual data is weak, making it difficult to adapt to different process scenarios or new types of bad points, and the practicality is limited.

[0004] Therefore, how to solve the problem of lack of training data and improve the accuracy and adaptability of bad point detection has become a technical problem to be solved in the field of semiconductor technology. SUMMARY

[0005] In view of the above problems, the present application provides a bad point detection model training method, product and equipment in a chip patterning process, which overcomes the above problems or at least partially solves the above problems.

[0006] An object of the present application is to train a more accurate artificial intelligence bad point detection model;

[0007] Another further object of the present application is to improve the detection performance of the bad point detection model.

[0008] In particular, the present application provides a bad point detection model training method in a chip patterning process, comprising:

[0009] Obtaining basic layout data used for training and basic scanning electron microscope images measured after the basic layout data undergoes a patterning process;

[0010] Establishing a basic bad point detection model according to the basic layout data and the corresponding basic scanning electron microscope images;

[0011] generating simulation training data through a basic defect detection model;

[0012] inputting the simulation training data and actual measurement data into a preset neural network architecture for training to obtain an artificial intelligence defect detection model, the actual measurement data being actual scanning electron microscope images and corresponding actual layout data obtained after performing a patterning process on actual layout data.

[0013] Optionally, the step of inputting the simulation training data and actual measurement data into the preset neural network architecture for training to obtain the artificial intelligence defect detection model comprises:

[0014] determining weight values of the simulation training data and actual measurement data in the training process;

[0015] inputting the simulation training data and actual measurement data into the preset neural network architecture;

[0016] training the simulation training data and actual measurement data in the preset neural network architecture according to the weight values to obtain the artificial intelligence defect detection model.

[0017] Optionally, the step of generating the simulation training data through the basic defect detection model comprises:

[0018] determining a target chip for training and obtaining complete layout data corresponding to the target chip;

[0019] determining a target training pattern in the complete layout data through a preset grouping algorithm;

[0020] generating a simulation contour on the target training pattern using the basic defect detection model, and taking the target training pattern and the simulation contour together as the simulation training data.

[0021] Optionally, the step of inputting the simulation training data and actual measurement data into the preset neural network architecture for training to obtain the artificial intelligence defect detection model is followed by further comprising:

[0022] continuously collecting wafer data and iterative layout data corresponding to the wafer data generated subsequently, the iterative layout data being layout data generated after the artificial intelligence defect detection model is trained, and the wafer data including patterning process results obtained after performing a patterning process on the iterative layout data;

[0023] generating a detection result by simulating the iterative layout data using the artificial intelligence defect detection model;

[0024] determining deviations existing between the detection result and the patterning process results at respective positions;

[0025] In a case where the deviation at the target position is greater than a preset threshold, an iterative scanning electron microscope image corresponding to the target position is determined;

[0026] The iterative layout data and the iterative scanning electron microscope image are used as iterative training data to iteratively optimize the artificial intelligence bad point detection model.

[0027] Optionally, the step of establishing the basic bad point detection model according to the basic layout data and the basic scanning electron microscope image corresponding to the basic layout data comprises:

[0028] An actual wafer contour in each basic scanning electron microscope image is extracted, and a feature point in the actual wafer contour is obtained;

[0029] Initial model parameters corresponding to the basic bad point detection model are determined;

[0030] The basic layout data is simulated based on the initial model parameters to obtain a simulated contour;

[0031] The initial model parameters are iteratively optimized according to the feature point and the simulated contour, so that the basic bad point detection model is obtained.

[0032] Optionally, the step of iteratively optimizing the initial model parameters according to the feature point and the simulated contour comprises:

[0033] A deviation distance between each feature point and the simulated contour is calculated;

[0034] An evaluation function corresponding to the basic bad point detection model is generated according to the deviation distance;

[0035] The initial model parameters are iteratively optimized until the evaluation function satisfies a preset convergence condition, so that the basic bad point detection model is obtained.

[0036] Optionally, in a case where the patterning process is photolithography, the basic bad point detection model and the artificial intelligence bad point detection model are bad point detection models for photolithography;

[0037] In a case where the patterning process is etching, the basic bad point detection model and the artificial intelligence bad point detection model are bad point detection models for etching.

[0038] According to another aspect of the present application, there is also provided a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of any of the bad point detection model training methods in a chip patterning process.

[0039] According to still another aspect of the present application, there is also provided a computer program product comprising a computer program, the computer program being executed by a processor to implement the steps of any of the bad point detection model training methods in a chip patterning process.

[0040] According to still another aspect of the present application, there is also provided a computer device comprising a memory, a processor, and a machine executable program stored on the memory and running on the processor, and the processor implements the steps of the method for training a detection model of a bad spot in a chip patterning process of any of the above when executing the machine executable program.

[0041] The method for training a detection model of a bad spot in a chip patterning process of the present application acquires basic layout data used for training and basic scanning electron microscope images measured after the basic layout data undergoes a patterning process; establishes a basic bad spot detection model according to the basic layout data and the corresponding basic scanning electron microscope images; generates simulation training data through the basic bad spot detection model; inputs the simulation training data and actual measurement data into a preset neural network architecture for training to obtain an artificial intelligence bad spot detection model, the actual measurement data being actual scanning electron microscope images measured after actual layout data undergoes a patterning process and the corresponding actual layout data. The method of the present application generates simulation training data using a basic bad spot detection model, which can make up for the defects of high cost and limited sample size of real process data collection, thereby expanding the coverage of training data and ultimately constructing a more excellent artificial intelligence bad spot detection model, which significantly improves the precision and speed of bad spot detection.

[0042] Further, the method for training a detection model of a bad spot in a chip patterning process of the present application also continuously collects wafer data and iteration layout data corresponding to the wafer data generated subsequently after obtaining the artificial intelligence bad spot detection model; generates detection results by simulating the iteration layout data using the artificial intelligence bad spot detection model; determines the deviation between the detection results and the patterning process results at each position; determines the iteration scanning electron microscope images corresponding to the target position in the case where the deviation of the target position is greater than a preset threshold; and iteratively optimizes the artificial intelligence bad spot detection model using the iteration layout data and the iteration scanning electron microscope images as iteration training data. This method can continuously adjust the artificial intelligence bad spot detection model according to the latest data, so that the simulation results of the artificial intelligence bad spot detection model can more effectively represent the actual patterning process results of the layout at the moment.

[0043] Still further, the method for training a detection model of a bad spot in a chip patterning process of the present application, in the case where the patterning process is photolithography, the basic bad spot detection model and the artificial intelligence bad spot detection model are bad spot detection models for photolithography; and in the case where the patterning process is etching, the basic bad spot detection model and the artificial intelligence bad spot detection model are bad spot detection models for etching. This method can make the artificial intelligence bad spot detection model applicable to both photolithography data and etching data, thereby increasing the generality of the method of the present application.

[0044] The above and other objects, advantages and features of the present application will become more apparent from the following detailed description of some embodiments thereof, when taken in conjunction with the annexed drawings, in which: BRIEF DESCRIPTION OF DRAWINGS

[0045] Some embodiments of the present application will now be described in detail with reference to the drawings, which are provided as illustrative examples so as to enable those skilled in the art to practice the present application. Notably, the figures are not drawn to scale, and like reference numerals are used to designate throughout the figures similar or identical structural elements or portions. In the figures:

[0046] Figure 1 FIG. 1 is a schematic diagram of a flow of a method for training a bad point detection model in a chip patterning process according to an embodiment of the present application;

[0047] Figure 2 FIG. 2 is a schematic diagram of a flow of establishing a basic bad point detection model in the method for training a bad point detection model in a chip patterning process according to an embodiment of the present application;

[0048] Figure 3 FIG. 3 is a schematic diagram of a flow of continuously optimizing an artificial intelligence bad point detection model in the method for training a bad point detection model in a chip patterning process according to an embodiment of the present application;

[0049] Figure 4 FIG. 4 is a schematic diagram of a computer program product according to an embodiment of the present application;

[0050] Figure 5 FIG. 5 is a schematic diagram of a computer readable storage medium according to an embodiment of the present application; and

[0051] Figure 6 FIG. 6 is a schematic diagram of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0052] It should be understood by those skilled in the art that the embodiments described below are only some embodiments of the present application, but not all embodiments of the present application, and the embodiments are intended to explain the technical principles of the present application, but not to limit the protection scope of the present application. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor should fall within the protection scope of the present application.

[0053] It is to be appreciated that the logical and / or steps represented in the flow diagrams or otherwise described herein, for example, can be considered as a list of executable instructions for implementing logic functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device, such as a computer-based system, processor- based system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions, or combination thereof.

[0054] In the current semiconductor technology field, the most core step in semiconductor chip manufacturing is to transfer the design pattern of the chip to the wafer. Among the many process steps in chip manufacturing, the processes directly related to pattern transfer are mainly photolithography and etching, which are usually referred to as patterning. In the current mainstream integrated circuit production process, the lithography technology is to cause the photoresist to undergo chemical changes under the exposure of special wavelength light, such as 193 nm or 248 nm, and then transfer the pattern designed on the mask to the photoresist topography on the wafer through development. The etching process is to selectively remove unnecessary materials based on the photoresist topography, thereby finally creating the required fine pattern on the wafer.

[0055] With the continuous evolution of chip technology nodes, the size of the design layout has been far smaller than the wavelength of lithography (193 nm), which leads to a strong diffraction effect, usually referred to as optical proximity effect, thereby causing a large deviation between the topography of the chip design layout and the topography printed on the photoresist through lithography. In order to compensate for this deviation, in the manufacturing process of integrated circuits, the foundry (Fabrication, referred to as FAB) needs to obtain the mask data (Mask) after optical proximity correction (Optical Proximity Correction, referred to as OPC) from the original design layout, and then take the mask data to flow. In actual operation, the original design pattern is input to the OPC Recipe for processing. The so-called OPC recipe is a technical solution for lithography image correction, which is essentially a series of optimization strategies and parameter settings. The general process is to implement OPC optimization on the design layout, then perform lithography simulation detection (LRC), and if the detection finds bad points, the OPC Recipe is iteratively improved.

[0056] Etching after lithography will cause etching bias, that is, the line width of photoresist before etching and the line width of etching material after photoresist is removed are not the same. The size of etching bias is related to many factors: substrate material, line width of pattern on photoresist, parameters of etching process, etc. Etching bias will cause the overall size to change after etching, and the size of the same pattern after lithography will also become different after etching. An optional method is to first modify the designed layout according to an etching bias table (Etching Bias Table, referred to as SSA Table) to compensate the etching bias into the target pattern of lithography. Usually such etching bias table is created according to the line width (width) and pitch (space) of the pattern.

[0057] The model used by the current wafer factory (FAB) to simulate and detect bad points based on input mask data is generally an optical proximity correction model (OPC model), because the OPC model is used to correct the mask, which must fully reflect the actual process.

[0058] The OPC lithography model generally includes an optical model and a photoresist model. The optical model is based on first principles and strictly calculates the aerial image from the mask image (MI) according to physical methods, while the photoresist model is derived from the aerial image based on empirical models in production practice. Based on real scanning electron microscopy (SEM) measurement data, a semi-empirical and semi-physical method is used to linearly add multiple photoresist terms to select the optimal model from the preset solution space. The smaller the error or evaluation function between the simulation results of the model and the actual situation, the better the model.

[0059] However, in actual application, the OPC Recipe and the OPC lithography model remain unchanged, because the OPC Recipe and the OPC lithography model have been determined in the technology node development stage, and are responsible for generating all mask data of the process layer corresponding to this technology node. Pull one hair and move the whole body, it cannot be easily modified, and it cannot continue to evolve with the fine tuning of the process, which greatly reduces its value as a process bad point model.

[0060] And the data used to establish the model is generally in the wafer factory new node research and development, in practice, the wafer factory will use critical dimension scanning electron microscope (Critical Dimension Scanning Electronic Microscope, CD-SEM) to measure tens of thousands of measurement patterns (Gauge), in order to obtain more accurate, efficient measurement data, the measurement pattern is generally a relatively simple test pattern containing the core characteristics of the layout. The model established in this way has considerable universality, which can be used for OPC mask correction in practice, but it is based on simple test patterns, not fully optimized for complex layout shapes, and independent bad spot simulation prediction based on mask data needs to face different chip design products, whose layout is very complex, which limits the accuracy of the model in predicting the bad spots of complex layouts in actual chips.

[0061] For etching prediction, the current wafer factory mainly considers etching effect based on etching deviation table, without incorporating etching effect into the framework of bad spot simulation prediction, and the SSA table mainly determines how much the deviation should be according to the width and space of the current polygon edge. This method is accurate and sufficient for simple patterns, but when the pattern becomes complex, the accuracy will be a problem. As mentioned earlier, bad spot simulation prediction based on mask data needs to face different chip design products, whose layout is very complex, so etching prediction alone is far from enough.

[0062] Therefore, the current semiconductor technology field urgently needs a bad spot detection model with sufficient precision and speed in the lithography process and the etching process.

[0063] To solve the above problems, the present application provides a bad spot detection model training method in chip patterning process, Figure 1 The chip patterning process bad spot detection model training method according to an embodiment of the present application is shown in the flowchart, which at least includes the following steps S101 to S104.

[0064] Step S101, obtain the basic layout data used for training and the basic scanning electron microscope image measured after the basic layout data undergoes a patterning process. The basic layout data refers to the pattern data that is about to undergo a patterning process, and the scanning electron microscope image is an actual measurement image obtained by using a scanning electron microscope (SEM) to image the wafer surface after the basic layout data undergoes a patterning process. The scanning electron microscope image directly reflects the physical form of the pattern after the process. In this way, by establishing the original data correlation of "design input-process output", data basis is provided for subsequent model learning of the mapping relationship between layout design and actual process result.

[0065] The wafer generally refers to a substrate wafer that has undergone basic processing such as cutting, grinding, and polishing to meet the precision requirements of device manufacturing, or a functional carrier that has undergone pretreatment such as epitaxy and oxidation for carrying chip patterning processes. It is the direct object of core processes in the chip manufacturing process. The wafer can be a silicon-based wafer or various compound semiconductor wafers (such as silicon carbide wafers, gallium nitride wafers, etc.), as well as other special wafers (such as sapphire wafers for LED manufacturing, quartz wafers for optical devices, etc.). Those skilled in the art can determine the specific material of the wafer according to actual conditions.

[0066] The patterning process is a core process that accurately transfers the circuit pattern in the design layout to the wafer, and is a key link from design to physical implementation of the chip. It generally includes steps such as photolithography and etching, so as to draw a nanoscale circuit pattern consistent with the design on the wafer. The basic scanning electron microscope image contains defect characteristics (such as line width deviation and edge irregularity) in the actual process, which provides initial sample basis for model identification of bad points and avoids the model from deviating from the actual process scenario.

[0067] Step S102, establish a basic bad point detection model according to the basic layout data and the corresponding basic scanning electron microscope image.

[0068] In some optional embodiments, step S102 can generally include: extracting an actual wafer contour in each basic scanning electron microscope image and obtaining feature points in the actual wafer contour; determining initial model parameters corresponding to the basic bad point detection model; performing simulation operation on the basic layout data based on the initial model parameters to obtain a simulated contour; and iteratively optimizing the initial model parameters according to the feature points and the simulated contour, thereby obtaining the basic bad point detection model.

[0069] The operation of extracting feature points can generally be performed on the basic scanning electron microscope (SEM) image obtained in step S101. The physical contour of the actual pattern on the wafer surface, i.e., the actual wafer contour, such as the geometric shapes of line edges, corners, and via boundaries, is extracted by image segmentation and edge detection algorithms (such as Canny operator and threshold segmentation). Then, key feature points (point gauges) such as edge inflection points, line width extreme points, and defect region boundary coordinates are selected from the contour. These points accurately reflect the process deviation (such as line width shrinkage and edge depression) and potential bad point characteristics of the pattern.

[0070] The step of subsequently determining the initial model parameters corresponding to the basic bad point detection model can generally be to preset an initial parameter set of the basic bad point detection model according to the physical law of the patterning process. The initial parameters can be set based on theoretical calculation or historical data of the same type of process, serving as the starting point for model optimization.

[0071] The step of subsequently determining the initial model parameters corresponding to the basic bad point detection model can generally be to preset an initial parameter set of the basic bad point detection model according to the physical law of the patterning process. The initial parameters can be set based on theoretical calculation or historical data of the same type of process, serving as the starting point for model optimization.

[0072] Finally, the initial model parameters are iteratively optimized according to the feature points and the simulated contour, thereby obtaining the basic bad point detection model. Alternatively, the step of iteratively optimizing the initial model parameters according to the feature points and the simulated contour can generally include: calculating the deviation distance between each feature point and the simulated contour; generating an evaluation function corresponding to the basic bad point detection model according to the deviation distance; iteratively optimizing the initial model parameters until the evaluation function satisfies a preset convergence condition, thereby obtaining the basic bad point detection model.

[0073] The operation of calculating the deviation distance can generally be to calculate the spatial distance (such as Euclidean distance) between each feature point in the actual wafer contour and the corresponding position on the simulated contour, thereby quantifying the difference between the actual process result and the model prediction result. The greater the deviation, the lower the model prediction accuracy.

[0074] Subsequently, an evaluation function (such as mean square error MSE and mean absolute error MAE) is constructed based on the deviation distances of all feature points to comprehensively measure the overall goodness of fit between the simulated contour and the actual wafer contour. For example, the evaluation function can be defined as the square sum of all feature point deviation distances, and the smaller the value, the better the model prediction effect.

[0075] And the step of iterative optimization can generally be to use optimization methods such as gradient descent, genetic algorithm, etc., to continuously adjust the initial parameters of the model (such as lithography exposure dose, etching power), and regenerate the simulation profile, calculate the deviation distance and evaluate the function value; repeat the above process until the evaluation function value is less than the preset threshold (such as the average deviation distance <1nm), at which time the model parameters reach the optimal state, and the final basic hotspot detection model is output. By iteration, the deviation between simulation and reality is eliminated, so that the prediction result of the basic model is maximized to approach the real process rule, and the subsequent generated simulation training data has physical credibility.

[0076] Finally, the mapping model between the design layout and the corresponding process result is constructed through step S102, and through this model, the physical impact of the patterning process on the layout can be simulated. However, since this model is based on a semi-empirical and semi-physical method, it is optimized from a preset solution space by linearly adding multiple resist terms to minimize the error with wafer data, so its accuracy itself is difficult to be further improved in the macro level. That is, the basic hotspot detection model obtained by the current training can only make the modeling data more based on the SEM image of the complex layout, so that the model is more suitable for the application scenario of hotspot simulation prediction, and cannot fundamentally further improve the accuracy.

[0077] Step S103, generating simulation training data through the basic hotspot detection model. In order to further increase the accuracy and speed of hotspot simulation prediction, the present application selects to introduce artificial intelligence (Artificial Intelligence, AI for short) to generate an artificial intelligence hotspot detection model. In order to distinguish, the basic hotspot detection model can be called Basic Hotspot Detection Model, abbreviated as Basic HDM, and the artificial intelligence hotspot detection model can be called AI Hotspot Detection Model, abbreviated as AI HDM.

[0078] Since AI can effectively improve the fitting ability of the model, but the SEM image used for general HDM modeling is several hundred to several thousand, which is too small for large-scale AI modeling, and is very easy to overfit (overfitting). Although the fitting level of the model on the current data is improved, the risk of prediction error on new layouts in the future is greatly increased. Therefore, the present application selects to generate a large amount of simulation training data from the basic hotspot detection model, and then integrates the simulation training data and the actual measurement data together to train AI.

[0079] Step S104, input the simulation training data and the actual measurement data into the preset neural network architecture for training to obtain the artificial intelligence bad point detection model. The actual measurement data is the actual scanning electron microscope image and the corresponding actual layout data measured after the actual layout data is subjected to the patterning process, that is, the data extracted from the scanning electron microscope image actually measured on the wafer and the actual layout data before the wafer is subjected to the patterning process. The data simulated by the basic bad point detection model can be massive, ranging from hundreds of thousands to millions of images in practice, which can effectively prevent overfitting of the artificial intelligence bad point detection model, and ensure sample coverage by the simulation training data and prediction accuracy of the model by the actual measurement data, solving the limitation of single data source training. It should be noted that the actual measurement data can reuse part or all of the actual measurement data of the previously trained basic bad point detection model, or other data actually measured, and those skilled in the art can determine the source of the actual measurement data according to the actual situation.

[0080] Finally, the method of the present application generates simulation data by the basic bad point detection model to make up for the lack of actual measurement data, and combines the actual measurement data to ensure the accuracy of the artificial intelligence bad point detection model, which can improve the accuracy of the bad point detection model for actual measurement SEM, and can further improve the simulation speed of the model by replacing the traditional modeling system with a pure AI model.

[0081] The simulation training data is generated by the basic model, which has the advantages of large sample size and wide coverage, but has the deviation between simulation and real process; the actual measurement data is directly obtained from wafer measurement, which has high accuracy and strong authenticity, but has limited sample size (high acquisition cost) and may have incomplete scene coverage. If direct training is performed, the obtained model may rely too much on simulation data, resulting in decreased generalization ability, or may be difficult to learn real defect characteristics due to insufficient actual measurement data. Therefore, in some optional embodiments, the step of inputting the simulation training data and the actual measurement data into the preset neural network architecture for training to obtain the artificial intelligence bad point detection model generally can include: determining the weight value of the simulation training data and the actual measurement data in the training process; inputting the simulation training data and the actual measurement data into the preset neural network architecture; training the simulation training data and the actual measurement data in the preset neural network architecture according to the weight value to obtain the artificial intelligence bad point detection model. For example, in order to highlight the importance of the actual measurement data, the actual measurement data can be given a higher weight in neural network training, thereby effectively preventing overfitting of the AI model.

[0082] By this method, the actual measurement data with high weight can be relied on to ensure that the model is anchored to the real process characteristics and reduce the interference caused by the deviation of simulation data; the simulation data with low weight supplements the scarce scene samples, so that the model can accurately identify rare bad points (such as dense line bridging and special corner pinch-off) in complex layouts, and solve the problem of poor generalization caused by insufficient actual measurement data.

[0083] In the process of generating simulation training data, since the patterns at some positions may be too simple or not representative, in order to accelerate the training efficiency and ensure the generalization ability of the artificial intelligence bad point detection model, the application further enters the pattern grouping technology (Pattern Grouping) in the process of generating simulation training data. In some optional embodiments, the step of generating simulation training data by the basic bad point detection model generally can include: determining the target chip for training, and obtaining the complete layout data corresponding to the target chip; determining the target training pattern in the complete layout data by a preset grouping algorithm; generating a simulation contour on the target training pattern by using the basic bad point detection model, and taking the target training pattern and the simulation contour together as simulation training data. The preset grouping algorithm, i.e. the Pattern Grouping technology, generally can include algorithms such as Exact Grouping and Fuzzy Grouping. Finally, similar patterns are classified into different groups according to their geometric characteristics (such as line width, spacing, shape structure, etc.), so that representative typical patterns are selected from a large number of patterns.

[0084] This step solves the efficiency problem caused by the redundancy of complete layout data by grouping mechanism, and also ensures the targeted coverage of data for complex layouts and high-incidence bad point scenes, finally provides efficient, accurate and comprehensive training input for the artificial intelligence bad point detection model, improves the generalization ability of the artificial intelligence bad point detection model, and helps the artificial intelligence bad point detection model to achieve high-precision bad point identification in actual chip production.

[0085] In actual chip production, as chips are gradually iteratively updated, in order to ensure that the previously trained basic defect detection model and the artificial intelligence defect detection model can be updated synchronously, the method of the present application selects the basic defect detection model and the artificial intelligence defect detection model to continuously evolve with the increase of the tape-out data, thereby ensuring the high accuracy and high efficiency of the defect prediction at all times. Therefore, in some other optional embodiments, the step of inputting the simulation training data and the actual measurement data into the preset neural network architecture for training to obtain the artificial intelligence defect detection model can generally further include: continuously collecting subsequent generated wafer data and iteration layout data corresponding to the wafer data, the iteration layout data being generated after the artificial intelligence defect detection model is trained, and the wafer data including a patterning process result obtained after the iteration layout data is subjected to a patterning process; using the artificial intelligence defect detection model to simulate the iteration layout data to generate a detection result; determining a deviation existing between the detection result and the patterning process result at each position; in the case that the deviation at a target position is greater than a preset threshold, determining an iteration scanning electron microscope image corresponding to the target position; and using the iteration layout data and the iteration scanning electron microscope image as iteration training data to iteratively optimize the artificial intelligence defect detection model.

[0086] The wafer data generally includes actual process results measured by a SEM or the like after a subsequent iteration layout is subjected to a patterning process, an etching process or the like; and the iteration layout data is design layout data corresponding to a new iteration chip (such as a layout structure updated due to product upgrading or process improvement, which can include a new pattern type, size or layout). The newly collected iteration layout data is input into the trained artificial intelligence defect detection model, and the model simulates a detection result based on the existing parameters; then, the deviation between the detection result and the actual process result in the wafer data is calculated by a comparison algorithm, thereby locating a region (such as a newly introduced high-density line region) where the model prediction is inaccurate (such as a line width deviation far greater than the actual measurement value). Then, a deviation threshold (such as a line width deviation > 5 nm, a defect omission rate > 10%) is set, and when the deviation at a target position exceeds the threshold, the region is determined as a “weak point” of the model, and an iteration scanning electron microscope (SEM) image corresponding to the position is extracted; finally, the filtered iteration layout data (new design features) and the corresponding iteration SEM image (new process defect features) are combined to form “iteration training data”, which is input into the preset neural network architecture for incremental training: by adjusting the network parameters and strengthening the learning weight of the features of the high-deviation region, the model is adapted to the new layout structure and process characteristics, and finally an optimized artificial intelligence defect detection model is output.

[0087] The step realizes the closed-loop mechanism of "continuous data acquisition-accurate deviation positioning-targeted incremental optimization", so that the simulation result of the HDM can always more effectively represent the actual wafer result of the current layout, and solves the core problem that the model is easy to be outdated in the chip iteration scene. The core value lies in that the basic bad point detection model and the artificial intelligence bad point detection model can dynamically adapt to the feature changes brought by new processes and new designs, realize long-term stability of the model performance with minimum resource investment, and finally guarantee the high precision and high efficiency of bad point prediction in the chip production process, and provide continuous and reliable technical support for process optimization and yield improvement.

[0088] The above example only illustrates the iteration process of the artificial intelligence bad point detection model, and the continuous updating logic of the basic bad point detection model is the same, that is, the current HDM is fine-tuned and updated according to new wafer data, which will not be described here.

[0089] The above graphic process generally includes photolithography and etching, so the training data obtained by different graphic processes will also be different in the actual training process, and the finally trained model is also a bad point detection model for a specific graphic process. That is, in the case of photolithography, the basic bad point detection model and the artificial intelligence bad point detection model are bad point detection models for photolithography; in the case of etching, the basic bad point detection model and the artificial intelligence bad point detection model are bad point detection models for etching.

[0090] Figure 2 is the establishment process schematic diagram of the basic bad point detection model in the bad point detection model training method of the chip graphic process according to an embodiment of the application, as shown in Figure 2 The bad point detection model training method of the chip graphic process at least includes the following steps S201 to step S210.

[0091] Step S201, obtain the basic layout data used for training and the basic scanning electron microscope image measured after the basic layout data is subjected to the graphic process. This step provides original input data for model construction, which specifically includes two parts: basic layout data: reference circuit pattern data (such as GDSII format) generated in the chip design stage, containing design geometric information such as device structure, interconnection line, etc.; basic scanning electron microscope (SEM) image: after the basic layout data is transferred to the wafer through photolithography, etching and other graphic processes, the actual measured image is photographed by SEM, which directly reflects the physical form (such as actual line width, edge contour, potential defects) of the pattern after the process.

[0092] Step S202, extract the actual wafer contour in each base scanning electron microscope image and obtain the feature points in the actual wafer contour. The physical boundary of the wafer surface pattern (i.e. the actual wafer contour) is extracted from the base SEM image by image segmentation, edge detection algorithm, etc., including line edges, corners, via boundaries and complete geometric shapes; further, key feature points are selected from the contour.

[0093] Step S203, determine the initial model parameters corresponding to the base bad point detection model. According to the physical principle of the patterning process (such as optical parameters in lithography, chemical reaction parameters in etching), the initial parameter set of the base bad point detection model is preset. For example: in the lithography scenario, the parameters can include light source wavelength, numerical aperture, photoresist sensitivity, exposure dose, etc.; in the etching scenario, the parameters can include etching gas ratio, radio frequency power, etching time, etc. The initial parameters can be set based on theoretical calculation (such as optical diffraction formula) or historical data of the same type of process, to ensure that they are within a physically reasonable range. The initial state of the model is provided to avoid falling into meaningless local optimal solution during parameter optimization, and to shorten the model convergence time;

[0094] Step S204, simulate the base layout data based on the initial model parameters to obtain a simulated contour. The base layout data is input into the base bad point detection model, and the model simulates the physical process of the patterning process based on the initial parameters of step S203, and finally outputs a simulated contour, i.e. the pattern shape that the wafer surface should form after the process. The simulated contour needs to correspond to the geometric structure of the base layout one by one, so as to be compared with the actual wafer contour extracted in step S202.

[0095] Step S205, calculate the deviation distance between each feature point and the simulated contour. For each actual wafer contour feature point extracted in step S202, the deviation distance between the corresponding position of the simulated contour generated in step S204 is calculated, and the larger the value is, the more significant the difference between the model prediction and the actual process is. Through this operation, the difference between the simulation and the actual can be converted into a quantifiable numerical index, providing a clear correction direction for model parameter optimization (the areas with large deviations need to be adjusted);

[0096] Step S206, generate an evaluation function corresponding to the base bad point detection model according to the deviation distance. Based on all the feature point deviation distances calculated in step S205, a comprehensive evaluation function (such as mean square error MSE, mean absolute error MAE) is constructed to quantify the overall goodness of fit between the simulated contour and the actual wafer contour.

[0097] Step S207, the initial model parameters are iteratively optimized. Gradient descent, genetic algorithm, and other optimization methods are used to adjust the model parameters (such as fine-tuning lithography exposure dose, etching gas ratio) according to the feedback of the evaluation function: for the areas with large deviations, the relevant parameters are corrected. In this way, the simulation and the actual deviation are gradually reduced through iteration, and the model parameters are adjusted to better fit the real process, improving the accuracy of the simulation profile.

[0098] Step S208, it is judged whether the evaluation function meets the preset convergence condition. In the case of no in step S208, the iterative optimization of step S207 is continued. It is checked whether the updated evaluation function value in step S206 is less than the preset threshold (such as deviation distance mean < 1 nm, or the evaluation function value change amount of continuous 3 iterations < 0.1%, etc.). If not, return to step S207 for iteration; if yes, it is considered that the model parameters have reached the optimal state, and the optimization is stopped.

[0099] Step S209, in the case of yes in step S208, the iterative optimization operation is ended, and the basic bad point detection model is obtained. When the evaluation function meets the convergence condition, the current optimized model parameters are output, and the final basic bad point detection model is formed. Based on the input layout data, the simulation profile highly consistent with the actual process result can be generated.

[0100] Step S210, continuously obtain new wafer data to fine-tune and update the basic bad point detection model. In the chip production process, new wafer data (such as newly added SEM images, process parameter fluctuation records) and corresponding layout data are continuously collected; the new data is input into the basic bad point detection model, and the local optimization process (such as adjusting only the parameters related to the new deviation) of steps S202-S208 is repeated, to realize the dynamic fine-tuning of the model. Thus, the basic model can adapt to process fluctuations and avoid the decline of simulation accuracy caused by model solidification.

[0101] Through this method, a high-precision and evolvable basic bad point detection model is finally constructed. The core technical value lies in: taking the actual process data as the benchmark, through quantitative deviation and iterative optimization, the model has the ability to accurately simulate complex processes; at the same time, through the continuous fine-tuning mechanism, the model ensures stable performance as the process evolves, laying a reliable foundation for the generation of subsequent simulation training data and the training of artificial intelligence bad point detection model.

[0102] The continuous optimization logic of the artificial intelligence bad point detection model is similar to the logic of the basic bad point detection model, Figure 3 is a continuous optimization process diagram of the artificial intelligence bad point detection model in the bad point detection model training method of the chip patterning process according to an embodiment of the application, like Figure 3As shown, the training method of the defect detection model in the chip patterning process includes at least the following steps S301 to S305.

[0103] Step S301, continuously collect subsequent generated wafer data and corresponding iteration layout data. The wafer data generally includes actual process results obtained by scanning electron microscope (SEM), optical measuring instrument and other equipment after the iteration layout undergoes photolithography, etching and other patterning processes. The iteration layout data is the design data corresponding to the new iteration chip, which may include new pattern structures (such as denser lines, new via layout) or size adjustments (such as smaller line width, pitch) introduced due to product upgrade and process improvement.

[0104] Step S302, simulate the generation of detection results by using the artificial intelligence defect detection model on the iteration layout data. The iteration layout data collected in step S301 is input into the trained artificial intelligence defect detection model. The model simulates the patterning process based on the current parameters, and outputs the detection results, which generally include the predicted post-process pattern profile, defect position, risk level, etc. (such as predicting that there is a line width out-of-tolerance risk in a certain area, or a corner may have a pinch-off defect). In this way, the existing model is used to pre-evaluate the new design layout, thereby quickly positioning the prediction ability of the model for new structures, and providing a benchmark for subsequent deviation analysis.

[0105] Step S303, determine the deviation existing between the detection results and the patterning process results at each position. By image registration and feature comparison algorithm, the detection results (model prediction) generated in step S302 and the wafer data (actual process results) in step S301 are compared point by point, and the deviation between them is calculated, so as to accurately locate the weak link of the model (such as large prediction deviation for newly introduced high-density line area), provide a clear direction for subsequent optimization, avoid blind adjustment of model parameters, and improve optimization efficiency.

[0106] Step S304, in the case where the deviation at the target position is greater than the preset threshold, determine the iteration scanning electron microscope image corresponding to the target position. By setting the deviation threshold (for example, line width deviation > 5 nm, defect omission rate > 10%, the threshold can be adjusted according to the process node requirement), the target positions with excessive deviation are screened out; the iteration SEM images corresponding to these positions are extracted, which include new features (such as edge roughness caused by new materials, etching unevenness caused by new pattern structures) that are not accurately recognized by the model.

[0107] Step S305, the iterative layout data and the iterative scanning electron microscope image are taken as the iterative training data to iteratively optimize the artificial intelligence bad point detection model. The iterative layout data (new design features) screened in step S304 and the corresponding iterative SEM image (new process defect features) are combined to form iterative training data, and are input into a preset neural network architecture for incremental training, and finally an optimized artificial intelligence bad point detection model is output.

[0108] Through the method, the generalization capability of the model for a complex scene can be improved, the model can identify new bad points in the iteration chip by learning new defect features, the long-term effectiveness of the model is ensured, the model continuously evolves with the chip iteration, the performance decay caused by process or design changes is avoided, and stable support for yield improvement in the whole product life cycle is ensured.

[0109] To sum up, the method of the application on the one hand constructs a set of wafer measured SEM image-based workflow, so that a basic bad point detection model can be efficiently constructed and maintained, and potential process bad points can be predicted through the simulation profile of the model. On the other hand, the application further introduces AI technology, and integrates the measured data and the simulation data of the previous basic bad point model together to construct a more powerful, unified lithography and etching bad point simulation prediction modeling framework, and the precision and speed of bad point detection are obviously improved. Different combinations of the steps involved in the scheme, or replacement or simplification of a certain step to form a workflow should be regarded as an alternative scheme of the scheme. For example, the AI model of the scheme is suitable for both lithography data and etching data; the sampling in the scheme is performed by using the precise grouping algorithm or the fuzzy grouping algorithm, or can be ordinary random sampling. The person skilled in the art can select the specific sampling method according to the actual situation.

[0110] It should be understood that in some embodiments, parts can be realized by hardware, software, firmware or a combination thereof. In the above implementation, a plurality of steps or methods can be realized by software or firmware stored in a memory and executed by a suitable instruction execution system.

[0111] The embodiment also provides a computer program product 10, a computer readable storage medium 20 and a computer device 30. Figure 4 is a schematic diagram of the computer program product 10 according to an embodiment of the application, Figure 5 is a schematic diagram of the computer readable storage medium 20 according to an embodiment of the application, Figure 6is a schematic diagram of a computer device 30 according to an embodiment of the present application. The computer program product 10 comprises a computer program 11 which, when executed by the processor 32, implements the steps of any of the methods for training a model for detecting defects in a chip patterning process described above. The computer readable storage medium 20 has stored thereon the computer program 11 which, when executed by the processor 32, implements the steps of any of the methods for training a model for detecting defects in a chip patterning process described above. The computer device 30 can comprise a memory 31, a processor 32 and the computer program 11 stored on the memory 31 and running on the processor 32.

[0112] The computer program 11 for performing the operations of the present application can be in an assembly language, an Instruction Set Architecture (ISA) language, machine language, a high-level procedural language, an object-oriented language, a functional language, a logical language, a procedural language, a machine related language, a microcode, a firmware language, state-setting data, configuration data for integrated circuits, or any combinations of one or more of the above languages. The computer program 11 can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application.

[0113] For the purposes of the description of the present embodiment, the computer program product 10 is a tangible computer program product comprising the computer program 11. For the purposes of the description of the present embodiment, the computer readable storage medium 20 is a tangible device that can retain and store the computer program 11, which can be any apparatus that can contain, store, communicate, propagate or transport the program 11 for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer readable storage medium 20 include the following: portable computer diskette, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, a floppy disk, a mechanical encoder device, and any suitable combination of the foregoing.

[0114] The computer device 30 can be, for example, a server, a desktop computer, a notebook computer, a tablet computer, or a smartphone. In some examples, the computer device 30 can be a cloud computing node. The computer device 30 can be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, and the like, that perform particular tasks or implement particular abstract data types. The computer device 30 can be practiced in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules can be located in local or remote computer system storage media including memory storage devices.

[0115] The computer device 30 can include a processor 32 adapted to execute instructions stored in a memory 31, which in operation provide temporary storage of the instructions during execution. The processor 32 can be a single core processor, a multi-core processor, a computing cluster, or any number of other configurations. The memory 31 can include random access memory (RAM), read only memory, flash memory, or any other suitable memory systems.

[0116] The computer device 30 can also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows for input and output of data with external devices that can be connected to the computer device. The network adapter / interface can provide for communication between the computer device and a network, generally illustrated as communication network.

[0117] At this point, those skilled in the art will appreciate that although specific exemplary embodiments of the application have been described herein, the present application also encompasses many other variations or modifications in accordance with the principles of the application as set forth above. Accordingly, the scope of the present application should be understood to include all such variations and modifications.

Claims

1. A method for training a defect detection model in a chip patterning process, comprising: obtaining basic layout data used for training and basic scanning electron microscope (SEM) images measured after the basic layout data undergoes a patterning process; establishing a basic defect detection model according to the basic layout data and the basic SEM images corresponding to the basic layout data; generating simulation training data by using the basic defect detection model; inputting the simulation training data and actual measurement data into a preset neural network architecture to train an artificial intelligence defect detection model, wherein the actual measurement data is actual SEM images measured after actual layout data undergoes the patterning process and actual layout data corresponding to the actual SEM images; the step of establishing the basic defect detection model according to the basic layout data and the basic SEM images corresponding to the basic layout data comprises: extracting actual wafer contours in each of the basic SEM images and obtaining feature points in the actual wafer contours; determining initial model parameters corresponding to the basic defect detection model; simulating the basic layout data based on the initial model parameters to obtain simulated contours; iteratively optimizing the initial model parameters according to the feature points and the simulated contours, thereby obtaining the basic defect detection model; and the step of inputting the simulation training data and the actual measurement data into the preset neural network architecture to train the artificial intelligence defect detection model comprises: determining weight values of the simulation training data and the actual measurement data in a training process; inputting the simulation training data and the actual measurement data into the preset neural network architecture; and training the simulation training data and the actual measurement data in the preset neural network architecture according to the weight values to obtain the artificial intelligence defect detection model. 2.The method of claim 1, wherein the step of generating simulation training data by using the basic defect detection model comprises: determining a target chip used for training and obtaining complete layout data corresponding to the target chip; determining a target training pattern in the complete layout data by using a preset grouping algorithm; and generating a simulation contour on the target training pattern by using the basic defect detection model, and taking the target training pattern and the simulation contour together as the simulation training data. 3.The method of claim 1, wherein the method further comprises, after the step of inputting the simulation training data and the actual measurement data into the preset neural network architecture to train the artificial intelligence defect detection model: continuously collecting wafer data generated subsequently and iterative layout data corresponding to the wafer data, wherein the iterative layout data is layout data generated after the artificial intelligence defect detection model is trained, and the wafer data comprises patterning process results obtained after the iterative layout data undergoes the patterning process; simulating the iterative layout data by using the artificial intelligence defect detection model to generate detection results. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ determining a deviation existing between each position of the detection result and the result of the patterning process; in a case where the deviation of the target position is greater than a preset threshold, determining an iterative scanning electron microscope image corresponding to the target position; taking the iterative layout data and the iterative scanning electron microscope image as iterative training data to iteratively optimize the artificial intelligence bad point detection model.

4. The bad point detection model training method for a chip patterning process according to claim 1, wherein the step of iteratively optimizing the initial model parameters according to the feature points and the simulated contour comprises: calculating a deviation distance between each of the feature points and the simulated contour; generating an evaluation function corresponding to the basic bad point detection model according to the deviation distance; iteratively optimizing the initial model parameters until the evaluation function satisfies a preset convergence condition, thereby obtaining the basic bad point detection model.

5. The bad point detection model training method for a chip patterning process according to claim 1, wherein in a case where the patterning process is photolithography, the basic bad point detection model and the artificial intelligence bad point detection model are bad point detection models for photolithography; in a case where the patterning process is etching, the basic bad point detection model and the artificial intelligence bad point detection model are bad point detection models for etching.

6. A computer readable storage medium having stored thereon a computer program, characterized in that The computer program is executed by a processor to implement the steps of the bad point detection model training method for a chip patterning process according to any one of claims 1 to 5.

7. A computer program product comprising a computer program which, when executed by a processor, implements the steps of the bad point detection model training method for a chip patterning process according to any one of claims 1 to 5.

8. A computer device comprising a memory, a processor, and a machine executable program stored on the memory and running on the processor, and the processor implements the steps of the bad point detection model training method for a chip patterning process according to any one of claims 1 to 5 when executing the machine executable program.

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