Storage device

Abstract

The invention discloses a storage device, and relates to the technical field of semiconductor storage, the storage device comprises a storage block, the storage block comprises a plurality of storage areas, each storage area comprises a storage array, the storage array comprises a common storage array and a redundant storage array, redundant bit lines in the redundant storage array are used for mapping and replacing common bit lines in the common storage array, so that redundant storage units in the redundant storage array are used for mapping and replacing damaged common storage units in the common storage array; the burning storage circuit comprises a plurality of burning storage modules, and each burning storage module corresponds to one main storage area and at least one auxiliary storage area so as to store damaged bit line addresses in the main storage areas and damaged bit line addresses in the auxiliary storage areas. Based on the mode, the reliability of the storage device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage technology, and in particular to a storage device. Background Art

[0002] In the prior art, a storage block typically has two storage planes, one storage plane typically being provided with two or more storage areas, each storage area typically being provided with a storage array. The storage array on a single storage area includes a normal storage array and a redundant storage array. The redundant bit lines of the redundant storage array in each storage array are typically used to map and replace damaged normal bit lines in the normal storage array for data storage.

[0003] A drawback of the prior art is that a burn-in storage circuit is typically used to store the addresses of damaged common bit lines in a storage array on a storage area. However, the number of addresses that can be stored by the burn-in storage circuit is generally limited by its size, which can easily lead to a situation where the number of damaged bit lines in a storage area exceeds the number of addresses that can be stored by the burn-in storage circuit on the storage area. As a result, damaged storage portions that cannot be successfully mapped and replaced exist in the storage block, affecting the normal use of the storage device and reducing the reliability of the storage device. Summary of the Invention

[0004] The main technical problem solved by this application is how to improve the reliability of the storage device.

[0005] In order to solve the above technical problems, the technical solution adopted in the present application is: a storage device, comprising: a storage block, comprising multiple storage areas, each storage area comprising a normal storage array and a redundant storage array, and the redundant bit lines in the redundant storage array are used to map and replace the normal bit lines in the normal storage array; a burning storage circuit, comprising multiple burning storage modules, each burning storage module is respectively arranged corresponding to two or more storage areas, and the burning storage module includes multiple address registers, each address register is respectively used to store a damaged bit line address and an identification bit, the identification bit indicating whether the damaged bit line address stored in each address register corresponds to a main storage area or an auxiliary storage area among the two or more storage areas.

[0006] The storage block includes two storage planes, each storage plane includes a primary storage area and at least one auxiliary storage area; each burning storage module corresponds to a primary storage area and an auxiliary storage area on the same storage plane, or each burning storage module corresponds to a primary storage area on one storage plane and an auxiliary storage area on another storage plane.

[0007] The storage device further includes: a command decoder configured to generate a corresponding bit line addressing address in response to a user instruction; a processing circuit coupled to the burn storage circuit, the command decoder and the storage block; the processing circuit configured to receive a bit line addressing address and a damaged bit line address to perform bit line addressing; and in response to the bit line addressing address matching a damaged bit line address, generating a corresponding redundant bit line enable signal to drive the redundant bit line mapping corresponding to the matched damaged bit line address to replace the normal bit line corresponding to the bit line addressing address.

[0008] The processing circuit includes an address matching circuit coupled to the programming storage circuit and the command decoder. The address matching circuit is configured to receive a damaged bit line address from the programming storage circuit and a bit line addressing address from the command decoder, and compare the bit line addressing address with the damaged bit line address to determine whether the bit line addressing address matches at least one of the damaged bit line addresses.

[0009] The processing circuit further includes: a redundant bit line decoding circuit coupled to the address matching circuit, wherein the redundant bit line decoding circuit is configured to determine, in response to the address matching circuit, that the bit line addressing address matches at least one damaged bit line address, receive the matched damaged bit line address, and generate a corresponding redundant bit line enable signal based on the matched damaged bit line address to drive the redundant bit line mapping in a group of redundant bit lines corresponding to the matched damaged bit line address to replace a group of normal bit lines corresponding to the bit line addressing address.

[0010] Among them, a corresponding redundant bit line enable signal is generated based on the matched damaged bit line address to drive the redundant bit line mapping in a group of redundant bit line groups corresponding to the matched damaged bit line address to replace a group of normal bit lines corresponding to the bit line addressing address, including: based on the matched damaged bit line address and the identification bit, determining the storage area corresponding to the matched damaged bit line address in the main storage area and the auxiliary storage area, generating a corresponding redundant bit line enable signal to drive the redundant bit line mapping in a group of redundant bit line groups corresponding to the matched damaged bit line address in the storage area corresponding to the matched damaged bit line address to replace a group of normal bit lines corresponding to the bit line addressing address.

[0011] Among them, based on the matched damaged bit line address and the identification bit, the storage area corresponding to the matched damaged bit line address in the main storage area and the auxiliary storage area is determined, and the corresponding redundant bit line enable signal is generated, including: determining the storage area corresponding to the damaged bit line address based on the identification bit, and generating the redundant bit line enable signal corresponding to the storage area corresponding to the damaged bit line address based on the matched damaged bit line address and the identification bit.

[0012] The processing circuit further includes: a normal bit line decoding circuit coupled to the address matching circuit, wherein the normal bit line decoding circuit is configured to receive the bit line addressing address in response to the address matching circuit determining that the bit line addressing address does not match any damaged bit line address, and generate a corresponding normal bit line enable signal based on the bit line addressing address to drive the normal bit lines in a group of normal bit line groups corresponding to the matched bit line addressing address.

[0013] Before the storage device leaves the factory, the identification bit and the damaged bit line address are both burned into each burning storage module.

[0014] Among them, the storage array also includes multiple sense amplifiers, the ordinary storage array includes multiple ordinary bit lines and multiple word lines, and the redundant storage array includes multiple redundant bit lines and multiple word lines; the ordinary bit lines are directly or indirectly connected to each sense amplifier and each word line, and the redundant bit lines are directly or indirectly connected to each sense amplifier and each word line.

[0015] The beneficial effects of the present application are as follows: different from the prior art, in the technical solution of the present application, the storage block includes multiple storage areas, each storage area includes a normal storage array and a redundant storage array, the redundant bit lines in the redundant storage array are used to map and replace the normal bit lines in the normal storage array, the burning storage circuit includes multiple burning storage modules, each burning storage module is respectively arranged corresponding to two or more storage areas, the burning storage module includes multiple address registers, each address register is respectively used to store a damaged bit line address and at least one identification bit, the identification bit indicates whether the damaged bit line address stored in each burning storage module corresponds to a main storage area or an auxiliary storage area among the two or more storage areas. Based on the above method, an address register originally belonging to the main storage area can be reused for an auxiliary storage area, so that when a large number of damaged bit line addresses need to be stored in any one of the main storage area and the auxiliary storage area, more storage resources in the burning storage modules corresponding to the main storage area and the auxiliary storage area are called to store them. While maintaining the average storage resources of the burning storage modules corresponding to any storage area in the storage block unchanged, the flexibility of storage resource allocation is improved, thereby reducing the possibility of the number of damaged bit lines in a storage area exceeding the number of addresses that can be stored by the burning storage circuit on the storage area, reducing the possibility of abnormality of the storage device, and improving the reliability of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 This is one of the structural diagrams of an embodiment of the storage device of the present application;

[0018] Figure 2 is a schematic structural diagram of an embodiment of a conventional storage device;

[0019] Figure 3 This is a schematic structural diagram of an embodiment of a storage block of the present application;

[0020] Figure 4 It is a structural diagram of an embodiment of the storage block, the burning storage circuit and the processing circuit of the present application;

[0021] Figure 5 It is a structural diagram of another embodiment of the storage block, the burning storage circuit and the processing circuit of the present application;

[0022] Figure 6 It is a structural diagram of an embodiment of the storage device of the present application;

[0023] Figure 7 This is the second structural diagram of an embodiment of the storage device of the present application.

[0024] Figure 1: numerals: storage block 11, storage area 111, normal storage array 1111, redundant storage array 1112, burned storage circuit 12, burned storage module 121, address register 1211, command decoder 13, processing circuit 14, address matching circuit 141, redundant bit line decoding circuit 142, normal bit line decoding circuit 143. DETAILED DESCRIPTION

[0025] The present application will be further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only intended to illustrate the present application and are not intended to limit the scope of the present application. Similarly, the following examples are only some examples of the present application and not all examples. All other examples obtained by those of ordinary skill in the art without creative work are intended to fall within the scope of protection of this application.

[0026] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0027] In the description of this application, it should be noted that, unless otherwise specified or limited, the terms "installed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can mean fixed connection, detachable connection, or integral connection; mechanical connection or electrical connection; direct connection or connection through an intermediate medium. Those skilled in the art will be able to understand the specific meanings of the above terms in this application in specific circumstances.

[0028] In the prior art, a storage block typically has two storage surfaces, located on the front and back sides respectively. Two storage areas are typically provided on one storage surface, and each storage area is typically provided with a storage array. The storage array on a single storage area includes a normal storage array and a redundant storage array. The redundant bit lines of the redundant storage array in each storage array are typically used to map and replace damaged normal bit lines in the normal storage array for data storage.

[0029] It should be noted that a memory array is usually formed by a plurality of bit lines and a plurality of word lines being cross-distributed, and memory transistors are provided at the intersections. The bit lines and word lines are respectively connected by the memory transistors to form memory cells, so as to form a plurality of memory cells in the memory array for storing data. In the memory array, a normal memory array has a plurality of normal memory cells, and a redundant memory array has a plurality of redundant memory cells.

[0030] In the process of manufacturing storage devices, there are inevitable yield issues. The manufactured storage devices may contain unusable storage cells, word lines, or bit lines. In this case, it is necessary to use redundant storage resources to map and replace the damaged storage resources corresponding to these unusable storage cells, word lines, or bit lines. Usually, after the output test, the damaged bit line addresses of the damaged storage resources are stored in the corresponding burned-in storage module. However, since the redundant storage array corresponding to the redundant storage resources and the burned-in storage module required to record the damaged bit line addresses of the damaged storage resources require a large area, how to utilize the storage resources in the limited area of ​​the redundant storage array to achieve efficient, flexible, and reasonable mapping and replacement of damaged storage resources to reduce the possibility of the storage device not being able to be used normally has become a research focus in this field.

[0031] A drawback of the prior art is that each storage area is usually provided with a burn-in storage module, which is usually used to store the addresses of damaged common bit lines in the storage array on the storage area where it is located. However, the number of addresses that can be stored by the burn-in storage module is usually limited by its size, which easily leads to the situation where the number of damaged bit lines in a storage area exceeds the number of addresses that can be stored by the burn-in storage module on the storage area, resulting in damaged storage parts in the storage block that cannot be successfully mapped and replaced, affecting the normal use of the storage device and reducing the reliability of the storage device.

[0032] For an example, see Figure 2 , Figure 2 Schematic diagram of a conventional storage device according to an embodiment of the present invention. Figure 2 As shown, the storage block includes a storage plane (Plane) P0 and a storage plane P1, and the storage plane P0 includes a storage area (Mat) M0 and a storage area M1. In a traditional storage device, each storage area is usually separately configured with a dedicated redundant bit line decoding circuit and a burning storage module. After determining that the address of the normal bit line to be processed (storing data or reading data) is the damaged bit line address stored in the burning storage module of a storage area, the damaged bit line address can be obtained from the burning storage module of the storage area, and the redundant bit line decoding circuit of the storage area is used to determine and drive the redundant bit line to be mapped and replaced based on the damaged bit line address. Since each storage area of ​​the traditional storage device is usually separately configured with a dedicated redundant bit line decoding circuit and a burning storage module, each burning storage module The block includes multiple address registers, and one address register can usually store the address of a damaged common bit line. That is, each burned-in storage module can usually record the addresses of multiple damaged common bit lines. Therefore, the redundant bit line mapping in the storage area with the damaged common bit line is usually driven to replace the damaged common bit line. That is, each storage area can only use its own redundant bit line mapping to replace its own damaged common bit line, and it is impossible to use the redundant bit line mapping of one storage area to replace the common bit line of another storage area. This will result in that if the number of damaged common bit lines in a storage area is too large, it will be impossible to use the redundant bit line decoding circuit and the burned-in storage module configured therein to complete the mapping replacement of all damaged common bit lines, thereby affecting the normal use of the storage device and reducing the reliability of the storage device.

[0033] This application proposes a storage device, see Figure 1 and Figure 7 , Figure 1 This is one of the structural diagrams of an embodiment of the storage device of the present application. Figure 7 This is a second structural diagram of an embodiment of the storage device of the present application. Figure 1 and Figure 7As shown, the storage device includes a storage block 11 and a burning storage circuit 12.

[0034] The storage block 11 includes multiple storage areas 111 , each of which includes a normal storage array and a redundant storage array. That is, each storage area 111 includes a storage array, and the storage array includes a normal storage array and a redundant storage array.

[0035] The redundant bit lines in the redundant memory array are used to map and replace the ordinary bit lines in the ordinary memory array, so that the redundant memory cells in the redundant memory array map and replace the damaged ordinary memory cells in the ordinary memory array.

[0036] For an example, see Figure 3 , Figure 3 This is a structural diagram of an embodiment of the storage block of the present application, as shown in FIG. Figure 3 As shown, the memory block 11 may include multiple memory areas 111. The memory array within each memory area 111 may include a normal memory array 1111 and a redundant memory array 1112. The number of memory cells in the normal memory array 1111 is generally greater than the number of memory cells in the redundant memory array 1112. When a damaged normal bit line (an entire damaged bit line or a bit line with partially damaged memory cells) exists in the normal memory array 1111, the data of the damaged normal bit line is usually mapped and replaced by storing or reading a redundant bit line in the redundant memory array 1112 when storing or reading data of the damaged normal bit line, so as to maintain normal operation of the memory device.

[0037] The programming storage circuit 12 includes multiple programming storage modules 121. Each programming storage module 121 is provided for one or more storage areas 111. The two or more storage areas 111 may include a primary storage area and at least one auxiliary storage area. Each programming storage module 121 includes multiple address registers 1211. The address registers 1211 are respectively used to store a damaged bit line address and an identification bit in the primary storage area or to store a damaged bit line address and an identification bit in the auxiliary storage area. That is, each address register 1211 is respectively used to store a damaged bit line address and an identification bit. The identification bit is used to indicate whether the damaged bit line address stored in each address register 1211 corresponds to a primary storage area or an auxiliary storage area in the two or more storage areas 111. It is worth noting that the storage space size of the primary storage area and each auxiliary storage area can be the same or different. For example, multiple address registers 1211 in a single burned storage module 121 can be used to store damaged bit line addresses and identification bits of more than two storage areas, wherein one address register 1211 can be used to store one damaged bit line address and one identification bit, and the storage areas corresponding to the damaged bit line addresses stored in one address register 1211 are configured with different identification bits at different times.

[0038] When the memory block 11 includes two memory planes, and a single memory plane includes two memory areas, one burn memory module 121 can be used to store the damaged bit line addresses of the two memory areas 111, such as Figure 1 Taking the storage block shown as an example, one burned storage module 121 stores the damaged bit line address of the storage area M0 on the storage plane P0 and the damaged bit line address of the storage area M0 on the storage plane P1, and another burned storage module 121 stores the damaged bit line address of the storage area M1 on the storage plane P0 and the damaged bit line address of the storage area M1 on the storage plane P1. The storage capacity of a burned storage module 121 in the present application is equivalent to the total storage capacity of the burned storage modules corresponding to more than two storage areas in the traditional storage device, that is, the number of address registers 1211 included in a burned storage module 121 in the present application is equivalent to the number of address registers 1211 included in the burned storage modules corresponding to more than two storage areas 111 in the traditional storage device.

[0039] In one example, if Figure 1 As shown, the storage block 11 may include two storage planes, each storage plane includes more than two storage areas 111, and the more than two storage areas 111 include a main storage area and at least one auxiliary storage area. The main storage area may refer to the storage plane P0 and the auxiliary storage area may refer to the storage plane P1.

[0040] Among them, each burning storage module 121 can respectively correspond to the main storage area and the auxiliary storage area on the same storage surface, that is, one burning storage module 121 can be used to store the damaged bit line addresses of the main storage area and the auxiliary storage area located on the same storage surface; or each burning storage module 121 can respectively correspond to the main storage area of ​​one storage surface and the auxiliary storage area of ​​another storage surface, that is, one burning storage module 121 can be used to store the damaged bit line addresses of the main storage area on one storage surface and the auxiliary storage area on another storage surface.

[0041] In summary, the two or more storage areas to which the damaged bit line addresses stored in one programming storage module 121 belong may all be located on the same storage plane, or may not be located on the same storage plane, which is not limited here.

[0042] Based on the above configuration, in the first case, when there are fewer damaged bit line addresses in the storage area M0 of the storage plane P0 and more damaged bit line addresses in the storage area M0 of the storage plane P1, one programming memory module 121 can store more damaged bit line addresses in the storage area M0 of the storage plane P0 and fewer damaged bit line addresses in the storage area M0 of the storage plane P1, thereby achieving flexible allocation of storage resources. In the second case, when the number of damaged bit line addresses in the storage area M0 of the storage plane P0 and the number of damaged bit line addresses in the storage area M0 of the storage plane P1 are similar or equal, one programming memory module 121 can store the same number of damaged bit line addresses in the storage area M0 of the storage plane P0 and the storage area M0 of the storage plane P1, respectively.

[0043] In the above example, the burned storage module 121 corresponds to a main storage area and an auxiliary storage area, which correspond one-to-one to the storage area M0 of the storage surface P0 and the storage area M0 of the storage surface P1, respectively. The main storage area and the auxiliary storage area can also be replaced by any two areas of the storage area M0 of the storage surface P0, the storage area M1 of the storage surface P0, the storage area M0 of the storage surface P1, and the storage area M1 of the storage surface P1, which is not limited here.

[0044] It should be noted that before the storage device leaves the factory, the identification bit and the damaged bit line address are both burned into each programming memory module. Specifically, regarding the identification bit and the damaged bit line address, before the storage device leaves the factory, the address of the damaged normal bit line is typically determined through bit line detection and recorded as the damaged bit line address. A corresponding identification bit is then determined based on the storage region to which the damaged normal bit line belongs. The identification bit and the damaged bit line address corresponding to each damaged normal bit line are then both burned into an address register 1211 in each programming memory module 121, thereby recording relevant information regarding the damaged normal bit line.

[0045] Different from the prior art, in the technical solution of the present application, the storage block includes multiple storage areas, each storage area includes a normal storage array and a redundant storage array, the redundant bit lines in the redundant storage array are used to map and replace the normal bit lines in the normal storage array, the burning storage circuit includes multiple burning storage modules, each burning storage module is respectively arranged corresponding to two or more storage areas, the burning storage module includes multiple address registers, each address register is respectively used to store a damaged bit line address and at least one identification bit, the identification bit indicates whether the damaged bit line address stored in each burning storage module corresponds to a main storage area or an auxiliary storage area among the two or more storage areas. Based on the above method, an address register originally belonging to the main storage area can be reused for an auxiliary storage area, so that when a large number of damaged bit line addresses need to be stored in any one of the main storage area and the auxiliary storage area, more storage resources in the burning storage modules corresponding to the main storage area and the auxiliary storage area are called to store them. While maintaining the average storage resources of the burning storage modules corresponding to any storage area in the storage block unchanged, the flexibility of storage resource allocation is improved, thereby reducing the possibility of the number of damaged bit lines in a storage area exceeding the number of addresses that can be stored by the burning storage circuit on the storage area, reducing the possibility of abnormality of the storage device, and improving the reliability of the storage device.

[0046] In one embodiment, see Figure 4 , Figure 4 FIG. 1 is a structural diagram of an embodiment of the storage block, the burning storage circuit and the processing circuit of the present application. Figure 4 As shown, the processing circuit 14 may be specifically provided with a corresponding logic circuit, which is used to determine the redundant bit line to be driven based on the damaged bit line address provided by the burning storage module 121. For example, it can be determined based on the identification bit stored in the corresponding address register 1211 in the burning storage module 121 whether the normal bit line to be mapped and replaced belongs to the storage area M0 of the storage plane P0 or the storage area M0 of the storage plane P1. If it belongs to the storage area M0 of the storage plane P0, the output terminal B can output 1 to abandon the AND gate X1. If it belongs to the storage area M0 of the storage plane P1, the output terminal B can output 0, and the AND gate X2 is enabled through the inversion conversion of the inverter X3. Then, based on the damaged bit line address stored in the corresponding address register 1211, the output terminal A is controlled to output the corresponding address signal, so that the AND gate X1 or the AND gate X2 drives the redundant bit line in the corresponding storage area, and performs the corresponding mapping and replacement operation of the normal bit line.

[0047] Furthermore, in another embodiment, see Figure 5 , Figure 5 FIG. 1 is a structural diagram of another embodiment of the storage block, the burning storage circuit and the processing circuit of the present application. Figure 5 As shown, the processing circuit 14 may be specifically provided with a corresponding logic circuit, which is used to determine the redundant bit line to be driven based on the damaged bit line address provided by the burning storage module 121. For example, it can be determined based on the identification bit stored in the corresponding address register 1211 in the burning storage module 121 whether the normal bit line to be mapped and replaced this time belongs to the storage area M0 of the storage plane P0 or the storage area M1 of the storage plane P0. If it belongs to the storage area M0 of the storage plane P0, the output terminal B can output 1 to abandon the AND gate X1. If it belongs to the storage area M1 of the storage plane P0, the output terminal B can output 0, and the AND gate X2 is enabled through the inversion conversion of the inverter X3. Then, based on the damaged bit line address stored in the corresponding address register 1211, the output terminal A is controlled to output the corresponding address signal, so that the AND gate X1 or the AND gate X2 drives the redundant bit line in the corresponding storage area, and performs the corresponding mapping and replacement operation of the normal bit line.

[0048] It should be noted that, in one example, all information stored in an address register 1211 may specifically include the column address (CA) of a damaged normal bit line and an identification bit. The damaged bit line address mentioned above is the column address. The identification bit can be output via output terminal B. The identification bit does not simultaneously drive redundant bit lines in different storage regions. The column address is output via output terminal A to allocate redundant bit lines within the corresponding storage region for driving, ultimately selecting a redundant bit line to map and replace the damaged normal bit line. The number of bits of the identification bit is at least one. The more bits of the identification bit, the more storage regions can be distinguished, which is not limited here.

[0049] The processing circuit 14 may also include a redundant bit line driver configured for each storage area. The redundant bit line driver is used to drive each redundant bit line of the corresponding storage area to map and replace the damaged normal bit line in the storage area. The redundant bit line driver can determine the redundant bit line in the storage area to be driven based on the received signal for driving. The redundant bit line driver can be specifically as follows: Figure 1 The portion of the redundant bit line decoding circuit shown may also be a device located between the processing circuit 14 and the storage area 111 and connected to the processing circuit 14 and the storage area 111 respectively. It may also be arranged on the storage area 111 in other ways to drive the redundant bit lines in the corresponding area, which is not limited here.

[0050] In one embodiment, see Figure 6 , Figure 6 FIG. 1 is a schematic structural diagram of an embodiment of the storage device of the present application. Figure 6 As shown, the storage device further includes a command decoder 13 and a processing circuit 14 .

[0051] The command decoder 13 is configured to generate corresponding bit line addressing addresses in response to user instructions.

[0052] Processing circuit 14 is coupled to programming memory circuit 12, command decoder 13, and memory block 11. Processing circuit 14 is configured to receive a bit line addressing address and a damaged bit line address to perform bit line addressing. In response to the bit line addressing address matching a damaged bit line address, processing circuit 14 generates a corresponding redundant bit line enable signal to drive the redundant bit line corresponding to the matched damaged bit line address to map and replace the normal bit line corresponding to the bit line addressing address.

[0053] Specifically, if Figure 6 As shown, the relevant circuits connected to a storage area 111 are shown. The command decoder 13 can be used to generate a bit line addressing address of a normal bit line to be written or read according to a user instruction, and input the bit line addressing address into the processing circuit 14. In addition, the burning storage module 121 inputs the damaged bit line address into the processing circuit 14 respectively. The processing circuit 14 can match the bit line addressing address with each damaged bit line address based on the received address. If the match is not successful, the normal bit line corresponding to the bit line addressing address in the normal storage array 1111 is driven to read and write data. If the match is successful, the redundant bit line corresponding to the matched damaged bit line address in the redundant storage array 1112 is driven to map and replace the normal bit line corresponding to the bit line addressing address to read and write data.

[0054] Based on the above method, normal processing can be performed when the common bit lines to be read and written are normal, and when the common bit lines to be read and written are damaged, the corresponding redundant bit lines can be driven for mapping replacement to maintain the normal operation of the storage device and improve the reliability of the storage device.

[0055] Alternatively, as Figure 6 As shown, the processing circuit 14 includes an address matching circuit 141 .

[0056] The address matching circuit 141 is coupled to the programming storage circuit 12 and the command decoder 13, wherein the address matching circuit 141 is configured to receive the damaged bit line address from the programming storage circuit 12 and the bit line addressing address from the command decoder 13, and compare the bit line addressing address with the damaged bit line address to determine whether the bit line addressing address matches at least one of the damaged bit line addresses.

[0057] Specifically, the address matching circuit 141 can be connected to a burning storage module 121 in the burning storage circuit 12. The address matching circuit 141 can perform the above-mentioned steps of matching the bit line addressing address with the addresses of each damaged bit line, so as to achieve normal processing when the ordinary bit line to be read or written is normal, and drive the corresponding redundant bit line to perform mapping replacement when the ordinary bit line to be read or written is damaged, so as to maintain the normal operation of the storage device and improve the reliability of the storage device.

[0058] Furthermore, if Figure 6 As shown, the processing circuit 14 further includes a redundant bit line decoding circuit 142 .

[0059] The redundant bit line decoding circuit 142 is coupled to the address matching circuit 141, wherein the redundant bit line decoding circuit 142 is configured to receive the matched damaged bit line address in response to the address matching circuit 141 determining that the bit line addressing address matches at least one damaged bit line address, and generate a corresponding redundant bit line enable signal based on the matched damaged bit line address to drive the redundant bit line mapping in a group of redundant bit line groups corresponding to the matched damaged bit line address to replace a group of normal bit lines corresponding to the bit line addressing address.

[0060] Specifically, if Figure 6 As shown, a related circuit corresponding to a storage area 111 is shown. The command decoder 13 can be used to generate a bit line addressing address of a common bit line required to be written or read according to a user instruction, and input the bit line addressing address and the first enable signal EN1 into the address matching circuit 141 to drive the address matching circuit to perform an address matching operation.

[0061] The programming memory module 121 may be used to input the stored damaged bit line addresses into the address matching circuit 141 , so that the address matching circuit 141 performs the above-mentioned address matching operation and compares the bit line addressing address with the damaged bit line addresses in the programming memory module 121 .

[0062] Based on the above comparison, if the bit line addressing address successfully matches a damaged bit line address, it indicates that the normal bit line to be written or read is damaged. The address matching circuit 141 can output a second enable signal EN2 of a second level to drive the redundant bit line decoding circuit 142 to determine the redundant bit line to be driven in the normal memory array 1111 based on the successfully matched damaged bit line address received from the burn memory module 121 or the address matching circuit 141, and output a third enable signal EN3 to write or read data on the driven redundant bit line, mapping the related operations of replacing the damaged normal bit line. The first level and the second level are different. For example, the first level can be a high level and the second level can be a low level, or the first level can be a low level and the second level can be a high level.

[0063] Based on the above approach, when a normal bit line to be read or written is damaged, the corresponding redundant bit line can be driven to perform mapping replacement, thereby maintaining normal operation of the storage device and improving the reliability of the storage device.

[0064] Furthermore, the step of generating a corresponding redundant bit line enable signal based on the matched damaged bit line address to drive a redundant bit line mapping in a group of redundant bit lines corresponding to the matched damaged bit line address to replace a group of normal bit lines corresponding to the bit line addressing address may specifically include:

[0065] Based on the matched damaged bit line address and the identification bit, a storage area 111 corresponding to the matched damaged bit line address in the main storage area and the auxiliary storage area is determined, and a corresponding redundant bit line enable signal is generated to drive a redundant bit line in a group of redundant bit lines corresponding to the matched damaged bit line address in the storage area 111 corresponding to the matched damaged bit line address, and to map a group of normal bit lines corresponding to the bit line addressing address.

[0066] Specifically, the address register 1211 storing the damaged bit line address also stores an identification bit for identifying the storage area 111 to which the redundant bit line to be mapped and replaced belongs. Based on the information contained in the identification bit, it can be determined which storage area's redundant bit line to drive for mapping and replacement. Based on this setting, the redundant bit line to be driven and the storage area to which it belongs can be determined according to the matching damaged bit line address and its corresponding identification bit for mapping and replacement, thereby maintaining the normal operation of the storage device and improving the reliability of the storage device.

[0067] For example, in one example, all information stored in an address register includes a damaged bit line address of a damaged normal bit line and an identification bit for identifying the storage area 111 to which the damaged normal bit line belongs. The damaged bit line address can also be called a column address (CA) of the damaged normal bit line.

[0068] The steps of determining the storage area 111 corresponding to the matched damaged bit line address in the main storage area and the auxiliary storage area based on the matched damaged bit line address and the identification bit, and generating a corresponding redundant bit line enable signal may specifically include:

[0069] The storage area corresponding to the damaged bit line address is determined based on the identification bit, and a redundant bit line enable signal corresponding to the storage area corresponding to the damaged bit line address is generated based on the matched damaged bit line address and the identification bit.

[0070] Based on the above method, the storage area to which the redundant bit lines that need to be driven corresponding to each damaged bit line address belong can be reasonably distinguished through the identification bit, so that the redundant bit lines in different storage areas are mapped and replaced with the normal bit lines through the information stored in different address registers 1211 in the same burning storage module 121, thereby improving the flexibility of allocating storage resources for the damaged bit line addresses in the burning storage module 121, maintaining the normal operation of the storage device, and improving the reliability of the storage device.

[0071] Furthermore, the processing circuit 14 further includes a normal bit line decoding circuit 143 .

[0072] The normal bit line decoding circuit 143 is coupled to the address matching circuit 141, wherein the normal bit line decoding circuit 143 is configured to receive the bit line addressing address in response to the address matching circuit 141 determining that the bit line addressing address does not match any damaged bit line address, and generate a corresponding normal bit line enable signal based on the bit line addressing address to drive the normal bit lines in a group of normal bit line groups corresponding to the matched bit line addressing address.

[0073] Specifically, if Figure 6 As shown, based on the comparison described above, if the bit line addressing address does not successfully match any damaged bit line address, it means that the normal bit line to be written or read is not damaged, and the address matching circuit 141 can output the second enable signal EN2 of the first level to drive the normal bit line decoding circuit 143 to determine the normal bit line to be driven in the normal storage array 1111 based on the bit line addressing address received from the command decoder 13 or the address matching circuit 141, and output the fourth enable signal EN4 to write or read data on the driven normal bit line.

[0074] Based on the above method, when the common bit line to be read or written is damaged, the corresponding redundant bit line can be driven to perform mapping replacement to maintain the normal operation of the storage device, and when the common bit line to be read or written is not damaged, the corresponding common bit line can be driven to perform normal reading and writing processing, thereby improving the reliability of the storage device.

[0075] In one embodiment, the memory array may further include a plurality of sense amplifiers, the normal memory array may include a plurality of normal bit lines and a plurality of word lines, and the redundant memory array may include a plurality of redundant bit lines and a plurality of word lines.

[0076] The normal bit lines are directly or indirectly connected to the sense amplifiers and the word lines, respectively. The redundant bit lines are directly or indirectly connected to the sense amplifiers and the word lines, respectively.

[0077] Specifically, the memory array can be divided into multiple memory sub-areas along the bit line extension direction, each memory sub-area can be provided with a corresponding sensitive amplifier, and ordinary bit lines or redundant bit lines can form a memory unit through corresponding transistors and corresponding bit lines. Each bit line can be connected to each sensitive amplifier respectively to improve the voltage sensitivity of each memory sub-area, thereby improving the storage efficiency and further improving the reliability of the memory device.

[0078] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0079] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0080] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0081] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (which can be a personal computer, server, network device, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0082] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A storage device, characterized in that: include: A memory block includes a plurality of memory areas, each of the memory areas includes a normal memory array and a redundant memory array, wherein redundant bit lines in the redundant memory array are used to map and replace normal bit lines in the normal memory array; The programming storage circuit includes a plurality of programming storage modules, each of which is respectively arranged corresponding to the two or more storage areas. The programming storage modules include a plurality of address registers, each of which is used to store a damaged bit line address and an identification bit, wherein the identification bit indicates whether the damaged bit line address stored in each address register corresponds to a main storage area or an auxiliary storage area among the two or more storage areas.

2. The storage device according to claim 1, wherein The storage block includes two storage planes, each of the storage planes includes the primary storage area and at least one auxiliary storage area; Each of the burning storage modules corresponds to the main storage area and one of the auxiliary storage areas on the same storage surface, or each of the burning storage modules corresponds to the main storage area of ​​one storage surface and one of the auxiliary storage areas of another storage surface.

3. The storage device according to claim 1 or 2, characterized in that The storage device further includes: a command decoder configured to generate a corresponding bit line addressing address in response to a user command; A processing circuit is coupled to the burn storage circuit, the command decoder, and the storage block; the processing circuit is configured to receive the bit line addressing address and the damaged bit line address to perform bit line addressing; in response to the bit line addressing address matching the damaged bit line address, generate a corresponding redundant bit line enable signal to drive the redundant bit line mapping corresponding to the matched damaged bit line address to replace the normal bit line corresponding to the bit line addressing address.

4. The storage device according to claim 3, wherein: The processing circuit comprises: An address matching circuit is coupled to the burn storage circuit and the command decoder, wherein the address matching circuit is configured to receive the damaged bit line address from the burn storage circuit and the bit line addressing address from the command decoder, and compare the bit line addressing address with the damaged bit line address to determine whether the bit line addressing address matches at least one of the damaged bit line addresses.

5. The storage device according to claim 4, wherein: The processing circuit further includes: A redundant bit line decoding circuit is coupled to the address matching circuit, wherein the redundant bit line decoding circuit is configured to receive the matched damaged bit line address in response to the address matching circuit determining that the bit line addressing address matches at least one damaged bit line address, and generate a corresponding redundant bit line enable signal based on the matched damaged bit line address to drive the redundant bit line mapping in a group of redundant bit lines corresponding to the matched damaged bit line address to replace the group of normal bit lines corresponding to the bit line addressing address. The storage device according to claim 5 , wherein: The generating a corresponding redundant bit line enable signal based on the matched damaged bit line address to drive a redundant bit line mapping in a group of redundant bit lines corresponding to the matched damaged bit line address to replace a group of normal bit lines corresponding to the bit line addressing address includes: Based on the matched damaged bit line address and the identification bit, a storage area corresponding to the matched damaged bit line address in the main storage area and the auxiliary storage area is determined, and a corresponding redundant bit line enable signal is generated to drive the redundant bit line mapping of a group of redundant bit lines corresponding to the matched damaged bit line address in the storage area corresponding to the matched damaged bit line address to replace a group of normal bit lines corresponding to the bit line addressing address.

7. The storage device according to claim 6, wherein: The determining, based on the matched damaged bit line address and the identification bit, a storage area corresponding to the matched damaged bit line address in the main storage area and the auxiliary storage area, and generating a corresponding redundant bit line enable signal, includes: The storage area corresponding to the damaged bit line address is determined based on the identification bit, and a redundant bit line enable signal corresponding to the storage area corresponding to the damaged bit line address is generated based on the matched damaged bit line address and the identification bit.

8. The storage device according to claim 4, wherein: The processing circuit further includes: A normal bit line decoding circuit is coupled to the address matching circuit, wherein the normal bit line decoding circuit is configured to receive the bit line addressing address in response to the address matching circuit determining that the bit line addressing address does not match any of the damaged bit line addresses, and generate a corresponding normal bit line enable signal based on the bit line addressing address to drive the normal bit lines in a group of the normal bit line groups corresponding to the matched bit line addressing addresses.

9. The storage device according to claim 1 or 2, characterized in that: Before the storage device leaves the factory, the identification bit and the damaged bit line address are jointly burned into each of the burning storage modules.

10. The storage device according to claim 1 or 2, characterized in that: The memory array further includes a plurality of sense amplifiers, the normal memory array includes a plurality of normal bit lines and a plurality of word lines, and the redundant memory array includes a plurality of redundant bit lines and a plurality of word lines; The normal bit lines are directly or indirectly connected to the sense amplifiers and the word lines, respectively. The redundant bit lines are directly or indirectly connected to the sense amplifiers and the word lines, respectively.

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