Capacitor with overvoltage protection function and preparation method thereof

Abstract

The application discloses a capacitor with overvoltage protection function and a preparation method thereof, and relates to the technical field of capacitors and preparation methods thereof. The capacitor comprises a capacitor unit, the capacitor unit comprises an X7R characteristic dielectric layer, an inner electrode and an end electrode, and further comprises: a pressure-sensitive resistor unit, which is arranged in parallel at the bottom or top of the capacitor unit and has a nonlinear overvoltage protection characteristic; and a permeation layer, which is used for combining the pressure-sensitive resistor unit with the dielectric layer of the capacitor unit to form a parallel overvoltage protection path. The pressure-sensitive resistor unit is combined with the capacitor unit by the permeation layer to form a parallel overvoltage protection path, so that the surge current path is controlled, and the overvoltage protection effect is realized.

Description

Technical Field

[0001] This invention relates to the technical field of capacitors and their manufacturing methods, specifically to a capacitor with overvoltage protection function and its manufacturing method. Background Technology

[0002] The surge protection capability of a capacitor refers to its ability to maintain structural integrity and avoid breakdown or performance degradation when subjected to transient high voltage or high current surges (such as lightning strikes, switching, electrostatic discharge, etc.) for a short period of time.

[0003] DC power supplies often have loads with large pulsating power, so large-capacity capacitors are often connected in parallel at the load's power supply terminal to store energy, providing pulse power and reducing disturbances to the input power supply. However, the connection of large-capacity capacitors can cause input surge problems when devices are powered on; that is, when the input voltage jumps sharply upwards, it causes a large inrush current, which can damage the capacitor.

[0004] The voltage surge resistance of ceramic capacitors is usually measured by the dielectric withstand voltage, which is generally 2.5 times the rated voltage (hereinafter referred to as U). R This represents the rated voltage, but the actual surge voltage that a capacitor withstands under complex operating conditions may exceed 2.5µV. R Typical values ​​can reach 3 to 10 times that of U. R .

[0005] Because the voltage surges they withstand exceed the design and production control requirements of capacitors, traditional ceramic capacitors are easily damaged when faced with excessively high surge voltages or voltage transients. Failure modes include dielectric breakdown, internal electrode melting, and crack propagation, all of which are short-circuit failures that affect the stability and reliability of the entire circuit.

[0006] In existing electronic systems, ceramic capacitors (MLCCs) are widely used as key energy storage and filtering components. Their surge voltage withstand capability directly determines the system's withstand threshold for transient overvoltages. To protect MLCCs from surge voltage damage, existing technologies typically employ the following measures in circuit design:

[0007] I. Existing Technology 1: Adding Surge Suppression Components

[0008] (1) Parallel varistors: A varistor is a non-linear resistor. When the voltage exceeds its threshold, the resistance will drop rapidly. Parallel varistors can absorb and dissipate excessive voltage.

[0009] (2) External diodes share surge pressure: Diodes can withstand high-energy pulses in a short time and clamp the voltage within a safe range. Adding diodes can suppress transient voltage.

[0010] (3) Series current limiting resistor: Connecting an appropriate resistor in series at the power input terminal can limit the magnitude of the surge current, thereby protecting the capacitor.

[0011] The limitations of existing surge suppression components: Regardless of the type of component added, a complete PCB layout is required. Furthermore, adding discrete components increases parasitic inductance, potentially increasing surge voltage. Additionally, the lifespan and soldering process risks of each new component must be considered, impacting the overall reliability of the device.

[0012] II. Existing Technology 2: Setting a Soft-Start Circuit

[0013] To suppress inrush current upon power-up, prior art 2 involves designing a soft-start circuit by adding a variable resistor unit at the front end of the capacitor. The variable resistor unit initially presents a high resistance value to limit the current upon power-up, and then changes to a low resistance value to reduce the impact on the circuit. During circuit startup, the voltage or current is gradually increased to avoid instantaneous high-voltage surges.

[0014] Existing technology 2: Limitations of soft-start circuit: (1) Soft-start circuit will reduce the response time of the circuit, delaying the original nanosecond response to hundreds of nanoseconds or even microseconds, making it unusable for sensitive circuits; (2) The impedance of the variable resistor unit in the soft-start circuit is at the ohm level, which is much higher than the milliohm equivalent series resistance of the ceramic capacitor, which will significantly increase circuit losses; (3) Soft-start circuit also requires the addition of other components, which brings new failure risks and reduces the reliability of the system and the whole machine.

[0015] III. Existing Technology 3: Software Control

[0016] A sensor is added to the input terminal to monitor voltage changes in real time. The switching status of the circuit is controlled by software, and protective measures are taken in time when a surge voltage is detected.

[0017] Existing technology 3: Limitations of software control: Existing technology 3 requires the addition of external control circuits, which increases system complexity, increases device size, extends the research and development cycle, and increases manufacturing costs.

[0018] While the above-mentioned existing technologies can effectively protect ceramic capacitors from surge voltage, they all inevitably change the PCB design, add new components, and increase the size of the device, thus limiting their use in space-sensitive fields such as aerospace power supplies, medical equipment, and automotive electronics.

[0019] With the miniaturization of electronic devices, circuit designs place increasingly stringent requirements on capacitor size to save circuit board space. However, existing capacitors often fail to provide effective transient voltage protection while maintaining a small size, and capacitor failure can easily lead to short circuits and more serious consequences. For example, in aerospace and implantable medical fields, capacitors in high-density miniaturized devices are difficult to repair or replace once they fail. Therefore, there is an urgent need for a capacitor that maintains large capacitance and small size while providing overvoltage protection. Summary of the Invention

[0020] The purpose of this invention is to provide a capacitor with overvoltage protection function and its preparation method, so as to solve the problem of weak overvoltage protection capability of small-volume ceramic capacitors in the prior art.

[0021] First, this embodiment of the invention provides a capacitor with overvoltage protection function, including a capacitor unit, the capacitor unit including an X7R characteristic dielectric layer, an internal electrode and a terminal electrode, and further including:

[0022] A varistor unit, connected in parallel at the bottom or top of the capacitor unit, has non-linear overvoltage protection characteristics;

[0023] The permeation layer is used to combine the dielectric layer of the varistor unit and the capacitor unit to form a parallel overvoltage protection path.

[0024] Secondly, this embodiment of the invention also provides a method for preparing a capacitor with overvoltage protection function, including the following steps:

[0025] S1: Powder preparation, including the preparation of barium zinc titanate dielectric ceramic powder and zinc oxide varistor ceramic powder;

[0026] S2: Casting film, the prepared barium zinc titanate dielectric ceramic powder and zinc oxide varistor ceramic powder are cast into dielectric ceramic film and varistor ceramic film respectively;

[0027] S3: In sequence, perform internal electrode printing, lamination and isostatic pressing, cutting, glue removal, sintering, chamfering, end sealing and electroplating.

[0028] As an optional implementation, the preparation of the barium zinc titanate dielectric ceramic powder in S1 includes using Ba... 1- X Zn X TiO3 is the main phase, where 0.1 ≤ x ≤ 0.3;

[0029] Add SrZrO3 or CaZrO3 as a second phase; dope Al 3+ and Mn 4+The weight ratio is 0.8~1.2:0.8~1.2, and the total doping amount does not exceed 0.5wt%. The composite powder is synthesized by the oxalate method.

[0030] Specifically, Al 3+ and Mn 4+ Simultaneous doping can balance charge defects, Al 3+ Replace Ti 4+ When a negative charge is introduced, Mn 4+ By occupying different lattice sites or providing positive charge compensation, the overall lattice electrical neutrality is maintained. Both work synergistically to reduce oxygen vacancies and decrease defect density, thereby optimizing the dielectric properties and stability of the ceramic.

[0031] In an embodiment of the present invention, Al 3+ and Mn 4+ The preferred weight ratio is 0.8~1.2:0.8~1.2, more preferably 1:1, if Al 3+ Excessive Al content will cause an increase in grain boundary resistance. 3+ Occupy Ti 4+ Excessive acceptor defects at Mn sites hinder carrier migration, reducing current carrying capacity (decreased surge withstand performance) and degrading product performance. This also increases dielectric loss due to the increased loss tangent (tgδ). 4+ Excessive amounts of Mn can cause oxygen vacancy out-of-control conditions. 4+ As a donor dopant, it increases the oxygen vacancy concentration, leading to increased leakage current and decreased insulation resistance (DC insulation resistance at room temperature is less than 10000MΩ).

[0032] In this embodiment of the invention, the total doping amount is set to no more than 0.5 wt%, which can avoid the deterioration of grain boundary properties caused by excessive doping. This is because excessive doping leads to the degradation of the main phase (Ba). 1-x Zn x TiO3 lattice distortion forms unexpected secondary phases (Al2O3 or MnO2 clusters), which disrupts the material's uniformity and leads to a significant decrease in the dielectric constant (ε).

[0033] Preferably, Ba is used. 1-X Zn X TiO3 (x=0.15~0.25) oxalate coprecipitated powder reduces the sintering activation energy, enabling the dielectric layer to be fully densified at 950~1050℃.

[0034] As an optional implementation, the main phase, the second phase, and the dopant in the barium zinc titanate dielectric ceramic powder are 84-90 wt%, 8-14 wt%, and 0.1-0.5 wt%, respectively. Preferably, the second phase is 10-14 wt% SrZrO3, forming a fine-grained structure (grain size ≤ 2 μm), which improves the mechanical strength of the dielectric layer and suppresses crack propagation during co-firing.

[0035] It should be noted that, in this embodiment of the invention, due to the mismatch in sintering temperatures between the barium zinc titanate dielectric ceramic and the zinc oxide varistor ceramic, the barium zinc titanate requires low-temperature sintering (900~1050℃) to match the melting point of the palladium-silver electrode (Ag / Pd = 80 / 20, melting point ~950℃). However, the sintering temperature of the traditional zinc oxide varistor layer is >1100℃. High temperatures can cause silver volatilization and palladium oxidation in the palladium-silver electrode, generating a brittle phase and disrupting electrode continuity. Furthermore, as a high-dielectric material, barium zinc titanate typically has a coefficient of thermal expansion of 8 × 10⁻⁶. -6 The coefficient of thermal expansion is approximately 6 × 10⁻⁶ K, while zinc oxide, as a pressure-sensitive material, typically has a coefficient of thermal expansion of 6 × 10⁻⁶. -6 The two phases have different coefficients of thermal expansion, which are around K. During sintering and cooling, internal stress is generated at the interface of the two phases due to the difference in shrinkage, which can easily lead to microcracks or delamination.

[0036] To address the aforementioned issues, liquid-phase sintering aids can be introduced to lower the sintering temperature of zinc oxide, and a permeation layer can be introduced as a thermal expansion buffer structure to achieve a gradual transition. For example, the preparation of the varistor layer powder includes using zinc oxide as the main component, adding auxiliary components, doping with low-temperature sintering aids and grain boundary engineering additives, and then sintering the mixture.

[0037] Preferably, the auxiliary components include CaCO3, Cr2O3, MnO2, Sb2O3, Bi2O3, and Pr6O. 11 ;

[0038] The low-temperature sintering aid includes a Bi2O3-SiO2-ZnO glass phase;

[0039] The grain boundary engineering additives include MnCO3 and Co2O3;

[0040] The zinc oxide component accounts for more than 90 wt% of the total weight; the weight percentages of the auxiliary components are as follows: CaCO3 0.5~2.0 wt%, Cr2O3 0.1~1.5 wt%, MnO2 0.1~1.5 wt%, Sb2O3 0.4~1.0 wt%, Bi2O3 0.1~1.0 wt%, and Pr6O 11 The weight percentage of Bi2O3-SiO2-ZnO glass is 3-5 wt%; the weight percentage of MnCO3 is 0.5-1.5 wt%; and the weight percentage of Cr2O3 is 0.3-0.8 wt%.

[0041] It should be noted that MnCO3 decomposes into MnO2 during sintering, inhibiting grain growth, stabilizing grain boundary electrical properties, and improving the nonlinear coefficient of the varistor and reducing leakage current by forming the Zn2MnO4 grain boundary phase. Co in Co2O3... 2+ / Co 3+ Redox reactions can regulate the concentration of oxygen vacancies and charge distribution at grain boundaries, which is beneficial for adjusting the height of the grain boundary barrier, enhancing the voltage gradient and surge resistance of the material. The two work together to improve the product's withstand voltage. Adding either component alone may lead to performance imbalance. Adding only MnCO3 will reduce the voltage gradient, while adding only Co2O3 will increase the leakage current.

[0042] By doping with low-temperature sintering aids, the sintering temperature of zinc oxide is reduced from >1100℃ to 850~950℃. The glassy phase forms a liquid phase during sintering, promoting grain boundary diffusion in zinc oxide and lowering the densification temperature. Preferably, doping with MnCO3 (0.2~0.5wt%) and Co2O3 (0.1~0.3wt%) can inhibit excessive growth of zinc oxide grains. The reaction of MnCO3 and Co2O3 to form a spinel phase acts as a penetration layer at the interface between barium zinc titanate and zinc oxide, alleviating interfacial stress caused by the difference in thermal expansion coefficients between the two phases and avoiding thermal expansion coefficient mismatch.

[0043] As an optional implementation, the stacking and isostatic pressing in S3 includes alternately stacking dielectric ceramic films and inner electrode layers according to the designed number of layers, and then stacking varistor films after completing the stacking of dielectric ceramic films; after completing the stacking of all dielectric ceramic films and varistor films, isostatic pressing is performed at a pressure of 8000~12000PSI; preferably 10000PSI.

[0044] As an optional implementation, the sintering described in S3 includes co-firing at 950~1050℃ under a reducing atmosphere. A mixture of N2 + 2.5%~3.5% H2 gas is introduced throughout the co-firing process, and the oxygen partial pressure is controlled to be <10. -10 atm prevents Ag oxidation and Pd migration.

[0045] As an optional implementation, the co-firing in S3 includes seven stages: heating stage, debinding stage, pre-sintering stage, sintering stage, heat preservation stage, stress release stage, and cooling stage.

[0046] For example, the heating stage includes: raising the temperature from room temperature to 450~550℃ at a heating rate of 1.8~2.2℃ / min, with slow heating to avoid rapid decomposition of organic matter leading to porosity; the debinding stage includes: holding at 450~550℃ for 55~65min to ensure sufficient decomposition and volatilization of the organic binder; the pre-sintering stage includes: raising the temperature from 450~550℃ to 900~1000℃, causing the glass phase to soften and form a liquid phase filling the grain boundary pores; the sintering stage includes: raising the temperature from 900~1000℃ to 1000~1100℃, with the palladium-silver internal electrode at N2+2.5%~3 Sintering is completed under a weak reducing atmosphere of 0.5% H2; the holding stage includes: holding at 1000~1100℃ for 110~130min, where barium zinc titanate and zinc oxide achieve chemical bonding through glass phase diffusion to form a permeation layer; the stress release stage includes: cooling from 1000~1100℃ to 750~800℃ at a rate of 0.8~1.2℃ / min to slowly release the residual thermal stress between barium zinc titanate and zinc oxide, avoiding interlayer cracks; the cooling stage includes: cooling from 750~800℃ to room temperature with the furnace, and stopping the charging of H2 under controlled atmosphere to avoid H2 reacting with the material at low temperature.

[0047] The embodiments of the present invention promote interlayer densification by designing a reasonable sintering curve and combining it with atmosphere sintering, thereby reducing the porosity to <1%.

[0048] Compared with the prior art, the embodiments of the present invention have the following advantages and beneficial effects:

[0049] 1. In this embodiment of the invention, the varistor unit is combined with the capacitor unit through a permeation layer to form a parallel overvoltage protection path, thereby controlling the surge current path and achieving the effect of overvoltage protection.

[0050] 2. This invention, through material composite and structural innovation, employs co-firing of varistor ceramic and X7R characteristic dielectric ceramic to integrate the varistor function into the ceramic capacitor, forming a parallel structure of a chip varistor and a ceramic capacitor. This provides overvoltage protection for the capacitor, protecting it from excessively high surge voltages or transient overvoltages. The temperature-stable X7R dielectric design ensures the stability of the capacitance value over a wide temperature range (-55℃ to +125℃), meeting the requirements of use in complex environments. The internal electrode uses a silver-palladium alloy internal electrode, forming a capacitor structure between the dielectric layers. Varistor units are placed at the bottom or top and bottom of the capacitor's axial plane, and the zinc oxide varistor layer and the two end electrodes are embedded inside the capacitor. Through a permeation layer (Al2O3-SiO2-ZnO glass phase) combined with the dielectric layer, a parallel overvoltage protection path is formed (e.g., ...). Figure 1(As shown) The surge current path is controlled to achieve overvoltage protection. Through optimized design and manufacturing processes, a miniaturized surface-mount capacitor form factor is achieved, minimizing board space occupation and facilitating reflow operations during board-level assembly. The parallel structure of the ceramic capacitor and the thin-film varistor provides transient voltage protection for the capacitor, effectively preventing damage from excessive surge voltage or voltage transients.

[0051] 3. The capacitor provided in this embodiment of the invention has the advantage of functional integration, achieving filtering and overvoltage protection with a single component. Compared with discrete component technology, the PCB area is reduced by 50% to 70%. It also has repeatable surge voltage withstand capability, a line response speed of <10ns, and a withstand current of >2.5U under an 8 / 20μs waveform. R Furthermore, ΔC / C < 5%. Within the temperature range of -55℃ to +125℃, the capacitance change rate is ≤ ±10%, the varistor voltage drift is ≤ ±5%, and the overall stability is better than that of discrete combinations.

[0052] 4. The capacitor manufacturing process provided by the embodiments of the present invention has high compatibility, short production cycle and low manufacturing cost. It adopts low temperature co-firing technology (≤1050℃), which is compatible with existing ceramic capacitor production lines, reduces mass production costs, ensures component miniaturization and process compatibility, and the production cycle is the same as that of existing ceramic capacitors. Compared with the discrete component technology solution, the cycle is shortened by more than 50%. Attached Figure Description

[0053] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of a capacitor structure provided in an embodiment of the present invention;

[0055] Figure 2 This is a flowchart of the capacitor manufacturing process in an embodiment of the present invention;

[0056] Figure 3 This is a graph showing the sintering temperature of the capacitor in an embodiment of the present invention.

[0057] Figure 4 This is a schematic diagram of the installation for the capacitor bending strength test in an embodiment of the present invention.

[0058] The attached diagram shows the markings and corresponding component names:

[0059] 1-Capacitor unit; 2-Varistor unit. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0062] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0063] In the description of this invention, it should be noted that the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0064] This invention provides a ceramic capacitor with overvoltage protection and its manufacturing method. Its features include small size, minimizing circuit board space, maintaining the electrical parameters of the original circuitry, and allowing reflow soldering during board-level assembly. It achieves an integrated design of capacitor and overvoltage protection, improving the capacitor's tolerance to transient overvoltages and overcoming the shortcomings of traditional soft-start circuits, such as large size, slow response speed, long development cycle, and high manufacturing cost. This meets the high reliability and miniaturization requirements of modern electronic equipment in aerospace, medical, and automotive industries.

[0065] Traditional ceramic capacitors employ a temperature-stable X7R dielectric design, allowing for operation over a wide temperature range and exhibiting good capacitance stability. They offer advantages such as low ESR and a high capacitance-to-weight ratio in high-frequency circuits, but suffer from insufficient surge protection. Varistors (such as zinc oxide varistors) provide non-linear overvoltage protection, but cannot directly replace the function of capacitors. Current technologies often utilize combinations of discrete components such as capacitors, resistors, and diodes, leading to increased circuit size and higher costs.

[0066] Varistors are primarily made of semiconductor or insulating materials such as zinc oxide ceramic. Under the influence of an external voltage, the conductivity of the material changes, causing a change in resistance. When the voltage across the varistor falls below a certain threshold (varistor voltage, hereinafter referred to as V), the resistance changes. 1mAWhen the voltage exceeds a certain threshold, the resistance of a varistor is relatively high, similar to a small capacitor, and does not significantly affect the current. When the voltage exceeds this threshold, the resistance drops sharply, allowing a large current to flow, thus quickly dissipating surge current and protecting downstream circuitry from damage. Varistors have a very fast response time, typically within 10ns, enabling them to respond to voltage changes in an extremely short time. In electronic circuits, varistors are often used as overvoltage protection components, especially at AC input terminals, where they absorb and disperse high voltages, preventing circuit damage due to overvoltage.

[0067] This patented technology utilizes the high-voltage path principle of varistor ceramic materials. Through material composite and structural innovation, it employs co-firing of varistor ceramic and X7R characteristic dielectric ceramic, integrating the varistor function into the ceramic capacitor. This forms a multilayer structure of varistor and ceramic capacitor connected in parallel, providing overvoltage protection to the capacitor from excessively high surge voltage or transient voltage. The capacitor unit of this patented product uses a temperature-stable X7R dielectric design, ensuring the stability of the capacitance value over a wide temperature range (-55℃ to +125℃), meeting the needs of use in complex environments. The internal electrode uses a silver-palladium alloy internal electrode, forming a capacitor structure between the dielectric layers. Varistor units are placed at the bottom or top and bottom of the capacitor's axial plane, and the zinc oxide varistor layer and the two end electrodes are embedded inside the capacitor. Through a permeation layer (Al2O3-SiO2-ZnO glass phase) combined with the dielectric layer, a parallel overvoltage protection path (such as...) is formed. Figure 1 (As shown) The surge current path is controlled to achieve overvoltage protection. Through optimized design and manufacturing processes, a miniaturized surface-mount capacitor form factor is achieved, minimizing board space occupation and facilitating reflow operations during board-level assembly. The parallel structure of the ceramic capacitor and the thin-film varistor provides transient voltage protection for the capacitor, effectively preventing damage from excessive surge voltage or voltage transients.

[0068] Specifically, such as Figure 2 As shown, this embodiment of the invention provides a method for manufacturing a capacitor with overvoltage protection function, including the following:

[0069] 1. Powder preparation: The main phase of the dielectric ceramic layer is barium zinc titanate (Ba). 1-X Zn X TiO3 (0.1≤x≤0.3%), accounting for 84~90wt%, provides a high dielectric constant; the second phase is SrZrO3 / CaZrO3 (8~14wt%), forming a perovskite structure with both tetragonal and rhombohedral crystals, enhancing performance; Al doping... 3+ Mn 4+ (0.1~0.5wt%), reduces grain boundary resistance and improves current carrying capacity. Mix barium zinc titanate (Ba) in a specified proportion. 1-X Zn XTiO3), SrZrO3 and dopants (Al) 3+ Mn 4+ The composite powder was synthesized using the oxalate method.

[0070] The varistor layer is mainly composed of zinc oxide (ZnO), with auxiliary components added (0.5~2.0wt% CaCO3, 0.1~1.5wt% Cr2O3, 0.1~1.5wt% MnO2, 0.4~1.0wt% Sb2O3, 0.1~1.0wt% Bi2O3, 0.01~0.2wt% Pr6O). 11 These materials are mixed and shaped into thin layers for subsequent stacking. Zinc oxide varistor ceramic powder is doped with a low-temperature sintering aid Bi2O3-SiO2-ZnO glass phase (3~5wt%) and grain boundary engineering additives MnCO3 (0.5~1.5wt%) and Co2O3 (0.3~0.8wt%), and then sintered at low temperatures (850~950℃) to form a permeation layer precursor.

[0071] Zinc oxide raw material: Zinc oxide is the main raw material (weight ratio greater than 90wt%), and a small amount of fillers such as calcium carbonate, chromium oxide, manganese oxide, antimony oxide, bismuth oxide, and praseodymium oxide are added on this basis. A small amount of glass material and oxide additives are also added. All raw materials are weighed accurately according to the proportion and then fully mixed. Ball milling or jar milling can be used to ensure uniform distribution.

[0072] Because the two materials have different performance requirements and reaction characteristics, barium titanate and zinc oxide raw materials are ball-milled and mixed separately to ensure their respective properties.

[0073] Cast films: The prepared barium zinc titanate ceramic slurry and zinc oxide ceramic slurry are cast into thin films with various thicknesses of 10μm, 13μm, 15μm, 18μm, 20μm, 25μm, 30μm, etc. The thickness fluctuation of the ceramic film is controlled within ±0.5μm.

[0074] 2. Internal electrode printing: Palladium-silver internal electrode paste is printed on the dielectric ceramic film. The pattern and printing thickness of the internal electrode need to be precisely controlled.

[0075] 3. Stacking: The dielectric ceramic films are stacked layer by layer according to the designed number of layers. The dielectric layers are staggered with the films printed with internal electrode paste to ensure that the internal electrodes form a facing area. The stacking is carried out in the order of completing the dielectric ceramic film stacking first, and then the varistor film stacking.

[0076] 4. During the stacking process, the stacking thickness of the dielectric layer (barium zinc titanate layer) and the varistor layer (zinc oxide layer) is determined according to the design requirements of the capacitor's capacitance and rated operating voltage.

[0077] Since the varistor voltage is directly proportional to the thickness of the varistor layer and inversely proportional to the electrode area, the formula is approximately:

[0078] V 1mA ∝Thickness / Electrode Area

[0079] The varistor layer thickness can be adjusted by controlling the number of zinc oxide ceramic film layers, thereby linearly regulating the varistor voltage value.

[0080] The higher the rated operating voltage of the capacitor unit in the composite, the smaller the nominal capacitance, the fewer dielectric layers are required, and the more stacking space is left for the varistor unit; the larger the nominal capacitance of the capacitor unit in the composite, the lower the rated operating voltage, the thinner the varistor layer is required, and the thicker the dielectric ceramic layer can be stacked. By balancing the relationship between capacitance and dielectric strength, the volume of the composite can be maintained within a relatively small range.

[0081] 5. Isostatic pressing: After all dielectric ceramic films and varistor films are laminated, isostatic pressing is performed at 10,000 PSI pressure to ensure tight adhesion and uniformity between the two layers and avoid delamination or interface defects.

[0082] 6. Cutting: Cut the stacked material to the required dimensions to obtain individual composite blanks. The cutting process must ensure smooth cuts and dimensional accuracy to avoid affecting subsequent performance.

[0083] 7. Debinding: Similar to the debinding process for single materials, the composite preform is debinded before sintering. The debinding process requires careful control of temperature and time to ensure that organic additives and other components in the preform fully volatilize and are expelled, preventing defects such as bubbles during sintering.

[0084] Since the two materials use different organic solvents, their debinding characteristics may differ. Therefore, it is necessary to take into account the requirements of both materials and formulate a suitable debinding process.

[0085] 8. Sintering: Sintering is a crucial step in the preparation of the composite, requiring simultaneous fulfillment of the sintering requirements for both barium titanate ceramic capacitors and zinc oxide ceramic varistors. Generally, barium titanate has a higher sintering temperature, while zinc oxide has a relatively lower sintering temperature. Therefore, a suitable sintering temperature and time need to be selected to ensure good sintering results for both materials. This patent employs segmented sintering and a special atmosphere to optimize the sintering process and improve the performance of the composite. The stacked composite is sintered at high temperature to form a dense rectangular parallelepiped structure. During the sintering process, the liquid phases between the barium zinc titanate and zinc oxide particles interpenetrate, filling the pores and increasing the density, tightly bonding the dielectric layers of the varistor unit and the capacitor unit to form a parallel overvoltage protection path.

[0086] This patented product is co-fired in a weak reducing atmosphere (N2 + 3% H2) (950~1050℃). The sintering process curve is shown below. Figure 3 The process steps are designed as shown in Table 1 below:

[0087] Table 1

[0088] Serial Number stage temperature heating rate atmosphere Process Step Design Description 1 warming phase Room temperature → 500℃ 2℃ / min dry air Slowly increase the temperature to avoid rapid decomposition of organic matter that could lead to porosity. 2 De-glue stage 500℃→500℃ Keep warm for 60 minutes dry air Air is introduced to assist in the oxidation and decomposition of organic matter, ensuring that the organic adhesive is fully decomposed and volatilized, and thoroughly removing organic solvents (such as PVB and plasticizers) and residual carbon from the cast film. 3 Pre-sintering stage 500℃→950℃ 3℃ / min <![CDATA[Pure N2]]> The glassy phase begins to soften, forming a liquid phase that fills the grain boundary pores, promoting initial interfacial contact between barium zinc titanate and zinc oxide, and reducing the stress caused by the difference in thermal expansion coefficients in the subsequent high-temperature stage. 4 Sintering stage 950℃→1050℃ 1℃ / min <![CDATA[N2+3%H2]]> <![CDATA[Slow heating rate reduces thermal stress. The palladium-silver inner electrode is sintered in a weakly reducing atmosphere to avoid silver volatilization and palladium oxidation, and the H2 content is controlled to inhibit the formation of excessive oxygen vacancies in the BaTiO3 dielectric layer. <!-- 8 -->]]> 5 Insulation stage 1050℃→1050℃ Keep warm for 120 minutes <![CDATA[N2+3%H2]]> Barium zinc titanate and zinc oxide interpenetrate to achieve chemical bonding, forming a gradient layer at the interface, reducing the difference in thermal expansion coefficients and improving the bonding strength. 6 Stress relief stage 1050℃→780℃ 1℃ / min <![CDATA[N2+3%H2]]> The uniform distribution of the glassy phase at the grain boundaries inhibits abnormal growth of zinc oxide grains. Slow cooling releases residual thermal stress between barium zinc titanate and zinc oxide, preventing interlayer cracks. 7 Cooling stage 780℃ → Room temperature Cooling with furnace <![CDATA[Pure N2]]> <![CDATA[Cool with the furnace to lock the microstructure, maintain high density and interfacial bonding strength, control the atmosphere with pure N2 to prevent the reaction between H2 and the material at low temperatures.]]>

[0089] 9. Chamfering: Chamfering is performed on the sintered composite to remove sharp edges and improve the mechanical stability and electrical properties of the composite.

[0090] 10. End sealing: Two external electrode pastes (first end electrode and second end electrode) are coated on the end face of the sintered body and connected to the corresponding internal electrodes through metallic silver.

[0091] The end electrodes need to cover part of the adjacent surfaces (such as the side surface, bottom surface, and top surface) to ensure the reliability of the electrical connection.

[0092] 11. Electroplating: Electroplating is performed on the end electrodes to improve their thermal shock resistance and solderability. The electroplating process needs to be adjusted according to the requirements of the electrode material and the composite.

[0093] Example 1: A method for manufacturing a capacitor with overvoltage protection function, comprising the following:

[0094] 1. Powder preparation: The main phase of the dielectric ceramic layer is barium zinc titanate (Ba). 1-X Zn X TiO3 (x=0.2), comprising 90wt%, provides a high dielectric constant; the second phase is SrZrO3 / CaZrO3 (9.5wt%), forming a perovskite structure with both tetragonal and rhombohedral crystals, enhancing performance; Al doping... 3+ Mn 4+ (Total doping amount 0.5wt%, Al) 3+ and Mn 4+ The ratio is 1:1), which reduces grain boundary resistance and improves current carrying capacity. Barium zinc titanate (Ba) is mixed in a specific ratio. 1-X Zn X TiO3), SrZrO3 and dopants (Al) 3+ Mn 4+ The composite powder was synthesized using the oxalate method.

[0095] The varistor layer is mainly composed of zinc oxide (ZnO, accounting for 92wt%), with the addition of auxiliary components (CaCO3, Cr2O3, MnO2, Sb2O3, Bi2O3, Pr6O). 11The total percentage was 4.1 wt%, of which CaCO3 was 0.8 wt%, Cr2O3 was 0.5 wt%, MnO2 was 0.8 wt%, Sb2O3 was 0.95 wt%, Bi2O3 was 0.95 wt%, and Pr6O2 was 0. 11 (0.1 wt%). These materials are mixed and shaped into thin layers for subsequent stacking. Zinc oxide varistor powder is sintered at low temperature (900 °C) with the low-temperature sintering aid Bi2O3-SiO2-ZnO glass phase (3 wt%) and grain boundary engineering additives MnCO3 (0.5 wt%) and Co2O3 (0.4 wt%).

[0096] Zinc oxide raw material: Zinc oxide is the main raw material (more than 90% of the raw material weight ratio). On this basis, a small amount of calcium carbonate filler, as well as rare earth oxides such as chromium oxide, manganese oxide, antimony oxide, bismuth oxide, and praseodymium oxide are added. A small amount of glass material and oxide additives are also added. All raw materials are weighed accurately according to the proportion and then fully mixed. Ball milling can be used to ensure uniform distribution.

[0097] Because the two materials have different performance requirements and reaction characteristics, barium titanate and zinc oxide raw materials are ball-milled and mixed separately to ensure their respective properties.

[0098] 2. Casting film: The prepared barium titanate ceramic slurry and zinc oxide ceramic slurry are cast into thin films with a thickness of 15μm.

[0099] 3. Internal electrode printing: Print silver-palladium internal electrodes according to the designed internal electrode pattern and number of layers.

[0100] 4. Lamination and Isostatic Pressing: Dielectric ceramic films are stacked layer by layer, with adjacent inner electrode films stacked in a staggered manner according to design requirements. The layout of the internal electrodes needs to be precisely controlled to ensure that the electrodes form a facing area. First, complete the barium zinc titanate lamination according to the designed number of layers, then perform the varistor (zinc oxide layer) lamination, followed by warm isostatic pressing. During the lamination process, ensure tight adhesion and uniformity between the two layers to avoid delamination or interface defects.

[0101] Since the varistor voltage is directly proportional to the thickness of the varistor layer and inversely proportional to the electrode area, the formula is approximately:

[0102] V 1mA ∝Thickness / Electrode Area

[0103] The chip thickness can be adjusted by controlling the number of zinc oxide ceramic film layers, and the varistor voltage value can be linearly adjusted.

[0104] After all dielectric ceramic films and varistor films are laminated, isostatic pressing is performed at 10,000 PSI pressure to ensure tight adhesion and uniformity between the two layers and avoid delamination or interface defects.

[0105] 5. Cutting: Cut the stacked material to the required dimensions to obtain individual composite blanks. The cutting process must ensure smooth cuts and dimensional accuracy to avoid affecting subsequent performance.

[0106] 6. Debinding: Similar to the debinding process for single materials, the composite preform is debinded before sintering. The debinding process requires careful control of temperature and time to ensure that organic additives and other contaminants in the preform are completely volatilized and expelled, preventing defects such as bubbles during sintering.

[0107] 7. Sintering: Sintering is a crucial step in the preparation of the composite, requiring simultaneous compliance with the sintering requirements of both barium titanate ceramic capacitors and zinc oxide ceramic varistors. Generally, barium titanate has a higher sintering temperature, while zinc oxide has a relatively lower sintering temperature. Therefore, a suitable sintering temperature and time need to be selected to ensure good sintering results for both materials. Segmented sintering or special sintering processes can be used to optimize the sintering process and improve the performance of the composite. The stacked structure is sintered at high temperature to form a dense rectangular parallelepiped sintered body. During sintering, auxiliary components precipitate at the ZnO grain boundaries, forming nonlinear resistive characteristics.

[0108] This patented product is co-fired (1050℃) in a weakly reducing atmosphere (N2 + 3% H2 mixed gas), ensuring that the oxygen partial pressure remains at an extremely low level (<10) during the sintering process. -10 The electrode uses an atm (atm) to prevent silver (Ag) migration and palladium (Pd) oxidation, ensuring electrode continuity. H2, as a reducing agent, can inhibit the oxidation of palladium (Pd) in the internal electrode metal, preventing the formation of a brittle phase.

[0109] The sintering process steps are shown in Table 2 below:

[0110] Table 2

[0111] Serial Number stage temperature heating rate atmosphere Process Control Instructions 1 warming phase Room temperature → 500℃ 2℃ / min dry air Slowly increase the temperature to avoid rapid decomposition of organic matter that could lead to porosity. 2 De-glue stage 500℃→500℃ Keep warm for 60 minutes dry air Air is introduced to assist in the oxidation and decomposition of organic matter, ensuring that the organic adhesive is fully decomposed and volatilized, and thoroughly removing organic solvents (such as PVB and plasticizers) and residual carbon from the cast film. 3 Pre-sintering stage 500℃→950℃ 3℃ / min <![CDATA[Pure N2]]> The glassy phase begins to soften, forming a liquid phase that fills the grain boundary pores, promoting initial interfacial contact between barium zinc titanate and zinc oxide, and reducing the stress caused by the difference in thermal expansion coefficients in the subsequent high-temperature stage. 4 Sintering stage 950℃→1050℃ 1℃ / min <![CDATA[N2+3%H2]]> <![CDATA[Slow heating rate reduces thermal stress. The palladium-silver inner electrode is sintered in a weakly reducing atmosphere to avoid silver volatilization and palladium oxidation, and the H2 content is controlled to inhibit the formation of excessive oxygen vacancies in the BaTiO3 dielectric layer.]]> 5 Insulation stage 1050℃→1050℃ Keep warm for 120 minutes <![CDATA[N2+3%H2]]> Barium zinc titanate and zinc oxide interpenetrate to achieve chemical bonding, forming a gradient layer at the interface, reducing the difference in thermal expansion coefficients and improving the bonding strength. 6 Stress relief stage 1050℃→780℃ 1℃ / min <![CDATA[N2+3%H2]]> The uniform distribution of the glassy phase at the grain boundaries inhibits abnormal growth of zinc oxide grains. Slow cooling releases residual thermal stress between barium zinc titanate and zinc oxide, preventing interlayer cracks. 7 Cooling stage 780℃ → Room temperature Cooling with the furnace <![CDATA[Pure N2]]> <![CDATA[Atmosphere control: pure N2 to prevent the reaction between H2 and the material at low temperatures, lock the microstructure, and maintain high density and interfacial bonding strength.]]>

[0112] 8. Chamfering: Chamfering is performed on the sintered composite to remove sharp edges and improve the mechanical stability and electrical properties of the composite.

[0113] 9. End sealing: Two external electrodes (first end electrode and second end electrode) are coated on the end face of the sintered body and connected to the corresponding internal electrodes through metallic silver.

[0114] The end electrode needs to cover part of the adjacent surface (such as the side surface, bottom surface and top surface) to ensure the reliability of the connection between the end electrode and the ceramic body.

[0115] 10. Electroplating: Electroplating is performed on the terminal electrodes to improve the capacitor's thermal shock resistance and solderability. The electroplating process needs to be adjusted according to the requirements of the electrode material and the composite.

[0116] Example 2: A method for preparing a capacitor with overvoltage protection function is provided. The difference from Example 1 is that x=0.25, while the other steps remain unchanged.

[0117] Example 3: A method for preparing a capacitor with overvoltage protection function is provided. The difference from Example 1 is that x=0.15, while the other steps remain unchanged.

[0118] Comparative Example 1: A method for preparing a capacitor is provided, the difference from Example 1 is that x=0.4, and the other steps remain unchanged.

[0119] In this comparative example, excessive zinc doping caused lattice distortion in barium titanate, disrupting the ferroelectric domain structure, introducing defects, and reducing the material's density. Lattice defects increased leakage current, raising tgδ to 0.05, which does not meet the standard requirement of tgδ≤0.025. Performance results are shown in Table 5.

[0120] Comparative Example 2: A method for preparing a capacitor is provided, the difference from Example 1 is that x=0.05, and the other steps remain unchanged.

[0121] In this comparative example, the zinc content is very low. Insufficient zinc content makes it difficult to effectively control the crystal structure of barium titanate, resulting in insufficient optimization of the material's ferroelectricity and a low dielectric constant. According to the data in Table 5 (Comparative Example 2, with lower x), the dielectric constant is only 2310, lower than the dielectric constant (2750) of Example 1 with a higher x value. The loss tangent (tgδ≤0.02) and insulation resistance (≥10) are also lower. 11 Although the Ω) meets the standard, the room for improvement in dielectric constant is limited.

[0122] Comparative Example 3: A method for preparing a capacitor is provided, which differs from Example 1 in that the low-temperature sintering aid Bi2O3-SiO2-ZnO glass phase is not doped, while the remaining steps remain unchanged.

[0123] The main function of the low-temperature sintering aid Bi₂O₃-SiO₂-ZnO glass phase is to lower the sintering temperature of zinc oxide (ZnO) by forming a liquid phase, thereby allowing it to react with barium zinc titanate (Ba). 1-X Zn XThe sintering temperature (≤1050℃) of TiO3 and palladium / silver (Ag / Pd) electrodes is compatible. Lowering the sintering temperature of zinc oxide (ZnO) from >1100℃ to 850~950℃ allows for liquid phase filling during low-temperature sintering, creating grain boundary pores, promoting bonding between the dielectric ceramic and the varistor ceramic surface, and enhancing the overall strength of the product. Without the addition of the Bi2O3-SiO2-ZnO glass phase, the process and performance significantly degrade. Due to the sintering temperature mismatch between barium zinc titanate and ZnO, thermal stress accumulates at the interface, leading to microcracks or delamination, and reducing the varistor voltage (V). 1mA The requirements are not met; the bending strength does not meet the requirements.

[0124] Example 4: A method for preparing a capacitor with overvoltage protection function is provided. The difference from Example 1 is that the varistor layer is mainly composed of zinc oxide (ZnO, accounting for 91 wt%), and auxiliary components (CaCO3, Cr2O3, MnO2, Sb2O3, Bi2O3, Pr6O) are added. 11 The total content was 3 wt%, and the ratio of each component was the same as in Example 1, which was 0.8: 0.5: 0.8: 0.95: 0.95: 0.1. These materials were mixed and shaped into thin layers for subsequent stacking. Zinc oxide pressure-sensitive powder was doped with low-temperature sintering aid Bi2O3-SiO2-ZnO glass phase (5 wt%) and grain boundary engineering additives MnCO3 (0.5 wt%) and Co2O3 (0.5 wt%), and then sintered at low temperature (950 °C) to form a permeation layer precursor. The remaining steps remained unchanged.

[0125] In this embodiment, 5 wt% of a low-temperature sintering aid Bi₂O₃-SiO₂-ZnO glass phase is doped. More of the glass phase forms a liquid phase during sintering, promoting grain boundary diffusion, lowering the densification temperature, and shortening the sintering time. However, excess glass phase forms a continuous layer at the grain boundaries, potentially introducing a small amount of polarization loss. Simultaneously, excess glass phase may locally aggregate, forming amorphous regions, slightly affecting the dielectric response. Performance is shown in Table 5.

[0126] Example 5: A method for preparing a capacitor with overvoltage protection function is provided. The difference from Example 1 is that the varistor layer is mainly composed of zinc oxide (ZnO, accounting for 91 wt%), and auxiliary components (CaCO3, Cr2O3, MnO2, Sb2O3, Bi2O3, Pr6O) are added. 11The total content was 2 wt%, and the ratio of each component was the same as in Example 1, which was 0.8: 0.5: 0.8: 0.95: 0.95: 0.1. These materials were mixed and shaped into thin layers for subsequent stacking. Zinc oxide pressure-sensitive powder was doped with a low-temperature sintering aid Bi2O3-SiO2-ZnO glass phase (6 wt%) and grain boundary engineering additives MnCO3 (0.5 wt%) and Co2O3 (0.5 wt%), and then sintered at low temperature (850 °C) to form a permeation layer precursor. The remaining steps remained unchanged.

[0127] Excessive glass phase forms an excessive liquid phase, which, while promoting densification, inhibits normal grain growth and may cause localized overheating, leading to increased material brittleness. Excessive glass phase covering the surface of barium zinc titanate grains hinders their spontaneous polarization. The glass phase occupying the polarization-active region weakens the dielectric response, and the dielectric constant decreases significantly to 1800~2200.

[0128] Example 6: A method for preparing a capacitor with overvoltage protection function is provided. The difference from Example 1 is that the varistor layer is mainly composed of zinc oxide (ZnO, accounting for 93wt%), and auxiliary components (CaCO3, Cr2O3, MnO2, Sb2O3, Bi2O3, Pr6O) are added. 11 The total content was 3.5 wt%, and the ratio of each component was the same as in Example 1, which was 0.8: 0.5:0.8: 0.95: 0.95: 0.1. These materials were mixed and shaped into thin layers for subsequent stacking. The zinc oxide varistor powder was doped with the low-temperature sintering aid Bi2O3-SiO2-ZnO glass phase (3 wt%) and the grain boundary engineering additive MnCO3 (0.5 wt%), and then sintered at low temperature (900 °C), while the remaining steps remained unchanged.

[0129] Co2O3 is mainly used to regulate the concentration of oxygen vacancies and charge distribution at grain boundaries, which is beneficial for adjusting the grain boundary barrier height and enhancing the voltage gradient and surge resistance of materials. Adding MnCO3 alone results in a lack of Co. 2+ / Co 3+ The compensation effect leads to excessively high oxygen vacancy concentration, significantly reduced grain boundary resistance, insufficient barrier height, reduced varistor voltage, and increased fluctuation range.

[0130] Example 7: A method for preparing a capacitor with overvoltage protection function is provided. The difference from Example 1 is that the varistor layer is mainly composed of zinc oxide (ZnO, accounting for 93wt%), and auxiliary components (CaCO3, Cr2O3, MnO2, Sb2O3, Bi2O3, Pr6O) are added. 11The total content was 3.5 wt%, and the ratio of each component was the same as in Example 1, which was 0.8: 0.5:0.8: 0.95: 0.95: 0.1. These materials were mixed and shaped into thin layers for subsequent stacking. The zinc oxide varistor powder was doped with a low-temperature sintering aid Bi2O3-SiO2-ZnO glass phase (3 wt%) and a grain boundary engineering additive Co2O3 (0.5 wt%), and then sintered at low temperature (900 °C) to form a permeation layer precursor. The remaining steps remained unchanged.

[0131] The main mechanism of action of adding MnCO3 is that Mn 2+ As an acceptor dopant, replacing Ti 4+ Mn doping inhibits the migration of oxygen vacancies, thereby reducing bulk conductivity and leakage current, and minimizing interfacial polarization losses. Furthermore, Mn doping refines the grain size, increases material density, and improves anti-aging properties. When only Co2O3 is added, the disorder of the zinc oxide lattice increases, and the free migration of oxygen vacancies leads to increased leakage current, decreased insulation resistance, and a significant increase in the loss tangent.

[0132] Performance testing: Comprehensive performance testing was conducted on the composites prepared in Examples 1-3, including testing parameters such as capacitance, varistor voltage, nonlinear coefficient, and leakage current. The test items are shown in Table 3 below. Table 4 shows the performance test comparison between the capacitors prepared in Examples 1-3 and traditional capacitors. Table 5 shows the performance test results of the capacitors prepared in Comparative Examples 1-3 and Examples 4-7.

[0133] Table 3

[0134] parameter Test conditions Required value Capacity 1kHz, 1V, 25℃ The capacitance is within the allowable tolerance range. Loss tangent 1kHz, 1V, 25℃ ≤0.025 Insulation resistance <![CDATA[Apply rated voltage U R , 25 °C]]> ≥10000MΩ Dielectric withstand voltage <![CDATA[Apply a DC voltage of 2.5 U R at 25 °C]]> The capacitor shows no breakdown, arcing, or visible damage, and its insulation resistance value meets the initial requirements. Varistor voltage DC scan <![CDATA[V 1mA ±5% (adjustable from 25V to 300V) Surge tolerance <![CDATA[8 / 20 μs waveform, 3U R , 5 times, screening and eliminating products with insufficient tolerance]]> During the test, the capacitor's leakage current was >50mA, and the capacitor showed no breakdown, arcing, or visible damage; after the test, the insulation resistance value met the initial requirements, and the capacitance change rate did not exceed ±10%. flexural strength The capacitors are arranged with the varistor units mounted on the board and the capacitor units facing outwards. Figure 4 The specified mounting is performed on the printed circuit board, and then the printed circuit board is bent at a rate of 1 mm / s. The printed circuit board is bent by at least 2 mm and held in this bent state for 20 seconds ± 1 second. The capacitance is measured while the board is bent, and the change in capacitance compared to the initial measurement should not exceed ± 5.0%. Temperature shock cycle -55~125℃, 1000 cycles The capacitance change rate shall not exceed ±10%, and the varistor voltage drift shall not exceed ±5%. High-temperature electrical aging <![CDATA[125℃,2U R DC voltage, 96h After the test, the capacitor's dielectric withstand voltage, varistor voltage, insulation resistance, capacitance, and loss tangent met the initial requirements. Steady-state humid heat 1.5V, 85℃ / 85%RH, 1000h The insulation resistance shall not be less than the initial required value, and the capacitance change rate shall not exceed ±10%.

[0135] It should be noted that, in Figure 4 In the test, the width of the printed circuit board (PCB) is 1.6mm ± 0.1mm. There are two support points on the PCB, located at both ends. There are two solder points in the middle of the PCB for fixing capacitors. The capacitors are mounted on the PCB with the varistor units facing outwards. The PCB is bent during the test. The length of the bending tool is at least the actual width of both sides of the substrate plus 5mm. The radius of the bending tool is 5mm and the bending diameter is 20mm. During the bending process, the PCB is bent at a rate of 1mm / s for at least 2mm. After bending, the PCB is held in the bent state for 20s ± 1s. Then, the capacitance is measured in the bent state. The capacitance change rate is compared with the initial measurement value and does not exceed ± 5.0%.

[0136] Table 4

[0137] index Traditional multilayer ceramic capacitors Example 1 Example 2 Example 3 Dielectric constant (ε) 2000~3000 2650~2850 2510~2680 2700~3000 Loss tangent (tgδ) ≤0.025 0.019 0.022 0.018 Insulation resistance (Rj) <![CDATA[≥10 4 MΩ or 100MΩ·μF]]> <![CDATA[2.2×10 5 MΩ]]> <![CDATA[2.5×10 5 MΩ]]> <![CDATA[1.9×10 5 MΩ]]> <![CDATA[Breakdown voltage (V 1mA )]]> none 200V~240V 230V~270V 180V~210V Surge tolerance (8 / 20μs) <![CDATA[2.5U R DC withstand voltage <![CDATA[>3U R Repeatable <![CDATA[>3U R Repeatable <![CDATA[>3U R Repeatable Temperature characteristics (-55~125℃) ΔC / C ≤ ±15% (satisfies X7R characteristics) X7R+ Pressure Sensing Stability X7R+ Pressure Sensing Stability X7R+ Pressure Sensing Stability flexural strength 1mm 3mm 2mm 3mm

[0138] Table 5

[0139] index Comparative Example 1 Comparative Example 2 Comparative Example 3 Example 4 Example 5 Example 6 Example 7 Dielectric constant (ε) 1750~2150 2110~2510 1800~2200 2400~2750 1800~2200 2000~2300 1600~2000 Loss tangent (tgδ) 0.05 0.020 0.035 0.023 0.021 0.023 0.044 Insulation resistance (Rj) <![CDATA[2.2×10 5 MΩ]]> <![CDATA[2.2×10 5 MΩ]]> <![CDATA[2.2×10 5 MΩ]]> <![CDATA[2.2×10 5 MΩ]]> <![CDATA[2.2×10 5 MΩ]]> <![CDATA[2.2×10 5 MΩ]]> <![CDATA[0.7×10 5 MΩ]]> <![CDATA[Breakdown voltage (V 1mA )]]> 150V~180V 170V~190V Not satisfied 160V~200V 160V~200V 70V~160V 120V~180V Surge tolerance (8 / 20μs) <![CDATA[≤2.5U R ]]> <![CDATA[≤2.5U R ]]> <![CDATA[≤2.5U R ]]> <![CDATA[≥3U R ]]> <![CDATA[≤2.5U R ]]> <![CDATA[≤2.5U R ]]> <![CDATA[≤2.5U R ]]> Temperature characteristics (-55~125℃) ΔC / C≤±30% -30%≤ΔC / C≤+20% X7R X7R+ Pressure Sensing Stability X7R X7R X7R flexural strength 2mm 3mm Not meeting 1mm 2mm 2mm 2mm 2mm

[0140] Therefore, embodiments 1-7 of this invention integrate the varistor function into the ceramic capacitor through material composite and structural innovation, achieving an integrated design of capacitance and overvoltage protection. Through material composite and structural design, the physical coupling of capacitance and varistor functions is achieved. Zinc oxide varistor material is integrated into the barium titanate dielectric layer, with an internally integrated varistor path, realizing the overvoltage protection function of the filter capacitor. This solves the size, cost, and reliability problems of discrete solutions (capacitor + varistor + protection circuit), as shown in Table 6 below.

[0141] Table 6

[0142] Technical dimension Existing technology Example 1 Beneficial effects Volume fraction More than two components are required; capacitors, resistors, MOSFETs, etc., are discrete and need to be externally assembled. A single component, with the varistor layer integrated inside the capacitor, has a board area similar to that of a ceramic capacitor. PCB area is reduced by 50%~70%, traces are shortened, and loop inductance is reduced (parasitic inductance is reduced to <1nH). Surge Path Surge tolerance relies on external circuitry and has a slow response time. <![CDATA[Built-in high-pressure bypass (>2.5U R ), dynamic impedance regulation]]> <![CDATA[The response time is shortened to less than 10 ns, and the withstand voltage ability is increased to > 2.5 U R or more]]> Packaging Discrete surface mount package, non-standard form factor, requires separate interface design. Integrated surface mount structure, compatible with automatic placement machines, adaptable to standard pads, and reflow soldering. Improved assembly reliability, no new risks associated with solder joint quality or foreign matter, and enhanced resistance to mechanical stress. Production process Different components employ different manufacturing processes and rely on different production lines. Low-temperature co-firing (≤1050℃), compatible with AgPd electrodes and varistors Adapt to existing ceramic capacitor production lines, reducing energy consumption. reliability Discrete components are electrically connected via soldering; the lifespan of the devices is affected by the lifespan of the components themselves and the assembly process. <![CDATA[Bonding by sintering (penetration of Al2O3-SiO2-ZnO glass phase)]]> It features tight connections, no solder joints, no exposed electrodes, and a lifespan consistent with components, far exceeding that of devices. Temperature stability Independent temperature drift of components such as capacitors and resistors Synergistic temperature drift (ΔC / C≤±15%) Improved performance consistency across the entire temperature range Production costs High costs of discrete component procurement and assembly, plus material management costs for multiple components. Single component integration and the advantages of large-scale casting process Cost reduction of more than 40%

[0143] As shown in Tables 4-6, Examples 1-7 of this invention combine barium zinc titanate (a high dielectric constant dielectric) and zinc oxide (a nonlinear varistor material) through a SrZrO3 bridging phase to achieve a dual-function dielectric-varistor integration with a withstand voltage >2.5U. R (Traditional ceramic capacitors only have a dielectric withstand voltage of 2.5U) R ).

[0144] The capacitor and varistor units are designed in a thin parallel configuration and packaged in a standard unencapsulated surface-mount component package, improving assembly reliability. Through a multi-layer electrode design and a built-in variable resistor unit, a parallel connection is formed between the main capacitor path and the varistor bypass path, enabling a single component to achieve filtering and overvoltage protection, reducing PCB area by 50% to 70%.

[0145] Low-temperature co-firing technology (≤1050℃): The sintering temperature is reduced by using Bi2O3-SiO2-ZnO glass phase, which is compatible with Ag / Pd electrodes and avoids electrode oxidation caused by traditional high-temperature sintering of varistor (>1100℃).

[0146] The repeatable surge withstand capability of embodiments 1-7 of this invention demonstrates a withstand current >2.5U under an 8 / 20μs waveform. R (Traditional ceramic capacitors are 2.5uF) R More than 2.5U R (Even with the risk of failure), the circuit response speed is <10ns. It exhibits good temperature stability, with a capacitance change rate ΔC / C ≤ ±15% and varistor voltage drift ≤ ±5% within the range of -55~125℃, demonstrating superior stability across the entire temperature range compared to discrete combinations. The manufacturing process is compatible with existing ceramic capacitor production lines, reducing mass production costs; low-temperature co-firing (≤1050℃) ensures compatibility between the silver electrode and the varistor layer; and the combination of gradient heating and atmosphere-assisted sintering ensures the density of the multilayer structure and consistency of electrical performance.

[0147] The capacitors prepared in Examples 1-7 of this invention provide a disruptive solution for high-density, high-reliability modern electronic systems, especially those with strict requirements for circuit board space (such as aerospace, medical, and automotive), filling the market gap for integrated capacitor-overvoltage protection components.

[0148] For example, it can be effective in the following application scenarios:

[0149] 1. Aerospace Power Supply: Replaces existing soft-start circuits composed of discrete components, integrates EMI filtering and overvoltage protection, and reduces device size.

[0150] 2. Medical equipment: The compact design adapts to high-density PCB layouts and improves the overvoltage protection level of sensitive components.

[0151] 3. Automotive electronics: Withstand temperature fluctuations of -55℃ to 150℃ and resist engine ignition surges.

[0152] With the continuous development of electronic technology, the requirements for the performance and size of components are becoming increasingly stringent. The surge protection capacitor of this invention will have broad market prospects and application space. Table 7 compares the actual application scenarios of the capacitor prepared by the traditional solution and that of Example 1 of this invention.

[0153] Table 7

[0154] Scene Traditional solution (discrete components) Example 1 Advantages Space It requires an external diode and ceramic capacitor, resulting in a large size and high cost. A single component integrates filtering and protection, reducing size. Adaptable to alternating high and low temperature environments, resulting in extended lifespan. medical equipment Discrete varistor + capacitor + protection IC, complex PCB layout Directly replace ceramic capacitors, simplifying the design. Reduced system downtime under abnormal surge impact In-vehicle electronics Frequent surges cause ceramic capacitors to fail, resulting in high maintenance costs. Built-in pressure-sensitive function extends component lifespan Reduced failure rate

[0155] In addition, to better demonstrate the advantages of the capacitor prepared in Embodiment 1 of the present invention, Table 8 shows the comparison between Embodiment 1 of the present invention and the prior art patent CN111555599A; Table 9 shows the comparison between Embodiment 1 of the present invention and the prior art patent CN112993957B; Table 10 shows the comparison between Embodiment 1 of the present invention and the prior art patent CN221960839U; and Table 11 shows the comparison between Embodiment 1 of the present invention and the prior art patent CN114006362B.

[0156] Table 8

[0157] Technical dimension CN111555599A Example 1 Advantages and Innovation technical route External variable resistor unit (resistor + MOSFET) controls surge current The built-in varistor layer is combined with the capacitor dielectric, eliminating the need for external circuitry. Integration: Eliminating discrete components reduces PCB area by 50%~70%. Response speed Depends on the switching speed of the MOSFET (typically 10~100ns). Nonlinear conduction of the pressure-sensitive layer (<10ns) Ultra-fast response: Avoids the risk of overshoot caused by circuit delays. Cost and complexity Additional components are required (resistors, MOSFETs, Zener diodes). Single component integration, large-scale production of casting process Cost reduction of 40%: No need to assemble and debug discrete circuits

[0158] Table 9

[0159] Technical dimension CN112993957B Example 1 Advantages and Innovation Surge path design A gradually varying resistor and a capacitor are connected in series, relying on the resistor to dissipate surge energy through heat. The varistor directly bypasses the surge current, and the energy is absorbed through its nonlinear resistance characteristics. Efficiency Improvement: Energy absorption efficiency >90% (traditional solutions <70%) Thermal Management Resistance heating requires additional heat dissipation design The pressure-sensitive layer distributes heat evenly, with no localized hot spots. Enhanced reliability: Thermal cycling life increased to 1000 cycles (compared to 500 cycles). Dynamic impedance adjustment Controlling the MOSFET's turn-on rate using an RC delay network The impedance of the varistor material is automatically adjusted by its own nonlinear characteristics. Passive operation: No external control circuitry is required, reducing system complexity.

[0160] Table 10

[0161] Technical dimension CN221960839U Example 1 Advantages and Innovation technical route This type of protection utilizes the mechanical weaknesses in the copper claws to achieve fusing protection, and is classified as structural protection. By co-firing and integrating the varistor unit and the capacitor unit, a nonlinear overvoltage protection path is formed, which belongs to the category of material-functional composite type. No external fuse structure is required, achieving true electrical-material integrated overvoltage protection. Protection mechanism If the weak point fuses, the capacitor needs to be replaced; this is a one-time protection measure. Varistors have self-recovery properties and can repeatedly respond to surge impacts. Reusable, avoiding frequent replacements and improving system reliability and lifespan. Integration and size External connectors and weak point structures are required, which takes up a certain amount of space. A single component integrates capacitor and varistor functions, with a size comparable to traditional MLCCs, reducing PCB area by 50%–70%. Highly integrated and compact, it is suitable for high-density PCB layouts, especially for space-sensitive fields such as aerospace, medical, and automotive.

[0162] Table 11

[0163] Technical dimension CN114006362B Example 1 Advantages and Innovation Overvoltage detection mechanism Relies on external detection circuits (such as comparators and logic units). <![CDATA[The voltage threshold of the voltage-sensitive material itself triggers conduction (V 1mA = adjustable from 25 to 300 V)]]> Passive triggering: No external power supply or signal control required. Failure Mode A faulty detection circuit may cause the protection to fail. The varistor layer responds directly to physical properties, eliminating the risk of electronic component failure. Failure safety: No electronic component aging issues, lifespan equivalent to capacitors. Packaging compatibility Additional space required for IC placement Standard surface mount package (e.g., 1206), compatible with ceramic capacitor pads. Plug and play: Directly replaces traditional ceramic capacitors without requiring circuit modifications.

[0164] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the scope of protection of the invention. It should be noted that the structures or components illustrated in the accompanying drawings are not necessarily drawn to scale, and descriptions of well-known components, processing techniques, and processes have been omitted to avoid unnecessarily limiting the invention.

Claims

1. A capacitor with overvoltage protection function, comprising a capacitor unit, wherein the capacitor unit includes an X7R characteristic dielectric layer, an internal electrode, and terminal electrodes, characterized in that, Also includes: A varistor unit, connected in parallel at the bottom or top of the capacitor unit, has non-linear overvoltage protection characteristics; The permeation layer is used to combine the dielectric layer of the varistor unit and the capacitor unit to form a parallel overvoltage protection path; The X7R characteristic dielectric layer comprises a material prepared from barium zinc titanate dielectric ceramic powder, and the varistor unit comprises a material prepared from zinc oxide varistor ceramic powder. The zinc barium titanate dielectric ceramic powder is synthesized using the oxalate method, and the raw materials include the main phase Ba. 1-x Zn x TiO3, where 0.1 ≤ x ≤ 0.3; The zinc oxide varistor ceramic powder comprises a material prepared with zinc oxide as the main component, Bi2O3-SiO2-ZnO as the glass phase, and MnCO3 and Co2O3 as grain boundary engineering additives. The permeation layer includes a chemical bonded layer of barium zinc titanate and zinc oxide achieved by diffusion of the glass phase in the zinc oxide varistor ceramic powder, and the permeation layer also includes a spinel phase formed by the reaction of MnCO3 and Co2O3 at the interface of barium zinc titanate and zinc oxide; The barium zinc titanate and zinc oxide permeate each other in the permeation layer, forming a gradient structure.

2. A method for manufacturing a capacitor with overvoltage protection function as described in claim 1, characterized in that, Includes the following steps: S1: Powder preparation, including the preparation of barium zinc titanate dielectric ceramic powder and zinc oxide varistor ceramic powder; S2: Casting film, the prepared barium zinc titanate dielectric ceramic powder and zinc oxide varistor ceramic powder are cast into dielectric ceramic film and varistor ceramic film respectively; S3: In sequence, perform internal electrode printing, lamination and isostatic pressing, cutting, glue removal, sintering, chamfering, end sealing and electroplating.

3. The method for preparing a capacitor with overvoltage protection function according to claim 2, characterized in that, The preparation of the barium zinc titanate dielectric ceramic powder described in S1 includes using Ba... 1-x Zn x TiO3 is the main phase, where 0.1 ≤ x ≤ 0.3; SrZrO3 and / or CaZrO3 are added as the second phase; Al is doped. 3+ and Mn 4+ Al 3+ and Mn 4+ The ratio is 0.8~1.2:0.8~1.2, and the total doping amount does not exceed 0.5wt%. The composite powder is synthesized by the oxalate method.

4. The method for preparing a capacitor with overvoltage protection function according to claim 3, characterized in that, The weight percentages of the main phase, the second phase, and the dopant in the barium zinc titanate dielectric ceramic powder are 84~90wt%, 8~14wt%, and 0.1~0.5wt%, respectively.

5. A method for preparing a capacitor with overvoltage protection function according to claim 2, characterized in that, The preparation of the zinc oxide varistor ceramic powder includes using zinc oxide as the main component, adding auxiliary components, doping with low-temperature sintering aids, and doping with grain boundary engineering additives. The auxiliary components include CaCO3, Cr2O3, MnO2, Sb2O3, Bi2O3, and Pr6O. 11 ; The low-temperature sintering aid includes a Bi2O3-SiO2-ZnO glass phase; The grain boundary engineering additives include MnCO3 and Co2O3.

6. A method for preparing a capacitor with overvoltage protection function according to claim 5, characterized in that, The zinc oxide accounts for more than 90 wt% by weight; the auxiliary components have the following weight percentages: CaCO3 0.5~2.0 wt%, Cr2O3 0.1~1.5 wt%, MnO2 0.1~1.5 wt%, Sb2O3 0.4~1.0 wt%, Bi2O3 0.1~1.0 wt%, Pr6O 11 The weight percentage of the low-temperature sintering aid is 0.01~0.2wt%; the weight percentage of the grain boundary engineering additive MnCO3 is 3~5wt%; the weight percentage of the grain boundary engineering additive MnCO3 is 0.5~1.5wt%; and the weight percentage of Co2O3 is 0.3~0.8wt%.

7. A method for preparing a capacitor with overvoltage protection function according to claim 2, characterized in that, The printing described in S3 includes printing palladium-silver internal electrode paste on a dielectric ceramic film; The stacking and isostatic pressing include alternating stacking of dielectric ceramic films and inner electrode layers according to the designed number of layers. After the dielectric ceramic film stacking is completed, the varistor film is stacked. After all the dielectric ceramic films and varistor films are stacked, isostatic pressing is performed at a pressure of 8000~12000 PSI.

8. A method for preparing a capacitor with overvoltage protection function according to claim 2, characterized in that, The sintering described in S3 includes co-firing at 950~1050℃ in a reducing atmosphere.

9. A method for preparing a capacitor with overvoltage protection function according to claim 8, characterized in that, The co-firing process includes seven stages: heating stage, debinding stage, pre-sintering stage, sintering stage, heat preservation stage, stress release stage, and cooling stage.

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