Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, and the method comprises the steps: setting a barrier layer in a first wafer, and enabling the barrier layer to be located between a trimming region and a central region; trimming the first wafer in the trimming area; bonding the first wafer and the second wafer; trimming the first wafer and the second wafer together to expose the barrier layer; the first wafer is subjected to chemical mechanical polishing from the second surface, before the chemical mechanical polishing step, a recess is formed in the edge, close to the first surface, of the first wafer towards the center of the first wafer in the radial direction of the first wafer, and chemical mechanical polishing is stopped near the barrier layer. The barrier layer protects the edge of the first wafer in the chemical mechanical polishing process, the problem of excessive edge grinding is solved, and the recess prevents particles left in the polishing step from moving towards the center of the surface of the first wafer, so that the yield of the device is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] In semiconductor manufacturing, wafer bonding is a key step in achieving complex integrated circuit designs. Physically combining two or more wafers allows for the construction of more complex chip structures. However, after bonding, the upper wafer typically needs to be thinned to achieve the desired thickness and surface flatness. Chemical mechanical polishing (CMP) is a key technology used to planarize wafer surfaces in semiconductor manufacturing. This process uses a combination of chemical and mechanical friction to remove excess material from the wafer surface, achieving the desired flatness and smoothness. However, during the CMP process, the wafer edges are formed at right angles. Due to stress concentration at right angles, over-polishing often occurs at the edges. This phenomenon results in a wafer edge thickness that is lower than expected, impacting device performance and yield.

[0003] Furthermore, during the drying step after the CMP process, particles remaining on the wafer edge can migrate to the center of the wafer surface during the drying process, further reducing the wafer yield. These particles may originate from the polishing fluid, polishing pad wear, or other contaminants during the CMP process. Their adhesion to the wafer surface not only affects subsequent processes but can also lead to device performance degradation or even failure.

[0004] See also Figure 1 After CMP, residual particles on the edges of wafers 11 and 12 appear on the wafer surface. Figure 1 The 10 photos below are magnified structures of different particles. After CMP, the thickness of wafer 11 and wafer 12 needs to be tested. Figure 2 , the horizontal axis represents the distance from the center of the wafer along the radial direction of the wafer, in millimeters (mm); the vertical axis represents the thickness of the wafer, in angstroms (Å); the white dots represent the measurement data of wafer 11; the black dots represent the measurement data of wafer 12. Figure 2 As can be seen, the thickness drops sharply at the edge of the wafer. Therefore, it is hoped that the manufacturing process of semiconductor devices can be improved to increase the yield. Summary of the Invention

[0005] In view of the above problems, an improved method for manufacturing a semiconductor device is needed.

[0006] The present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] Disposing a barrier layer in a first wafer, wherein the first wafer includes a central region and an edge region, the edge region includes a trimmed region located at the outermost side of the first wafer, and the barrier layer is located between the trimmed region and the central region;

[0008] trimming the first wafer in the trimming area;

[0009] Bonding the first wafer to the second wafer, wherein the first wafer has a first surface and a second surface opposite to each other, and after bonding, the first surface is close to the second wafer;

[0010] trimming the first wafer and the second wafer together to expose the barrier layer; and

[0011] performing chemical mechanical polishing on the first wafer from the second surface,

[0012] Before the chemical mechanical polishing step, a recess is formed along the radial direction of the first wafer along the edge of the first wafer close to the first surface toward the center of the first wafer, so that the first wafer is in a boss shape, and the barrier layer covers the inner surface of the recess, and the chemical mechanical polishing stops near the barrier layer.

[0013] Optionally, in the chemical mechanical polishing step, the polishing liquid has different selectivity ratios for the barrier layer and the first wafer, and the polishing rate of the barrier layer is lower than the polishing rate of the first wafer.

[0014] Optionally, before the step of providing the barrier layer, the method further includes: forming a groove in the first wafer, wherein the groove is located in the edge region and between the trimming region and the central region, and the groove extends from the first surface into the first wafer.

[0015] The barrier layer covers the inner surface of the trench. After the barrier layer is formed, a filling layer is filled in the trench.

[0016] Optionally, after the step of collectively trimming, the filling layer is exposed, and the manufacturing method further comprises: removing the filling layer to expose the morphology of the recess.

[0017] Optionally, the groove is in a continuous ring shape.

[0018] Optionally, the material of the barrier layer is silicon oxide, and the material of the filling layer is silicon nitride.

[0019] Optionally, before the bonding step, the method further comprises:

[0020] forming at least a portion of a circuit structure based on the first wafer;

[0021] forming a first bonding layer over the first surface; and

[0022] forming a second bonding layer on the second wafer,

[0023] In the bonding step, the first bonding layer is bonded to the second bonding layer.

[0024] Optionally, after the bonding step and before the common trimming step, the method further includes rough thinning the first wafer from the second surface.

[0025] Optionally, after the polishing step, the method further comprises removing the barrier layer by a wet etching process.

[0026] The blocking layer is etched at a rate greater than the first wafer is etched.

[0027] Optionally, in the step of trimming the first wafer in the trimming area, the width of the first wafer removed includes a range of 1.3-1.6 mm, and the total width of the edge area is not greater than 3.5 mm.

[0028] One of the above technical solutions has the following unexpected technical effects:

[0029] By setting a barrier layer, chemical mechanical polishing stops near the barrier layer. At this time, the edge of the first wafer is surrounded by the barrier layer, and the stress originally concentrated on the right-angle edge of the first wafer is transferred to the barrier layer, thereby protecting the edge of the first wafer during the chemical mechanical polishing process and improving the problem of over-grinding of the edge.

[0030] In some embodiments, since the polishing rate of the barrier layer is lower than the polishing rate of the first wafer, the barrier layer is hardly polished during the chemical mechanical polishing process, thereby further protecting the edge of the first wafer.

[0031] Furthermore, before the chemical mechanical polishing step, a depression is formed along the radial direction of the first wafer, along the edge of the first wafer close to the bonding surface, toward the center of the first wafer, and the barrier layer covering the inner surface of the depression also has a depression morphology. After the polishing step, the polishing liquid needs to be blown dry. During the drying process, the residual particles located at the edge of the first wafer will be blocked by the barrier layer (contained in the groove) and will not be blown toward the surface of the first wafer, thereby improving the yield of the device.

[0032] In some embodiments, the barrier layer is formed in a groove on the first surface of the first wafer, and the distance from the bottom of the groove to the second surface of the first wafer is the thickness of the thinned wafer. Therefore, the control of the thinning amount can be transferred to the control of the depth of the groove, which is more convenient to operate.

[0033] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0035] Figure 1 The image shows the detection image of the position and morphology of particles remaining on the wafer surface after the polishing and drying step in the related art;

[0036] Figure 2 Shown Figure 1 Thickness inspection chart of two wafers after polishing.

[0037] Figures 3 to 13 Cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure at some stages are shown. DETAILED DESCRIPTION

[0038] The present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0039] Many specific details of the present disclosure are described below, such as device structures, materials, dimensions, processing techniques, and technologies, to provide a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be implemented without following these specific details.

[0040] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will appreciate that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in their functionality.

[0041] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0042] This application may be embodied in various forms, some examples of which are described below.

[0043] Figures 3 to 13 Cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure at some stages are shown.

[0044] like Figure 3 As shown, a groove 102 is formed in a first wafer 101. The first wafer 101 includes a central region 21 and an edge region 22, adjacent to each other. The edge region 22 includes a trimmed region 22a located at the outermost edge of the first wafer 101. The groove 102 is located between the trimmed region 22a and the central region 21. In some specific embodiments, the total width of the edge region 22 is no greater than 3.5 mm. The first wafer 101 has a first surface 101a and a second surface 101b facing each other. The groove 102 extends from the first surface 101a into the first wafer 101.

[0045] In this step, dry etching is used, for example, to form the trench 102. Optionally, the trench 102 is a continuous ring. The first wafer 101 can be a single wafer substrate or a stacked structure comprising a wafer substrate and an epitaxial layer. The material of the first wafer 101 is, for example, silicon. However, the disclosed embodiments are not limited thereto, and those skilled in the art may configure the material of the first wafer 101 in other ways as needed.

[0046] Furthermore, a barrier layer 110 is formed covering the inner surface of the trench 102 and the first surface 101a, and a filling layer 120 is formed covering the barrier layer 110 and filling the trench 102, as shown in FIG. Figure 4 shown.

[0047] In this step, a barrier layer 110 and a filling layer 120 are formed using processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). In the trench 102, the morphology of the barrier layer 110 is substantially consistent with the morphology of the trench 102, while the filling layer 120 fills the trench 102. In this embodiment, the barrier layer 110 is made of silicon oxide, and the filling layer 120 is made of silicon nitride. However, the disclosed embodiments are not limited to this. In subsequent steps, the barrier layer 110 is required to protect the first wafer 101 during the CMP step. Therefore, the barrier layer 110 is preferably made of a material having a harder hardness than the first wafer 101. In other words, the material of the barrier layer 110 should satisfy the following requirements: the barrier layer 110 has a different selectivity for the polishing liquid than the first wafer 101, and the polishing rate of the barrier layer 110 is lower than the polishing rate of the first wafer 101. Optionally, the etching selectivities of the materials of the first wafer 101 , the barrier layer 110 , and the filling layer 120 are different.

[0048] Furthermore, the barrier layer 110 and the filling layer 120 located above the first surface 101a are removed. Figure 5 In this step, for example, a CMP process is used to simultaneously remove the barrier layer 110 and the filling layer 120 above the first surface 101 a , thereby re-exposing the first surface 101 a .

[0049] Furthermore, at least a portion of the circuit structure is formed based on the first wafer 101, such as Figure 6 The circuit structure includes, for example, a doped region (not shown) formed in the central region 21 of the first wafer 101, a gate (not shown) formed above the first surface 101a, at least one interlayer dielectric layer 130, and at least one wiring layer 140. Specific components of the circuit structure can be configured as needed by those skilled in the art.

[0050] Furthermore, a first bonding layer 150 is formed above the first surface 101a, as shown in FIG. Figure 6 As shown, the first bonding layer 150 covers the interlayer dielectric layer 130 and the wiring layer 140 .

[0051] Furthermore, the first wafer 101, the interlayer dielectric layer 130, and the first bonding layer 150 are trimmed before bonding. This trimming stops at the outside of the trench 102, and the trimming depth exceeds the bottom of the trench 102. In some specific embodiments, in this trimming step, the width of the first wafer 101, the interlayer dielectric layer 130, and the first bonding layer 150 removed is in the range of 1.3-1.6 mm.

[0052] Furthermore, a second bonding layer 210 is first formed on the surface of the second wafer 201, and then the first wafer 101 is bonded to the second wafer 201, as shown in FIG. Figure 8 In this step, the first bonding layer 150 is bonded to the second bonding layer 210 , and after bonding, the first surface 101 a is close to the second wafer 201 .

[0053] Furthermore, the first wafer 101 is roughly thinned from the second surface 101b, such as Figure 9 In this step, for example, mechanical grinding is used to perform preliminary thinning on the first wafer 101. In this step, the grinding stops above the bottom of the trench 102, and there is a certain preset distance from the bottom of the trench 102.

[0054] Furthermore, the first wafer 101 and the second wafer 201 are jointly trimmed after bonding to expose the barrier layer 110 and the filling layer 120, as shown in FIG. Figure 10 After this trimming, the first wafer 101 is in an inverted boss shape, that is, along the radial direction of the first wafer 101, a depression 103 is formed on the edge of the first wafer 101 close to the first surface 101a toward the center of the first wafer 101. The depression 103 is formed by the groove 102 in the above step.

[0055] Furthermore, a wet etching process is used to remove the filling layer 120, and the remaining barrier layer 110 covers the inner surface of the recess 103. In this step, for example, hot phosphoric acid is used to remove the filling layer 120 of the silicon nitride material.

[0056] Furthermore, chemical mechanical polishing is performed on the first wafer 101 from the second surface 101b, such as Figure 12 As shown in the figure, during the chemical mechanical polishing step, the polishing slurry has different selectivity ratios for the barrier layer 110 and the first wafer 101. The polishing rate of the barrier layer 110 is lower than that of the first wafer 101, so the chemical mechanical polishing stops near the surface of the barrier layer 110, thereby improving the edge over-polishing problem of the first wafer 101. After thinning the first wafer 101 using CMP, the polishing slurry is dried. The bonded structure needs to be erected first, and then dried using isopropyl alcohol (IPA). At this time, the barrier layer 110 prevents particles in the recess 103 from migrating to the second surface 101b.

[0057] Furthermore, the barrier layer 110 is removed by a wet etching process to expose the edge sidewall of the first wafer 101 again, as shown in FIG. Figure 13In this step, for example, a tetramethylammonium hydroxide (TMAH) solution is used to clean the semiconductor structure, and the etching rate of the barrier layer 110 is greater than the etching rate of the first wafer 101 .

[0058] Furthermore, other circuit structures are formed based on the first wafer 101, thereby completing the manufacturing process of the semiconductor device.

[0059] One of the above technical solutions has the following unexpected technical effects:

[0060] By setting a barrier layer, chemical mechanical polishing stops near the barrier layer. At this time, the edge of the first wafer is surrounded by the barrier layer, and the stress originally concentrated on the right-angle edge of the first wafer is transferred to the barrier layer, thereby protecting the edge of the first wafer during the chemical mechanical polishing process and improving the problem of over-grinding of the edge.

[0061] In some embodiments, since the polishing rate of the barrier layer is lower than the polishing rate of the first wafer, the barrier layer is hardly polished during the chemical mechanical polishing process, thereby further protecting the edge of the first wafer.

[0062] Furthermore, before the chemical mechanical polishing step, a depression is formed along the radial direction of the first wafer, along the edge of the first wafer close to the bonding surface, toward the center of the first wafer, and the barrier layer covering the inner surface of the depression also has a depression morphology. After the polishing step, the polishing liquid needs to be blown dry. During the drying process, the residual particles located at the edge of the first wafer will be blocked by the barrier layer (contained in the groove) and will not be blown toward the surface of the first wafer, thereby improving the yield of the device.

[0063] In some embodiments, the barrier layer used to constitute the barrier layer is formed in a groove on the first surface of the first wafer, and the distance from the bottom of the groove to the second surface of the first wafer is the thickness of the wafer being thinned. Therefore, the control of the thinning amount can be transferred to controlling the depth of the groove formation, which makes the operation more convenient.

[0064] In addition, the manufacturing method provided by the embodiment of the present disclosure is not limited to the bonding of two wafers, and the bonding of multiple wafers can also be used.

[0065] The embodiments of the present disclosure are as described above, but these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and the modifications based on the present disclosure. The scope of protection of the present disclosure shall be based on the scope defined by the claims of the present disclosure and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: Disposing a barrier layer in a first wafer, wherein the first wafer includes a central region and an edge region, the edge region includes a trimmed region located at the outermost side of the first wafer, and the barrier layer is located between the trimmed region and the central region; trimming the first wafer in the trimming area; Bonding the first wafer to the second wafer, wherein the first wafer has a first surface and a second surface opposite to each other, and after bonding, the first surface is close to the second wafer; trimming the first wafer and the second wafer together to expose the barrier layer; as well as performing chemical mechanical polishing on the first wafer from the second surface, Before the chemical mechanical polishing step, a recess is formed along the radial direction of the first wafer at the edge of the first wafer close to the first surface toward the center of the first wafer, and the barrier layer covers the inner surface of the recess, and the chemical mechanical polishing stops near the barrier layer.

2. The manufacturing method according to claim 1, wherein In the chemical mechanical polishing step, the polishing liquid has different selectivity ratios for the barrier layer and the first wafer, and the polishing rate of the barrier layer is lower than the polishing rate of the first wafer.

3. The manufacturing method according to claim 1, further comprising, before the step of providing the barrier layer: forming a groove in the first wafer, the groove being located in the edge region and between the trimming region and the central region, the groove extending from the first surface into the first wafer, The barrier layer covers the inner surface of the trench. After the barrier layer is formed, a filling layer is filled in the trench.

4. The manufacturing method according to claim 3, wherein after the step of collectively trimming, the filling layer is exposed, and the manufacturing method further comprises: The filling layer is removed to expose the topography of the recess.

5. The manufacturing method according to claim 3, wherein: The groove is in a continuous ring shape.

6. The manufacturing method according to claim 3, wherein: The material of the barrier layer is silicon oxide, and the material of the filling layer is silicon nitride.

7. The manufacturing method according to claim 1, further comprising, before the bonding step: forming at least a portion of a circuit structure based on the first wafer; forming a first bonding layer above the first surface; as well as forming a second bonding layer on the second wafer, In the bonding step, the first bonding layer is bonded to the second bonding layer. 8 . The manufacturing method according to claim 1 , further comprising, after the bonding step and before the collective trimming step, performing rough thinning on the first wafer from the second surface.

9. The manufacturing method according to claim 1, further comprising, after the polishing step, removing the barrier layer by a wet etching process. in, The blocking layer is etched at a rate greater than the first wafer is etched.

10. The manufacturing method according to any one of claims 1 to 9, wherein: In the step of trimming the first wafer in the trimming area, the width of the first wafer removed is in the range of 1.3-1.6 mm, and the total width of the edge area is no more than 3.5 mm.

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