Semiconductor structure and forming method thereof
By controlling the etching rate and selectivity in the etching process of the silicon germanium channel, the bird's beak problem and height difference of the silicon germanium channel are solved, and the performance of the semiconductor device is improved.
Patent Information
- Application Number
- CN202410340336.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-22
- Publication Date
- 2025-10-03
AI Technical Summary
In the prior art, P-type metal oxide transistors with silicon germanium channels have a bird's beak problem and a height difference between the silicon and silicon germanium channels, which affects device performance.
By making the etching rates unequal during the etching process of the initial channel layer and the initial epitaxial layer, and controlling the etching thickness and etching selectivity, the channel layer and the epitaxial layer are formed, and the height difference is reduced.
The morphology of the channel layer is improved, the height difference between the fin and gate structures of silicon and silicon germanium is reduced, and the device performance is improved.
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Figure CN120749013A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] With the continuous advancement of semiconductor technology, integrated circuit feature sizes continue to shrink. Beyond the 5nm technology node, to further improve the performance of PMOS (Positive Channel Metal Oxide Semiconductor) transistors, silicon germanium (SiGe), with its higher carrier mobility, has replaced traditional silicon as the channel material for PMOS transistors. With the introduction of SiGe channels, controlling SiGe channel morphology, the height difference between the silicon and SiGe surfaces, and SiGe morphology loss has become crucial.
[0003] However, there are still many problems with the current P-type metal oxide transistor with silicon germanium channel. Summary of the Invention
[0004] The problem solved by the present invention is how to optimize the bird's beak problem of the silicon germanium channel, improve the morphology of the silicon germanium channel and reduce the height difference between the silicon and silicon germanium channels.
[0005] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an initial epitaxial layer on the substrate; forming a channel groove in the initial epitaxial layer; forming an initial channel layer in the channel groove, wherein the material of the initial channel layer is different from the material of the initial epitaxial layer; etching the initial channel layer and the initial epitaxial layer to form a channel layer and an epitaxial layer, wherein the etching process has unequal etching rates for the material of the initial channel layer and the material of the initial epitaxial layer.
[0006] Optionally, in the step of etching the initial channel layer and the initial epitaxial layer, the etching process is at least one of wet etching and RST dry etching.
[0007] Optionally, the etching solution for the wet etching includes: hydrofluoric acid solution and ozone solution; the etching gas for the RST dry etching includes: nitrogen trifluoride and hydrogen.
[0008] Optionally, in the step of etching the initial channel layer and the initial epitaxial layer, an etching selectivity ratio of the initial channel layer material to the initial epitaxial layer material ranges from 0.5:1 to 5:1.
[0009] Optionally, the thickness of the initial epitaxial layer and the depth of the channel groove are determined according to the etching thickness in the step of etching the initial channel layer and the initial epitaxial layer.
[0010] Optionally, in the step of etching to form the channel layer and the epitaxial layer, the etching thickness is 10 angstroms to 50 angstroms.
[0011] Optionally, it also includes: before the step of forming an initial channel layer in the channel groove, forming a mask layer on the initial epitaxial layer outside the channel groove; after forming the initial channel layer, using the mask layer as a stop layer, flattening the initial channel layer; after flattening the initial channel layer, removing the mask layer; forming a cap layer on the channel layer and the epitaxial layer; after removing the mask layer and before forming the cap layer on the channel layer and the epitaxial layer and in at least one of the processes of removing the mask layer, etching the initial epitaxial layer, the flattened initial channel layer, and the mask layer to form the channel layer and the epitaxial layer.
[0012] Optionally, it also includes: after removing the mask layer, forming a composite marking structure on the initial channel layer and the initial epitaxial layer, the composite marking structure including a first marking layer, a second marking layer located on the first marking layer, and a third marking layer located on the second marking layer; flattening the composite marking structure until the second marking layer is exposed; etching the remaining second marking layer and the first marking layer in sequence to remove the second marking layer and the first marking layer; etching the initial epitaxial layer and the initial channel layer in at least one of a process after etching the first marking layer and before forming a cap layer on the channel layer and the epitaxial layer and a process of etching the first marking layer to form the channel layer and the epitaxial layer.
[0013] Optionally, the thickness of the mask layer is 30 angstroms to 40 angstroms.
[0014] Optionally, the first marking layer is made of silicon oxide; the second marking layer is made of silicon nitride; and the third marking layer is made of silicon oxide. Optionally, in the step of forming a mask layer on the initial epitaxial layer outside the trench, the mask layer is made of silicon oxide.
[0015] Optionally, the step of forming an initial channel layer in the channel groove includes: a Siconi process.
[0016] Optionally, the material of the initial epitaxial layer includes silicon, and the material of the initial channel layer includes silicon germanium.
[0017] Correspondingly, the technical solution of the present invention further provides a semiconductor structure, which is formed by the method for forming a semiconductor structure as described in any of the above technical solutions.
[0018] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0019] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the etching process etches the material of the initial channel layer and the material of the initial epitaxial layer at different rates, thereby minimizing the height difference between the epitaxial layer and the channel layer after the etching process, thereby improving the morphology of the channel layer. This reduction in the height difference between the channel layer and the epitaxial layer also reduces the height difference between the silicon and silicon germanium fins, as well as the height difference between the silicon and silicon germanium gate structures, thereby improving device performance.
[0020] In an optional solution of the present invention, the thickness of the initial epitaxial layer and the depth of the channel groove are determined based on the etched thickness during the step of etching the initial channel layer and the initial epitaxial layer, and based on the ratio of the etching rates of silicon germanium, the material of the initial channel layer, and silicon, the material of the initial epitaxial layer, during the etching process. This minimizes the height difference between the epitaxial layer and the channel layer after the etching process, thereby improving the morphology of the channel layer. By reducing the height difference between the channel layer and the epitaxial layer, the height difference between the silicon and silicon germanium fins and the height difference between the silicon and silicon germanium gate structures are reduced, thereby improving device performance.
[0021] In an optional solution of the present invention, in at least one of the following processes, after removing the mask layer and before forming a cap layer on the channel layer and the epitaxial layer, and in the process of removing the mask layer, the initial epitaxial layer, the initial channel layer after planarization, and the mask layer are etched to form the channel layer and the epitaxial layer. In at least one of the following processes, after etching the first marking layer and before forming a cap layer on the channel layer and the epitaxial layer, and in the process of etching the first marking layer, the initial epitaxial layer and the initial channel layer are etched to form the channel layer and the epitaxial layer. The etching process is applicable to multiple nodes and can minimize the surface height difference between the epitaxial layer and the channel layer without making major changes to the process, thereby improving the performance of semiconductor devices.
[0022] In an optional solution of the present invention, in the step of etching the initial channel layer and the initial epitaxial layer, the etching selectivity ratio of the initial channel layer material to the initial epitaxial layer material ranges from 0.5:1 to 5:1. The wide range of controllable etching selectivity increases the process window. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figures 1 to 3 It is a cross-sectional structural diagram of the formation process of a semiconductor structure;
[0024] Figures 4 to 12 is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present invention;
[0025] Figures 13 to 17 FIG. 4 is a schematic cross-sectional structural diagram of a semiconductor structure forming process according to another embodiment of the present invention. DETAILED DESCRIPTION
[0026] As can be seen from the background, existing methods for forming semiconductor structures suffer from a bird's beak problem in the silicon-germanium channel and a height difference between the silicon and silicon-germanium. This results in height differences between the silicon and silicon-germanium fins and between the silicon and silicon-germanium gate structures, impacting device performance. This article analyzes the causes of these problems using a semiconductor structure formation method.
[0027] Figures 1 to 3 It is a cross-sectional structural diagram of the formation process of a semiconductor structure.
[0028] Please refer to Figure 1 , providing a substrate 100; forming an epitaxial layer 101 on the substrate 100; forming a channel groove (not shown) in the epitaxial layer 101; forming a mask layer 102 on the epitaxial layer 101 outside the channel groove; forming an initial channel layer in the channel groove, wherein the material of the initial channel layer is different from the material of the epitaxial layer 101; and planarizing the initial channel layer to form a channel layer 103.
[0029] The epitaxial layer 101 is made of silicon; the channel layer 103 is made of silicon germanium.
[0030] The thickness of the mask layer 102 is greater than 45 angstroms.
[0031] Please refer to Figure 2 After forming the channel layer, the mask layer 102 is removed.
[0032] Please refer to Figure 3 After removing the mask layer 102 , a cap layer 104 is formed on the channel layer 103 and the epitaxial layer 101 .
[0033] In the method for forming the semiconductor structure, the step of forming the initial channel layer in the channel groove includes a Siconi process. The Siconi process will undercut the mask layer 102, resulting in the formation of an initial channel layer with a bird's beak structure. The thickness of the bird's beak structure formed by the Siconi process is greater than 25 angstroms. In addition, in the step of planarizing the initial channel layer to form the channel layer 103, the mask layer 102 serves as a stop layer. The residual thickness of the mask layer 102 after planarization is approximately 30 to 40 angstroms, resulting in a height difference of 30 to 40 angstroms between the channel layer and the epitaxial layer 101. The height difference between the channel layer 103 and the epitaxial layer 101 will result in a height difference between the silicon and silicon germanium fins, and a height difference between the silicon and silicon germanium gate structures, seriously affecting the performance of the device.
[0034] The formation process of the other half of the semiconductor structure also includes: after removing the mask layer 102, before forming the cap layer 104 on the channel layer 103 and the epitaxial layer 101, forming a composite marking structure on the channel layer 103 and the epitaxial layer 101, the composite marking structure including a first marking layer, a second marking layer located on the first marking layer, and a third marking layer located on the second marking layer; planarizing the composite marking structure until the second marking layer is exposed; after the planarization treatment, etching the remaining second marking layer and the first marking layer in sequence to remove the second marking layer and the first marking layer.
[0035] The material of the first marking layer includes silicon oxide; the material of the second marking layer includes silicon nitride; and the material of the third marking layer includes silicon oxide.
[0036] In the method for forming the semiconductor structure, the first and third marking layers are both made of silicon oxide. During the formation and removal of the first and third marking layers, the channel layer 103 is consumed at a faster rate than the epitaxial layer 101. There is an 18 angstrom height difference between the channel layer 103 and the epitaxial layer 101. This height difference between the channel layer 103 and the epitaxial layer 101 results in height differences between the silicon and silicon germanium fins, and between the silicon and silicon germanium gate structures, impacting device performance.
[0037] In order to solve the technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming an initial epitaxial layer on the substrate; forming a channel groove in the initial epitaxial layer; forming an initial channel layer in the channel groove, wherein the material of the initial channel layer is different from the material of the initial epitaxial layer; etching the initial channel layer and the initial epitaxial layer to form a channel layer and an epitaxial layer, wherein the etching rate of the material of the initial channel layer and the material of the initial epitaxial layer are not equal.
[0038] In the method for forming a semiconductor structure according to the technical solution of the present invention, the thickness of the initial epitaxial layer and the depth of the channel groove are determined based on the etched thickness in the step of etching the initial channel layer and the initial epitaxial layer, and based on the ratio of the etching rates of silicon germanium, the material of the initial channel layer, and silicon, the material of the initial epitaxial layer, during the etching process. This minimizes the height difference between the epitaxial layer and the channel layer after the etching process, thereby improving the morphology of the channel layer. By reducing the height difference between the channel layer and the epitaxial layer, the height difference between the silicon and silicon germanium fins and the height difference between the silicon and silicon germanium gate structures are reduced, thereby improving device performance.
[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0040] Figures 4 to 12 FIG. 1 is a schematic cross-sectional structural diagram of a semiconductor structure forming process according to an embodiment of the present invention.
[0041] Please refer to Figure 4 , providing a substrate 200.
[0042] The substrate 200 is made of silicon. Specifically, in this embodiment, the substrate 200 is a silicon substrate.
[0043] Please refer to Figure 5 , an initial epitaxial layer 201 is formed on the substrate 200 .
[0044] The material of the initial epitaxial layer 201 includes silicon. Specifically, in this embodiment, the initial epitaxial layer 201 is a silicon epitaxial layer.
[0045] The thickness of the initial epitaxial layer 201 is determined based on the etching thickness in the step of etching the initial channel layer 204 and the initial epitaxial layer 201. In the step of etching the initial channel layer 204 and the initial epitaxial layer 201 to form the channel layer 205 and the epitaxial layer 206, the etching thickness of the initial channel layer 204 is 10 angstroms to 50 angstroms.
[0046] Please refer to Figure 6 , a channel groove 202 is formed in the initial epitaxial layer 201 .
[0047] The depth of the channel groove 202 is determined based on the etching thickness of the initial channel layer 204 and the initial epitaxial layer 201. In the step of etching the initial channel layer 204 and the initial epitaxial layer 201 to form the channel layer 205 and the epitaxial layer 206, the etching thickness of the initial channel layer 204 is 10 angstroms to 50 angstroms.
[0048] The channel groove 202 provides a structural foundation for forming the channel layer 205. The method for forming the channel groove 202 includes: forming a channel mask layer (not shown) on the surface of the initial epitaxial layer 201, wherein the channel mask layer exposes a portion of the surface of the initial epitaxial layer 201; and etching the initial epitaxial layer 201 using the channel mask layer as a mask to form the channel groove 202.
[0049] Please refer to Figures 7 and 8 An initial channel layer 204 is formed in the channel trench 202 , and the material of the initial channel layer 204 is different from that of the initial epitaxial layer 201 .
[0050] The steps of forming the initial channel layer 204 include: Figure 7 As shown, a mask layer 203 is formed on the initial epitaxial layer 201 outside the trench 202; Figure 8 As shown, an initial channel layer 204 is formed in the channel trench 202 .
[0051] In the step of forming a mask layer 203 on the initial epitaxial layer 201 outside the trench 202, the mask layer 203 is made of silicon oxide and has a thickness of 30 angstroms to 40 angstroms.
[0052] The material of the initial epitaxial layer 201 includes silicon. The material of the initial channel layer 204 includes silicon germanium. Compared with silicon, silicon germanium increases the carrier mobility of the initial channel layer 204, thereby improving the device performance of the P-type metal oxide transistor.
[0053] The step of forming the initial channel layer 204 in the channel trench 202 includes a Siconi process, which mainly includes two steps: etching and sublimation.
[0054] like Figure 9 As shown, after the initial channel layer 204 is formed, the initial channel layer 204 is planarized using the mask layer 203 as a stop layer.
[0055] Planarization methods include mechanical polishing, chemical polishing, fluid polishing, and chemical-mechanical polishing. Specifically, in this embodiment, the planarization method is chemical-mechanical polishing. Unlike traditional purely mechanical or purely chemical polishing methods, chemical-mechanical polishing, through the combined action of chemical and mechanical forces, avoids the surface damage caused by mechanical polishing alone and the shortcomings of chemical polishing alone, such as slow polishing speed, poor surface flatness, and poor polishing consistency. Chemical-mechanical polishing is widely used for high-planarization nanoscale polishing of various materials.
[0056] like Figure 10 As shown, after the initial channel layer 204 is planarized, the mask layer 203 is removed.
[0057] The method of removing the mask layer 203 includes wet etching.
[0058] like Figure 11 As shown, the initial channel layer 204 and the initial epitaxial layer 201 are etched to form a channel layer 205 and an epitaxial layer 206 . The etching process has different etching rates for the material of the initial channel layer 204 and the material of the initial epitaxial layer 201 .
[0059] In the step of etching the initial channel layer 204 and the initial epitaxial layer 201 , the etching selectivity ratio of the material of the initial channel layer 204 to the material of the initial epitaxial layer 201 is in the range of 0.5:1 to 5:1.
[0060] In the step of etching to form the channel layer 205 and the epitaxial layer 206 , the etching thickness of the initial channel layer 204 is in the range of 10 angstroms to 50 angstroms.
[0061] The etched thickness of the initial channel layer 204 is determined based on the etched thickness during the step of etching the initial channel layer 204 and the initial epitaxial layer 201, and based on the ratio of the etching rates of silicon germanium (the material of the initial channel layer 204) to silicon (the material of the initial epitaxial layer 201). When the etched thickness during the step of etching the initial channel layer 204 and the initial epitaxial layer 201 is 18 angstroms and the etching selectivity ratio of silicon germanium to silicon during the etching is 2:1, the etched thickness of the initial channel layer 204 is 36 angstroms.
[0062] When the etching selectivity ratio of the material of the initial channel layer 204 to the material of the initial epitaxial layer 201 is 2:1, the thickness of the bird's beak structure of the channel layer 205 obtained after the etching process can be less than 5 angstroms, thereby improving the morphology of the channel layer 205.
[0063] In the step of etching the initial channel layer 204 and the initial epitaxial layer 201 , the etching process is at least one of wet etching and RST (Radical Surface Treatment) dry etching, wherein the RST dry etching is a free radical surface treatment dry etching.
[0064] The wet etching solution includes a hydrofluoric acid solution and an ozone solution. In a mixed solution of hydrofluoric acid solution and ozone solution at a certain concentration, as the wet etching time increases from 0 seconds to 60 seconds, the etching selectivity of the etching solution to silicon germanium material and silicon material gradually decreases.
[0065] The etching gases used in the RST dry etch include nitrogen trifluoride and hydrogen. When the ratio of nitrogen trifluoride to hydrogen flow is greater than 15, the RST dry etch has an etching selectivity of less than 20 for silicon germanium over silicon. When the ratio of nitrogen trifluoride to hydrogen is between 3 and 5, the RST dry etch has an etching selectivity of less than 3 for silicon over silicon germanium.
[0066] like Figure 12 As shown, a cap layer 207 is formed on the channel layer 205 and the epitaxial layer 206 .
[0067] The material of the cap layer 207 includes silicon.
[0068] In at least one of the processes after removing the mask layer 203 and before forming the cap layer 207 on the channel layer 205 and the epitaxial layer 206 and the process of removing the mask layer 203, the initial epitaxial layer 201, the initial channel layer 204 after planarization, and the mask layer 203 are etched to form the channel layer 205 and the epitaxial layer 206.
[0069] In some embodiments, during the process of removing the mask layer 203 , the initial epitaxial layer 201 , the initial channel layer 204 after planarization, and the mask layer 203 are etched to form the channel layer 205 and the epitaxial layer 206 .
[0070] The etching process includes wet etching. The mask layer 203 is made of silicon oxide, and the wet etching solution includes a hydrofluoric acid solution and an ozone solution. The hydrofluoric acid solution can etch and remove the silicon oxide. The initial channel layer 204 is made of silicon germanium, and silicon germanium oxide is readily soluble in water. By adjusting the mass percentage concentration of the hydrofluoric acid solution and the mass percentage concentration of the ozone solution, a suitable etching selectivity is achieved, so that the height difference between the surface of the channel layer 205 and the surface of the epitaxial layer 206 after the etching process is as small as possible.
[0071] In other embodiments, after removing the mask layer 203 and before forming the cap layer 207 on the channel layer 205 and the epitaxial layer 206, the initial epitaxial layer 201 and the initial channel layer 204 after planarization are etched to form the channel layer 205 and the epitaxial layer 206.
[0072] The etching process includes wet etching and dry etching. When the etching process is wet etching, the etching solution of the wet etching includes: hydrofluoric acid solution and ozone solution. The hydrofluoric acid solution can etch and remove silicon oxide. The material of the initial channel layer 204 is silicon germanium. The oxide of silicon germanium is easily soluble in water. By adjusting the mass percentage concentration of the hydrofluoric acid solution and the mass percentage concentration of the ozone solution, a suitable etching selectivity is obtained, so that the height difference between the surface of the channel layer 205 after the etching process and the surface of the epitaxial layer 206 is minimized. When the etching process is dry, RST dry etching is used. The etching gases of RST dry etching include: nitrogen trifluoride and hydrogen. By adjusting the gas flow rate ratio of nitrogen trifluoride to hydrogen, the etching selectivity of the RST dry etching for silicon germanium and silicon is adjusted, so that the height difference between the surface of the channel layer 205 after the etching process and the surface of the epitaxial layer 206 is minimized.
[0073] Please Figures 4 to 10 Based on reference Figures 13 to 17 , Figures 13 to 17 FIG. 4 is a schematic cross-sectional structural diagram of a semiconductor structure forming process according to another embodiment of the present invention.
[0074] Please Figures 4 to 10 Based on reference Figure 13 After removing the mask layer 203, a composite marking structure is formed on the initial channel layer 204 and the initial epitaxial layer 201, and the composite marking structure includes a first marking layer 208, a second marking layer 209 located on the first marking layer 208, and a third marking layer 210 located on the second marking layer 209.
[0075] The material of the first marking layer 208 includes silicon oxide; the material of the second marking layer 209 includes silicon nitride; and the material of the third marking layer 210 includes silicon oxide.
[0076] The materials of the first marking layer 208 and the third marking layer 210 are both silicon oxide. During the deposition of the first marking layer 208 and the third marking layer 210, the consumption of silicon germanium material is greater than the consumption of silicon material, which reduces the height difference between the initial channel layer 204 and the initial epitaxial layer 201.
[0077] Please refer to Figure 14 , performing a planarization process on the composite marking structure until the second marking layer 209 is exposed.
[0078] The planarization process removes the third marking layer 210 , the material of which includes silicon oxide. During the removal of the third marking layer 210 , the consumption of silicon germanium material is greater than that of silicon material, thereby reducing the height difference between the initial channel layer 204 and the initial epitaxial layer 201 .
[0079] Please refer to Figure 15 , and sequentially etch the remaining second marking layer 209 (such as Figure 14 As shown) and the first marking layer 208 (as shown Figure 14 ), so as to remove the second marking layer 209 and the first marking layer 208.
[0080] The material of the first marking layer 208 includes silicon oxide. During the process of etching and removing the first marking layer 208 , the consumption of silicon germanium material is greater than that of silicon material, thereby reducing the height difference between the initial channel layer 204 and the initial epitaxial layer 201 .
[0081] Please refer to Figure 16 , the initial channel layer 204 and the initial epitaxial layer 201 are etched to form a channel layer 211 and an epitaxial layer 212, and the etching process is performed on the initial channel layer 204 (such as Figure 15) and the initial epitaxial layer 201 (as shown Figure 15 The etch rates of the materials shown are not equal.
[0082] In the step of etching the initial channel layer 204 and the initial epitaxial layer 201 , the etching selectivity ratio of the material of the initial channel layer 204 to the material of the initial epitaxial layer 201 is in the range of 0.5:1 to 5:1.
[0083] In the step of etching to form the channel layer 211 and the epitaxial layer 212 , the etching thickness of the initial channel layer 204 is in the range of 10 angstroms to 50 angstroms.
[0084] The etched thickness of the initial channel layer 204 is determined based on the etched thickness during the step of etching the initial channel layer 204 and the initial epitaxial layer 201, and based on the ratio of the etching rates of silicon germanium (the material of the initial channel layer 204) to silicon (the material of the initial epitaxial layer 201). When the etched thickness during the step of etching the initial channel layer 204 and the initial epitaxial layer 201 is 18 angstroms and the etching selectivity ratio of silicon germanium to silicon during the etching is 2:1, the etched thickness of the initial channel layer 204 is 36 angstroms.
[0085] When the etching selectivity ratio of the material of the initial channel layer 204 to the material of the initial epitaxial layer 201 is 2:1, the thickness of the bird's beak structure of the channel layer 211 obtained after the etching process can be less than 5 angstroms, thereby improving the morphology of the channel layer 211.
[0086] In the step of etching the initial channel layer 204 and the initial epitaxial layer 201 , the etching process is at least one of wet etching and RST (Radical Surface Treatment) dry etching, wherein the RST dry etching is a free radical surface treatment dry etching.
[0087] The wet etching solution includes a hydrofluoric acid solution and an ozone solution. In a mixed solution of hydrofluoric acid solution and ozone solution at a certain concentration, as the wet etching time increases from 0 seconds to 60 seconds, the etching selectivity of the etching solution to silicon germanium material and silicon material gradually decreases.
[0088] The etching gases used in the RST dry etch include nitrogen trifluoride and hydrogen. When the ratio of nitrogen trifluoride to hydrogen flow is greater than 15, the RST dry etch has an etching selectivity of less than 20 for silicon germanium over silicon. When the ratio of nitrogen trifluoride to hydrogen is between 3 and 5, the RST dry etch has an etching selectivity of less than 3 for silicon over silicon germanium.
[0089] Please refer to Figure 17, a cap layer 213 is formed on the channel layer 211 and the epitaxial layer 212 .
[0090] The material of the cap layer 213 includes silicon.
[0091] The initial epitaxial layer 201 and the initial channel layer 204 are etched in at least one of a process after etching the first marking layer 208 and before forming the cap layer 213 on the channel layer 211 and the epitaxial layer 212 and a process of etching the first marking layer 208 to form the channel layer 211 and the epitaxial layer 212.
[0092] In some embodiments, during the etching of the first marking layer 208 , the initial epitaxial layer 201 and the initial channel layer 204 are etched to form the channel layer 211 and the epitaxial layer 212 .
[0093] The etching process includes wet etching. The material of the first marking layer 208 is silicon oxide. The etching solution for the wet etching includes a hydrofluoric acid solution and an ozone solution. The hydrofluoric acid solution can etch and remove the silicon oxide. The material of the initial channel layer 204 is silicon germanium. Silicon germanium oxide is easily soluble in water. By adjusting the mass percentage concentration of the hydrofluoric acid solution and the mass percentage concentration of the ozone solution, a suitable etching selectivity is obtained, minimizing the height difference between the surface of the channel layer 211 and the surface of the epitaxial layer 212 after the etching process.
[0094] In some other embodiments, after etching the first marking layer 208 and before forming the cap layer 213 on the channel layer 211 and the epitaxial layer 212 , the initial epitaxial layer 201 and the initial channel layer 204 are etched to form the channel layer 211 and the epitaxial layer 212 .
[0095] The etching process includes wet etching and dry etching. When the etching process is wet etching, the etching solution of the wet etching includes: hydrofluoric acid solution and ozone solution, and the hydrofluoric acid solution can etch and remove silicon oxide. The material of the initial channel layer 204 is silicon germanium, and the oxide of silicon germanium is easily soluble in water. By adjusting the mass percentage concentration of the hydrofluoric acid solution and the mass percentage concentration of the ozone solution, a suitable etching selectivity is obtained, so that the height difference between the surface of the channel layer 211 after the etching process and the surface of the epitaxial layer 212 is minimized. When the etching process is dry processing, RST dry etching is adopted, and the etching gas of RST dry etching includes: nitrogen trifluoride and hydrogen. By adjusting the gas flow ratio of nitrogen trifluoride and hydrogen, the etching selectivity of the RST dry etching to silicon germanium and silicon is adjusted, so that the height difference between the surface of the channel layer 211 after the etching process and the surface of the epitaxial layer 212 is minimized.
[0096] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned method for forming a semiconductor structure, which will not be described in detail here.
[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming an initial epitaxial layer on the substrate; forming a trench in the initial epitaxial layer; forming an initial channel layer in the channel trench, wherein the material of the initial channel layer is different from the material of the initial epitaxial layer; The initial channel layer and the initial epitaxial layer are etched to form a channel layer and an epitaxial layer, wherein the etching process has different etching rates for the material of the initial channel layer and the material of the initial epitaxial layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of etching the initial channel layer and the initial epitaxial layer, the etching process is at least one of wet etching and RST dry etching.
3. The method for forming a semiconductor structure according to claim 2, wherein: The etching solution of the wet etching method includes: hydrofluoric acid solution and ozone solution; The etching gases for RST dry etching include nitrogen trifluoride and hydrogen.
4. The method for forming a semiconductor structure according to claim 2 or 3, wherein: In the step of etching the initial channel layer and the initial epitaxial layer, the etching selectivity ratio of the initial channel layer material to the initial epitaxial layer material is in the range of 0.5:1 to 5:
1.
5. The method for forming a semiconductor structure according to claim 4, wherein: The thickness of the initial epitaxial layer and the depth of the channel groove are determined according to the etching thickness in the step of etching the initial channel layer and the initial epitaxial layer.
6. The method for forming a semiconductor structure according to claim 5, wherein: In the step of etching to form the channel layer and the epitaxial layer, the etching thickness is 10 angstroms to 50 angstroms.
7. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before the step of forming the initial channel layer in the trench, forming a mask layer on the initial epitaxial layer outside the trench; After forming the initial channel layer, performing a planarization process on the initial channel layer using the mask layer as a stop layer; After planarizing the initial channel layer, removing the mask layer; forming a cap layer on the channel layer and the epitaxial layer; In at least one of the processes after removing the mask layer and before forming a cap layer on the channel layer and the epitaxial layer and the process of removing the mask layer, the initial epitaxial layer, the initial channel layer after planarization, and the mask layer are etched to form the channel layer and the epitaxial layer.
8. The method for forming a semiconductor structure according to claim 7, wherein: Also includes: After removing the mask layer, forming a composite marking structure on the initial channel layer and the initial epitaxial layer, the composite marking structure comprising a first marking layer, a second marking layer located on the first marking layer, and a third marking layer located on the second marking layer; performing a planarization process on the composite marking structure until the second marking layer is exposed; Sequentially etching the remaining second marking layer and the first marking layer to remove the second marking layer and the first marking layer; The initial epitaxial layer and the initial channel layer are etched in at least one of a process after etching the first mark layer and before forming a cap layer on the channel layer and the epitaxial layer and a process of etching the first mark layer to form the channel layer and the epitaxial layer.
9. The method for forming a semiconductor structure according to claim 7, wherein: The thickness of the mask layer is 30 angstroms to 40 angstroms.
10. The method for forming a semiconductor structure according to claim 8, wherein: The material of the first marking layer includes silicon oxide; the material of the second marking layer includes silicon nitride; and the material of the third marking layer includes silicon oxide.
11. The method for forming a semiconductor structure according to claim 7, wherein: In the step of forming a mask layer on the initial epitaxial layer outside the trench, the material of the mask layer includes silicon oxide.
12. The method for forming a semiconductor structure according to claim 7 or 11, wherein: The step of forming an initial channel layer in the channel groove includes: a Siconi process.
13. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial epitaxial layer includes silicon, and the material of the initial channel layer includes silicon germanium.
14. A semiconductor structure, characterized in that The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 13.