Preparation method of fine controllable patterned GaN array and GaN array

Abstract

The invention discloses a preparation method of a fine controllable patterned GaN array. The preparation method comprises the following steps: S1, preparing a patterned GaN epitaxial wafer on a semiconductor substrate; s2, carrying out ICP (Inductively Coupled Plasma) etching on the patterned GaN epitaxial wafer; the etching gas is a mixed gas of Cl2 and BCl3, and conversion and size control of GaN with different morphologies are realized by adjusting RF power and ICP power; and the inclination angle of the side wall of GaN is regulated and controlled by adjusting the flow of Cl2. According to the method, ICP etching and KOH corrosion modification are carried out on the patterned GaN epitaxial wafer, so that the defects that the GaN film has many defects and the pattern regulation and control precision is insufficient in a traditional process are overcome, high-precision and customizable micro / nano ordered array preparation is realized, and a basis is provided for a high-performance semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor material preparation, and in particular to a preparation method of a finely controllable patterned GaN array and a GaN array. Background Art

[0002] Over the past few years, GaN, a representative of third-generation wide-bandgap semiconductors, has garnered widespread attention for its exceptional performance. As a core material for third-generation semiconductors, GaN, due to the lack of naturally occurring GaN crystals, can only be deposited on exotic substrates, such as sapphire, through heteroepitaxial growth. However, the significant lattice and thermal mismatch between GaN and sapphire substrates leads to a high density of dislocation defects, which compromise device performance. Therefore, obtaining high-quality GaN films is crucial.

[0003] Research has found that high-quality GaN films can be obtained by patterning GaN films and then performing homogeneous lateral growth. However, there is currently no systematic method for controlling the etching of GaN patterns. Inductively coupled plasma (ICP) etching, on the other hand, uses an upper and lower RF source to convert gas into plasma and then move the plasma downward to the etched surface, achieving the desired etching effect. This allows for better control over the etching of structures with high aspect ratios and good verticality.

[0004] In the existing technology, ICP etching is widely used in GaN patterning processing, but it has the following problems: (1) the etching parameters (such as ICP power, RF power, and gas flow) have a complex impact on the morphology and are difficult to accurately control; (2) the side surface roughness after etching is high, and additional process repair is required. Summary of the Invention

[0005] Based on the above technical problems, the present invention improves the defects of GaN films in traditional processes, such as many defects and insufficient pattern control accuracy, by performing ICP etching and KOH corrosion modification on patterned GaN epitaxial wafers, and realizes the preparation of high-precision and customizable micro / nano ordered arrays, providing a foundation for high-performance semiconductor devices.

[0006] The specific scheme of the present invention is as follows:

[0007] One of the purposes of the present invention is to provide a method for preparing a finely controlled patterned GaN array, comprising the following steps:

[0008] S1. Preparing a patterned GaN epitaxial wafer on a semiconductor substrate;

[0009] S2. Perform ICP etching on the patterned GaN epitaxial wafer; the etching gas is a mixture of Cl2 and BCl3. By adjusting the RF power and ICP power, the conversion and size control of GaN with different morphologies are achieved; by adjusting the Cl2 flow rate, the side wall tilt angle of GaN is controlled.

[0010] Preferably, the method further comprises S3, then using a KOH solution to corrode and modify the GaN pattern obtained in S2 to obtain a GaN array.

[0011] Preferably, in S2, the flow ratio of Cl2 to BCl3 in the etching gas is 48:2-8, the flow rate of Cl2 is 24-96 sccm; the RF power is 100-200W, and the ICP power is 300-1500W.

[0012] Preferably, in S3, the diameter of the GaN array is regulated by controlling the time of the corrosion modification; preferably, the time of the corrosion modification is 10 to 14 minutes.

[0013] Preferably, in S3, the concentration of the KOH solution is 0.5 to 3 mol / L; more preferably, the corrosion modification is performed in a water bath at 85 to 95°C.

[0014] Preferably, S1 specifically includes: (1) sequentially growing a GaN buffer layer and an undoped GaN layer on a semiconductor substrate to form a GaN epitaxial wafer; (2) growing a SiO2 mask layer on the surface of the undoped GaN layer of the GaN epitaxial wafer, and then transferring a preset pattern to the SiO2 mask layer by photolithography and reactive ion etching to obtain a patterned GaN epitaxial wafer.

[0015] Preferably, in S1, the semiconductor substrate is selected from at least one of a sapphire substrate, a silicon carbide substrate or a silicon substrate.

[0016] Preferably, in S1, the thickness of the GaN buffer layer is 10-80 nm, and the thickness of the undoped GaN layer is 2-8 μm; more preferably, in S1, the thickness of the GaN buffer layer is 30-40 nm, and the thickness of the undoped GaN layer is 4-6 μm.

[0017] Preferably, in S1, a GaN buffer layer and an undoped GaN layer are sequentially grown on a semiconductor substrate by metal organic chemical vapor deposition; more preferably, the growth temperature of the undoped GaN layer is 1000-1100°C.

[0018] In actual operation, an atomic force microscope (AFM) is used to detect the surface flatness of the non-doped GaN layer in step S1, requiring the root mean square roughness (RMS) of a 2 μm×2 μm area to be ≤0.1703 nm, and the RMS of a 5 μm×5 μm area to be ≤0.2538 nm.

[0019] Preferably, in S1, a plasma enhanced chemical vapor deposition process is used to grow the SiO2 mask layer.

[0020] Preferably, in S1, the thickness of the SiO2 mask layer is 100 nm to 500 nm.

[0021] A second object of the present invention is to provide a patterned GaN array, which is prepared by the above method.

[0022] The beneficial effects of the present invention are:

[0023] The present invention performs ICP etching and KOH corrosion modification on patterned GaN epitaxial wafers, thereby improving the defects of GaN films in traditional processes, such as many defects and insufficient pattern control accuracy, and realizes the preparation of high-precision and customizable micro / nano ordered arrays, providing a foundation for high-performance semiconductor devices.

[0024] Specifically, in the ICP etching process, we conducted in-depth research on the influence of parameters such as RF source, ICP source power and Cl2 flow on GaN graphics, achieving precise control of graphic shape, size and sidewall inclination, and meeting diverse process requirements.

[0025] Furthermore, by combining KOH solution corrosion modification to reduce sidewall damage, and by controlling the corrosion modification time, the diameter of the GaN array can be precisely controlled (reduced to 563nm), effectively improving the graphic accuracy and surface quality of the GaN array, and laying a solid foundation for the application of GaN in high-end semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the process of preparing a GaN array according to the present invention;

[0027] Figure 2 The morphology distribution diagrams of GaN arrays obtained under different ICP process conditions in Examples 1-3; wherein, Figures (a)-(d) correspond to Example samples A to D, respectively;

[0028] Figure 3 The morphology distribution diagrams of the GaN arrays obtained under different ICP process conditions in Examples 4-5 and Example 1, wherein Figures (a)-(c) correspond to Sample E, Sample A, and Sample F, respectively;

[0029] Figure 4 These are morphologies of the GaN arrays prepared under different corrosion modification conditions in Examples 6-7, where (a) is the GaN pattern before KOH solution corrosion, and (b)-(c) correspond to sample G and sample H, respectively. DETAILED DESCRIPTION

[0030] Hereinafter, the technical solutions of the present invention will be described in detail through specific embodiments. However, it should be clearly stated that these embodiments are provided for illustration only and are not to be construed as limiting the scope of the present invention.

[0031] Example 1

[0032] A method for preparing a cylindrical GaN array comprises the following steps:

[0033] S1. Preparing a patterned GaN epitaxial wafer on a semiconductor substrate

[0034] (1) According to the MOCVD process standard, a 30nm GaN buffer layer is first grown on a sapphire substrate with a (0001) crystal plane, and then a 4μm undoped GaN layer is grown at 1030℃ to form a GaN epitaxial wafer;

[0035] After the growth is completed, AFM detection shows that the root mean roughness (RMS) under the 2μm×2μm area is 0.168nm, and the root mean roughness (RMS) under the 5μm×5μm area is 0.250nm, which meets the subsequent process requirements.

[0036] (2) placing a qualified GaN epitaxial wafer in a PECVD chamber and growing it at 350°C for 30 minutes to obtain a 200nm thick SiO2 mask layer; then, using photolithography technology to make a photoresist pattern and perform a post-baking process, and then etching the SiO2 mask layer using RIE, cleaning and removing the remaining photoresist, and transferring the preset pattern to the SiO2 mask layer to obtain a patterned GaN epitaxial wafer;

[0037] S2. ICP etching of the patterned GaN epitaxial wafer

[0038] A two-inch patterned GaN epitaxial wafer was cut into 1cm×1cm samples and placed in the ICP etching equipment chamber for etching; the etching gas was a mixture of Cl2 and BCl3, with a Cl2 flow rate of 48sccm and a BCl3 flow rate of 6sccm, a flow ratio of 48 / 6, and the chamber pressure was maintained at 10mTorr; the RF power was set to 200W and the ICP power was set to 300W, and the etching was carried out for 5 minutes to obtain a cylindrical GaN array with a diameter of about 2um, a column spacing of about 2um, and an etching depth of about 3um.

[0039] The cylindrical GaN array finally obtained in this embodiment is marked as sample A.

[0040] Example 2

[0041] A method for preparing a truncated cone-shaped GaN array is described. The only difference from Example 1 is the difference in step S2. Steps S1 and S3 and their parameters are the same as those in Example 1. Specifically, Example S2 includes the following steps:

[0042] (1) Obtain a cylindrical GaN array according to the method of Example 1;

[0043] (2) Then, keeping other conditions unchanged, the RF power was reduced to 100 W, the ICP power was increased to 1000 W, and etching was continued for 1 minute to obtain a truncated cone-shaped GaN array, which was marked as sample B.

[0044] Example 3

[0045] A method for preparing a conical GaN array differs from Example 2 only in step S2. Specifically, step S2 of this embodiment includes the following steps:

[0046] (1) Obtain a truncated cone-shaped GaN array according to the method of Example 2;

[0047] (2) Then, keeping other conditions unchanged, the RF power was increased to 200 W, the ICP power was further increased to 1500 W, and etching was performed for 1 minute to obtain sample C. Subsequently, the RF power was reduced to 100 W, and etching was continued for 1 minute to finally obtain a conical GaN array, which was marked as sample D.

[0048] The morphology of the GaN arrays prepared under different ICP process conditions in the above Examples 1-3 is shown in FIG. Figure 2 As shown, Figures (a)-(d) correspond to example samples AD respectively.

[0049] It can be seen that the present invention realizes the conversion of GaN with different morphologies by adjusting the RF power and the ICP power. The GaN graphic morphology corresponding to samples AD is transformed from cylindrical to truncated cone and then to conical.

[0050] Comparing Figures (a) and (b), it can be seen that for samples A and B, reducing the RF power can reduce the impact energy of the bombarding particles on GaN and alleviate material damage. At the same time, increasing the ICP power can reduce the GaN / SiO2 selectivity, prompting the GaN pattern to transform from a cylinder to a truncated cone, and ultimately successfully obtaining a truncated cone-shaped GaN array.

[0051] Comparing Figures (b) and (c) of Samples B and C, the increased ICP power increases the plasma density. However, increasing the RF power from 100W to 200W does not result in a rougher GaN surface, but rather a smoother one. This increased RF power improves the etching process, further transforming the frustum into a conical shape. Subsequently, the RF power is reduced to 100W, and after one minute of ICP etching, the conical GaN pattern shown in Figure (d) is obtained for Sample D.

[0052] Example 4

[0053] A method for preparing a GaN array differs from Example 1 only in step S2, while step S1 and parameters are the same as those in Example 1.

[0054] Specifically, in S2 of this embodiment, the etching gas is a mixture of Cl2 and BCl3, with a Cl2 flow rate of 24 sccm and a BCl3 flow rate of 3 sccm, maintaining a flow ratio of 48 / 6. Other steps and parameters are the same as step S2 of embodiment 1.

[0055] The GaN array obtained in this example is marked as sample E.

[0056] Example 5

[0057] A method for preparing a GaN array differs from Example 1 only in step S2, while step S1 and parameters are the same as those in Example 1.

[0058] Specifically, in S2 of this embodiment, the etching gas is a mixture of Cl2 and BCl3, with a Cl2 flow rate of 96 sccm and a BCl3 flow rate of 12 sccm, maintaining a flow ratio of 48 / 6. Other steps and parameters are the same as step S2 of embodiment 1.

[0059] The GaN array obtained in this embodiment is marked as sample F.

[0060] The morphology of the GaN arrays prepared in the above Examples 4-5 under different Cl2 flow rates is shown in FIG. Figure 3 As shown, Figures (a)-(c) correspond to sample E, sample A and sample F respectively.

[0061] Comparing the morphologies of samples A, E, and F, it can be seen that when the Cl2 flow rate is larger, the sidewall inclination angle is larger and the sidewall is steeper. This is because the increase in the Cl2 gas flow rate causes the reaction products after etching to be taken away from the sample surface faster, preventing the residue from further etching the sample. Compared with a smaller gas flow rate, it has better anisotropy, so the sidewall is also steeper.

[0062] Increasing the BCl3 gas flow rate has a similar effect on the GaN pattern sidewalls as increasing the Cl2 gas flow rate. By controlling the Cl2 and BCl3 gas flow rates, the GaN sidewall tilt angle can be controlled.

[0063] Example 6

[0064] A method for preparing a GaN array differs from Example 1 only in that step S3 is added, and steps S1 and S2 and parameters are the same as those in Example 1.

[0065] Specifically, step S3 of this embodiment includes:

[0066] The GaN epitaxial wafer sample (original diameter of about 2 μm) after S2 etching was immersed in KOH solution (1 mol / L, 90°C water bath) for 10 minutes, and the GaN pattern was corroded and modified to obtain a GaN array, which was marked as sample G.

[0067] In this embodiment, since SiO2 protects the upper surface, the etching damage of the GaN sidewall is reduced, and the diameter is reduced to 1 μm, forming a submicron-level ordered array.

[0068] Example 7

[0069] A method for preparing a GaN array differs from Example 1 only in that step S3 is added, and steps S1 and S2 and parameters are the same as those in Example 1.

[0070] Specifically, step S3 of this embodiment includes:

[0071] The GaN epitaxial wafer sample (original diameter of about 2 μm) after S2 etching was immersed in KOH solution (1 mol / L, 90°C water bath) for 14 minutes to etch and modify the GaN pattern to obtain a GaN array, which was marked as sample H.

[0072] The morphology of the GaN arrays prepared under different etching modification conditions in the above Examples 6-7 is shown in FIG. Figure 4 As shown, (a) is the GaN pattern before KOH solution corrosion; (b)-(c) are the GaN ordered arrays after modification with KOH solutions of corresponding concentrations, corresponding to samples G and H, respectively.

[0073] The test showed that the diameter of sample G was reduced from 2μm to 1μm, while the diameter of sample H was reduced from the original 2μm to 563nm. Compared with the formation of sample G, it shows that GaN micro / nano ordered arrays of different diameters can be obtained by controlling the KOH solution corrosion time.

[0074] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A method for preparing a finely controlled patterned GaN array, characterized in that: The following steps are involved: S1. Preparing a patterned GaN epitaxial wafer on a semiconductor substrate; S2. Perform ICP etching on the patterned GaN epitaxial wafer; the etching gas is a mixture of Cl2 and BCl3. By adjusting the RF power and ICP power, the conversion and size control of GaN with different morphologies are achieved; by adjusting the Cl2 flow rate, the side wall tilt angle of GaN is controlled.

2. The method for preparing a finely controlled patterned GaN array according to claim 1, wherein: The method further includes S3, wherein a KOH solution is used to etch and modify the GaN pattern obtained in S2 to obtain a GaN array.

3. The method for preparing a finely controlled patterned GaN array according to claim 1 or 2, characterized in that: In S2, the flow ratio of Cl2 to BCl3 in the etching gas is 48:2-8, the flow rate of Cl2 is 24-96 sccm; the RF power is 100-200W, and the ICP power is 300-1500W.

4. The method for preparing a finely controlled patterned GaN array according to claim 2, wherein: In S3, the diameter of the GaN array is regulated by controlling the time of the etching modification; preferably, the time of the etching modification is 10 to 14 minutes.

5. The method for preparing a finely controlled patterned GaN array according to claim 2, wherein: In S3, the concentration of the KOH solution is 0.5 to 3 mol / L; preferably, the corrosion modification is performed in a water bath at 85 to 95°C.

6. The method for preparing a finely controlled patterned GaN array according to claim 1, wherein: S1 specifically includes: (1) growing a GaN buffer layer and an undoped GaN layer in sequence on a semiconductor substrate to form a GaN epitaxial wafer; (2) growing a SiO2 mask layer on the surface of the undoped GaN layer of the GaN epitaxial wafer, and then transferring a preset pattern to the SiO2 mask layer through photolithography and reactive ion etching to obtain a patterned GaN epitaxial wafer.

7. The method for preparing a finely controlled patterned GaN array according to claim 6, wherein: In S1, the semiconductor substrate is selected from at least one of a sapphire substrate, a silicon carbide substrate, and a silicon substrate.

8. The method for preparing a finely controlled patterned GaN array according to claim 6 or 7, characterized in that: In S1, the thickness of the GaN buffer layer is 10-80 nm, and the thickness of the undoped GaN layer is 2-8 μm; preferably, in S1, the thickness of the GaN buffer layer is 30-40 nm, and the thickness of the undoped GaN layer is 4-6 μm.

9. The method for preparing a finely controlled patterned GaN array according to claim 6 or 7, characterized in that: In S1, a GaN buffer layer and a non-doped GaN layer are sequentially grown on a semiconductor substrate by metal organic chemical vapor deposition; and a SiO2 mask layer is grown by plasma enhanced chemical vapor deposition.

10. A patterned GaN array, characterized in that: The method is prepared by any one of claims 1 to 9.

Images