Etching method of semiconductor device

Abstract

The invention relates to an etching method of a semiconductor device. The semiconductor device comprises a stacked structure, a bottom anti-reflection layer and a mask layer which are sequentially arranged from bottom to top. The etching method comprises the following steps that first etching gas is provided, the first etching gas comprises main etching gas and protective gas, and the gas ratio of the main etching gas to the protective gas is determined; a first etching step: in a first etching gas atmosphere, etching the mask layer and the bottom anti-reflection layer until the laminated structure is exposed, and forming the mask layer with an inclined side wall; the inclined side wall inclines outwards from top to bottom. The invention provides an etching method of a semiconductor device, which can break through the line width of a laminated structure determined by the physical limit size of a rectangular mask layer by adjusting the gas ratio of a main etching gas to a protective gas, changing the deposition amount of a polymer on an inclined side wall and adjusting the inclination angle of the inclined side wall. And the line width of the laminated structure is increased, so that a groove with a smaller size is obtained.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to an etching method for a semiconductor device. Background Art

[0002] To improve performance indicators such as processor speed and analog frequency response, the semiconductor manufacturing industry is moving towards smaller critical dimensions (CDs). Photoresist (PR), a mask, plays a crucial role in determining the critical dimensions of semiconductor devices. These dimensions, including line and trench widths, directly impact device conductivity and integration density.

[0003] Related technologies typically employ lateral etching of a photoresist mask layer, directly reducing the size of the photoresist mask layer during the process, thereby reducing the line width of semiconductor devices. However, this technique still cannot overcome the physical size limit of the photoresist mask layer to adjust the line width of semiconductor devices. Summary of the Invention

[0004] The present invention aims to solve at least one technical problem existing in the related art, and proposes a method for preparing a semiconductor device. By adjusting the inclination angle of the inclined side wall of the mask layer, not only the line width of the semiconductor device can be increased, but also the line width of the semiconductor device can be reduced.

[0005] The present invention provides an etching method for a semiconductor device, wherein the semiconductor device comprises a stacked structure, a bottom anti-reflection layer and a mask layer arranged sequentially from bottom to top;

[0006] The etching method comprises the following steps:

[0007] Providing a first etching gas, wherein the first etching gas includes a main etching gas and a protective gas, and determining a gas ratio of the main etching gas to the protective gas;

[0008] In the first etching step, the mask layer and the bottom anti-reflection layer are etched in the first etching gas atmosphere until the stacked structure is exposed, thereby forming a mask layer with an inclined sidewall; wherein the inclined sidewall is inclined outward from top to bottom.

[0009] Optionally, the gas ratio of the first etching gas is positively correlated with the slope of the inclined sidewall, positively correlated with the width of the trench of the stacked structure, and negatively correlated with the line width of the stacked structure;

[0010] And / or, the cross-sectional shape of the mask layer with the inclined sidewall along the vertical direction is an isosceles trapezoid, an isosceles triangle, a combination of an isosceles trapezoid and a rectangle, or a combination of an isosceles triangle and a rectangle.

[0011] Optionally, the main etching gas is tetrafluoromethane, the protective gas is trifluoromethane, the flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of trifluoromethane is 0-300 sccm, the gas ratio of tetrafluoromethane to trifluoromethane is: 1:3-2:1, and the first etching time is 10-300 s;

[0012] Alternatively, the main etching gas is tetrafluoromethane, the protective gas is difluoromethane, the flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of difluoromethane is 0-300 sccm, the gas ratio of tetrafluoromethane to difluoromethane is 1:2.5-1:1.2, and the first etching time is 10-300 s.

[0013] Optionally, the gas ratio of tetrafluoromethane to trifluoromethane is 1:3-1:1, and the slope of the inclined sidewall is between 0.4-0.6; the gas ratio of tetrafluoromethane to trifluoromethane is 1:1-2:1, and the slope of the inclined sidewall is between 0.6-0.8;

[0014] Alternatively, the gas ratio of tetrafluoromethane to difluoromethane is 1:2.5-1:1.2, and the slope of the inclined sidewall is between 0.4-0.6; the gas ratio of tetrafluoromethane to difluoromethane is 1:1.2-1.8:1, and the slope of the inclined sidewall is between 0.6-0.8.

[0015] Optionally, the first etching gas further includes an inert gas, and the flow rate of the inert gas is 0-300 sccm.

[0016] Optionally, after the first etching step, the etching method further comprises:

[0017] In the second etching step, based on the mask layer with the inclined sidewall, the stacked structure is etched to obtain a patterned stacked structure, wherein the line width of the patterned stacked structure is equal to the distance between the intersection of the extension line of the inclined sidewall and the upper surface of the stacked structure.

[0018] Optionally, the stacked structure includes a first silicon oxide layer, and the first silicon oxide layer is located below the bottom anti-reflection layer;

[0019] The second etching step comprises:

[0020] In a second etching gas atmosphere, based on the mask layer with the inclined sidewall, the first silicon oxide layer is etched to form a patterned first silicon oxide layer; wherein the line width of the patterned first silicon oxide layer is equal to the distance between the intersection point of the extension line of the inclined sidewall and the upper surface of the first silicon oxide layer.

[0021] Optionally, the second etching gas includes: tetrafluoromethane, oxygen and inert gas, the flow rate of tetrafluoromethane is 0-300sccm, the flow rate of oxygen is 0-300sccm, the flow rate of inert gas is 10-500sccm, the ratio of tetrafluoromethane, oxygen and inert gas is: (1-7): (1-3): (6-17), and the second etching time is 5-300s.

[0022] Optionally, the stacked structure comprises a silicon bottom layer, a second silicon oxide layer and a silicon top layer arranged in sequence from bottom to top, and the silicon top layer is located below the first silicon oxide layer;

[0023] After the step of etching the first silicon oxide layer, the second etching step further includes:

[0024] In a third etching gas atmosphere, using the patterned first silicon oxide layer as a mask, the silicon top layer and the second silicon oxide layer are sequentially etched until the silicon bottom layer is exposed, thereby forming a patterned silicon top layer and a patterned second silicon oxide layer.

[0025] Optionally, the third etching gas includes tetrafluoromethane and an inert gas, the flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of the inert gas is 10-500 sccm, the ratio of tetrafluoromethane to the inert gas is: (1-7): (1-3), and the third etching time is 5-300 s.

[0026] The present invention provides a method for etching a semiconductor device, which has at least the following beneficial technical effects:

[0027] On the one hand, by adjusting the gas ratio of the main etching gas and the protective gas, the amount of polymer deposited on the inclined sidewall is changed to adjust the lateral etching rate, thereby adjusting the inclination angle of the inclined sidewall and the line width of the stacked structure;

[0028] On the other hand, the line width of the stacked structure determined by the physical limit size of the rectangular mask layer can be exceeded, and the line width of the stacked structure can be increased, thereby obtaining a smaller-sized trench;

[0029] In addition, the line width of the stacked structure determined by the physical limit size of the rectangular mask layer can be exceeded, and the line width of the stacked structure can be increased or reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 In a method for controlling mask size based on a dry etching process provided in the related art, a schematic diagram of the photoresist mask layer obtained in step S1 is shown. Figure 1 ;

[0031] Figure 2 In a method for controlling mask size based on a dry etching process provided in the related art, a schematic diagram of the photoresist mask layer obtained in step S2 is shown. Figure 2 ;

[0032] Figure 3 A process of a semiconductor etching method provided by an embodiment of the present invention Figure 1 ;

[0033] Figure 4 A structural diagram of a semiconductor device processed by a semiconductor etching method provided by an embodiment of the present invention;

[0034] Figure 5 A structural diagram of a mask layer with inclined sidewalls obtained in a first etching step when the ratio of the main etching gas to the protective gas is low in a semiconductor etching method provided by an embodiment of the present invention;

[0035] Figure 6 A schematic diagram of ion bombardment on a mask layer in a semiconductor etching method provided by an embodiment of the present invention;

[0036] Figure 7 A schematic diagram of the shielding effect of a mask layer with inclined sidewalls on ion bombardment in a semiconductor etching method provided by an embodiment of the present invention;

[0037] Figure 8 A schematic diagram of determining the line width of a stacked structure based on the slope of an inclined sidewall in a semiconductor etching method provided by an embodiment of the present invention;

[0038] Figure 9 A structural diagram of a mask layer with inclined sidewalls obtained in a first etching step in a semiconductor etching method provided by an embodiment of the present invention when the gas ratio of the main etching gas to the protective gas is high;

[0039] Figure 10 A process of a semiconductor etching method provided by an embodiment of the present invention Figure 2 ;

[0040] Figure 11 A schematic structural diagram of a semiconductor etching method provided in an embodiment of the present invention after etching the silicon top layer using the first silicon oxide layer as a mask.

[0041] Figure 12A schematic structural diagram of a semiconductor etching method provided in an embodiment of the present invention, in which a second silicon oxide layer is etched using a first silicon oxide layer as a mask.

[0042] Description of reference numerals:

[0043] 1. Substrate; 2. Photoresist mask layer; 10. Silicon bottom layer; 20. Second silicon oxide layer; 30. Silicon top layer; 40. First silicon oxide layer; 50. Bottom anti-reflection layer; 60. Mask layer; 70. Inclined sidewall. DETAILED DESCRIPTION

[0044] See attached Figure 1-Figure 2 , a related art discloses a method for controlling mask size based on a dry etching process, comprising the following steps:

[0045] S1: preparing a photoresist mask layer 2, specifically comprising: coating a uniform layer of photoresist on the surface of the substrate 1 to form a photoresist layer; generating corresponding patterned micro-nano structures on the surface of the substrate by optical exposure to form the photoresist mask layer 2;

[0046] S2: using a dry etching process to process the mask size of the photoresist mask layer prepared in S1 according to the desired pattern size;

[0047] S3: Perform subsequent pattern transfer etching using the photoresist mask layer obtained in S2.

[0048] As can be seen, in this related art, by laterally etching the photoresist mask layer 2, the size of the photoresist mask layer 2 is directly reduced, thereby reducing the pattern transfer size, that is, reducing the line width of the semiconductor device. The line width of the semiconductor device is equal to the line width of the photoresist mask layer 2 after the laterally etching, that is, equal to the physical limit size of the photoresist mask layer 2 after the laterally etching. However, this related art still cannot exceed the physical limit size of the photoresist mask layer 2 to adjust the line width of the semiconductor device.

[0049] In order to break through the physical limit size of the mask layer and adjust the line width of the semiconductor device, an embodiment of the present invention provides an etching method for a semiconductor device, which breaks through the physical limit size of the mask layer by adjusting the inclination angle of the inclined side wall of the mask layer to adjust the line width of the semiconductor device.

[0050] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the following Figure 3-Figure 12 The specific embodiments of the present invention are described in detail.

[0051] The embodiment of the present invention provides a method for etching a semiconductor device. Figure 4The semiconductor device includes a stacked structure, a bottom anti-reflection layer 50 and a mask layer 60 arranged in sequence from bottom to top; the number of mask layers 60 is not limited and can be one, two or other numbers. Figure 4 As shown, there are two mask layers 60, spaced apart in the lateral direction. The bottom anti-reflection layer 50 is primarily used to reduce light reflection during the photolithography process. When light strikes the surface of a semiconductor device, some light is reflected, while some light penetrates the bottom of the stacked structure. The reflected light then returns to the mask layer 60, potentially overexposure of the mask layer 60 and causing image blur and distortion. Therefore, to reduce the effects of reflection, the bottom anti-reflection layer 50 is provided.

[0052] See attached Figure 3 and Figure 5 , the etching method comprises the following steps:

[0053] S100, providing a first etching gas, the first etching gas including a main etching gas and a protective gas, and determining a gas ratio of the main etching gas to the protective gas;

[0054] S110, a first etching step, in a first etching gas atmosphere, etching the mask layer 60 and the bottom anti-reflection layer 5 until the stacked structure is exposed, forming the mask layer 60 with inclined sidewalls 70 and the patterned bottom anti-reflection layer 50; wherein the inclined sidewalls 70 are inclined outward from top to bottom.

[0055] It should be noted that the protective gas can form polymers on the inclined sidewalls 70 and the sidewalls of the patterned bottom anti-reflection layer 50, thereby reducing the lateral etching rate and adjusting the morphology of the mask layer 60. Figure 6 Before etching, the mask layer 60 is a rectangular mask layer with a right-angle region. During the etching process, the incident direction of ions is perpendicular to the surface of the rectangular mask layer. Since the electric field strength in the right-angle region is high, the right-angle region is more susceptible to ion bombardment, and thus the right-angle region is prone to forming a slope. Figure 7 The mask layer 60 with the inclined sidewall 70 has a shielding effect on the ion bombardment, thereby selectively etching the stacked structure. The area outside the intersection of the extension line of the inclined sidewall 70 and the upper surface of the stacked structure is more bombarded by the ions (such as the attached Figure 7 In the figure, the ions shown by the red arrows are etched; Figure 8 As shown, the stacked structure between the two mask layers 60 is etched away to form a trench; the area between the intersection of the extended line of the inclined sidewall 70 and the upper surface of the stacked structure is shielded and retained; that is, as shown in FIG. Figure 8As shown, the line width of the patterned stacked structure is equal to the distance between the intersection of the extended line of the inclined sidewall 70 and the upper surface of the stacked structure. The line width of the patterned stacked structure is the lateral dimension of the stacked structure retained by etching a portion of the thickness of the stacked structure.

[0056] The etching method for a semiconductor device provided by an embodiment of the present invention, on the one hand, adjusts the gas ratio of the main etching gas and the protective gas to change the deposition amount of the polymer on the inclined sidewall 70 to adjust the lateral etching rate, thereby adjusting the inclination angle of the inclined sidewall 70, adjusting the line width of the stacked structure, and adjusting the groove width of the stacked structure; on the other hand, the bottom side width of the mask layer 60 with the inclined sidewall 70 can be equal to the bottom side width of the rectangular mask layer before etching. The bottom side width of the mask layer 60 with the inclined sidewall 70 is amplified by the bottom anti-reflection layer 50 of a certain thickness, so that the line width of the stacked structure is greater than the bottom side width of the rectangular mask layer, that is, , it is possible to break through the line width of the stacked structure determined by the physical limit size of the rectangular mask layer, increase the line width of the stacked structure, and thus obtain a smaller-sized groove; in addition, the bottom edge width of the mask layer with the inclined sidewall 70 can also be smaller than the bottom edge width of the rectangular mask layer before etching, and the bottom edge width of the mask layer 60 with the inclined sidewall 70 is amplified by the bottom anti-reflection layer 50 of a certain thickness, so that the line width of the stacked structure can be greater than or less than the bottom edge width of the rectangular mask layer, that is, it is possible to break through the line width of the stacked structure determined by the physical limit size of the rectangular mask layer, increase the line width of the stacked structure, or reduce the line width of the stacked structure.

[0057] In the embodiment of the present invention, the gas ratio of the first etching gas is positively correlated with the slope of the inclined sidewall 70, positively correlated with the width of the trench of the stacked structure, and negatively correlated with the line width of the stacked structure. Figure 9 When the ratio of the main etching gas to the protective gas is high, the main etching gas is relatively more, the energy of the ion bombardment is enhanced, the vertical etching rate increases, and the protective gas is relatively less. The polymer coverage of the sidewall of the mask layer 60 is insufficient, resulting in a vertical etching rate greater than a lateral etching rate, thereby forming a steep inclined sidewall 70, that is, the slope of the inclined sidewall 70 is large, and the intersection point of the extended line of the inclined sidewall 70 and the upper surface of the stacked structure is close, that is, the line width of the stacked structure is small, but the groove width of the stacked structure is large; see the attached figure. Figure 5When the ratio of the main etching gas to the protective gas is low, the protective gas is relatively more, the polymer on the side wall of the mask layer 60 is uniform and dense, and the lateral etching rate is effectively suppressed. The main etching gas is relatively less, the ion bombardment energy is enhanced, and the vertical etching rate is reduced, resulting in a reduction in the difference between the vertical etching rate and the lateral etching rate, thereby forming a gently inclined side wall 70, that is, the slope of the inclined side wall 70 is small, and the intersection point of the extension line of the inclined side wall 70 with the upper surface of the stacked structure is far away, that is, the line width of the stacked structure is large, but the groove width of the stacked structure is small.

[0058] In the embodiment of the present invention, for example, when the slope of the inclined sidewall 70 is the first slope, the bottom width of the mask layer 60 having the inclined sidewall 70 is the first bottom width, the corresponding line width of the stacked structure is the first line width, and the corresponding groove width of the stacked structure is the first groove width; when the slope of the inclined sidewall 70 is the second slope, the bottom width of the mask layer 60 having the inclined sidewall 70 is the second bottom width, the corresponding line width of the stacked structure is the second line width, and the corresponding groove width of the stacked structure is the second groove width; wherein, the first slope is greater than the second slope, and the first bottom width is greater than the second bottom width; since the first slope is greater than the first slope, the distance between the extension line of the inclined sidewall 70 of the first slope and the intersection point of the stacked structure is closer, that is, a larger first bottom width results in a smaller first line width, that is, a wider mask layer results in a smaller first line width, achieving size reversal; conversely, a larger first groove width is obtained.

[0059] In an embodiment of the present invention, the cross-sectional shape of the mask layer 60 having the inclined sidewall 70 along the vertical direction is in various forms, for example, it can be an isosceles trapezoid; for another example, it can be an isosceles triangle; for another example, it can be a combination of an isosceles trapezoid and a rectangle, that is, the upper end is an isosceles trapezoid and the lower end is a rectangle; for another example, it can be a combination of an isosceles triangle and a rectangle, that is, the upper end is an isosceles triangle and the lower end is a rectangle; this cross-sectional shape is not limited here.

[0060] In the embodiment of the present invention, the main materials of the mask layer 60 and the bottom anti-reflection layer 50 are CH-based polymers, and the main etching gas and the protective gas are both fluorine-based gases, as follows:

[0061] For example, the main etching gas is tetrafluoromethane (CF4) and the protective gas is trifluoromethane (CHF3), wherein tetrafluoromethane (CF4) decomposes in a plasma environment to produce highly active substances such as fluorine free radicals, which react with CH-based polymers to generate volatile products, such as carbon tetrafluoride (CF4), thereby achieving etching of CH-based polymers; trifluoromethane (CHF3) can form polymers on the inclined sidewalls 70 of the mask layer 60 and the sidewalls of the patterned bottom anti-reflective layer 50. Specifically, for example, it decomposes in a plasma environment to generate carbon-containing free radicals (such as CF2). During the etching process, the carbon-containing free radicals are deposited on the inclined sidewalls 70 of the mask layer 60 to form a fluorocarbon polymer film, thereby reducing the lateral etching rate of the mask layer 60. The flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of trifluoromethane is 0-300 sccm, the gas ratio of tetrafluoromethane to trifluoromethane is 1:3-2:1, and the first etching time is 10-300 seconds. By adjusting the gas flow rates and gas ratios of tetrafluoromethane and trifluoromethane, the vertical and lateral etching rates can be adjusted, thereby adjusting the angle of the inclined sidewalls of the mask layer 60.

[0062] For another example, the main etching gas is tetrafluoromethane (CF4) and the protective gas is difluoromethane (CH2F2), wherein tetrafluoromethane (CF4) decomposes in a plasma environment to produce highly active substances such as fluorine free radicals, which react with CH-based polymers to generate volatile products, such as carbon tetrafluoride (CF4), thereby achieving etching of CH-based polymers; difluoromethane (CH2F2) can form polymers on the inclined sidewalls 70 of the mask layer 60 and the sidewalls of the patterned bottom anti-reflective layer 50. Specifically, for example, it decomposes in a plasma environment to generate carbon-containing free radicals (such as CF2). During the etching process, the carbon-containing free radicals are deposited on the inclined sidewalls 70 of the mask layer 60, thereby reducing the lateral etching rate of the mask layer 60. The flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of difluoromethane is 0-300 sccm, the gas ratio of tetrafluoromethane to difluoromethane is 1:2.5-1:1.2, and the first etching time is 10-300 seconds. By adjusting the gas flow rates and gas ratios of tetrafluoromethane and difluoromethane, the vertical and lateral etching rates can be adjusted, thereby adjusting the angle of the inclined sidewalls of the mask layer 60.

[0063] In the embodiment of the present invention, the gas ratio of tetrafluoromethane and trifluoromethane is 1:3-1:1, and the slope of the inclined sidewall is between 0.4-0.6; the gas ratio of tetrafluoromethane and trifluoromethane is 1:1-2:1, and the slope of the inclined sidewall is between 0.6-0.8.

[0064] In the embodiment of the present invention, the gas ratio of tetrafluoromethane and difluoromethane is 1:2.5-1:1.2, and the slope of the inclined sidewall is between 0.4-0.6; the gas ratio of tetrafluoromethane and difluoromethane is 1:1.2-1.8:1, and the slope of the inclined sidewall is between 0.6-0.8.

[0065] In an embodiment of the present invention, the first etching gas further comprises an inert gas with a flow rate of 0-300 sccm. The inert gas may be nitrogen, argon, or helium, and is used as a diluent gas to slow down the etching rate and avoid excessive etching caused by overreaction.

[0066] In the etching method provided in the embodiment of the present invention, see the attached Figure 3 The method further includes step S120, a second etching step, in which the stacked structure is etched based on the mask layer 60 having the inclined sidewalls 70 to obtain a patterned stacked structure, wherein the line width of the patterned stacked structure is equal to the distance between the intersection of the extended line of the inclined sidewalls 70 and the upper surface of the stacked structure. With this arrangement, compared to the related art in which the line width of the stacked structure is determined by the lateral dimensions of the rectangular mask layer, the etching method for a semiconductor device provided in the embodiment of the present invention determines the line width of the stacked structure by utilizing the slope of the inclined sidewalls 70 of the mask layer 60 and the bottom width of the mask layer 60. This method can exceed the line width of the stacked structure determined by the physical limit dimensions of the mask layer 60, that is, can increase or decrease the line width of the stacked structure.

[0067] In the embodiment of the present invention, see the attached Figure 4 The stacked structure includes a first silicon oxide layer 40, which is located below the bottom anti-reflection layer 50; see the attached Figure 3 Step S120 (second etching step) includes: Step S121, in a second etching gas atmosphere, etching the first silicon oxide layer 40 based on the mask layer 60 having the inclined sidewall 70 to form a patterned first silicon oxide layer 40; wherein the line width of the patterned first silicon oxide layer 40 is equal to the distance between the intersection of the extended line of the inclined sidewall 70 and the upper surface of the first silicon oxide layer 40. See Appendix Figure 7 The mask layer 60 with the inclined sidewall 70 has a shielding effect on the ion bombardment, thereby selectively etching the first silicon oxide layer 40. The area outside the intersection of the extension line of the inclined sidewall 70 and the upper surface of the first silicon oxide layer 40 is more bombarded by the ions (such as the attached Figure 7 The ions shown by the red arrows are etched; the area between the intersection of the extension line of the inclined side wall 70 and the upper surface of the first silicon oxide layer 40 is shielded and retained; that is, see the attached Figure 8The line width of the patterned first silicon oxide layer 40 is equal to the distance between the intersection of the extended line of the inclined sidewall 70 and the upper surface of the first silicon oxide layer 40. The line width of the patterned first silicon oxide layer 40 is the lateral dimension of the stacked structure remaining after the thickness of the stacked structure is etched. With this configuration, the first silicon oxide layer 40 is selectively etched by utilizing the shielding effect of the inclined sidewall 70 of the mask layer 60 on ion bombardment.

[0068] In the embodiment of the present invention, the second etching gas includes: tetrafluoromethane (CF4), oxygen (O2) and an inert gas. Tetrafluoromethane (CF4) is used as the main etching gas and dissociates in the plasma to generate highly active fluorine radicals (F). The fluorine radicals (F) react chemically with the first silicon oxide layer 40 to generate volatile products of silicon tetrafluoride (SiF4) and carbon dioxide (CO2). Oxygen (O2) can promote the dissociation of H atoms in the mask layer 60 of the CH-based polymer. The H atoms react chemically with the first silicon oxide layer 40 to generate water vapor. (H2O) and silicon (Si), thereby improving the etching rate of the first silicon oxide layer 40; wherein, the flow rate of tetrafluoromethane is 0-300sccm, the flow rate of oxygen is 0-300sccm, the flow rate of inert gas is 10-500sccm, the inert gas can be nitrogen, argon or helium, and the ratio of tetrafluoromethane, oxygen and inert gas is: (1-7): (1-3): (6-17), for example, the ratio of tetrafluoromethane, oxygen and inert gas can be 4:1:9, and the second etching time is 5s-300s. In this way, tetrafluoromethane and oxygen are used to etch the first silicon oxide layer 40, wherein oxygen can dissociate the H atoms in the CH-based polymer, thereby improving the etching rate of the first silicon oxide layer 40.

[0069] In the embodiment of the present invention, see the attached Figure 4 The stacked structure includes a silicon bottom layer 10, a second silicon oxide layer 20 and a silicon top layer 30 arranged in sequence from bottom to top, and the silicon top layer 30 is located below the first silicon oxide layer 40; see the attached Figure 10-12 Step S120 (second etching step) further includes: Step S122, in a second etching gas atmosphere, using the patterned first silicon oxide layer 40 as a mask, sequentially etching the silicon top layer 30 and the second silicon oxide layer 20 until the silicon bottom layer 10 is exposed, thereby forming a patterned silicon top layer 30 and a patterned second silicon oxide layer 20. In this manner, using the patterned first silicon oxide layer 40 as a mask, etching the silicon top layer 30 and the second silicon oxide layer 20 transfers the pattern to the silicon top layer 30 and the second silicon oxide layer 20.

[0070] In an embodiment of the present invention, the third etching gas includes: tetrafluoromethane and an inert gas, the flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of the inert gas is 10-500 sccm, the inert gas can be nitrogen, argon or helium, and the ratio of tetrafluoromethane to the inert gas is: (1-7): (1-3), for example, the ratio of tetrafluoromethane to the inert gas can be 4:1, and the third etching time is 5-300s.

[0071] In the embodiment of the present invention, the line width of the patterned bottom anti-reflection layer 50 is smaller than or equal to the bottom width of the mask layer 60 having the inclined sidewall 70 .

[0072] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for etching a semiconductor device, characterized in that: The semiconductor device comprises a stacked structure, a bottom anti-reflection layer (50) and a mask layer (60) which are sequentially arranged from bottom to top; The etching method comprises the following steps: Providing a first etching gas, wherein the first etching gas includes a main etching gas and a protective gas, and determining a gas ratio of the main etching gas to the protective gas; In a first etching step, in the first etching gas atmosphere, the mask layer (60) and the bottom anti-reflection layer (5) are etched until the stacked structure is exposed, thereby forming a mask layer (60) having an inclined sidewall (70); wherein the inclined sidewall (70) is inclined outward from top to bottom.

2. The etching method of a semiconductor device according to claim 1, wherein: The gas ratio of the first etching gas is positively correlated with the slope of the inclined sidewall (70), positively correlated with the width of the groove of the stacked structure, and negatively correlated with the line width of the stacked structure; And / or, the cross-sectional shape of the mask layer (60) with the inclined sidewall (70) along the vertical direction is an isosceles trapezoid or an isosceles triangle or a combination of an isosceles trapezoid and a rectangle or a combination of an isosceles triangle and a rectangle.

3. The etching method of a semiconductor device according to claim 1, wherein: The main etching gas is tetrafluoromethane, the protective gas is trifluoromethane, the flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of trifluoromethane is 0-300 sccm, the gas ratio of tetrafluoromethane to trifluoromethane is: 1:3-2:1, and the first etching time is 10-300 s; Alternatively, the main etching gas is tetrafluoromethane, the protective gas is difluoromethane, the flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of difluoromethane is 0-300 sccm, the gas ratio of tetrafluoromethane to difluoromethane is 1:2.5-1:1.2, and the first etching time is 10-300 s.

4. The etching method of a semiconductor device according to claim 3, wherein: The gas ratio of tetrafluoromethane to trifluoromethane is 1:3-1:1, and the slope of the inclined sidewall is between 0.4-0.6; the gas ratio of tetrafluoromethane to trifluoromethane is 1:1-2:1, and the slope of the inclined sidewall is between 0.6-0.8; Alternatively, the gas ratio of tetrafluoromethane to difluoromethane is 1:2.5-1:1.2, and the slope of the inclined sidewall is between 0.4-0.6; the gas ratio of tetrafluoromethane to difluoromethane is 1:1.2-1.8:1, and the slope of the inclined sidewall is between 0.6-0.

8.

5. The etching method of a semiconductor device according to claim 3, wherein: The first etching gas also includes an inert gas, and the flow rate of the inert gas is 0-300 sccm.

6. The etching method for a semiconductor device according to any one of claims 1 to 5, characterized in that: After the first etching step, the etching method further includes: In a second etching step, based on the mask layer (60) having the inclined sidewall (70), the stacked structure is etched to obtain a patterned stacked structure, wherein the line width of the patterned stacked structure is equal to the distance between the intersection point of the extension line of the inclined sidewall (70) and the upper surface of the stacked structure.

7. The etching method of a semiconductor device according to claim 6, wherein: The stacked structure comprises a first silicon oxide layer (40), wherein the first silicon oxide layer (40) is located below the bottom anti-reflection layer (50); The second etching step comprises: In a second etching gas atmosphere, based on the mask layer (60) having the inclined sidewall (70), the first silicon oxide layer (40) is etched to form a patterned first silicon oxide layer (40); wherein the line width of the patterned first silicon oxide layer (40) is equal to the distance between the intersection point of the extension line of the inclined sidewall (70) and the upper surface of the first silicon oxide layer (40).

8. The etching method of a semiconductor device according to claim 7, wherein: The second etching gas includes: tetrafluoromethane, oxygen and inert gas, the flow rate of tetrafluoromethane is 0-300sccm, the flow rate of oxygen is 0-300sccm, the flow rate of inert gas is 10-500sccm, the ratio of tetrafluoromethane, oxygen and inert gas is: (1-7): (1-3): (6-17), and the second etching time is 5-300s.

9. The etching method of a semiconductor device according to claim 7, wherein: The stacked structure comprises a silicon bottom layer (10), a second silicon oxide layer (20) and a silicon top layer (30) arranged in sequence from bottom to top, wherein the silicon top layer (30) is located below the first silicon oxide layer (40); After the step of etching the first silicon oxide layer (40), the second etching step further comprises: In a third etching gas atmosphere, the patterned first silicon oxide layer (40) is used as a mask to sequentially etch the silicon top layer (30) and the second silicon oxide layer (20) until the silicon bottom layer (10) is exposed, thereby forming a patterned silicon top layer (30) and a patterned second silicon oxide layer (20).

10. The etching method of a semiconductor device according to claim 9, wherein: The third etching gas includes tetrafluoromethane and an inert gas, the flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of the inert gas is 10-500 sccm, the ratio of tetrafluoromethane to the inert gas is: (1-7): (1-3), and the third etching time is 5-300s.

Images