Preparation method of semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure. The preparation method comprises the following steps that a substrate is provided, the substrate comprises a substrate body, a pad oxide layer and at least one groove set, the groove set comprises a first groove and a second groove, the pad oxide layer is formed on the surface of the substrate body, the first groove and the second groove are formed in the substrate body, and the upper portions of the first groove and the second groove penetrate through the pad oxide layer; forming a first barrier layer on the side wall of the first trench and the side wall of the second trench; forming a second barrier layer on the side wall of the first barrier layer; forming an isolation layer between the second barrier layers on the two sides of the second groove; replacing the second barrier layer with a first epitaxial layer and a heavily doped region which are sequentially arranged from bottom to top, and replacing the first barrier layer with a second epitaxial layer and a lightly doped region which are sequentially arranged from bottom to top; and forming a gate structure on a channel between the first groove and the second groove, and forming side wall structures on two sides of the gate structure. According to the preparation method, the manufacturing process can be simplified, the production efficiency is improved, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] In semiconductor manufacturing, with the development of ultra-large-scale integrated circuits (VLSI), integrated circuit feature sizes continue to shrink. To accommodate this reduction in feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) has also been continuously shortened. This shortens the distance between the device's source and drain, increasing the electric field strength. Electrons or holes are accelerated in the channel, gaining high energy and potentially being injected into the gate oxide. This can lead to device reliability issues, such as a drop in threshold voltage, a deterioration in subthreshold slope, and the occurrence of drain-induced barrier lowering (DIBL). By introducing a lightly doped drain (LDD) region between the drain and source, the electric field strength near the drain can be reduced, thereby mitigating the effects of hot carrier effects. Traditional fabrication methods require separate masks to form trench isolation structures, and ion implantation of the LDD, source, and drain requires additional masking and implantation steps, increasing process cycle time and manufacturing cost. Summary of the Invention

[0003] The present invention provides a method for preparing a semiconductor structure, which simplifies the manufacturing process, improves production efficiency and reduces manufacturing costs.

[0004] The present invention provides a method for preparing a semiconductor structure, comprising the following steps: Providing a substrate, the substrate comprising a substrate, a pad oxide layer, and at least one trench group, the trench group comprising a first trench and a second trench, the pad oxide layer being formed on a surface of the substrate, the first trench and the second trench being disposed in the substrate, and having an upper portion penetrating the pad oxide layer to form an opening, and the width of the first trench being smaller than the width of the second trench; forming a first barrier layer on both sidewalls of the first trench and on both sidewalls of the second trench respectively; forming a second barrier layer on the sidewalls of the first barrier layer in the first trench and the second trench respectively, and making the second barrier layer fill the first trench; forming an isolation layer between the second barrier layer on both sides of the second trench; Replacing the second barrier layer with the first epitaxial layer and the heavily doped region sequentially arranged from bottom to top, and replacing the first barrier layer with the second epitaxial layer and the lightly doped region sequentially arranged from bottom to top; A gate structure is formed on the channel between the first trench and the second trench, and sidewall structures are formed on both sides of the gate structure.

[0005] In one embodiment of the present invention, the substrate includes a plurality of trench groups, the heavily doped regions of the plurality of trench groups include a P-type heavily doped region and an N-type heavily doped region, and the lightly doped regions of the plurality of trench groups include a P-type lightly doped region and an N-type lightly doped region. Replacing the second barrier layer with a first epitaxial layer and a heavily doped region sequentially arranged from bottom to top, and replacing the first barrier layer with a second epitaxial layer and a lightly doped region sequentially arranged from bottom to top, comprises the following steps: Providing a first mask layer on the substrate, the first mask layer exposing the trench group corresponding to the P-type heavily doped region and the P-type lightly doped region, removing the second barrier layer in the trench group corresponding to the P-type heavily doped region and the P-type lightly doped region, and sequentially growing a first N-type epitaxial layer and a P-type heavily doped region at positions corresponding to the second barrier layer; removing the first barrier layer in the trench group corresponding to the P-type heavily doped region and the P-type lightly doped region, and sequentially growing a second N-type epitaxial layer and a P-type lightly doped region at positions corresponding to the first barrier layer; A second mask layer is provided on the substrate, the second mask layer exposes the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region, the second barrier layer in the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region is removed, and a first P-type epitaxial layer and an N-type heavily doped region are sequentially generated at corresponding positions of the second barrier layer; the first barrier layer in the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region is removed, and a second P-type epitaxial layer and an N-type lightly doped region are sequentially generated at corresponding positions of the first barrier layer.

[0006] In one embodiment of the present invention, forming a first barrier layer on both sidewalls of the first trench and on both sidewalls of the second trench respectively includes the following steps: depositing a first barrier in the first trench and the second trench, wherein the first barrier covers the substrate; The first barrier in the horizontal direction is removed, and the first barrier layer is formed on both sidewalls of the first trench and on both sidewalls of the second trench, respectively.

[0007] In one embodiment of the present invention, forming a second barrier layer on the sidewalls of the first barrier layer in the first trench and the second trench respectively, and making the second barrier layer fill the first trench, includes the following steps: Depositing a second barrier in the first trench and the second trench, wherein the second barrier covers the pad oxide layer, the first trench, the second trench, and the first barrier layer; The second barrier in the horizontal direction is removed, and a second barrier layer is formed on the sidewalls of the first barrier layer in the first trench and in the second trench respectively.

[0008] In one embodiment of the present invention, the depth of the first trench and the second trench is 150-330 nm.

[0009] In one embodiment of the present invention, the thickness of the lightly doped region is 20-100 nm, and the thickness of the heavily doped region is 50-220 nm.

[0010] In one embodiment of the present invention, the ion concentration of the heavily doped region is 1×10 20 ~5×10 20 cm -3 The ion concentration of the lightly doped region is 1×10 17 ~5×10 17 cm -3 .

[0011] In one embodiment of the present invention, after removing the first barrier layer and forming a second epitaxial layer and a lightly doped region in sequence at corresponding positions of the first barrier layer, the preparation method further includes removing the pad oxide layer and performing thermal oxidation treatment on the surface of the substrate to form an oxide layer on the surface of the substrate.

[0012] In one embodiment of the present invention, the temperature of the thermal oxidation treatment is 1000-1200° C., the time of the thermal oxidation treatment is 40-80 seconds, and the thickness of the oxide layer is 20-30 Å.

[0013] In one embodiment of the present invention, replacing the second barrier layer with a first epitaxial layer and a heavily doped region sequentially arranged from bottom to top, and replacing the first barrier layer with a second epitaxial layer and a lightly doped region sequentially arranged from bottom to top, comprises the following steps: removing the second barrier layer, and sequentially forming the first epitaxial layer and the heavily doped region at corresponding positions of the second barrier layer; removing the first barrier layer, and sequentially forming the second epitaxial layer and the lightly doped region at corresponding positions of the first barrier layer; The first barrier layer and the second barrier layer are removed by wet etching, and the wet etching has different selectivity ratios for the first barrier layer, the second barrier layer, and the isolation layer.

[0014] In summary, the present invention provides a method for fabricating a semiconductor structure, comprising forming a first barrier layer and a second barrier layer within a first trench, forming a first barrier layer, a second barrier layer, and an isolation layer within a second trench, replacing the second barrier layer with a first epitaxial layer and a heavily doped region sequentially arranged from bottom to top, replacing the first barrier layer with a second epitaxial layer and a lightly doped region sequentially arranged from bottom to top, forming a gate structure on the channel between the first trench and the second trench, and forming sidewalls on both sides of the gate structure. The present invention has the unexpected effect of forming an isolation layer within the second trench without the need for a separate mask, and without the need for additional masks and implantation processes when forming the source, drain, and lightly doped region, thereby simplifying the fabrication process, improving production efficiency, and reducing fabrication costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be derived from these drawings without inventive effort.

[0016] In the attached figure: Figure 1 A flow chart of manufacturing a semiconductor structure provided by one embodiment of the present invention; Figure 2 A schematic diagram of forming a pad oxide layer and a pad nitride layer on a substrate according to an embodiment of the present invention; Figure 3 A schematic diagram of forming a photoresist layer according to an embodiment of the present invention; Figure 4 A schematic diagram of forming a first trench and a second trench according to an embodiment of the present invention; Figure 5 A schematic diagram of removing a photoresist layer and a pad nitride layer provided in one embodiment of the present invention; Figure 6 A schematic diagram of depositing a first barrier according to an embodiment of the present invention; Figure 7 A schematic diagram of forming a first barrier layer according to an embodiment of the present invention; Figure 8 A schematic diagram of depositing a second barrier according to an embodiment of the present invention; Figure 9 A schematic diagram of forming a second barrier layer according to an embodiment of the present invention; Figure 10 A schematic diagram of depositing an insulating medium according to an embodiment of the present invention; Figure 11 A schematic diagram of forming an isolation layer according to an embodiment of the present invention; Figure 12 A schematic diagram of removing the second barrier layer provided in one embodiment of the present invention; Figure 13 A schematic diagram of forming a first epitaxial layer and a heavily doped region according to an embodiment of the present invention; Figure 14 A schematic diagram of removing the first barrier layer provided in one embodiment of the present invention; Figure 15 A schematic diagram of forming a second epitaxial layer and a lightly doped region according to an embodiment of the present invention; Figure 16 A schematic diagram of removing a pad oxide layer according to an embodiment of the present invention; Figure 17 A schematic diagram of forming an oxide layer according to an embodiment of the present invention; Figure 18 A schematic diagram of forming a gate and spacer structure provided in one embodiment of the present invention; Figure 19 A schematic diagram of forming a first barrier layer, a second barrier layer and an isolation layer on a substrate provided in another embodiment of the present invention; Figure 20 A schematic diagram of providing a first mask layer according to another embodiment of the present invention; Figure 21 A schematic diagram of forming a first N-type epitaxial layer, a P-type heavily doped region, a second N-type epitaxial layer and a P-type lightly doped region provided in another embodiment of the present invention; Figure 22 A schematic diagram of providing a second mask layer according to another embodiment of the present invention; Figure 23 This is a schematic diagram of forming a first P-type epitaxial layer and an N-type heavily doped region, a second P-type epitaxial layer and an N-type lightly doped region provided in another embodiment of the present invention.

[0017] The reference numerals are as follows: 100, base; 110, substrate; 111, well region; 1111, P-type well region; 1112, N-type well region; 120, pad oxide layer; 130, first trench; 140, second trench; 141, groove; 150, pad nitride layer; 160, photoresist layer; 161, first trench region; 162, second trench region; 170, oxide layer; 180, isolation structure; 200, first barrier layer; 300, second barrier layer; 400, isolation layer; 500, first epitaxial layer; 501, First P-type epitaxial layer; 502, first N-type epitaxial layer; 510, heavily doped region; 511, P-type heavily doped region; 512, N-type heavily doped region; 600, second epitaxial layer; 601, second P-type epitaxial layer; 602, second N-type epitaxial layer; 610, lightly doped region; 611, P-type lightly doped region; 612, N-type lightly doped region; 700, gate structure; 710, gate oxide layer; 720, gate material layer; 800, sidewall structure; 900, first mask layer; 910, second mask layer. DETAILED DESCRIPTION

[0018] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments. The details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention. The following embodiments and features therein may be combined with one another without conflict.

[0019] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. The drawings only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0020] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0021] See also Figures 1 to 18 As shown, the present invention provides a method for preparing a semiconductor structure, comprising the following steps: S1. Provide Figure 5The substrate 100 shown includes a substrate 110, a pad oxide layer 120, and at least one trench group. The trench group includes a first trench 130 and a second trench 140. The substrate 110 includes a well region 111 formed by doping impurities. The pad oxide layer 120 is formed on the surface of the substrate 110. The first trench 130 and the second trench 140 are disposed in the well region 111 of the substrate 110. The upper portions of the first trench 130 and the second trench 140 penetrate the pad oxide layer 120 to form an opening. The width W1 of the first trench 130 is smaller than the width W2 of the second trench 140. S2, such as Figure 7 As shown, a first barrier layer 200 is formed on both sidewalls of the first trench 130 and on both sidewalls of the second trench 140; S3, such as Figure 9 As shown, a second barrier layer 300 is formed on the sidewalls of the first barrier layer 200 in the first trench 130 and the second trench 140, respectively, and the second barrier layer 300 fills the first trench 130, and a groove 141 is formed between the second barrier layer 300 on both sides of the second trench 140; S4, such as Figure 11 As shown, an isolation layer 400 is formed in the groove 141; S5, such as Figures 12 to 15 As shown, the second barrier layer 300 is replaced by the first epitaxial layer 500 and the heavily doped region 510 arranged sequentially from bottom to top, and the first barrier layer 200 is replaced by the second epitaxial layer 600 and the lightly doped region 610 arranged sequentially from bottom to top; S6, such as Figure 18 As shown, a gate structure 700 is formed on the channel between the first trench 130 and the second trench 140 , and spacer structures 800 are formed on both sides of the gate structure 700 .

[0022] See also Figure 5 As shown, in step S1 of the present invention, substrate 110 can be any material suitable for forming a semiconductor structure, such as undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). The present invention does not limit the specific material and thickness of substrate 110, and substrate 110 can be a silicon substrate doped with impurities. Substrate 110 includes a well region 111 formed by doping with impurities. Well region 111 can be P-type doped or N-type doped. The impurity doping type can be flexibly set according to the semiconductor structure to be formed.

[0023] It should be noted that the base 100 can be a purchased semi-finished product or can be prepared by itself. In one embodiment, the base 100 is prepared by itself based on the substrate 110.

[0024] See also Figures 2 to 5 As shown, the preparation method of the substrate 100 is as follows: See also Figure 2 As shown, in one embodiment of the present invention, a pad oxide layer 120 is formed on the surface of the well region 111 of the substrate 110. The pad oxide layer 120 can serve as a protective layer for the substrate 110, and protect the substrate 110 covered by it in subsequent processes to prevent the substrate 110 from being damaged unnecessarily. Moreover, since the stress of the pad nitride layer 150 formed subsequently is relatively large, it is easy to cause dislocations on the surface of the substrate 110 when the pad nitride layer 150 is formed on the substrate 110. The pad oxide layer 120 can be used to provide a buffer when forming the pad nitride layer 150, to prevent the pad nitride layer 150 from causing dislocations on the substrate 110. In addition, the pad oxide layer 120 can also prevent the subsequent formation of an epitaxial layer on the surface of the substrate 110. The material of the pad oxide layer 120 can be a material such as silicon dioxide, and the pad oxide layer 120 can be formed using a deposition process, such as at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, and the like. The preparation process of the substrate 100 may further include cleaning the substrate 110 before forming the pad oxide layer 120 on the substrate 110. By cleaning the substrate 110, impurities on the surface of the substrate 110 can be removed, thereby preventing the impurities from affecting subsequent processes and ensuring the performance of the device. For example, the substrate 110 can be cleaned by cleaning with a cleaning solution or by purging the substrate 110 with a gas such as nitrogen.

[0025] See also Figure 2 As shown, in one embodiment of the present invention, after the pad oxide layer 120 is formed, a pad nitride layer 150 is formed on the pad oxide layer 120. The material of the pad nitride layer 150 can be silicon nitride or silicon oxynitride. In the present embodiment, the pad nitride layer 150 is, for example, silicon nitride. The pad nitride layer 150 can be prepared by any one of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition or high-density plasma chemical vapor deposition. For example, when the pad nitride layer 150 is prepared by a low-pressure chemical vapor deposition process, silicon nitride can be generated by reacting ammonia and dichlorosilane. By providing the pad nitride layer 150, it can be used as a mask in the subsequent formation process of the substrate 100 to protect the substrate 110 from damage when etching the substrate 110.

[0026] See also Figure 3 and Figure 4As shown, in one embodiment of the present invention, after forming the pad nitride layer 150, a photoresist is coated on the pad nitride layer 150 to form a photoresist layer 160. The type of photoresist material is not limited and can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, the coated photoresist is patterned by photolithography processes such as mask exposure and development to expose the first trench area 161 and the second trench area 162. Using the patterned photoresist layer 160 as a mask layer, the pad nitride layer 150, the pad oxide layer 120 and the well region 111 are sequentially etched to form the first trench 130 and the second trench 140. In this embodiment, the first trench 130 and the second trench 140 extend from the pad nitride layer 150 to the well region 111. The etching gas includes, for example, one or a mixture of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), or a combination thereof with oxygen (O2).

[0027] The first trench 130 and the second trench 140 have the same depth. For example, the depth of the first trench 130 and the second trench 140 is 150 to 300 nm, for example, 150 nm, 200 nm, 250 nm, or 300 nm, or any other value within the range. The width W1 of the first trench 130 is less than the width W2 of the second trench 140. For example, the width of the first trench 130 is greater than or equal to 160 nm, and the width of the second trench 140 is greater than or equal to 210 nm. In some embodiments of the present application, the aspect ratio of the first trench 130 is 1:1 to 2:1, for example, 1:1, 1.5:1, or 2:1, or any other value within the range. The aspect ratio of the second trench 140 is 3:4 to 3:2, for example, 3:4, 3:3, or 3:2, or any other value within the range.

[0028] See also Figure 5 As shown, in one embodiment of the present invention, after forming the first trench 130 and the second trench 140, the preparation of the substrate 100 further includes removing the photoresist layer 160 and the pad nitride layer 150. For example, the photoresist layer 160 can be removed by wet cleaning or ashing, and the pad nitride layer 150 can be removed by, for example, dry etching, wet etching, or a combination of dry etching and wet etching. In this embodiment, wet etching is used to remove the pad nitride layer 150.

[0029] See also Figure 6 and Figure 7As shown, in step S2 of the present invention, after removing the pad nitride layer 150, a first barrier is deposited in the first trench 130 and the second trench 140. The first barrier covers the substrate 100. The horizontal first barrier is removed, and a first barrier layer 200 is formed on both sidewalls of the first trench 130 and the second trench 140, respectively. The first barrier layer 200 is flush with the pad oxide layer 120. The first barrier can be deposited by any of low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), or high-density plasma chemical vapor deposition (HDPCD). In this embodiment, the first barrier is deposited by atmospheric pressure chemical vapor deposition (APCVD). Removal of the horizontal first barrier can be performed by, for example, dry etching, wet etching, or a combination of dry and wet etching. In this embodiment, dry etching is used, for example, to remove the horizontal first barrier. Materials for the first barrier include, for example, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbon nitride (SiCN).

[0030] See also Figure 8 and Figure 9As shown, in step S3 of the present invention, after forming the first barrier layer 200, a second barrier is deposited in the first trench 130 and the second trench 140. The second barrier covers the pad oxide layer 120, the first trench 130, the second trench 140, and the first barrier layer 200. The second barrier in the horizontal direction is removed, and a second barrier layer 300 is formed on the sidewalls of the first barrier layer 200 in the first trench 130 and the second trench 140, respectively. The second barrier layer 300 fills the first trench 130, and a groove 141 is formed between the second barrier layers 300 on both sides of the second trench 140. The second barrier layer 300 is flush with the pad oxide layer 120. The deposition method of the second barrier can be any one of low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, or high density plasma chemical vapor deposition. In this embodiment, the deposition method of the first barrier is atmospheric pressure chemical vapor deposition. When removing the second horizontal barrier, dry etching, wet etching, or a combination of dry and wet etching methods are used. In this embodiment, dry etching is used to remove the second horizontal barrier. The second barrier can be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbon nitride (SiCN). The second barrier is made of a different material than the first barrier. This allows the etchant to have a higher selectivity for the first barrier layer 200 and the second barrier layer 300 during the subsequent removal of the second barrier layer 300, thereby preventing damage to the first barrier layer 200 during the removal of the second barrier layer 300 and thus preventing subsequent processing from being affected. For example, the first barrier can be made of silicon nitride, while the second barrier can be made of silicon oxynitride or silicon carbon nitride. Alternatively, if the first barrier is made of silicon oxynitride, the second barrier can be made of silicon nitride or silicon carbon nitride. Alternatively, if the first barrier is made of silicon carbon nitride, the second barrier can be made of silicon nitride or silicon oxynitride.

[0031] See also Figure 10In step S4 of the present invention, after forming the second barrier layer 300 in the first trench 130 and the second trench 140, respectively, an insulating dielectric is deposited in the second trench 140. The insulating dielectric covers the pad oxide layer 120, the first barrier layer 200, the second barrier layer 300, and the recess 141. The present invention is not limited to the deposition method of the insulating dielectric. For example, it can be deposited by chemical vapor deposition (CVD) or high aspect ratio chemical vapor deposition (HARP CVD). In this embodiment, the isolation layer 400 is formed by depositing tetraethyl orthosilicate (TEOS). Specifically, TEOS and an oxygen-containing precursor, such as O2 or O3, are introduced, and the deposition time is controlled to obtain the isolation layer 400. Chemical vapor deposition is fast and can be deposited at low temperatures. The deposited isolation layer 400 has excellent hole-filling capability and is less likely to have voids or other problems. After the insulating medium is deposited, a high temperature annealing process may be performed to increase the density and stress of the isolation layer 400. In this embodiment, the insulating medium is, for example, silicon oxide (SiO x ). In other embodiments, the insulating medium may also be other insulating materials suitable for isolation. A wide range of options is available for controlling the isolation layer 400, the first barrier layer 200, and the second barrier layer 300, ensuring that the isolation layer 400 is not damaged during subsequent removal of the first barrier layer 200 and the second barrier layer 300, thereby avoiding impacting subsequent processes.

[0032] See also Figure 11As shown, after depositing the insulating dielectric, the dielectric is planarized, for example, using chemical mechanical polishing (CMP). The CMP removes a portion of the dielectric to form an isolation layer 400, which fills the recess 141. The present invention does not limit the insulating dielectric planarization to a specific location; it can be performed at any location based on semiconductor device design requirements, for example, until the insulating dielectric is flush with the first barrier layer 200 and the second barrier layer 300. For example, during the CMP process, endpoint detection (EPD) technology can accurately monitor the insulating dielectric removal status in real time. Based on the monitored data, it can accurately determine whether the dielectric has been polished to a predetermined position, thereby terminating the polishing process promptly and accurately. Due to the differences in the materials of the first barrier layer 200, the second barrier layer 300, and the insulating dielectric, their light reflection intensities vary. This difference in reflected light intensity between the first barrier layer 200, the second barrier layer 300, and the insulating dielectric can be exploited to accurately detect the polishing endpoint. During the grinding stage of the insulating medium, the intensity of the reflected light can remain relatively stable; however, when the grinding process advances to the point where the insulating medium is gradually removed and the first barrier layer 200 and the second barrier layer 300 are exposed, the intensity of the reflected light will show a significant change. This change can serve as a signal to terminate the grinding and stop the flattening process of the insulating medium.

[0033] The thickness of the isolation layer 400 is, for example, 150-300 nm, such as any value between 150 nm, 200 nm, 250 nm, or 300 nm. For example, when the node thickness is 90-65 nm, the thickness of the isolation layer 400 is 250 nm; when the node thickness is 40-28 nm, the thickness of the isolation layer 400 is 200 nm; and when the node thickness is 22 nm / 20 nm or below (particularly for fin field-effect transistors (FinFETs)), the isolation layer 400 is 150-200 nm or less.

[0034] See also Figure 12As shown, in step S5 of the present invention, in one embodiment of the present invention, the heavily doped region 510 has a doping type of P-type or N-type, and the lightly doped region 610 has the same doping type as the heavily doped region 510. In this embodiment, the number of trench groups is, for example, one. For example, the well region 111 has a doping type of P-type, and the heavily doped region 510 and the lightly doped region 610 have N-type doping. After forming the isolation layer 400, the second barrier layer 300 is removed. The present invention does not limit the method for removing the second barrier layer 300, and removal may be performed by, for example, dry etching, wet etching, or a combination of dry and wet etching. In this embodiment, wet etching is used to remove the second barrier layer 300. In this embodiment, the number of trench groups may also be multiple. When there are multiple trench groups, the heavily doped region 510 may all have a doping type of P-type or N-type, and the lightly doped region 610 may have the same doping type as the heavily doped region 510.

[0035] See also Figure 13 As shown, after removing the second barrier layer 300, a first epitaxial layer 500 is formed in the first trench 130 and the second trench 140. The first epitaxial layer 500 can be formed using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), or metal-organic chemical vapor deposition (MOCVD). The lattice orientation of the first epitaxial layer 500 is the same as that of the substrate 110, and the first epitaxial layer 500 and the well region 111 have the same doping type. For example, the substrate 110 is a P-type doped silicon substrate, and the first epitaxial layer 500 is also a P-type doped silicon material, with doping ions such as boron (B) or gallium (Ga). After forming the first epitaxial layer 500, heavily doped regions 510 are formed on the first epitaxial layer 500 to serve as the source and drain of the semiconductor structure. The heavily doped region 510 can be formed by molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), or metal-organic chemical vapor deposition (MOCVD). The heavily doped region 510 has an opposite doping type to the well region 111. For example, the heavily doped region 510 is N-type doped, and the doping ions are, for example, phosphorus (P) or arsenic (As). The ion concentration of the heavily doped region 510 is 1×10 20 ~5×10 20 cm -3 , for example 1×10 20 cm -3 , 3×10 20cm -3 or 5×10 20 cm -3 Equal 1×10 20 ~5×10 20 cm -3 After forming a first epitaxial layer 500 having the same doping type as the well region 111, a heavily doped region 510 having a doping type opposite to that of the well region 111 is formed on the first epitaxial layer 500. For example, the thickness of the first epitaxial layer 500 is 100-250 nm, for example, 100 nm, 200 nm, or 250 nm, and the thickness of the heavily doped region 510 is 50-200 nm, for example, 50 nm, 100 nm, or 200 nm, and the thickness of the heavily doped region 510 is 50-200 nm.

[0036] See also Figure 14 As shown, after forming the heavily doped region 510, the first barrier layer 200 is removed. The present invention does not limit the method for removing the first barrier layer 200, and removal can be performed by, for example, dry etching, wet etching, or a combination of dry etching and wet etching. In this embodiment, wet etching is used to remove the first barrier layer 200.

[0037] See also Figure 15As shown, after removing the first barrier layer 200, a second epitaxial layer 600 is formed in the first trench 130 and the second trench 140 at locations corresponding to the first barrier layer 200. The second epitaxial layer 600 can be formed using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), or metal-organic chemical vapor deposition (MOCVD). The lattice orientation of the second epitaxial layer 600 is the same as that of the substrate 110, and the second epitaxial layer 600 and the well region 111 have the same doping type. For example, the substrate 110 may be a P-type doped silicon substrate 110, and the second epitaxial layer 600 may also be a P-type doped silicon material, with doping ions such as boron (B) or gallium (Ga). After forming the second epitaxial layer 600 in the trenches, a lightly doped region 610 is formed on the second epitaxial layer 600. The lightly doped region 610 can be formed by molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), or metal-organic chemical vapor deposition (MOCVD). The doping type of the lightly doped region 610 is opposite to the doping type of the well region 111. The lightly doped region 610 is, for example, N-type doped, and the doping ions are, for example, phosphorus (P) or arsenic (As). The ion concentration of the lightly doped region 610 is 1×10 17 ~5×10 17 cm -3 , for example 1×10 17 cm -3 , 3×10 17 cm -3 or 5×10 17 cm -3 Equal 1×10 17 ~5×10 17 cm -3After forming a second epitaxial layer 600 having the same doping type as the well region 111, a lightly doped region 610 having the opposite doping type to the well region 111 is formed on the second epitaxial layer 600. For example, the thickness of the second epitaxial layer 600 is 50 to 280 nm, for example, 50 nm, 100 nm, 200 nm, or 280 nm, and the thickness of the lightly doped region 610 is 20 to 100 nm, for example, 20 nm, 50 nm, 80 nm, or 100 nm, and the interface between the lightly doped region 610 and the second epitaxial layer 600 is higher than the interface between the heavily doped region 510 and the first epitaxial layer 500, that is, the thickness of the lightly doped region 610 is less than the thickness of the heavily doped region 510. The present invention does not require additional masking and implantation processes when forming the heavily doped region 510 and the lightly doped region 610, thereby shortening the process cycle and reducing manufacturing costs.

[0038] In semiconductor structures, the doping concentration is inversely proportional to the carrier diffusion depth. The lightly doped region 610 has a lower impurity concentration, meaning carriers need a shorter distance to recombine with majority carriers to achieve electrical neutrality. Furthermore, the depletion region more easily penetrates the entire lightly doped layer, effectively controlling the channel. The heavily doped region 510, on the other hand, has a higher ion concentration and requires a thicker layer to accommodate more carriers and reduce series resistance, while also preventing excessive diffusion from damaging the device structure. Therefore, reducing the thickness of the lightly doped region 610 can enhance the gate's control over the channel (e.g., suppressing short-channel effects), while increasing the thickness of the heavily doped region 510 can provide lower contact resistance and mechanical stability. In traditional metal oxide semiconductor (MOS) fabrication, channel dopant ions in the lightly doped region are uniformly implanted into the channel, source, and drain regions. However, channel doping in the source and drain regions is ineffective and, instead, increases the impurity ion concentration in the source and drain regions, exacerbating GIDL leakage. On the other hand, the doping type of the lightly doped region is opposite to the channel doping. In order to offset the channel doping previously performed in the source and drain regions, it is necessary to increase the concentration of the lightly doped region, that is, to increase the impurity ion concentration in the source and drain regions, which will also aggravate GIDL leakage. The present application forms the heavily doped region 510 and the lightly doped region 610 by epitaxial doping. The ion concentration of the heavily doped region 510 and the lightly doped region 610 is not affected by the doping concentration of the channel region, which can reduce the channel doping concentration in the source and drain regions, thereby reducing the ion concentration in the subsequently formed lightly doped region 610, which can reduce the gate-induced drain leakage current.

[0039] See also Figure 16As shown, in one embodiment of the present application, after forming the lightly doped region 610, the method for preparing the semiconductor structure further includes removing the pad oxide layer 120. For example, the pad oxide layer 120 is removed by wet etching, and the wet etching solution is, for example, hydrofluoric acid or a buffered oxide etchant.

[0040] See also Figure 17 As shown, after the pad oxide layer 120 is removed, an oxide layer 170 is formed on the surface of the substrate 110. In this embodiment, taking a medium-voltage device as an example, the oxide layer 170 is formed by, for example, a dry oxygen oxidation method. For example, the substrate 100 is placed in a furnace tube, oxygen is introduced, and the exposed surface of the substrate 110 reacts with the oxygen at a high temperature to form the oxide layer 170. In this embodiment, the temperature of the thermal oxidation treatment is 1000-1200°C, for example, it can be any value within the range of 1000-1200°C, such as 1000°C, 1100°C, or 1200°C. The time of the thermal oxidation treatment is 40-80 seconds, for example, any value within the range of 40 seconds, 60 seconds, or 80 seconds. For example, the thickness of the oxide layer 170 is 20-30 Å, for example, any value within the range of 20-30 Å, such as 20 Å, 25 Å, or 30 Å. In other embodiments, wet oxygen oxidation may be used to oxidize the exposed surface of the substrate 110 using H 2 and O 2 at a preset temperature.

[0041] See also Figure 18 As shown, in step S6 of the present application, after the oxide layer 170 is formed on the surface of the substrate 110, a gate structure 700 is formed on the substrate 110. Specifically, a gate oxide layer 710 is first formed on the surface of the substrate 110, and then a gate material layer 720 is formed on the surface of the gate oxide layer 710. In this embodiment, the material of the gate oxide layer 710 is, for example, a silicon oxide material. The gate oxide layer 710 can be formed by, for example, thermal oxidation, chemical vapor deposition, or physical vapor deposition. The gate material layer 720 is, for example, a polysilicon layer, and the polysilicon layer can be P-type doped or N-type doped to ensure that the doping type of the polysilicon layer is different from the doping type of the well region 111 to improve the performance of the semiconductor device. In other embodiments, the material and thickness of the gate material layer 720 can be set according to actual needs. Then, the gate material layer 720 and the gate oxide layer 710 are etched by, for example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process to form the gate structure 700. In other embodiments, the gate material layer 720 may also be, for example, a metal gate layer.

[0042] See also Figure 18As shown, in one embodiment of the present invention, after forming the gate structure 700, sidewall structures 800 are formed on both sides of the gate structure 700. Specifically, a dielectric layer (not shown) is formed on the gate structure 700 and the substrate 110, and the dielectric layer includes, for example, a silicon oxide layer. The dielectric layer is formed, for example, by high-temperature thermal oxidation, such as dry thermal oxidation, wet thermal oxidation, or in-situ steam generation (ISSG). The dielectric layer is then nitrided, for example, by one or a combination of decoupled plasma nitridation (DPN), rapid thermal nitridation (RTN), or ammonia immersion, to form a nitride layer on the surface of the dielectric layer, thereby improving the stability of the sidewall structure 800. By using wet etching, dry etching, or a combination of wet and dry etching, the dielectric layer on both sides of the gate structure 700 is retained, thereby forming a single-layer or multi-layer spacer structure 800 on both sides of the gate, effectively controlling the influence of parasitic capacitance and improving semiconductor device performance. In this embodiment, the spacer structure 800 is multi-layered.

[0043] See also Figure 18 As shown, in some embodiments, after the spacer structure 800 is formed, the back-end-of-line (BEOL) process of integrated circuit manufacturing is performed, and an interlayer dielectric layer is covered on the surface of the substrate 100 through a metal interconnection process (for example, including at least one of a contact hole process, a damascene process, and a pad process), and a contact plug electrically contacting the electrostatic protection structure and a multi-layer metal interconnection line electrically connected to the contact plug are formed in the interlayer dielectric layer.

[0044] See also Figures 19 to 23As shown, in another embodiment of the present application, the substrate 100 includes multiple trench groups, the heavily doped regions 510 in the multiple trench groups include a P-type heavily doped region 511 and an N-type heavily doped region 512, and the lightly doped regions 610 in the multiple trench groups include a P-type lightly doped region 611 and an N-type lightly doped region 612. For example, the well region 111 includes a P-type well region 1111 and an N-type well region 1112, with an isolation structure 180 disposed between the P-type well region 1111 and the N-type well region 1112. The N-type heavily doped region 512 and the N-type lightly doped region 612 are formed in the trench group of the P-type well region 1111, and the P-type heavily doped region 511 and the P-type lightly doped region 611 are formed in the trench group of the N-type well region 1112. The doping type of the first epitaxial layer 500 and the second epitaxial layer 600 is the same as the doping type of the well region 111, that is, the doping type of the first epitaxial layer 500 includes N-type doping and P-type doping, and the doping type of the second epitaxial layer 600 includes N-type doping and P-type doping. When the well region 111 is an N-type well region 1112, the doping type of the first epitaxial layer 500 and the second epitaxial layer 600 is N-type doping, and the doping type of the heavily doped region 510 and the lightly doped region 610 is P-type. When the well region 111 is a P-type well region 1111, the doping type of the first epitaxial layer 500 and the second epitaxial layer 600 is P-type doping, and the doping type of the heavily doped region 510 and the lightly doped region 610 is N-type. In this embodiment, the difference between the preparation method of the semiconductor structure and the case where the doping type of the heavily doped region 510 and the lightly doped region 610 is either N-type doping or P-type doping is that Figures 11 to 15 .

[0045] See also Figures 20 to 23 As shown, in some other embodiments of the present application, the second barrier layer 300 is replaced by the first epitaxial layer 500 and the heavily doped region 510 sequentially arranged from bottom to top, and the first barrier layer 200 is replaced by the second epitaxial layer 600 and the lightly doped region 610 sequentially arranged from bottom to top, including the following steps: Figure 20 As shown, a first mask layer 900 is provided on the substrate 100, and the first mask layer 900 exposes the trench groups corresponding to the P-type heavily doped region 511 and the P-type lightly doped region 611. Figure 21As shown, the second barrier layer 300 in the trench group corresponding to the P-type heavily doped region 511 and the P-type lightly doped region 611 is removed, and the first N-type epitaxial layer 502 and the P-type heavily doped region 511 are sequentially generated at the corresponding positions of the second barrier layer 300. The first barrier layer 200 in the trench group corresponding to the P-type heavily doped region 511 and the P-type lightly doped region 611 is removed, and the second N-type epitaxial layer 602 and the P-type lightly doped region 611 are sequentially generated at the corresponding positions of the first barrier layer 200. For example, a patterned photoresist is used as the first mask layer 900. The type of photoresist material is not limited and can be a positive photoresist material or a negative photoresist material. The first mask layer 900 is, for example, a positive photoresist material. The method for removing the first barrier layer 200 and the second barrier layer 300 is the same as the method for removing the first barrier layer 200 when the substrate 100 includes a group of trench groups, and will not be repeated here.

[0046] See also Figure 22 As shown, after forming the P-type heavily doped region 511 and the P-type lightly doped region 611, the first mask layer 900 is removed and a second mask layer 910 is provided on the substrate 100. The second mask layer 910 exposes the trench groups corresponding to the N-type heavily doped region 512 and the N-type lightly doped region 612. Figure 23 As shown, the second barrier layer 300 in the groove group corresponding to the N-type heavily doped region 512 and the N-type lightly doped region 612 is removed, and the first P-type epitaxial layer 501 and the N-type heavily doped region 512 are sequentially generated at the corresponding positions of the second barrier layer 300. The first barrier layer 200 in the groove group corresponding to the N-type heavily doped region 512 and the N-type lightly doped region 612 is removed, and the second P-type epitaxial layer 601 and the N-type lightly doped region 612 are sequentially generated at the corresponding positions of the first barrier layer 200. The removal method of the first barrier layer 200 and the second barrier layer 300 is the same as the removal method when the substrate 100 includes a group of groove groups, and will not be repeated here. For example, a patterned photoresist is used as the second mask layer 910. The type of photoresist material is not limited, and can be a positive photoresist material or a negative photoresist material. The second mask layer 910 is, for example, a negative photoresist material. Second mask layer 910 and first mask layer 900 are made of materials with opposite photoresist properties. The same set of masks can be used to pattern second mask layer 910 and second mask layer 910, reducing mask preparation and simplifying the process. After the second P-type epitaxial layer 601 and the N-type lightly doped region 612 are formed, the second mask layer 910 is removed.

[0047] The substrate 100 includes a plurality of trench groups. The heavily doped regions 510 of the plurality of trench groups include a P-type heavily doped region 511 and a P-type heavily doped region 511. The lightly doped regions 610 of the plurality of trench groups include a P-type lightly doped region 611 and an N-type lightly doped region 612. When forming the P-type heavily doped region 511, the P-type heavily doped region 511, the N-type lightly doped region 612, and the N-type lightly doped region 612, only one set of photomasks is required to complete the arrangement of the first mask layer 900 and the second mask layer 910. No implantation process is required, which can significantly reduce the process cycle and manufacturing costs. The present invention does not limit the order of forming the N-type doped region and the P-type doped region. In other embodiments, the N-type heavily doped region 512 and the N-type lightly doped region 612 may be formed first, followed by the P-type heavily doped region 511 and the P-type lightly doped region 611.

[0048] In summary, the present invention provides a method for fabricating a semiconductor structure, comprising forming a first barrier layer and a second barrier layer within a first trench, forming a first barrier layer, a second barrier layer, and an isolation layer within a second trench, replacing the second barrier layer with a first epitaxial layer and a heavily doped region sequentially arranged from bottom to top, replacing the first barrier layer with a second epitaxial layer and a lightly doped region sequentially arranged from bottom to top, forming a gate structure on the channel between the first trench and the second trench, and forming sidewalls on both sides of the gate structure. The present invention has the unexpected effect of forming an isolation layer within the second trench without the need for a separate mask, and without the need for additional masks and implantation processes when forming the source, drain, and lightly doped region, thereby simplifying the fabrication process, improving production efficiency, and reducing fabrication costs.

[0049] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate, the substrate comprising a substrate, a pad oxide layer, and at least one trench group, the trench group comprising a first trench and a second trench, the pad oxide layer being formed on a surface of the substrate, the first trench and the second trench being disposed in the substrate, and having an upper portion penetrating the pad oxide layer to form an opening, and the width of the first trench being smaller than the width of the second trench; forming a first barrier layer on both sidewalls of the first trench and on both sidewalls of the second trench respectively; forming a second barrier layer on the sidewalls of the first barrier layer in the first trench and the second trench respectively, and making the second barrier layer fill the first trench; forming an isolation layer between the second barrier layer on both sides of the second trench; Replacing the second barrier layer with the first epitaxial layer and the heavily doped region sequentially arranged from bottom to top, and replacing the first barrier layer with the second epitaxial layer and the lightly doped region sequentially arranged from bottom to top; A gate structure is formed on the channel between the first trench and the second trench, and sidewall structures are formed on both sides of the gate structure.

2. The preparation method according to claim 1, characterized in that The substrate includes a plurality of trench groups, the heavily doped regions of the plurality of trench groups include a P-type heavily doped region and an N-type heavily doped region, and the lightly doped regions of the plurality of trench groups include a P-type lightly doped region and an N-type lightly doped region. Replacing the second barrier layer with a first epitaxial layer and a heavily doped region sequentially arranged from bottom to top, and replacing the first barrier layer with a second epitaxial layer and a lightly doped region sequentially arranged from bottom to top, comprises the following steps: Providing a first mask layer on the substrate, the first mask layer exposing the trench group corresponding to the P-type heavily doped region and the P-type lightly doped region, removing the second barrier layer in the trench group corresponding to the P-type heavily doped region and the P-type lightly doped region, and sequentially growing a first N-type epitaxial layer and a P-type heavily doped region at corresponding positions of the second barrier layer; removing the first barrier layer in the trench group corresponding to the P-type heavily doped region and the P-type lightly doped region, and sequentially growing a second N-type epitaxial layer and a P-type lightly doped region at positions corresponding to the first barrier layer; Providing a second mask layer on the substrate, the second mask layer exposing the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region, removing the second barrier layer in the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region, and sequentially growing a first P-type epitaxial layer and an N-type heavily doped region at corresponding positions of the second barrier layer; The first barrier layer in the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region is removed, and a second P-type epitaxial layer and an N-type lightly doped region are sequentially generated at corresponding positions of the first barrier layer.

3. The preparation method according to claim 1, characterized in that Forming a first barrier layer on both sidewalls of the first trench and on both sidewalls of the second trench respectively includes the following steps: depositing a first barrier in the first trench and the second trench, wherein the first barrier covers the substrate; The first barrier in the horizontal direction is removed, and the first barrier layer is formed on both sidewalls of the first trench and on both sidewalls of the second trench, respectively.

4. The preparation method according to claim 1, characterized in that Forming a second barrier layer on the sidewalls of the first barrier layer in the first trench and the second trench respectively, and filling the first trench with the second barrier layer, comprises the following steps: Depositing a second barrier in the first trench and the second trench, wherein the second barrier covers the pad oxide layer, the first trench, the second trench, and the first barrier layer; The second barrier in the horizontal direction is removed, and a second barrier layer is formed on the sidewalls of the first barrier layer in the first trench and in the second trench respectively.

5. The preparation method according to claim 1, characterized in that The depth of the first trench and the second trench is 150-330 nm.

6. The preparation method according to claim 1, characterized in that The thickness of the lightly doped region is 20-100 nm, and the thickness of the heavily doped region is 50-220 nm.

7. The preparation method according to claim 1, characterized in that The ion concentration of the heavily doped region is 1×10 20 ~5×10 20 cm -3 The ion concentration of the lightly doped region is 1×10 17 ~5×10 17 cm -3 .

8. The preparation method according to claim 1, characterized in that After removing the first barrier layer and sequentially forming a second epitaxial layer and a lightly doped region at corresponding positions of the first barrier layer, the preparation method further includes removing the pad oxide layer and performing thermal oxidation treatment on the surface of the substrate to form an oxide layer on the surface of the substrate.

9. The preparation method according to claim 8, characterized in that The temperature of the thermal oxidation treatment is 1000-1200° C., the time of the thermal oxidation treatment is 40-80 seconds, and the thickness of the oxide layer is 20-30 Å.

10. The preparation method according to claim 1, characterized in that Replacing the second barrier layer with a first epitaxial layer and a heavily doped region sequentially arranged from bottom to top, and replacing the first barrier layer with a second epitaxial layer and a lightly doped region sequentially arranged from bottom to top, comprising the following steps: removing the second barrier layer, and sequentially forming the first epitaxial layer and the heavily doped region at corresponding positions of the second barrier layer; removing the first barrier layer, and sequentially forming the second epitaxial layer and the lightly doped region at corresponding positions of the first barrier layer; The first barrier layer and the second barrier layer are removed by wet etching, and the wet etching has different selectivity ratios for the first barrier layer, the second barrier layer, and the isolation layer.

Images