Electrical parameter prediction method and device based on SiC wafer defect distribution

Abstract

The invention relates to an electrical parameter prediction method and device based on SiC wafer defect distribution, and the method comprises the steps: obtaining defect parameters of each test structure in a training wafer, and obtaining the electrical parameters of the test structures through the electrical test of the training wafer after tape-out; constructing a data set through defect parameter distribution and electrical parameters, and training the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model; obtaining instance defect parameters and a design layout of a to-be-evaluated wafer, inputting the instance defect parameters and the design layout into the wafer defect prediction model to obtain electrical parameters of each design test structure in the to-be-evaluated wafer, the training wafer and the to-be-evaluated wafer being SiC wafers, and the to-be-evaluated wafer being SiC wafers. The problems that in the prior art, the accuracy rate and the overall efficiency are low when the quality of the SiC wafer is judged manually depending on experience are solved, the grade of the wafer can be screened at the early stage of wafer manufacturing, and the SiC device suitable for manufacturing the wafer is given based on the evaluation index.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device quality inspection, and in particular to a method and device for predicting electrical parameters based on SiC wafer defect distribution. Background Art

[0002] Wafers, such as SiC wafers, are the core substrate in semiconductor manufacturing and the physical carrier of integrated circuits (ICs). Due to the high temperature of the growth environment used to prepare SiC wafers, the complex composition of the epitaxial growth, and the high stress environment during wafer polishing, SiC wafers can develop defects. The defect density of SiC wafers is typically 1-2 orders of magnitude higher than that of silicon wafers. The number and type of defects can seriously affect the performance of SiC devices. For example, basal plane dislocations (BPDs) and carrot defects affect the quality of the oxide layer of metal-oxide semiconductor field-effect transistors (MOSFETs), leading to increased interface state density, threshold voltage drift, increased leakage current, and reduced oxide layer life. The performance of SiC devices is closely related to their application areas. For example, high-voltage applications have higher requirements for SiC device withstand voltage performance, while low-voltage applications have higher requirements for SiC device on-resistance.

[0003] Currently, in traditional technologies, the accuracy and overall efficiency of manually judging the quality of SiC wafers with high defect density and their suitability for manufacturing SiC devices based on experience are low. Summary of the Invention

[0004] Based on this, it is necessary to provide a method, device and computer equipment that can efficiently and accurately judge the quality of SiC wafers and predict their electrical parameters based on defect distribution to address the above technical problems.

[0005] In a first aspect, the present application provides an electrical parameter prediction method based on SiC wafer defect distribution, the method comprising: obtaining defect parameters of each test structure in a training wafer based on a preset test layout; performing electrical testing on each of the test structures to obtain electrical parameters of each test structure; the test structure is obtained by tape-out of the wafer based on the preset test layout; constructing a data set through the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure, and training an initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model; obtaining instance defect parameters and a design layout of a wafer to be evaluated, and inputting the instance defect parameters and the design layout into the wafer defect prediction model to obtain electrical parameters of each designed test structure in the wafer to be evaluated; the training wafer and the wafer to be evaluated are SiC wafers.

[0006] In one embodiment, obtaining the defect parameters of each test structure in the training wafer based on a preset test layout includes: obtaining an optical microscope image and the photoluminescence spectrum based on a semiconductor defect detection device, performing defect detection on the training wafer, and obtaining the defect parameters of the training wafer; determining the defect parameters of each test structure based on the preset test layout and the defect parameters of the training wafer; and multiple test structures are designed in the preset test layout.

[0007] In one embodiment, the defect parameters include: black dot defects (PL_Black), surface contaminant particles (Particle), surface depressions (Pit) caused by chemical mechanical polishing over-etching, surface bump defects (Bump), scratch defects (ScratchTrace), pitting white etching defects (PL_White), micropipes, basal plane dislocations (BPD), stacking faults (Stacking Fault), extended stacking faults (PropagatedSF), carrot defects (Carrot), dark field defects (DF), a complex of DF defect and triangular structure (DF_Triangle), photoluminescent stacking faults (PL_SF), and triangular defects (Triangle) formed by metal impurity segregation.

[0008] In one embodiment, performing electrical testing on each of the test structures to obtain electrical parameters of each test structure includes: performing a capacitance-voltage test on each of the test structures to obtain a first electrical parameter; and performing an oxide layer leakage test on each of the test structures to obtain a second electrical parameter.

[0009] In one embodiment, the performing of a capacitance-voltage test on each of the test structures to obtain a first electrical parameter includes: performing a capacitance-voltage test on each target test structure to obtain oxide layer capacitance, low-frequency capacitance, high-frequency capacitance, total charge in the oxide layer, and interface state charge; the target test structure is any one of the multiple test structures; and determining the interface state density D according to the oxide layer capacitance, low-frequency capacitance, and high-frequency capacitance. it (Interface Trap Density); Determine the flat band voltage V according to the total charge in the oxide layer, the interface state charge, and the oxide layer capacitance FB (FlatBand Voltage); Determine the oxide layer thickness T based on the oxide layer capacitance and the capacitor plate area ox (Oxide Thickness); using the interface state density, flat band voltage and oxide layer thickness as the first electrical parameter.

[0010] In one embodiment, the oxide layer leakage test is performed on each test structure to obtain the second electrical parameter, which includes: performing an oxide layer leakage test on each target test structure to obtain an oxide layer breakdown voltage and a tunneling voltage; determining an oxide layer breakdown electric field E according to the oxide layer breakdown voltage and the oxide layer thickness. BD (Oxide Breakdown Electric Field); according to the tunneling voltage E FN (Fowler-Nordheim Tunneling Electric Field) and the thickness of the oxide layer are used to determine the tunneling electric field; the oxide layer breakdown electric field and the tunneling electric field are used as the second electrical parameter.

[0011] In one embodiment, the method further includes: performing anomaly detection on the electrical parameters of each test structure to determine an outlier; if the outlier corresponds to an interface state density, calculating the median of all the interface state densities except the outlier, and replacing the outlier with the median; if the outlier corresponds to a flat band voltage, calculating the median of all the flat band voltages except the outlier, and replacing the outlier with the median; if the outlier corresponds to an oxide layer thickness, calculating the average value of all the oxide layer thicknesses except the outlier, and replacing the outlier with the average value; if the outlier corresponds to a tunneling electric field, replacing the outlier with a first preset parameter value; if the outlier corresponds to an oxide layer breakdown electric field, replacing the outlier with a second preset parameter value.

[0012] In one embodiment, the method comprises constructing a data set based on the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and training the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model, including: constructing a first characteristic matrix corresponding to each test structure according to the defect parameters of each test structure; the first characteristic matrix is ​​a 15-dimensional characteristic matrix about the defect parameters; constructing a second characteristic matrix corresponding to each test structure according to the electrical parameters of each test structure; the second characteristic matrix is ​​a 5-dimensional characteristic matrix about the electrical parameters; constructing a data set based on the first characteristic matrix corresponding to each test structure, the second characteristic matrix corresponding to each test structure, and the preset test layout; training the initial wafer defect prediction model based on the data set, adjusting the model parameters of the initial wafer defect prediction model by the mean square error and the mean absolute error, and obtaining an iteratively optimized wafer defect prediction model;

[0013] The initial wafer defect prediction model is a 5-layer fully connected network built using a fully connected deep neural network (DNN). The ReLU activation function and Dropout regularization technology are used to linearly activate the output layer to achieve multi-target regression.

[0014] In a second aspect, the present application further provides an electrical parameter prediction device based on SiC wafer defect distribution, the electrical parameter prediction device of the SiC wafer comprising:

[0015] An acquisition module, configured to acquire defect parameters of each test structure in a training wafer based on a preset test layout;

[0016] A testing module, configured to perform electrical testing on each of the test structures to obtain electrical parameters of each test structure; the test structures are obtained by tape-out of the wafer based on the preset test layout;

[0017] A training module is used to construct a data set based on the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and to train the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model;

[0018] The verification module is used to obtain instance defect parameters and a design layout of a wafer to be evaluated, and input the instance defect parameters and the design layout into a wafer defect prediction model to obtain electrical parameters of each designed test structure in the wafer to be evaluated; the training wafer and the wafer to be evaluated are SiC wafers.

[0019] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements any one of the methods in the first aspect when executing the computer program.

[0020] The above-mentioned electrical parameter prediction method and device based on SiC wafer defect distribution obtains the defect parameters of each test structure in the training wafer, performs electrical testing on each test structure, obtains the electrical parameters of each test structure, and constructs a data set based on the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure. The initial wafer defect prediction model is trained to obtain an iteratively optimized wafer defect prediction model. The wafer defect prediction model can predict the electrical parameters of each designed test structure in the wafer to be evaluated based on the instance defect parameters and design layout of the wafer to be evaluated, thereby solving the problem of low accuracy and overall efficiency of manual judgment of SiC wafer quality based on experience in traditional technologies. It can also screen the grade of wafers in the early stage of wafer manufacturing and provide SiC devices suitable for the wafer to be evaluated based on evaluation indicators. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 FIG. 1 is an application environment diagram of an electrical parameter prediction method based on SiC wafer defect distribution in one embodiment;

[0022] Figure 2 1 is a flow chart of a method for predicting electrical parameters based on SiC wafer defect distribution in one embodiment;

[0023] Figure 3 Schematic diagram of an optical microscope image (OM) and a photoluminescence spectrum (PL) of surface contaminant particles and carrot defects in one embodiment;

[0024] Figure 4 Schematic diagram of a process for fabricating a test structure of a SiC wafer and a method for predicting its electrical parameters in one embodiment;

[0025] Figure 5 is a schematic diagram of a preset test layout in one embodiment;

[0026] Figure 6 A schematic diagram of extracting defect distribution for each field on a wafer according to a preset test pattern in one embodiment;

[0027] Figure 7 D is the capacitance of SiC wafer oxide layer in one embodiment. it Schematic diagram of interface state distribution results;

[0028] Figure 8 The surface particle partial defect and interface state D in one embodiment it , the relationship between photoluminescent stacking fault PL_SF and interface state D it Schematic diagram of the comparison between the actual value and the predicted value;

[0029] Figure 9 1 is a structural block diagram of an electrical parameter prediction device based on SiC wafer defect distribution in one embodiment;

[0030] Figure 10 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0032] The electrical parameter prediction method based on SiC wafer defect distribution provided in the embodiment of the present application can be applied to Figure 1In the application environment shown. The terminal 102 communicates with the server 104 via a network. The data storage system can store data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other network servers. The server 104 is used to execute the electrical parameter prediction method of the SiC wafer. The terminal 102 can be, but is not limited to, various personal computers, laptops, smart phones, tablets, Internet of Things devices and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The server 104 can be implemented as an independent server or a server cluster consisting of multiple servers.

[0033] In order to solve the above problem, in one embodiment of the present application, Figure 2 As shown, a method for predicting electrical parameters based on SiC wafer defect distribution is provided, comprising the following steps:

[0034] Step 201: Based on a preset test layout, obtain defect parameters of each test structure in a training wafer.

[0035] Among them, the preset test layout is a preset layout for dividing the wafer, which includes the position and range of each test structure of the wafer. After obtaining the defect parameters of the entire wafer, the defect parameters of the entire wafer can be classified according to the preset test layout, thereby obtaining the defect parameters of each test structure in the wafer. In this embodiment, the test structure is a capacitor structure with different areas, and the defect parameters refer to the type, quantity and area of ​​physical, chemical or structural anomalies existing on the surface or inside of the wafer (silicon wafer, silicon carbide wafer or other semiconductor material substrate) during the semiconductor manufacturing process, including but not limited to: black dot defects, surface contaminant particles, surface depressions formed by chemical mechanical polishing over-corrosion, surface protrusion defects, scratch defects, point-shaped white etching defects, micropipes, basal plane dislocations, stacking faults, extended stacking faults, carrot defects, dark field defects, complexes of dark field defects and triangular structures, photoluminescent stacking faults, and triangular defects formed by metal impurity segregation. For example, Figure 3 Schematic diagram of surface contaminant particles and carrot defects under optical microscopy (OM) and photoluminescence spectroscopy (PL) respectively. The boxes in the figure indicate the calculated defect area, unit (μm 2 ).

[0036] Step 202: Perform electrical testing on each test structure to obtain electrical parameters of each test structure.

[0037] That is, each test structure is tested for capacitance-voltage to obtain the first electrical parameter of each test structure, and each test structure is tested for oxide layer leakage to obtain the second electrical parameter of each test structure. Wherein, the test structure is obtained by tape-out of the wafer based on the preset test layout. For example, the preset test layout is as follows Figure 5 As shown, this includes the locations of 70 test structures on the wafer.

[0038] Specifically, in other embodiments of the present application, the electrical testing of each test structure to obtain the electrical parameters of each test structure includes: performing a capacitance-voltage test on each test structure to obtain a first electrical parameter; and performing an oxide layer leakage test on each test structure to obtain a second electrical parameter.

[0039] Step 203: constructing a data set through the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure, and training the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model.

[0040] Specifically, based on the preset test layout, the correspondence between the defect parameters of each test structure and the electrical parameters of each test structure is determined, thereby constructing a data set. This data set is used to train the initial wafer defect prediction model. The initial wafer defect prediction model is trained using the data set, resulting in an iteratively optimized wafer defect prediction model. The wafer defect prediction model is used to predict the electrical parameters of the test structure based on its defect parameters.

[0041] It should be noted that the only factor affecting the electrical parameters of the test structure is the defect parameters of the test structure, and the area of ​​the test structure does not affect the electrical parameters of the test structure. The initial wafer defect prediction model is a preset deep learning model or other artificial intelligence model.

[0042] Step 204: Obtain instance defect parameters and a design layout of the wafer to be evaluated, and input the instance defect parameters and the design layout into a wafer defect prediction model to obtain electrical parameters of each designed test structure in the wafer to be evaluated.

[0043] The instance defect parameters are the defect parameters of the entire wafer to be evaluated. The wafer defect prediction model will classify the instance defect parameters according to the design layout, thereby obtaining the defect parameters of each design test structure of the wafer to be evaluated, and predicting the electrical parameters of each design test structure of the wafer to be evaluated based on the defect parameters of each design test structure of the wafer to be evaluated. It should be noted that the electrical parameters of each design test structure in the wafer to be evaluated are the predicted values ​​of the electrical parameters of each design test structure of the wafer to be evaluated obtained by the wafer defect prediction model based on the instance defect parameters of the wafer to be evaluated and the design layout, and are not the actual values. The training wafer and the wafer to be evaluated are SiC wafers.

[0044] For example, Figure 8 As shown, the interface state density (D it ) and predicted values. Different symbols represent different wafers. As the number of surface contaminant particles (Particles) and photoluminescent stacking faults (PL_SFs) increases, the interface state density also increases. This shows a good fit between the predicted model and the true values. Wafers with high interface state density are not suitable for low-voltage, low-resistance SiC device manufacturing.

[0045] In another embodiment of the present application, after obtaining the instance defect parameters and design layout of the wafer to be evaluated, and inputting the instance defect parameters and design layout into the wafer defect prediction model to obtain the electrical parameters of each designed test structure in the wafer to be evaluated, it also includes: obtaining the real electrical parameters of each designed test structure in the wafer to be evaluated, and re-training the wafer defect prediction model based on the real electrical parameters and the electrical parameters of each designed test structure in the wafer to be evaluated.

[0046] It should be noted that, in this embodiment, the wafer is a SiC wafer, and the methods for preparing the test structure include but are not limited to thermal oxidation, TEOS deposition, wet oxidation and ALD atomic deposition.

[0047] In the above-mentioned electrical parameter prediction method based on SiC wafer defect distribution, the defect parameters of each test structure in the training wafer are obtained, and each test structure is electrically tested to obtain the electrical parameters of each test structure. A data set is constructed based on the defect parameters of each test structure, the preset test layout and the electrical parameters of each test structure, and the initial wafer defect prediction model is trained to obtain an iteratively optimized wafer defect prediction model. The wafer defect prediction model can be used to predict the electrical parameters of each designed test structure in the wafer to be evaluated based on the instance defect parameters and design layout of the wafer to be evaluated, so as to solve the problem of low accuracy and overall efficiency of manually judging the quality of wafers based on experience in traditional technologies, thereby efficiently and accurately judging the quality of wafers.

[0048] This electrical parameter prediction method based on SiC wafer defect distribution can be used to analyze the impact of wafer defect distribution on oxide layer quality and device reliability. Deep learning is used to establish a correlation between wafer defect distribution and oxide layer electrical parameters. Based on the predictions, the wafer's suitability for device manufacturing and application areas can be determined, improving SiC MOSFET device performance, yield, and reliability.

[0049] In other embodiments of the present application, obtaining defect parameters of each test structure in the training wafer based on a preset test layout includes:

[0050] Step 1: Obtain photoluminescence spectra and optical microscope images of the training wafer using semiconductor defect inspection equipment.

[0051] The photoluminescence spectrum is the spectrum produced by electrons in a training wafer after they transition from the valence band to the conduction band under light stimulation. This spectrum contains information about the material's structure, composition, and the atomic arrangement of its surroundings. Different crystal defects have different luminescence peaks at different wavelengths, and the locations of these characteristic peaks and optical microscopy images can be used to assist in determining the defect parameters of the training wafer.

[0052] Step 2: Based on the optical microscope and photoluminescence spectrum obtained by the semiconductor defect detection equipment, defect detection is performed on the training wafer to obtain the defect parameters of the training wafer.

[0053] Semiconductor defect detection equipment, such as a SiC wafer analyzer, is used to detect wafer defect parameters. For example, a SiC wafer analyzer is used to calibrate wafer defect parameters using optical microscope images and photoluminescence spectra. Defect parameters include defect type, number of defects, and defect area.

[0054] Step 3: Determine the defect parameters of each test structure based on the preset test layout and the defect parameters of the training wafer.

[0055] That is, according to a preset test layout, the position or coordinates of each test structure are calculated, thereby classifying the defect parameters of the training wafer and obtaining the defect parameters of each test structure.

[0056] In other embodiments of the present application, the electrical testing of each test structure to obtain the electrical parameters of each test structure includes: performing a capacitance-voltage test on each test structure to obtain a first electrical parameter; and performing an oxide layer leakage test on each test structure to obtain a second electrical parameter.

[0057] In other embodiments of the present application, performing a capacitance-voltage test on each of the test structures to obtain the first electrical parameter includes:

[0058] Step 1: Perform capacitance-voltage testing on each target test structure to obtain the oxide layer capacitance, low-frequency capacitance, high-frequency capacitance, total charge in the oxide layer, and interface state charge.

[0059] Among them, the oxide layer capacitance is the capacitance value of the oxide layer, which represents the dielectric properties of the insulating layer; the low-frequency capacitance is used to reflect the dynamic response of the interface state charge; the high-frequency capacitance is determined only by the depletion layer and oxide layer capacitance; the total charge in the oxide layer is the total amount of charge contained in the oxide layer; the interface state charge is the total amount of charge captured at the interface; and the capacitor plate area is the capacitor plate area of ​​the test structure.

[0060] The target test structure is any one of a plurality of test structures. In a specific application environment, the relevant steps of this embodiment will be performed on the plurality of test structures respectively.

[0061] Step 2: Determine the interface state density based on the oxide layer capacitance, low-frequency capacitance, and high-frequency capacitance.

[0062] For example, the interface state density D it The calculation formula is , where D it is the interface state density, unit , represents the defect density at the interface between semiconductor and oxide; q is the elementary charge, and its value is ; C OX is the oxide layer capacitance, unit , represents the dielectric properties of the insulating layer; C LF is the low-frequency capacitance, reflecting the dynamic response of the interface state charge; C HF It is a high-frequency capacitor determined only by the depletion layer and oxide layer capacitance.

[0063] Step 3: Determine the flat band voltage based on the total charge in the oxide layer, the interface state charge, and the oxide layer capacitance.

[0064] For example, the flatband voltage V FB The calculation formula is , where V FB is the flat band voltage, in volts (V); Φ ms is the metal-semiconductor work function difference, in volts (V); Q ox is the total charge in the oxide layer, in coulombs (C); Q it is the interface state charge, measured in coulomb (C).

[0065] Step 4: Determine the oxide layer thickness based on the oxide layer capacitance and the capacitor plate area.

[0066] Among them, the oxide layer thickness T ox The calculation formula is , T ox is the thickness of the oxide layer, in meters (m); ε ox is the relative dielectric constant of the oxide layer, dimensionless; ε0 is the dielectric constant of vacuum; A is the area of ​​the capacitor plate, unit square meter (m 2 ).

[0067] Step 5: Using the interface state density, flat band voltage, and oxide layer thickness as the first electrical parameter.

[0068] In other embodiments of the present application, performing an oxide layer leakage test on each of the test structures to obtain the second electrical parameter includes:

[0069] Step 1: Perform an oxide layer leakage test on each target test structure to obtain the oxide layer breakdown voltage and tunneling voltage.

[0070] Step 2: Determine the oxide layer breakdown electric field based on the oxide layer breakdown voltage and oxide layer thickness.

[0071] Among them, the oxide layer breakdown electric field E BD ,for , E BD is the breakdown electric field strength of the oxide layer, in volts per meter (MV.m -1 );V BD is the breakdown voltage of the oxide layer, in volts (V).

[0072] Step 3: Determine the tunneling electric field based on the tunneling voltage and the oxide layer thickness.

[0073] Among them, the tunneling electric field E FN for , where E FN is the tunneling electric field strength, V FN is the tunneling voltage.

[0074] Step 4: Using the oxide layer breakdown electric field and the tunneling electric field as the second electrical parameter.

[0075] In other embodiments of the present application, before constructing a data set using the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and training the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model, the method further includes:

[0076] Step 1: Perform anomaly detection on the electrical parameters of each test structure and determine the abnormal values.

[0077] It should be noted that due to defects and problems with semiconductor processes, the electrical parameters of some test structures may be abnormal. Whether the electrical parameters of the test structure are abnormal can be determined by judging whether they are within the normal range.

[0078] Step 2: If the outlier corresponds to the interface state density, calculate the median of all interface state densities except the outlier and replace the outlier with the median.

[0079] That is, when the type of outlier is interface state density, all interface state densities except the outlier are sorted to obtain the median, and the outlier is replaced by the median.

[0080] Step 3: If the outlier corresponds to a flat-band voltage, calculate the median of all flat-band voltages except the outlier and replace the outlier with the median.

[0081] That is, when the type of the outlier is flat-band voltage, all flat-band voltages except the outlier are sorted to obtain the median, and the outlier is replaced by the median.

[0082] Step 4: If the outlier corresponds to the oxide layer thickness, calculate the average value of all oxide layer thicknesses except the outlier and replace the outlier with the average value.

[0083] That is, when the type of the outlier is oxide layer thickness, the average value of all oxide layer thicknesses except the outlier is calculated, and the outlier is replaced by the average value.

[0084] Step 5: If the abnormal value corresponds to a tunneling electric field, the abnormal value is replaced by the first preset parameter value.

[0085] That is, when the type of the abnormal value is a tunneling electric field, the abnormal value is replaced by the first preset parameter value.

[0086] Step 6: If the abnormal value corresponds to the oxide layer breakdown electric field, the abnormal value is replaced by the second preset parameter value.

[0087] That is, when the type of the abnormal value is the oxide layer breakdown electric field, the abnormal value is replaced by the second preset parameter value.

[0088] It should be noted that the first preset parameter value and the second preset parameter value are preset fixed parameter values. In this embodiment, the first preset parameter value and the second preset parameter value are both 0.

[0089] In other embodiments of the present application, the step of constructing a data set using the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and training the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model includes:

[0090] Step 1: Construct a first characteristic matrix corresponding to each test structure according to the defect parameters of each test structure.

[0091] The first characteristic matrix is ​​a 15-dimensional characteristic matrix related to defect parameters.

[0092] Step 2: Construct a second characteristic matrix corresponding to each test structure according to the electrical parameters of each test structure.

[0093] The second characteristic matrix is ​​a 5-dimensional characteristic matrix related to electrical parameters.

[0094] Step 3: Construct a data set according to the first characteristic matrix corresponding to each test structure, the second characteristic matrix corresponding to each test structure, and the preset test layout.

[0095] Step 4: Train the initial wafer defect prediction model based on the data set, adjust the model parameters of the initial wafer defect prediction model through the mean square error and mean absolute error, and obtain an iteratively optimized wafer defect prediction model.

[0096] That is, the first characteristic matrix and the second characteristic matrix are normalized. For example, the matrix [1.5, 2.0, 2.5] is normalized to [-1.0, 0.0, 1.0].

[0097] The initial wafer defect prediction model is a 5-layer fully connected network constructed by a fully connected deep neural network (DNN), which uses the ReLU activation function and Dropout regularization technology to realize linear activation of the output layer to achieve multi-target regression.

[0098] In other specific embodiments of the present application, Figure 4 As shown, the electrical parameter prediction method of SiC wafer includes:

[0099] Step S1: Extracting silicon carbide wafer defect distribution data using a SiC wafer analyzer.

[0100] That is, the SiC epitaxial wafer is subjected to standard RCA cleaning to remove polishing chemical residues and contamination, and the SiC defect type is calibrated using an optical microscope and photoluminescence spectrum using a SiC wafer analyzer. Finally, based on the preset test layout, the coordinates of each device are calculated to extract the defect type, quantity and area in each test structure in each field.

[0101] For example, Figure 5 Schematic diagram of the preset layout test structure.

[0102] Figure 6 Schematic diagram of defect extraction for one of the test structures in each field on the wafer.

[0103] Step S2: Complete different test structure tape-outs, the flow chart is as follows Figure 4 shown.

[0104] Step S3: Perform wafer distributed electrical testing on the test structures on multiple wafers to construct a training set of data on the relationship between defects and electrical properties of the oxide layer.

[0105] For example, a power device analyzer is used to test the oxide layer leakage (with an accuracy of nA or above) at test frequencies of 1k and 1M; and electrical parameters are obtained through oxide layer leakage testing and high and low frequency capacitance calculations, including interface state density, flat band voltage, oxide layer thickness, FN tunneling electric field, and oxide layer breakdown electric field.

[0106] Step S4: Enhance the preprocessing of defect data, standardize and jointly model multi-dimensional defect features, and establish a deep learning neural network.

[0107] That is, to perform defect data enhancement preprocessing, adopt feature-oriented null value filling strategy, and it and V FB The parameters use median filling, T ox Parameters fixed filling mean, E FN and E BD Fill with 0 value. Construct a system that includes 15 defect characteristic parameters (BPD, Particle, Pit, etc.) and 5 electrical index target parameters (D it 、V FB 、T oxetc.); and perform Z-score normalization on the first and second feature matrices respectively through a double normalizer to eliminate dimensional differences; then establish a 5-layer fully connected network constructed by a fully connected deep neural network (DNN), and use the ReLU activation function and Dropout regularization technology to implement linear activation of the output layer to achieve multi-target regression; then evaluate the model performance through the dual indicators of MSE (mean square error) and MAE (mean absolute error), and generate a scatter plot of predicted values ​​and true values; save the complete Keras model architecture and double normalizer parameters to achieve end-to-end call in the prediction stage, and finally repeatedly adjust the model through the wafer defect prediction model and the real data set to reduce the MSE and MAE dual indicators to iteratively optimize the prediction model.

[0108] Step S5: Extract defect information from the SiC wafer to be evaluated, predict the quality of its oxide layer after oxidation, screen the wafer grade in the early stage of SiC wafer MOS device manufacturing, and provide the electrical indicators and application areas of SiCMOSFET devices suitable for the wafer to be evaluated based on the predicted evaluation.

[0109] That is, the defect information of the wafer to be evaluated is extracted, its electrical parameters are predicted, and based on the evaluation indicators, the device area and electrical characteristic indicators of the SiC MOSFET device suitable for the epitaxial wafer are given, such as the interface state density D it Low parameters are suitable for preparing devices with a load of about 1200V. The on-resistance and oxide layer breakdown electric field E BD Devices with high parameters are suitable for high voltages above 6500V.

[0110] It should be noted that the MOSFET devices in this application include but are not limited to planar MOSFET, trench MOSFET, and fin-type FinFET. The above steps S1, S2, and S3 are the data collection in the early stage of the invention and are an important basis for the invention. S4 is the processing of the data set and the establishment of the neural network. S5 is the application demonstration of the implementation of the invention.

[0111] In other embodiments of the present application, completing different test structure tape-outs is specifically as follows:

[0112] Step S21: RCA cleaning is performed on the SiC wafer. After sacrificial oxidation of the SiC once, the surface silicon oxide layer is removed using hydrofluoric acid (HF). A 50±5 nm oxide layer is grown using a standard thermal oxidation process. This oxide layer is used for the final quality characterization.

[0113] Step S22: performing NO or N2O annealing on the SiC oxide wafer, with the annealing time being 60 minutes and the annealing temperature being 1000°C-1400°C.

[0114] Step S23: depositing polysilicon gates on the SiC oxide wafer using a low-pressure chemical vapor deposition method and performing phosphorus annealing.

[0115] Step S24: performing photolithography and etching on the annealed polysilicon to form a polysilicon gate.

[0116] Step S25: low pressure chemical vapor deposition is used to deposit an insulating dielectric layer forming the gate, source, and drain.

[0117] Step S26: perform photolithography, etch the gate opening, and evaporate Ti / Al to form the gate metal.

[0118] Step S27: After BOE etching (using a mixture of hydrofluoric acid and ammonium fluoride) is performed on the back side of the SiC oxide wafer to remove the back polycrystalline, the back side is subjected to magnetron sputtering to sputter metal nickel, and annealing is performed in a rapid annealing device, with inert gas internal annealing at a temperature of 950°C for 5 minutes.

[0119] In other embodiments of the present application, performing wafer distributed electrical testing on test structures on multiple wafers to construct a training set of data on the relationship between defects and electrical properties of oxide layers includes:

[0120] Step S31: constructing a power analysis wafer mapping scanning program to calibrate the power analyzer.

[0121] Step S32: Perform capacitance-voltage tests at 1k and 1M high and low frequencies on the SiC oxidation test capacitor, and perform a breakdown voltage breakdown test (oxide layer leakage test) on the capacitor, with a maximum voltage of 100V, a current limit of 1mA, and a step size of 0.1V.

[0122] A SiC wafer oxidation quality dataset can be constructed. Figure 7 is the SiC wafer oxide layer capacitance D it Interface state distribution results, low D it The interface state indicates that there are fewer dangling bonds and carbon clusters on the surface of the oxide layer SiC wafer, which further represents the channel mobility of the MOS device. The resulting MOS resistance is low. The low interface state density is also related to the stability of the threshold voltage. The interface state density range is 10 10 cm 2 ev -1 to 10 12 cm 2 ev -1 It can be seen that the interface state density at different positions on the same SiC wafer is not the same and fluctuates greatly. This is related to the quality of the areas at different positions of the wafer and is greatly affected by the defect distribution. Therefore, the defect distribution can be used to analyze and predict its relationship with electrical parameters.

[0123] Step S5: Predicting the oxidation quality of SiC epitaxial wafers, extracting defect information from the wafer to be evaluated, predicting the quality of the oxide layer after oxidation, and screening the wafer grade in the early stage of SiC wafer MOS device manufacturing. Figure 8 This chart compares the actual and predicted values, with different symbols representing different wafers. The interface state density increases with increasing surface contaminant particles (Particles) and photoluminescent stacking faults (PL_SFs). This shows a good fit between the predicted model and the actual values. Wafers with high interface state density are not suitable for low-voltage, low-resistance SiC device manufacturing.

[0124] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0125] Based on the same inventive concept, the embodiments of the present application also provide a device for predicting electrical parameters of SiC wafers for implementing the aforementioned method for predicting electrical parameters based on SiC wafer defect distribution. The implementation solution provided by the device is similar to the implementation solution described in the aforementioned method. Therefore, the specific limitations of the embodiments of the device for predicting electrical parameters of one or more SiC wafers provided below can be found in the limitations of the method for predicting electrical parameters of SiC wafers above, and will not be repeated here.

[0126] In one embodiment of the present application, Figure 9 As shown, a device for predicting electrical parameters of a SiC wafer is provided, comprising:

[0127] The acquisition module 100 is used to acquire defect parameters of each test structure in the training wafer based on a preset test layout.

[0128] The test module 200 is used to perform electrical testing on each of the test structures to obtain electrical parameters of each test structure; the test structure is obtained by tape-out of the wafer based on the preset test layout.

[0129] The training module 300 is used to construct a data set based on the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure, and train the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model.

[0130] Verification module 400 is used to obtain instance defect parameters and design layout of the wafer to be evaluated, and input the instance defect parameters and design layout into the wafer defect prediction model to obtain electrical parameters of each designed test structure in the wafer to be evaluated; the training wafer and the wafer to be evaluated are SiC wafers.

[0131] In other embodiments of the present application, the acquisition module 100 is further used to obtain a photoluminescence spectrum of the training wafer; based on semiconductor defect detection equipment, an optical microscope and the photoluminescence spectrum, defect detection is performed on the training wafer to obtain defect parameters of the training wafer; according to the preset test layout and the defect parameters of the training wafer, the defect parameters of each test structure are determined; and a plurality of test structures are designed in the preset test layout.

[0132] In other embodiments of the present application, the test module 200 is further configured to perform a capacitance-voltage test on each of the test structures to obtain a first electrical parameter; and perform an oxide layer leakage test on each of the test structures to obtain a second electrical parameter.

[0133] In other embodiments of the present application, the test module 200 is also used to perform a capacitance-voltage test on each target test structure to obtain the oxide layer capacitance, low-frequency capacitance, high-frequency capacitance, the total charge in the oxide layer, the interface state charge, the oxide layer capacitance and the capacitor plate area; the target test structure is any one of a plurality of test structures; the interface state density is determined based on the oxide layer capacitance, low-frequency capacitance and high-frequency capacitance; the flatband voltage is determined based on the total charge in the oxide layer, the interface state charge and the oxide layer capacitance; the oxide layer thickness is determined based on the oxide layer capacitance and the capacitor plate area; and the interface state density, flatband voltage and oxide layer thickness are used as the first electrical parameters.

[0134] In other embodiments of the present application, the test module 200 is also used to perform an oxide layer leakage test on each target test structure to obtain an oxide layer breakdown voltage and a tunneling voltage; determine an oxide layer breakdown electric field based on the oxide layer breakdown voltage and the oxide layer thickness; determine a tunneling electric field based on the tunneling voltage and the oxide layer thickness; and use the oxide layer breakdown electric field and the tunneling electric field as a second electrical parameter.

[0135] In other embodiments of the present application, the training module 300 is also used to perform anomaly detection on the electrical parameters of each test structure and determine the outlier; if the outlier corresponds to the interface state density, the median of all the interface state densities except the outlier is counted, and the outlier is replaced by the median; if the outlier corresponds to the flat band voltage, the median of all the flat band voltages except the outlier is counted, and the outlier is replaced by the median; if the outlier corresponds to the oxide layer thickness, the average value of all the oxide layer thicknesses except the outlier is counted, and the outlier is replaced by the average value; if the outlier corresponds to the tunneling electric field, the outlier is replaced by the first preset parameter value; if the outlier corresponds to the oxide layer breakdown electric field, the outlier is replaced by the second preset parameter value.

[0136] In other embodiments of the present application, the training module 300 is also used to construct a first characteristic matrix corresponding to each test structure based on the defect parameters of each test structure; construct a second characteristic matrix corresponding to each test structure based on the electrical parameters of each test structure; construct a data set based on the first characteristic matrix corresponding to each test structure, the second characteristic matrix corresponding to each test structure and a preset test layout; train the initial wafer defect prediction model based on the data set, adjust the model parameters of the initial wafer defect prediction model through the mean square error and the mean absolute error, and obtain an iteratively optimized wafer defect prediction model.

[0137] Each module in the aforementioned SiC wafer electrical parameter prediction device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a memory in the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0138] In one embodiment of the present application, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 10 As shown. The computer device includes a processor, a memory, and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store all relevant data for executing an electrical parameter prediction method based on SiC wafer defect distribution. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a method for predicting electrical parameters based on SiC wafer defect distribution is implemented.

[0139] Those skilled in the art will understand that Figure 10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0140] In one embodiment of the present application, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps of the method for predicting electrical parameters of SiC wafers in the above embodiment are implemented.

[0141] In one embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. The computer program is executed by a processor to implement the steps of the electrical parameter prediction method based on SiC wafer defect distribution in the above-mentioned method embodiments.

[0142] In one embodiment of the present application, a computer program product is provided, including a computer program, which, when executed by a processor, implements the steps of the electrical parameter prediction method based on SiC wafer defect distribution in the above-mentioned method embodiments.

[0143] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0144] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The above-mentioned computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Among them, any reference to memory, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), data processing logic devices based on quantum computing, and the like.

[0145] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0146] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for predicting electrical parameters based on SiC wafer defect distribution, characterized in that: The method comprises: Based on the preset test layout, the defect parameters of each test structure in the training wafer are obtained; Performing electrical testing on each of the test structures to obtain electrical parameters of each test structure; the test structures are obtained by tape-out of the wafer based on the preset test layout; A data set is constructed using the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure. The initial wafer defect prediction model is trained to obtain an iteratively optimized wafer defect prediction model. The example defect parameters and design layout of the wafer to be evaluated are obtained, and the example defect parameters and design layout are input into the wafer defect prediction model to obtain the electrical parameters of each designed test structure in the wafer to be evaluated; the training wafer and the wafer to be evaluated are SiC wafers.

2. The electrical parameter prediction method based on SiC wafer defect distribution according to claim 1, characterized in that: The method of obtaining defect parameters of each test structure in the training wafer based on the preset test layout includes: Obtaining an optical microscope image and a photoluminescence spectrum based on a semiconductor defect detection device, performing defect detection on the training wafer to obtain defect parameters of the training wafer; Determine the defect parameters of each test structure according to the preset test layout and the defect parameters of the training wafer; a plurality of test structures are designed in the preset test layout.

3. The electrical parameter prediction method based on SiC wafer defect distribution according to claim 1, characterized in that: The defect parameters include: black dot defects, surface contaminant particles, surface depressions caused by chemical mechanical polishing over-corrosion, surface protrusion defects, scratch defects, pitting white etching defects, micropipes, basal plane dislocations, stacking faults, extended stacking faults, carrot defects, dark field defects, complexes of dark field defects and triangular structures, photoluminescent stacking faults, and triangular defects formed by metal impurity segregation.

4. The electrical parameter prediction method based on SiC wafer defect distribution according to claim 1, characterized in that: The performing electrical testing on each of the test structures to obtain electrical parameters of each test structure includes: Performing a capacitance-voltage test on each of the test structures to obtain a first electrical parameter; An oxide layer leakage test is performed on each of the test structures to obtain a second electrical parameter.

5. The electrical parameter prediction method based on SiC wafer defect distribution according to claim 4, characterized in that: The performing a capacitance-voltage test on each of the test structures to obtain a first electrical parameter includes: Performing a capacitance-voltage test on each target test structure to obtain oxide layer capacitance, low-frequency capacitance, high-frequency capacitance, total charge in the oxide layer, and interface state charge; the target test structure is any one of the multiple test structures; Determining interface state density based on the oxide layer capacitance, low-frequency capacitance, and high-frequency capacitance; The flat band voltage is determined based on the total amount of charge in the oxide layer, the interface state charge, and the oxide layer capacitance; Determine the thickness of the oxide layer based on the oxide layer capacitance and the area of ​​the capacitor plate; The interface state density, flat band voltage and oxide layer thickness are used as first electrical parameters.

6. The electrical parameter prediction method based on SiC wafer defect distribution according to claim 4, characterized in that: The performing of an oxide layer leakage test on each of the test structures to obtain a second electrical parameter includes: Performing oxide layer leakage testing on each target test structure to obtain oxide layer breakdown voltage and tunneling voltage; Determining the oxide layer breakdown electric field according to the oxide layer breakdown voltage and the oxide layer thickness; Determining a tunneling electric field according to the tunneling voltage and the thickness of the oxide layer; The oxide layer breakdown electric field and tunneling electric field are used as the second electrical parameter.

7. The electrical parameter prediction method based on SiC wafer defect distribution according to claim 1, characterized in that: Before constructing a data set using the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure and training the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model, the method further includes: Perform anomaly detection on the electrical parameters of each test structure and determine the abnormal values; If the outlier corresponds to the interface state density, the median of all the interface state densities except the outlier is calculated, and the outlier is replaced by the median; If the abnormal value corresponds to a flat-band voltage, the median of all the flat-band voltages except the abnormal value is calculated, and the abnormal value is replaced by the median; If the abnormal value corresponds to the thickness of the oxide layer, then calculating the average value of all the oxide layer thicknesses except the abnormal value, and replacing the abnormal value with the average value; If the abnormal value corresponds to a tunneling electric field, replacing the abnormal value with a first preset parameter value; If the abnormal value corresponds to the oxide layer breakdown electric field, the abnormal value is replaced by the second preset parameter value.

8. The electrical parameter prediction method based on SiC wafer defect distribution according to claim 1, characterized in that: The method constructs a data set by using the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and trains the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model, including: According to the defect parameters of each test structure, a first characteristic matrix corresponding to each test structure is constructed; the first characteristic matrix is ​​a 15-dimensional characteristic matrix about the defect parameters; According to the electrical parameters of each test structure, a second characteristic matrix corresponding to each test structure is constructed; the second characteristic matrix is ​​a 5-dimensional characteristic matrix about the electrical parameters; Construct a data set according to the first feature matrix and the second feature matrix corresponding to each test structure; Training an initial wafer defect prediction model based on the data set, adjusting model parameters of the initial wafer defect prediction model by using mean square error and mean absolute error to obtain an iteratively optimized wafer defect prediction model; The initial wafer defect prediction model uses a 5-layer fully connected network built with a fully connected deep neural network (DNN).

9. An electrical parameter prediction device based on SiC wafer defect distribution, characterized in that: The electrical parameter prediction device based on SiC wafer defect distribution includes: An acquisition module, configured to acquire defect parameters of each test structure in a training wafer based on a preset test layout; A testing module, configured to perform electrical testing on each of the test structures to obtain electrical parameters of each test structure; the test structures are obtained by tape-out of the wafer based on the preset test layout; A training module is used to construct a data set based on the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and to train the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model; The verification module is used to obtain instance defect parameters and a design layout of a wafer to be evaluated, and input the instance defect parameters and the design layout into a wafer defect prediction model to obtain electrical parameters of each designed test structure in the wafer to be evaluated; the training wafer and the wafer to be evaluated are SiC wafers.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

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