Method and apparatus for predicting electrical parameters based on SiC wafer defect distribution

Abstract

This application relates to a method and apparatus for predicting electrical parameters based on SiC wafer defect distribution, comprising: acquiring defect parameters of each test structure in a training wafer; acquiring electrical parameters of the test structures through electrical testing after the training wafer is fabricated; constructing a dataset through defect parameter distribution and electrical parameters; training an initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model; acquiring instance defect parameters and design layout of the wafer to be evaluated; inputting the instance defect parameters and design layout into the wafer defect prediction model to obtain electrical parameters of each design test structure in the wafer to be evaluated, wherein the training wafer and the wafer to be evaluated are SiC wafers. This method solves the problem of low accuracy and overall efficiency in traditional technologies that rely on manual experience to judge the quality of SiC wafers, enabling the screening of wafer grades in the early stage of wafer manufacturing and providing suitable SiC devices for fabrication based on evaluation indicators.

Description

Technical Field

[0001] This application relates to the field of semiconductor device quality inspection, and in particular to a method and apparatus for predicting electrical parameters based on the defect distribution of SiC wafers. Background Technology

[0002] Wafers are the core substrate for semiconductor manufacturing and the physical carrier of integrated circuits (ICs), such as SiC wafers. Because the growth environment for SiC wafers is high-temperature, the epitaxial layer contains complex compositions, and during the polishing process, SiC wafers generate defects under high stress, the defect density of SiC wafers is typically 1-2 orders of magnitude higher than that of silicon wafers. The number and types of defects severely affect the performance of SiC devices. For example, basal plane dislocations (BPDs) and carrot defects affect the quality of the oxide layer in metal-oxide-semiconductor field-effect transistors (MOSFETs), leading to increased interface state density, threshold voltage drift, a surge in leakage current, and reduced oxide layer lifetime. The performance of SiC devices is related to their application areas; for example, high-voltage applications require high withstand voltage performance of SiC devices, while low-voltage applications require high on-resistance.

[0003] Currently, in traditional technologies, relying on manual experience to judge the quality of SiC wafers with high defect density and their suitability for manufacturing SiC devices has low accuracy and overall efficiency. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, and computer equipment for efficiently and accurately judging the quality of SiC wafers and predicting their electrical parameters based on defect distribution, in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a method for predicting electrical parameters based on the defect distribution of SiC wafers. The method includes: obtaining defect parameters of each test structure in a training wafer based on a preset test layout; performing electrical tests on each test structure to obtain electrical parameters of each test structure; wherein the test structure is obtained by fabricating the wafer based on the preset test layout; constructing a dataset using the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure, and training an initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model; obtaining instance defect parameters and design layout of the wafer to be evaluated, and inputting the instance defect parameters and design layout into the wafer defect prediction model to obtain electrical parameters of each design test structure in the wafer to be evaluated; wherein the training wafer and the wafer to be evaluated are SiC wafers.

[0006] In one embodiment, obtaining the defect parameters of each test structure in the training wafer based on a preset test layout includes: obtaining an optical microscope image and the photoluminescence spectrum based on a semiconductor defect detection device, performing defect detection on the training wafer to obtain the defect parameters of the training wafer; determining the defect parameters of each test structure according to the preset test layout and the defect parameters of the training wafer; the preset test layout includes multiple test structures.

[0007] In one embodiment, the defect parameters include: black dot-shaped defects (PL_Black), surface contaminant particles (Particle), surface pits (Pit) formed by chemical mechanical polishing over-etching, surface bumps (Bump), scratches (ScratchTrace), point-like white etching defects (PL_White), micropipes (Micropipe), basal dislocations (BPD), stacking faults (Stacking Fault), propagated stacking faults (PropagatedSF), carrot defects (Carrot), dark field defects (DF), a complex of DF defects and triangular structures (DF_Triangle), photoluminescent stacking faults (PL_SF), and triangular defects (Triangle) formed by the segregation of metallic impurities (Triangle).

[0008] In one embodiment, the step of performing electrical tests on each of the test structures to obtain the electrical parameters of each test structure includes: performing a capacitance-voltage test on each of the test structures to obtain a first electrical parameter; and performing an oxide layer leakage current test on each of the test structures to obtain a second electrical parameter.

[0009] In one embodiment, performing a capacitance-voltage test on each of the test structures to obtain the first electrical parameter includes: performing a capacitance-voltage test on each target test structure to obtain the oxide layer capacitance, low-frequency capacitance, high-frequency capacitance, total charge in the oxide layer, and interface state charge; the target test structure is any one of a plurality of test structures; and determining the interface state density D based on the oxide layer capacitance, low-frequency capacitance, and high-frequency capacitance. it (Interface Trap Density); Determine the flat-band voltage V based on the total charge in the oxide layer, the interface state charge, and the oxide layer capacitance. FB (FlatBand Voltage); Determine the oxide layer thickness T based on the oxide layer capacitance and capacitor plate area. ox (OxideThickness); The interface state density, flat band voltage, and oxide layer thickness are used as the first electrical parameters.

[0010] In one embodiment, the step of performing oxide layer leakage current testing on each of the test structures to obtain the second electrical parameter includes: performing oxide layer leakage current testing on each target test structure to obtain the oxide layer breakdown voltage and tunneling voltage; and determining the oxide layer breakdown electric field E based on the oxide layer breakdown voltage and oxide layer thickness. BD (OxideBreakdown Electric Field); according to the tunneling voltage E FN The tunneling electric field is determined by the Fowler-Nordheim Tunneling Electric Field and the oxide layer thickness; the breakdown electric field and tunneling electric field of the oxide layer are used as the second electrical parameters.

[0011] In one embodiment, before constructing a dataset using the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and training an initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model, the method further includes: performing anomaly detection on the electrical parameters of each test structure to determine anomalies; if the anomaly corresponds to an interface state density, then calculating the median of all interface state densities except the anomaly, and replacing the anomaly with the median; if the anomaly corresponds to a flat band voltage, then calculating the median of all flat band voltages except the anomaly, and replacing the anomaly with the median; if the anomaly corresponds to an oxide layer thickness, then calculating the average of all oxide layer thicknesses except the anomaly, and replacing the anomaly with the average; if the anomaly corresponds to a tunneling electric field, then replacing the anomaly with a first preset parameter value; if the anomaly corresponds to an oxide layer breakdown electric field, then replacing the anomaly with a second preset parameter value.

[0012] In one embodiment, the step of constructing a dataset using the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and training an initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model includes: constructing a first feature matrix corresponding to each test structure based on the defect parameters of each test structure; the first feature matrix is ​​a 15-dimensional feature matrix about the defect parameters; constructing a second feature matrix corresponding to each test structure based on the electrical parameters of each test structure; the second feature matrix is ​​a 5-dimensional feature matrix about the electrical parameters; constructing a dataset based on the first feature matrix, the second feature matrix, and the preset test layout; training the initial wafer defect prediction model based on the dataset, and adjusting the model parameters of the initial wafer defect prediction model using mean square error and mean absolute error to obtain an iteratively optimized wafer defect prediction model;

[0013] The initial wafer defect prediction model is a 5-layer fully connected network constructed using a fully connected deep neural network (DNN). The ReLU activation function and Dropout regularization technique are used to linearly activate the output layer to achieve multi-objective regression.

[0014] Secondly, this application also provides an electrical parameter prediction device based on the defect distribution of SiC wafers, the electrical parameter prediction device for SiC wafers comprising:

[0015] The acquisition module is used to acquire the defect parameters of each test structure in the training wafer based on a preset test layout;

[0016] The testing module is used to perform electrical tests on each of the test structures to obtain the electrical parameters of each test structure; the test structure is obtained by fabricating the wafer based on the preset test layout;

[0017] The training module is used to construct a dataset using the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure, and to train the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model.

[0018] The verification module is used to obtain instance defect parameters and design layout of the wafer to be evaluated, and input the instance defect parameters and design layout into the wafer defect prediction model to obtain the electrical parameters of each design test structure in the wafer to be evaluated; the training wafer and the wafer to be evaluated are SiC wafers.

[0019] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement any of the methods described in the first aspect above.

[0020] The aforementioned method and apparatus for predicting electrical parameters based on SiC wafer defect distribution acquires the defect parameters of each test structure in the training wafer, performs electrical tests on each test structure to obtain the electrical parameters of each test structure, and constructs a dataset based on the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure. This dataset is then used to train an initial wafer defect prediction model, resulting in an iteratively optimized wafer defect prediction model. This model can then predict the electrical parameters of each designed test structure in the wafer to be evaluated based on the instance defect parameters and design layout of the wafer under evaluation. This addresses the problem of low accuracy and overall efficiency in traditional technologies that rely on manual experience to judge the quality of SiC wafers. Furthermore, it can screen wafer grades in the early stages of wafer manufacturing and provide suitable SiC devices for fabrication based on evaluation metrics. Attached Figure Description

[0021] Figure 1 This is an application environment diagram of an electrical parameter prediction method based on SiC wafer defect distribution in one embodiment;

[0022] Figure 2 This is a flowchart illustrating an electrical parameter prediction method based on SiC wafer defect distribution in one embodiment.

[0023] Figure 3 This is a schematic diagram of an optical microscope (OM) image and a photoluminescence (PL) pattern of surface contaminant particles and carrot defects in one embodiment;

[0024] Figure 4 This is a flowchart illustrating the fabrication of a test structure for a SiC wafer and the method for predicting its electrical parameters in one embodiment.

[0025] Figure 5 This is a schematic diagram of a preset test layout in one embodiment;

[0026] Figure 6 This is a schematic diagram illustrating the extraction of defect distribution for each field on a wafer based on a preset test layout in one embodiment;

[0027] Figure 7 In one embodiment, the D on the SiC wafer oxide layer capacitor it A schematic diagram of the interface state distribution results;

[0028] Figure 8 In one embodiment, surface particle partial defects and interface state D it Relationship between photoluminescent stacking faults PL_SF and interface states D it A diagram showing the comparison between the actual and predicted values;

[0029] Figure 9 This is a structural block diagram of an electrical parameter prediction device based on SiC wafer defect distribution in one embodiment;

[0030] Figure 10 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0032] The electrical parameter prediction method based on SiC wafer defect distribution provided in this application embodiment can be applied to, for example... Figure 1In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104 or located in the cloud or on other network servers. Server 104 is used to execute the electrical parameter prediction method for the SiC wafer. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, etc. Portable wearable devices can include smartwatches, smart bracelets, head-mounted devices, etc. Server 104 can be implemented using a standalone server or a server cluster consisting of multiple servers.

[0033] To address the aforementioned problems, in one embodiment of this application, such as Figure 2 As shown, a method for predicting electrical parameters based on the defect distribution of SiC wafers is provided, including the following steps:

[0034] Step 201: Based on the preset test layout, obtain the defect parameters of each test structure in the training wafer.

[0035] The preset test layout is a pre-defined layout that divides the wafer, including the position and extent of each test structure. After obtaining the overall defect parameters of the wafer, the overall defect parameters can be classified according to the preset test layout to obtain the defect parameters of each test structure in the wafer. In this embodiment, the test structures are capacitor structures with different areas. Defect parameters refer to the types, quantities, and areas of physical, chemical, or structural anomalies existing on or inside the surface of the wafer (silicon wafer, silicon carbide wafer, or other semiconductor material substrate) during the semiconductor manufacturing process, including but not limited to: black dot-shaped defects, surface contaminant particles, surface depressions formed by chemical mechanical polishing over-etching, surface protrusion defects, scratch defects, point-like white etching defects, microtubes, basal dislocations, stacking faults, extended stacking faults, carrot defects, dark field defects, complexes of dark field defects and triangular structures, photoluminescent stacking faults, and triangular defects formed by metal impurity segregation. For example, Figure 3 This image shows schematic diagrams of surface contaminant particles and carrot-shaped defects under an optical microscope (OM) and a photoluminescence spectrometer (PL), respectively. The boxes in the images indicate the calculated defect areas, in μm. 2 ).

[0036] Step 202: Perform electrical tests on each test structure to obtain the electrical parameters of each test structure.

[0037] Specifically, capacitance-voltage tests are performed on each test structure to obtain the first electrical parameters of each test structure, and oxide layer leakage current tests are performed on each test structure to obtain the second electrical parameters of each test structure. The test structures are obtained by fabricating the wafer based on the preset test layout. For example, the preset test layout is as follows: Figure 5 As shown, this includes the locations of 70 test structures on the wafer.

[0038] Specifically, in other embodiments of this application, the step of performing electrical tests on each of the test structures to obtain the electrical parameters of each test structure includes: performing a capacitance-voltage test on each test structure to obtain a first electrical parameter; and performing an oxide layer leakage test on each test structure to obtain a second electrical parameter.

[0039] Step 203: Construct a dataset using the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure, and train the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model.

[0040] Based on a pre-defined test layout, the correspondence between the defect parameters and electrical parameters of each test structure is determined, thereby constructing a dataset. This dataset is used to train an initial wafer defect prediction model. By training the initial wafer defect prediction model using the dataset, an iteratively optimized wafer defect prediction model is obtained. This wafer defect prediction model is used to predict the electrical parameters of the test structure based on its defect parameters.

[0041] It should be noted that the only factors affecting the electrical parameters of the test structure are its defect parameters; the area of ​​the test structure does not affect its electrical parameters. The initial wafer defect prediction model is a pre-defined deep learning model or other artificial intelligence model.

[0042] Step 204: Obtain the instance defect parameters and design layout of the wafer to be evaluated, and input the instance defect parameters and design layout into the wafer defect prediction model to obtain the electrical parameters of each design test structure in the wafer to be evaluated.

[0043] The instance defect parameters are the overall defect parameters of the wafer to be evaluated. The wafer defect prediction model classifies the instance defect parameters according to the design layout, thereby obtaining the defect parameters of each design test structure of the wafer to be evaluated. Based on the defect parameters of each design test structure of the wafer to be evaluated, the electrical parameters of each design test structure of the wafer to be evaluated are predicted. It should be noted that the electrical parameters of each design test structure in the wafer to be evaluated are predicted values ​​obtained by the wafer defect prediction model based on the instance defect parameters and design layout of the wafer to be evaluated, and are not the actual values. The training wafer and the wafer to be evaluated are SiC wafers.

[0044] For example, such as Figure 8 As shown, the interface state density (D) is the electrical parameter of each designed test structure. it This diagram illustrates the comparison between the actual and predicted values ​​of the model, where different symbols represent different wafers. The interface state density increases with the increase of surface contaminant particles and photoluminescent stacking faults (PL_SF). It shows a good fit between the predicted model and the actual values. Wafers with high interface state density are not suitable for manufacturing low-voltage, low-resistivity SiC devices.

[0045] In another embodiment of this application, after obtaining the instance defect parameters and design layout of the wafer to be evaluated, and inputting the instance defect parameters and design layout into the wafer defect prediction model to obtain the electrical parameters of each design test structure in the wafer to be evaluated, the method further includes: obtaining the actual electrical parameters of each design test structure in the wafer to be evaluated, and retraining the wafer defect prediction model based on the actual electrical parameters and the electrical parameters of each design test structure in the wafer to be evaluated.

[0046] It should be noted that, in this embodiment, the wafer is a SiC wafer, and the methods for preparing the test structure include, but are not limited to, thermal oxidation, TEOS deposition, wet oxidation, and ALD atomic deposition.

[0047] In the aforementioned method for predicting electrical parameters based on SiC wafer defect distribution, the defect parameters of each test structure in the training wafer are obtained, and electrical tests are performed on each test structure to obtain the electrical parameters of each test structure. A dataset is then constructed based on the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure. The initial wafer defect prediction model is trained to obtain an iteratively optimized wafer defect prediction model. This allows the wafer defect prediction model to predict the electrical parameters of each designed test structure in the wafer to be evaluated based on the instance defect parameters and design layout of the wafer to be evaluated. This solves the problem of low accuracy and overall efficiency in traditional technologies that rely on manual experience to judge wafer quality, thus enabling efficient and accurate judgment of wafer quality.

[0048] The aforementioned method for predicting electrical parameters based on SiC wafer defect distribution can be used to analyze the impact of wafer defect distribution on oxide layer quality and device reliability. By establishing the correlation between wafer defect distribution and oxide layer electrical parameters using deep learning, and by providing predictions, the method identifies suitable electrical parameters and application areas for manufacturing devices using the wafer, thereby improving the performance, yield, and reliability of SiC MOSFET devices.

[0049] In other embodiments of this application, obtaining the defect parameters of each test structure in the training wafer based on a preset test layout includes:

[0050] Step 1: Obtain the photoluminescence spectrum and optical microscope image of the training wafer using semiconductor defect detection equipment.

[0051] Photoluminescence spectrum refers to the spectrum produced when electrons in a training wafer recombine after transitioning from the valence band to the conduction band under light excitation. It includes information about the material's structure, composition, and the arrangement of surrounding atoms. Different crystal defects produce emission peaks with different wavelengths, and the positions of these characteristic peaks, along with optical microscopic images, can help determine the defect parameters of the training wafer.

[0052] Step 2: Based on the optical microscope and photoluminescence spectrum obtained by the semiconductor defect detection equipment, perform defect detection on the training wafer to obtain the defect parameters of the training wafer.

[0053] Semiconductor defect detection equipment is used to detect defect parameters of wafers, such as SiC wafer analyzers. For example, using a SiC wafer analyzer, the defect parameters of the wafer are determined by optical microscopy images and photoluminescence spectra. These defect parameters include the type of defect, the number of defects, and the area of ​​the defects.

[0054] Step 3: Determine the defect parameters of each test structure based on the preset test layout and the defect parameters of the training wafer.

[0055] Based on a preset test layout, the position or coordinates of each test structure are calculated to classify the defect parameters of the training wafer, thus obtaining the defect parameters for each test structure. The preset test layout includes multiple test structures.

[0056] In other embodiments of this application, the step of performing electrical tests on each of the test structures to obtain the electrical parameters of each test structure includes: performing a capacitance-voltage test on each test structure to obtain a first electrical parameter; and performing an oxide layer leakage test on each test structure to obtain a second electrical parameter.

[0057] In other embodiments of this application, the step of performing a capacitance-voltage test on each of the test structures to obtain the first electrical parameter includes:

[0058] Step 1: Perform capacitance-voltage tests on each target test structure to obtain oxide layer capacitance, low-frequency capacitance, high-frequency capacitance, total charge in the oxide layer, and interface state charge.

[0059] Among them, the oxide layer capacitance is the capacitance value of the oxide layer, representing the dielectric properties of the insulating layer; the low-frequency capacitance is used to reflect the dynamic response of the interface state charge; the high-frequency capacitance is determined only by the depletion layer and the oxide layer capacitance; the total charge in the oxide layer is the total amount of charge contained in the oxide layer; the interface state charge is the total amount of charge trapped at the interface; and the capacitor plate area is the capacitor plate area of ​​the test structure.

[0060] The target test structure can be any one of multiple test structures. In a specific application environment, the relevant steps of this embodiment will be executed on each of the multiple test structures.

[0061] Step 2: Determine the interface state density based on the oxide layer capacitance, low-frequency capacitance, and high-frequency capacitance.

[0062] For example, the interface state density D it The calculation formula is: , where D it The density of interface states, in units , representing the defect density at the semiconductor-oxide interface; q is the elementary charge, with a value of C OX For oxide layer capacitance, unit , representing the dielectric properties of the insulating layer; C LF It is a low-frequency capacitor that reflects the dynamic response of interface state charges; C HF It is a high-frequency capacitor, determined solely by the capacitance of the depletion layer and the oxide layer.

[0063] Step 3: Determine the flat band voltage based on the total charge in the oxide layer, the interface state charge, and the oxide layer capacitance.

[0064] For example, the flat band voltage V FB The calculation formula is V FB This is the flat-band voltage, measured in volts (V); Φ ms Q is the difference in work function between a metal and a semiconductor, expressed in volts (V). ox Q represents the total charge in the oxide layer, expressed in coulombs (C). it denoted as interface state charge, in units of coulombs (C).

[0065] Step 4: Determine the oxide layer thickness based on the oxide layer capacitance and the capacitor plate area.

[0066] Among them, the oxide layer thickness T ox The calculation formula is T ox ε represents the oxide layer thickness in meters (m). ox ε0 is the relative permittivity of the oxide layer, dimensionless; εvacuum is the permittivity; A is the area of ​​the capacitor plates, in square meters (m2). 2 ).

[0067] Step 5: Use the interface state density, flat band voltage, and oxide layer thickness as the first electrical parameters.

[0068] In other embodiments of this application, the step of performing oxide layer leakage current testing on each of the test structures to obtain the second electrical parameter includes:

[0069] Step 1: Perform oxide layer leakage current test on each target test structure to obtain oxide layer breakdown voltage and tunneling voltage.

[0070] Step 2: Determine the breakdown electric field of the oxide layer based on the breakdown voltage and thickness of the oxide layer.

[0071] Among them, the breakdown electric field E of the oxide layer BD ,for E BD The breakdown electric field strength of the oxide layer is expressed in volts per meter (MV·m). -1 ); V BD The breakdown voltage of the oxide layer is expressed in volts (V).

[0072] Step 3: Determine the tunneling electric field based on the tunneling voltage and oxide layer thickness.

[0073] Among them, the tunneling electric field E FN for E FN V is the tunneling electric field strength. FN This is the tunneling voltage.

[0074] Step 4: Use the breakdown electric field and tunneling electric field of the oxide layer as the second electrical parameters.

[0075] In other embodiments of this application, before constructing a dataset using the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and training the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model, the method further includes:

[0076] Step 1: Perform anomaly detection on the electrical parameters of each test structure and identify abnormal values.

[0077] It should be noted that due to defects and semiconductor process issues, the electrical parameters of some test structures may be abnormal. The abnormality of the electrical parameters of the test structure can be determined by checking whether the electrical parameters are within the normal range.

[0078] Step 2: If the outlier corresponds to the interface state density, then calculate the median of all interface state densities except for the outlier, and replace the outlier with the median.

[0079] That is, when the outlier type is interface density of states, all interface densities of states except the outlier are sorted to obtain the median, and the outlier is replaced with the median.

[0080] Step 3: If the outlier corresponds to a flat band voltage, then calculate the median of all flat band voltages except the outlier, and replace the outlier with the median.

[0081] That is, when the outlier type is flat band voltage, all flat band voltages except the outlier are sorted to obtain the median, and the outlier is replaced with the median.

[0082] Step 4: If the outlier corresponds to the oxide layer thickness, calculate the average value of all oxide layer thicknesses except for the outlier, and replace the outlier with the average value.

[0083] That is, when the outlier type is oxide layer thickness, calculate the average value of all oxide layer thicknesses except for the outlier, and replace the outlier with the average value.

[0084] Step 5: If the abnormal value corresponds to a tunneling electric field, then replace the abnormal value with the first preset parameter value.

[0085] That is, when the type of the outlier is tunneling electric field, the outlier is replaced with the first preset parameter value.

[0086] Step 6: If the abnormal value corresponds to the breakdown electric field of the oxide layer, then replace the abnormal value with the second preset parameter value.

[0087] That is, when the type of the outlier is oxide layer breakdown electric field, the outlier is replaced with the second preset parameter value.

[0088] It should be noted that the first preset parameter value and the second preset parameter value are preset fixed parameter values. In this embodiment, both the first preset parameter value and the second preset parameter value are 0.

[0089] In other embodiments of this application, the step of constructing a dataset using the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and training an initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model includes:

[0090] Step 1: Construct the first feature matrix corresponding to each test structure based on the defect parameters of each test structure.

[0091] The first feature matrix is ​​a 15-dimensional feature matrix relating to the defect parameters.

[0092] Step 2: Based on the electrical parameters of each test structure, construct the second feature matrix corresponding to each test structure.

[0093] The second characteristic matrix is ​​a 5-dimensional characteristic matrix relating to electrical parameters.

[0094] Step 3: Construct a dataset based on the first feature matrix corresponding to each test structure, the second feature matrix corresponding to each test structure, and the preset test layout.

[0095] Step 4: Train the initial wafer defect prediction model based on the dataset, and adjust the model parameters of the initial wafer defect prediction model by means of mean square error and mean absolute error to obtain an iteratively optimized wafer defect prediction model.

[0096] That is, the first feature matrix and the second feature matrix are normalized. For example, the matrix [1.5, 2.0, 2.5] is normalized to [-1.0, 0.0, 1.0].

[0097] The initial wafer defect prediction model is a 5-layer fully connected network constructed by a fully connected deep neural network (DNN). The ReLU activation function and Dropout regularization technique are used to achieve linear activation of the output layer and realize multi-objective regression.

[0098] In other specific embodiments of this application, such as Figure 4 As shown, the methods for predicting the electrical parameters of SiC wafers include:

[0099] Step S1: Use a SiC wafer analyzer to extract defect distribution data of silicon carbide wafers.

[0100] The process involves performing standard RCA cleaning on SiC epitaxial wafers to remove polishing chemical residues and contaminants. Then, using a SiC wafer analyzer, the types of SiC defects are identified through optical microscopy and photoluminescence spectroscopy. Finally, based on the preset test layout, the coordinates of each device are calculated, and the types, quantities, and areas of defects in each field and each test structure are extracted.

[0101] For example, Figure 5 This is a schematic diagram of the preset layout test structure.

[0102] Figure 6 This is a schematic diagram of the extraction of a test structural defect for each field on the wafer.

[0103] Step S2: Complete the fabrication of different test structures, as shown in the flowchart below. Figure 4 As shown.

[0104] Step S3: Perform wafer-level electrical testing on the test structures on multiple wafers to construct a training set of data on the relationship between defects and the electrical properties of the oxide layer.

[0105] For example, the oxide layer leakage current is tested using a power device analyzer (accuracy above nA) at frequencies of 1k and 1MHz; and electrical parameters are obtained through oxide layer leakage current testing and high and low frequency capacitance calculations, including interface state density, flat band voltage, oxide layer thickness, FN tunneling electric field, and oxide layer breakdown electric field.

[0106] Step S4: Enhance the preprocessing of defect data, standardize and jointly model multi-dimensional defect features, and establish a deep learning neural network.

[0107] This involves performing defect data enhancement preprocessing, employing a feature-guided null value imputation strategy for D. it and V FB The parameters are filled with the median, T ox Parameter is fixed, fill average value, E FN and E BD Fill with 0 values. Construct a system containing 15 defect feature parameters (BPD, Particle, Pit, etc.) and 5 electrical performance target parameters (D). it V FB T oxThe model is constructed using a dataset (e.g., a wafer defect prediction model). The first and second feature matrices are Z-score standardized using a double standardizer to eliminate dimensional differences. A 5-layer fully connected deep neural network (DNN) is then built, employing ReLU activation and Dropout regularization to achieve linear activation of the output layer for multi-objective regression. Model performance is evaluated using both MSE (mean squared error) and MAE (mean absolute error), generating a scatter plot of predicted and actual values. The complete Keras model architecture and double standardizer parameters are saved for end-to-end access during the prediction phase. Finally, the model is iteratively optimized using both MSE and MAE metrics by repeatedly adjusting the wafer defect prediction model and real datasets.

[0108] Step S5: Extract defect information from the SiC wafer to be evaluated, predict the quality of the oxide layer after oxidation, and select the wafer grade in the early stage of SiC wafer MOS device manufacturing. Based on the prediction and evaluation, give the electrical indicators and application fields of suitable SiC MOSFET devices to be manufactured from the wafer to be evaluated.

[0109] This involves extracting defect information from the wafer under evaluation, predicting its electrical parameters, and based on evaluation metrics, providing the device area and electrical characteristics of suitable SiC MOSFET devices fabricated from the epitaxial wafer, such as the interface state density D. it Low parameters are suitable for fabricating devices with a load of around 1200V, and the on-resistance and oxide breakdown electric field E are also suitable. BD Devices with high parameters are suitable for high voltages of 6500V and above.

[0110] It should be noted that the MOSFET devices in this application include, but are not limited to, planar MOSFETs, trench MOSFETs, and fin-type FinFETs. The above steps S1, S2, and S3 are the data acquisition in the early stage of the invention and are an important basis for the invention. S4 is the processing of the dataset and the establishment of the neural network. S5 is the application demonstration of the invention implementation.

[0111] In other embodiments of this application, the different test structure fabrication processes are specifically carried out as follows:

[0112] Step S21: Perform RCA cleaning on the SiC wafer, perform one sacrificial oxidation on the SiC, remove the surface silicon oxide layer using hydrofluoric acid (HF), and grow an oxide layer of 50±5 nm using a standard thermal oxidation process. This oxide layer is used for the final quality characterization.

[0113] Step S22: Anneal the SiC oxide wafer with NO or N2O for 60 min at a temperature of 1000℃-1400℃.

[0114] Step S23: Deposit a polysilicon gate on the SiC oxide wafer using low-pressure chemical vapor deposition and perform phosphorus annealing.

[0115] Step S24: Perform photolithography and etching on the annealed polysilicon to form a polysilicon gate.

[0116] Step S25: Low-pressure chemical vapor deposition is used to deposit insulating dielectric layers for the gate, source, and drain.

[0117] Step S26: Perform photolithography to etch the gate opening and form the gate metal by evaporating Ti / Al.

[0118] Step S27: After removing the polycrystalline back side of the SiC oxide wafer by BOE etching (using a mixture of hydrofluoric acid and ammonium fluoride), the back side is then magnetron sputtered with metallic nickel and annealed in a rapid annealing apparatus under inert gas at a temperature of 950°C for 5 minutes.

[0119] In other embodiments of this application, wafer-level electrical testing is performed on test structures on multiple wafers to construct a training set of data on the relationship between defects and oxide layer electrical properties, including:

[0120] Step S31: Build a power analysis wafer mapping scanning program to calibrate the power analyzer.

[0121] Step S32: Perform capacitance-voltage tests on the SiC oxide test capacitor at high and low frequencies of 1k and 1M, and perform breakdown voltage breakdown tests (oxide layer leakage tests) on the capacitor, with a maximum voltage of 100V, a current limit of 1mA, and a step size of 0.1V.

[0122] A dataset of SiC wafer oxidation quality can be constructed. Figure 7 Capacitor D of SiC wafer oxide layer it Interface state distribution results, low D it Interface state density indicates a lower content of dangling bonds and carbon clusters on the SiC oxide wafer surface. This further represents the channel mobility of MOS devices, resulting in lower MOS resistance. A low interface state density is also related to the stability of the threshold voltage. Interface state density ranges from 10-1. 10 cm 2 ev -1 Up to 10 12 cm 2 ev -1 It can be seen that the interface state density is not the same at different locations on the same SiC wafer and fluctuates greatly. This is related to the quality of different regions on the wafer and is greatly affected by the defect distribution. Therefore, the electrical parameters can be predicted by analyzing the defect distribution.

[0123] Step S5: SiC epitaxial wafer oxidation quality prediction. Defect information is extracted from the wafer to be evaluated, and the quality of the oxide layer after oxidation is predicted. This is used to screen wafer grades in the early stages of SiC wafer MOS device manufacturing. Figure 8 This graph compares the actual and predicted values, with different symbols representing different wafers. The interface state density increases with the increase of surface contaminant particles and photoluminescent stacking faults (PL_SF). This demonstrates a good fit between the predicted model and the actual values. Wafers with high interface state density are not suitable for manufacturing low-voltage, low-resistivity SiC devices.

[0124] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0125] Based on the same inventive concept, this application also provides an electrical parameter prediction device for SiC wafers to implement the above-described method for predicting electrical parameters based on SiC wafer defect distribution. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more embodiments of the electrical parameter prediction device for SiC wafers provided below can be found in the limitations of the electrical parameter prediction method for SiC wafers described above, and will not be repeated here.

[0126] In one embodiment of this application, such as Figure 9 As shown, an electrical parameter prediction device for SiC wafers is provided, comprising:

[0127] The acquisition module 100 is used to acquire the defect parameters of each test structure in the training wafer based on a preset test layout.

[0128] The test module 200 is used to perform electrical tests on each of the test structures to obtain the electrical parameters of each test structure; the test structure is obtained by fabricating the wafer based on the preset test pattern.

[0129] The training module 300 is used to construct a dataset using the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure, and to train the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model.

[0130] The verification module 400 is used to obtain instance defect parameters and design layout of the wafer to be evaluated, and input the instance defect parameters and design layout into the wafer defect prediction model to obtain the electrical parameters of each design test structure in the wafer to be evaluated; the training wafer and the wafer to be evaluated are SiC wafers.

[0131] In other embodiments of this application, the acquisition module 100 is further configured to acquire the photoluminescence spectrum of the training wafer; perform defect detection on the training wafer based on a semiconductor defect detection device, an optical microscope, and the photoluminescence spectrum to obtain the defect parameters of the training wafer; determine the defect parameters of each test structure according to the preset test layout and the defect parameters of the training wafer; the preset test layout includes multiple test structures.

[0132] In other embodiments of this application, the test module 200 is further configured to perform a capacitance-voltage test on each of the test structures to obtain a first electrical parameter; and to perform an oxide layer leakage test on each of the test structures to obtain a second electrical parameter.

[0133] In other embodiments of this application, the test module 200 is further configured to perform capacitance-voltage testing on each target test structure to obtain oxide layer capacitance, low-frequency capacitance, high-frequency capacitance, total charge in the oxide layer, interface state charge, oxide layer capacitance, and capacitor plate area; the target test structure is any one of multiple test structures; the interface state density is determined based on the oxide layer capacitance, low-frequency capacitance, and high-frequency capacitance; the flat-band voltage is determined based on the total charge in the oxide layer, interface state charge, and oxide layer capacitance; the oxide layer thickness is determined based on the oxide layer capacitance and capacitor plate area; and the interface state density, flat-band voltage, and oxide layer thickness are used as first electrical parameters.

[0134] In other embodiments of this application, the test module 200 is further configured to perform oxide layer leakage current testing on each target test structure to obtain oxide layer breakdown voltage and tunneling voltage; determine oxide layer breakdown electric field based on the oxide layer breakdown voltage and oxide layer thickness; determine tunneling electric field based on the tunneling voltage and oxide layer thickness; and use the oxide layer breakdown electric field and tunneling electric field as second electrical parameters.

[0135] In other embodiments of this application, the training module 300 is further configured to perform anomaly detection on the electrical parameters of each test structure and determine anomaly values; if the anomaly value corresponds to an interface state density, then the median of all interface state densities except the anomaly value is calculated, and the anomaly value is replaced with the median; if the anomaly value corresponds to a flat band voltage, then the median of all flat band voltages except the anomaly value is calculated, and the anomaly value is replaced with the median; if the anomaly value corresponds to an oxide layer thickness, then the average value of all oxide layer thicknesses except the anomaly value is calculated, and the anomaly value is replaced with the average value; if the anomaly value corresponds to a tunneling electric field, then the anomaly value is replaced with a first preset parameter value; if the anomaly value corresponds to an oxide layer breakdown electric field, then the anomaly value is replaced with a second preset parameter value.

[0136] In other embodiments of this application, the training module 300 is further configured to: construct a first feature matrix corresponding to each test structure based on the defect parameters of each test structure; construct a second feature matrix corresponding to each test structure based on the electrical parameters of each test structure; construct a dataset based on the first feature matrix corresponding to each test structure, the second feature matrix corresponding to each test structure, and a preset test layout; train an initial wafer defect prediction model based on the dataset; adjust the model parameters of the initial wafer defect prediction model through mean square error and mean absolute error to obtain an iteratively optimized wafer defect prediction model.

[0137] Each module in the aforementioned SiC wafer electrical parameter prediction device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0138] In one embodiment of this application, a computer device is provided, which may be a server, and its internal structure diagram may be as follows. Figure 10 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database stores all relevant data for executing an electrical parameter prediction method based on SiC wafer defect distribution. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements an electrical parameter prediction method based on SiC wafer defect distribution.

[0139] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0140] In one embodiment of this application, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the electrical parameter prediction method for SiC wafers in the above embodiments.

[0141] In one embodiment of this application, a computer-readable storage medium is provided, on which a computer program is stored. The computer program is executed by a processor to implement the steps of the electrical parameter prediction method based on SiC wafer defect distribution in the above-described method embodiments.

[0142] In one embodiment of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the electrical parameter prediction method based on SiC wafer defect distribution in the above-described method embodiments.

[0143] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0144] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0145] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0146] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for predicting electrical parameters based on the defect distribution of SiC wafers, characterized in that, The method includes: Based on a preset test layout, obtain the defect parameters of each test structure in the training wafer; Each of the test structures is subjected to electrical tests to obtain the electrical parameters of each test structure; the test structure is obtained by fabricating the wafer based on the preset test layout. A dataset is constructed by using the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure. The initial wafer defect prediction model is then trained to obtain an iteratively optimized wafer defect prediction model. Obtain instance defect parameters and design layout of the wafer to be evaluated, and input the instance defect parameters and design layout into the wafer defect prediction model to obtain the electrical parameters of each design test structure in the wafer to be evaluated; the training wafer and the wafer to be evaluated are SiC wafers.

2. The method for predicting electrical parameters based on SiC wafer defect distribution according to claim 1, characterized in that, The process of obtaining defect parameters for each test structure in the training wafer based on a preset test layout includes: Based on the optical microscope image and photoluminescence spectrum obtained by the semiconductor defect detection equipment, the training wafer is subjected to defect detection to obtain the defect parameters of the training wafer; Based on the preset test layout and the defect parameters of the training wafer, the defect parameters of each test structure are determined; the preset test layout includes multiple test structures.

3. The method for predicting electrical parameters based on SiC wafer defect distribution according to claim 1, characterized in that, The defect parameters include: black dot-shaped defects, surface contaminant particles, surface depressions formed by chemical mechanical polishing over-etching, surface protrusion defects, scratch defects, dot-shaped white etching defects, microtubules, basal dislocations, stacking faults, extended stacking faults, carrot defects, dark field defects, complexes of dark field defects and triangular structures, photoluminescent stacking faults, and triangular defects formed by the segregation of metallic impurities.

4. The method for predicting electrical parameters based on the defect distribution of SiC wafers according to claim 1, characterized in that, The electrical testing of each of the test structures to obtain the electrical parameters of each test structure includes: A capacitance-voltage test is performed on each of the test structures to obtain the first electrical parameters; An oxide layer leakage current test was performed on each of the test structures to obtain the second electrical parameters.

5. The method for predicting electrical parameters based on the defect distribution of SiC wafers according to claim 4, characterized in that, The capacitance-voltage test performed on each of the test structures to obtain the first electrical parameter includes: Capacitance-voltage tests are performed on each target test structure to obtain oxide layer capacitance, low-frequency capacitance, high-frequency capacitance, total charge in the oxide layer, and interface state charge; the target test structure can be any one of multiple test structures. The interface state density is determined based on the oxide layer capacitance, low-frequency capacitance, and high-frequency capacitance. The flat-band voltage is determined based on the total charge in the oxide layer, the interface state charge, and the oxide layer capacitance. The oxide layer thickness is determined based on the oxide layer capacitance and the capacitor plate area. The interface state density, flat band voltage, and oxide layer thickness are used as the first electrical parameters.

6. The method for predicting electrical parameters based on the defect distribution of SiC wafers according to claim 4, characterized in that, The oxide layer leakage current test performed on each of the test structures to obtain the second electrical parameter includes: Oxide layer leakage current test was performed on each target test structure to obtain oxide layer breakdown voltage and tunneling voltage; The breakdown electric field of the oxide layer is determined based on the breakdown voltage and thickness of the oxide layer. The tunneling electric field is determined based on the tunneling voltage and oxide layer thickness. The breakdown electric field and tunneling electric field of the oxide layer are used as the second electrical parameters.

7. The method for predicting electrical parameters based on SiC wafer defect distribution according to claim 1, characterized in that, Before constructing a dataset using the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and training the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model, the process further includes: Anomaly detection was performed on the electrical parameters of each test structure to identify outliers; If the outlier corresponds to the interface state density, then the median of all interface state densities except the outlier is calculated, and the outlier is replaced with the median. If the outlier corresponds to a flat band voltage, then the median of all flat band voltages excluding the outlier is calculated, and the outlier is replaced with the median. If the outlier corresponds to the oxide layer thickness, then calculate the average value of all oxide layer thicknesses except for the outlier, and replace the outlier with the average value; If the outlier corresponds to a tunneling electric field, then the outlier is replaced with the first preset parameter value; If the abnormal value corresponds to the breakdown electric field of the oxide layer, then the abnormal value is replaced with the second preset parameter value.

8. The method for predicting electrical parameters based on the defect distribution of SiC wafers according to claim 1, characterized in that, The process involves constructing a dataset using the defect parameters of each test structure, a preset test layout, and the electrical parameters of each test structure, and then training the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model, including: Based on the defect parameters of each test structure, a first feature matrix is ​​constructed for each test structure; the first feature matrix is ​​a 15-dimensional feature matrix with respect to the defect parameters. Based on the electrical parameters of each test structure, a second feature matrix is ​​constructed for each test structure; the second feature matrix is ​​a 5-dimensional feature matrix with respect to the electrical parameters. Construct a dataset based on the first feature matrix and the second feature matrix corresponding to each test structure; The initial wafer defect prediction model is trained based on the dataset. The model parameters of the initial wafer defect prediction model are adjusted by the mean square error and the mean absolute error to obtain an iteratively optimized wafer defect prediction model. The initial wafer defect prediction model uses a 5-layer fully connected network constructed from a fully connected deep neural network (DNN); The defect parameters include: black dot-shaped defects, surface contaminant particles, surface depressions formed by chemical mechanical polishing over-etching, surface protrusion defects, scratch defects, dot-shaped white etching defects, microtubules, basal dislocations, stacking faults, extended stacking faults, carrot defects, dark field defects, complexes of dark field defects and triangular structures, photoluminescent stacking faults, and triangular defects formed by segregation of metal impurities. The electrical parameters include a first electrical parameter and a second electrical parameter. The first electrical parameter includes the interface state density, flat band voltage, and oxide layer thickness. The second electrical parameter includes the oxide layer breakdown electric field and tunneling electric field.

9. An electrical parameter prediction device based on SiC wafer defect distribution, characterized in that, The electrical parameter prediction device based on SiC wafer defect distribution includes: The acquisition module is used to acquire the defect parameters of each test structure in the training wafer based on a preset test layout; The testing module is used to perform electrical tests on each of the test structures to obtain the electrical parameters of each test structure; the test structure is obtained by fabricating the wafer based on the preset test layout; The training module is used to construct a dataset using the defect parameters of each test structure, the preset test layout, and the electrical parameters of each test structure, and to train the initial wafer defect prediction model to obtain an iteratively optimized wafer defect prediction model. The verification module is used to obtain instance defect parameters and design layout of the wafer to be evaluated, and input the instance defect parameters and design layout into the wafer defect prediction model to obtain the electrical parameters of each design test structure in the wafer to be evaluated; the training wafer and the wafer to be evaluated are SiC wafers.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

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