A tunable laser chip integrated with quantum dot array and a preparation method thereof

Abstract

The application provides a tunable laser chip integrated with a quantum dot array and a preparation method, and relates to the technical field of laser chips.The chip comprises a substrate and a semiconductor laminated structure grown on the substrate.The semiconductor laminated structure comprises a central core light emitting channel and a gradient band gap buffer protection layer formed integrally with the core light emitting channel in the lateral direction.The protection layer is formed by low-temperature selective impurity ion implantation and rapid thermal annealing technology, so that the quantum dots and the potential barrier material on both sides of the core light emitting channel are mixed atomically, forming a continuous single crystal structure with an energy band width gradually increasing outward.The gradient structure can be divided into a band gap gradual transition zone and a wide band gap mixed zone.Through the built-in structure, the sidewall defects introduced by the traditional etching process are eliminated, the leakage current is significantly suppressed, and the service life of the chip is prolonged.The gradient structure effectively buffers the mechanical stress generated by the difference in the thermal expansion coefficients of different materials, greatly improving the thermal stability and the anti-electric breakdown capability of the chip.

Description

Technical Field

[0001] This invention relates to the field of laser chip technology, specifically to a tunable laser chip with an integrated quantum dot array and its fabrication method. Background Technology

[0002] According to Chinese Patent No. CN102659070B, an integrated photonic chip and its fabrication method are disclosed. First, a tunable laser based on a nanowire array, an integrated waveguide-type optical isolator, a surface plasmon-based optical coupler, and a photodetector are fabricated, and these devices are made into individual 'sub-chips'. Based on this, these individual 'sub-chips' are integrated onto the same 'mother chip' using a hybrid integration method to form the integrated photonic chip.

[0003] According to Chinese Patent No. CN115799991A, a laser chip with discrete sidewall gratings and its fabrication method are disclosed. The laser chip includes, along the epitaxial growth direction of the chip, a substrate layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer, and a ridge waveguide; and a grating, wherein the grating is a discrete nanopillar grating composed of discrete nanopillars located near the sidewall of the ridge waveguide. This invention, by simultaneously etching the ridge waveguide and the discrete nanopillar grating, simplifies the etching process. Furthermore, separating the grating from the sidewalls avoids increasing the sidewall area of ​​the laser chip, reduces defect recombination, and ensures the abrupt change in refractive index. This effectively improves the grating's control over the optical field, thereby achieving the narrow linewidth and wavelength tunable characteristics of a semiconductor laser.

[0004] The aforementioned patent documents and prior art have the following technical problems when used:

[0005] Question 1: In the manufacturing process of traditional laser chips, multiple epitaxial, etching, and dielectric deposition steps introduce a large number of surface states and defects on the sidewalls and key interfaces of the active region (the region where quantum dots are located). These defects are the main channels for leakage current and the root cause of chip performance degradation (aging) during long-term operation. Current and heat will concentrate at these defects, accelerating material degradation.

[0006] Question 2: Chips are made of a variety of different materials with different coefficients of thermal expansion. When the chip is working, the heat generated by the chip will cause huge mechanical stress between the layers. This stress will cause the lattice of the quantum dot region to deform, affecting its light-emitting properties. In severe cases, it may even cause micro-cracks and permanent damage.

[0007] Question 3: Traditional electrode and insulation layer structures have limited protection capabilities when encountering static electricity or surges. The electric field tends to concentrate at sharp boundaries or defects in the material, leading to localized electrical breakdown. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention provides a tunable laser chip with an integrated quantum dot array and its fabrication method, solving the problems mentioned in the background section.

[0009] To achieve the above objectives, the present invention provides the following technical solution: a tunable laser chip integrating a quantum dot array, the tunable laser chip comprising a substrate and a semiconductor stack structure grown thereon, the semiconductor stack structure comprising, in the lateral direction:

[0010] The core light-emitting channel, located in the center, is composed of quantum dots and barrier materials that maintain the original epitaxial structure.

[0011] A gradient bandgap buffer protection layer, which is integrated with the core light-emitting channel, is formed on both sides of the core light-emitting channel;

[0012] The gradient bandgap buffer protection layer is a semiconductor alloy region formed by atomic phase mixing of the quantum dots and the barrier material. Its bandgap gradually increases from the adjacent core light-emitting channel outwards, and forms a continuous single crystal structure with the core light-emitting channel.

[0013] Preferably, the gradient bandgap buffer protective layer is further divided laterally into:

[0014] The bandgap gradient transition region adjacent to the core light-emitting channel exhibits a gradient distribution in the degree of phase mixing between quantum dots and barrier materials.

[0015] And a wide bandgap mixing region located outside the bandgap gradient transition region, in which quantum dots and barrier materials are completely mixed.

[0016] Preferably, the wide bandgap hybrid region is a quaternary and pentagonal semiconductor alloy, whose lattice constant and coefficient of thermal expansion are between those of the quantum dot material and the barrier material of the core light-emitting channel.

[0017] Preferably, the tunable laser chip further includes a tuning electrode disposed above the semiconductor stacked structure, and the gradient bandgap buffer protection layer serves as an electrical isolation layer and a thermal stress buffer layer between the tuning electrode and the core light-emitting channel.

[0018] Preferably, the fabrication method of the tunable laser chip is as follows:

[0019] Sp1: A semiconductor stack structure containing a multilayer quantum dot array is epitaxially grown on a substrate;

[0020] Sp2: Provide an ion implantation mask, wherein the mask is an opaque area at the position corresponding to the core light-emitting channel of the future chip, and a transparent area at the position corresponding to the wide bandgap mixing region of the future chip;

[0021] Sp3: Selective, low-dose impurity ion implantation is performed on the semiconductor stacked structure through the ion implantation mask, so that the impurity ions are implanted only into the region where the gradient bandgap buffer protection layer is to be formed, while the region where the core light-emitting channel is to be formed is not implanted.

[0022] Sp4: After removing the mask, the entire chip wafer is subjected to a low-temperature rapid thermal annealing process. This annealing causes the quantum dots in the impurity-implanted region to mix with the barrier material, forming the wide bandgap mixing region, while the region without impurity implantation retains the original quantum dot structure, forming the core light-emitting channel.

[0023] Sp5: After completing the phase-mixed semiconductor stacked structure, subsequent ridge waveguide etching, insulating layer filling, electrode fabrication, and passivation processes are performed.

[0024] Preferably, the impurity ions implanted in the Sp3 are electrically neutral atoms selected from boron atoms, fluorine atoms, and phosphorus atoms.

[0025] Preferably, the ion implantation mask used in Sp2 has a specially treated, contour-blurred semi-transparent structure in the region corresponding to the junction of the core luminescent channel and the gradient bandgap buffer protection layer, in order to form a laterally gradient impurity ion concentration distribution.

[0026] Preferably, the set temperature for the low-temperature rapid thermal annealing in Sp4 is higher than the activation temperature required for impurity-induced atomic phase mixing, while being lower than the thermal degradation temperature at which the quantum dot material suffers structural damage.

[0027] Preferably, the etching depth of the ridge waveguide etching process in Sp5 is precisely controlled to ensure that the two sidewalls of the finally formed ridge waveguide are completely located within the wide gap mixing region formed by atomic phase mixing.

[0028] Preferably, the ion implantation in Sp3 is at an angle, with the implantation direction having a preset angle with the surface normal of the semiconductor stacked structure, in order to control the scattering range of impurity ions in the lateral direction, thereby assisting in the formation of the transition region with the bandgap gradient.

[0029] This invention provides a tunable laser chip with an integrated quantum dot array and its fabrication method. It offers the following advantages:

[0030] 1. This invention employs low-temperature selective quantum well phase mixing technology to generate a gradient bandgap buffer protective layer in situ on both sides of the core light-emitting channel of the chip. Unlike the physical sidewalls and external passivation formed by etching in traditional processes, the protective layer in this solution is a continuous single-crystal structure with the core light-emitting channel, fundamentally eliminating surface states and defects caused by etching. This protective layer has a high bandgap, forming a natural energy barrier that firmly "traps" injected electrons and holes within the core light-emitting region, greatly suppressing lateral leakage current. Therefore, current and heat are no longer concentrated at the defect site, eliminating non-radiative recombination at the source and significantly slowing down the degradation rate of the chip material. Through this method, this invention solves the problems of high leakage current, low luminous efficiency, and long-term performance degradation caused by interface defects in traditional technologies, greatly improving the chip's lifespan and reliability.

[0031] 2. This invention employs a built-in gradient bandgap buffer protection layer, which is formed by atomic phase mixing. Its lattice constant and thermal expansion coefficient are between those of the quantum dot material and the barrier material in the core light-emitting channel, forming a perfect "stress spring". When the chip generates mechanical stress due to heat during operation, this gradient lattice structure can absorb and release stress step by step, avoiding stress concentration at a single material interface. This effectively protects the quantum dot lattice in the core light-emitting channel from deformation or damage. In addition, this built-in structure enables the chip to maintain excellent thermal stability under extreme temperature changes. Its high characteristic temperature ensures that the light-emitting characteristics are not affected by the ambient temperature, fundamentally solving the problem of lattice damage and performance degradation caused by thermal stress.

[0032] 3. This invention employs a high-energy bandgap built-in buffer protective layer as an electrical isolation layer between the tuning electrode and the core light-emitting channel. This protective layer is formed by completely mixing quantum dots and barrier materials, and its bandgap is more than 100 millielectron volts higher than that of the core region, forming an extremely high electrical energy barrier. It can not only effectively confine charge carriers, but more importantly, its smooth, defect-free single-crystal characteristics avoid the electric field concentration effect that is prone to occur at material interfaces or sharp boundaries in traditional insulating layers. When the chip encounters static electricity or surge, this built-in protective layer can effectively disperse the electric field and prevent local electrical breakdown, providing a robust electrical barrier for the core light-emitting channel. This fundamentally improves the chip's anti-static and anti-surge capabilities, ensuring the stability and long-term reliability of the device. Attached Figure Description

[0033] Figure 1 This is a structural diagram of the tunable laser chip of the present invention;

[0034] Figure 2 This is a diagram illustrating the chip fabrication method of the present invention;

[0035] Figure 3This is a cross-sectional view of the front of the chip of the present invention.

[0036] The components include: 1. Substrate; 2. Semiconductor stacked structure; 3. Core light-emitting channel; 4. Gradient bandgap buffer protection layer; and 5. Tuning electrode. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Specific Implementation Example 1:

[0039] like Figures 1 to 3 As shown, a tunable laser chip integrating a quantum dot array is disclosed. The tunable laser chip includes a substrate 1 and a semiconductor stacked structure 2 grown thereon. The semiconductor stacked structure 2 includes, in the lateral direction: a central core light-emitting channel 3, which is composed of quantum dots and barrier materials maintaining the original epitaxial structure; and a gradient bandgap buffer layer 4 integrated with the core light-emitting channel 3, which is formed on both sides of the core light-emitting channel 3. The gradient bandgap buffer layer 4 is a semiconductor alloy region formed by atomic phase mixing of quantum dots and barrier materials. Its bandgap gradually increases from the adjacent core light-emitting channel 3 outwards, forming a continuous single-crystal structure with the core light-emitting channel 3. The gradient bandgap buffer protection layer 4 is further divided laterally into: a bandgap gradient transition region adjacent to the core light-emitting channel 3, in which the degree of mixing between quantum dots and barrier materials is gradient distributed; and a wide bandgap mixing region located outside the bandgap gradient transition region, in which quantum dots and barrier materials are completely mixed. The wide bandgap mixing region is a quaternary and pentagonal semiconductor alloy, whose lattice constant and thermal expansion coefficient are between those of the quantum dot material and the barrier material of the core light-emitting channel 3. The tunable laser chip also includes a tuning electrode 5 disposed above the semiconductor stacked structure 2. The gradient bandgap buffer protection layer 4 serves as an electrical isolation layer and a thermal stress buffer layer between the tuning electrode 5 and the core light-emitting channel 3.

[0040] Substrate 1, located at the bottom of the chip, serves as the foundation for the growth of all epitaxial layers. It is typically a 3- or 4-inch diameter N-type doped indium phosphide single-crystal wafer with a thickness of approximately 350 to 500 micrometers. This is because the lattice constant of indium phosphide is highly compatible with indium arsenide quantum dots and related barrier materials used in the 1.3 to 1.55 micrometer communication band. This ensures the subsequent growth of a high-quality, low-defect single-crystal semiconductor stack structure 2 on it. Furthermore, indium phosphide possesses excellent cleavage properties, facilitating the fabrication of the flat reflective cavity surface required for lasers. N-type doping elements are usually sulfur and silicon because, in the PIN junction structure of the laser, substrate 1 needs to serve as the common negative electrode (N-electrode) for the entire device. N-type doping provides good electronic conductivity, facilitating the formation of low-resistance ohmic contacts. The semiconductor stack structure 2, the functional core built layer by layer on the indium phosphide substrate 1 using epitaxial growth technology, mainly includes a lower cladding layer, a lower waveguide confinement layer, and a quantum doped layer. The system consists of a dot array active region, an upper waveguide confinement layer, and an upper cladding layer. The lower cladding layer is grown directly on substrate 1 and is typically 1.5 to 2.0 micrometers thick. It is made of N-type doped indium phosphide, whose low refractive index acts as the first "light wave reflector" for light waves with a center wavelength of 1.55 micrometers. When light propagates in a medium with a high refractive index, it undergoes total internal reflection when it encounters a medium with a low refractive index. This thick, low-refractive-index cladding layer ensures that light waves do not leak into substrate 1, which has a high absorptivity, thus confining the light energy firmly to the central region in the vertical direction. The lower waveguide confinement layer is an undoped indium gallium arsenide phosphide quaternary alloy grown on the lower cladding layer. It is 150 nanometers thick and has a refractive index higher than that of the lower cladding layer but lower than that of the barrier layer of the active region. Its function is similar to a gentle slope, allowing the light field mode from the cladding layer to smoothly transition and focus onto the smaller active region, thereby maximizing the coupling of light field energy.

[0041] The active region of the quantum dot array is the heart of the chip, located at the very center of the entire stack. It consists of five layers of indium arsenide quantum dot thin films and six layers of indium phosphide barrier layers stacked alternately. The planar density of each quantum dot layer is approximately 5 x 10^10 quantum dots per square centimeter, the height of each quantum dot is approximately 5 to 7 nanometers, and the thickness of each barrier layer is 35 nanometers. The quantum dots serve as the light-emitting medium. In this structure, the indium arsenide quantum dots form a three-dimensional quantum confinement, with discrete energy levels. This results in extremely high electron-hole recombination luminescence efficiency. The gain of a single quantum dot layer is insufficient to overcome the cavity loss of the laser; multi-layer stacking effectively increases the total volume of the gain medium, providing sufficient mode gain to achieve laser lasing. The 35-nanometer-thick indium phosphide barrier layer... Its thickness is carefully selected. It must be thick enough to prevent tunneling coupling of the electronic wavefunction between adjacent quantum dots, ensuring the independence of each quantum dot layer. At the same time, it cannot be too thick to ensure that the injected charge carriers can be transported smoothly and effectively captured by each quantum dot layer. Under current injection, electrons and holes recombine within the quantum dots, generating stimulated emission, which is the source of laser gain. The natural non-uniformity of the quantum dot size provides it with a broad gain spectrum, which is the basis for achieving tunability. The upper waveguide confinement layer and the upper cladding layer correspond to the lower waveguide confinement layer and the lower cladding layer, respectively, and are symmetrically grown on the active region. The difference is that the upper cladding layer is P-type doped, and the doping element is usually zinc, which serves as a channel for injected holes and forms P-electrode contacts.

[0042] The aforementioned semiconductor stacked structure 2 forms three closely connected, seamless regions in the lateral direction, collectively constituting a "ridge waveguide" body typically 2 to 3 micrometers wide. The core light-emitting channel 3 is located on the central axis of the device, forming a strip-shaped region 1.2 micrometers wide. The semiconductor stacked structure 2 in this region remains unmodified, completely retaining its original state after high-quality epitaxial growth. This is the only path for laser gain generation, light wave oscillation, and propagation along the length direction. The gradient bandgap buffer layer 4 is not an independent layer, but rather a region formed by the semiconductor stacked material on both sides of the core light-emitting channel 3 after "phase mixing" modification. It is related to... The core light-emitting channel 3 is a single crystal without any physical interfaces. Its core function is to absorb and buffer mechanical stress from the upper electrodes and the packaging process, protecting the quantum dot lattice of the core region. Its wider energy band forms an extremely high energy barrier, firmly "trapping" the injected electrons and holes within the core light-emitting channel 3, preventing leakage current and thus improving luminous efficiency. Furthermore, because it is "generated" inside the epitaxial layer, rather than being physically etched from the outside, it fundamentally eliminates surface defects and non-radiative recombination centers caused by the etching process. It includes a bandgap gradient transition region and a wide bandgap mixing region, with the bandgap gradient transition region closely attached to the core light-emitting channel. On both sides of channel 3, each approximately 0.3 micrometers wide, the concentration of injected impurities and the degree of atomic phase mixing are gradually varied. This results in a smooth and continuous increase in the semiconductor bandgap width from the core outwards. The reason for choosing a gradual rather than abrupt change is that a smooth energy barrier can most gently confine the charge carriers, avoiding carrier reflection and interface charge accumulation that may be caused by abrupt barrier changes. At the same time, a gradually changing lattice constant structure can release stress step by step like a spring, avoiding stress concentration at a single interface. The wide bandgap mixing region is located outside the transition region, each approximately 0.5 micrometers wide. The atomic phase mixing is most thorough in this region, and the original... The quantum dot structure has completely disappeared, forming a uniform, new quaternary or quinary semiconductor alloy with a band width that is more than 100 millielectron volts higher than that of the core light-emitting channel 3. The uniform alloy formed in this region is preferably made of quaternary or quinary alloys such as indium gallium arsenide phosphide or aluminum gallium indium arsenide formed by the intermingling of atoms in the main lattice. It has excellent stability and physical properties. The reason for choosing complete mixing is that a sufficiently high energy barrier needs to be formed to effectively block the lateral leakage of charge carriers under high temperature operation. At the same time, the uniform composition of the alloy is formed, and its physical properties such as thermal conductivity and coefficient of thermal expansion are determined, which is convenient for thermal and stress simulation design.

[0043] The top-level device structure includes an insulating and planarization layer and a tuning electrode 5. The insulating and planarization layer is located on both sides of the ridge waveguide structure, filled with dielectrics such as silicon dioxide and silicon nitride. The entire chip surface is chemically and mechanically polished to form a flat surface, providing a flat platform for the fabrication of the upper metal electrode and providing additional electrical isolation. The tuning electrode 5 is fabricated on the planarized chip surface, facing the ridge waveguide below, with a titanium-platinum-gold three-layer metal electrode. This electrode serves as both a P-electrode for injecting current into the active region and can also be designed as a micro-heater to fine-tune the laser wavelength by changing the local temperature, thus achieving tunability. The titanium layer is used to form a good ohmic contact with p-type indium phosphide, and the platinum layer acts as a barrier layer to prevent gold atoms from diffusing into the semiconductor. The gold layer has excellent conductivity and oxidation resistance, facilitating subsequent wire bonding. The metal strip itself also has a certain resistance. When wavelength tuning is required, an independent DC current can be passed through it to generate Joule heating as a micro-heater. Through the thermo-optic effect, the refractive index of the lower waveguide is changed, thereby achieving laser wavelength tuning. Specific Implementation Example 2:

[0045] like Figures 1 to 3 As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0046] The specific method for fabricating tunable laser chips is as follows:

[0047] Sp1: A semiconductor stacked structure 2 containing a multilayer quantum dot array is epitaxially grown on a substrate 1;

[0048] Using a metal-organic chemical vapor deposition (MOCVD) system, high-quality single-crystal thin films are grown layer by layer on an N-type indium phosphide substrate 1 according to the aforementioned “semiconductor stack structure 2” design. The entire process is carried out under ultra-high vacuum protection, with a growth temperature of approximately 450 to 600 degrees Celsius. During the growth process, real-time monitoring can be achieved using techniques such as reflective high-energy electron diffraction to ensure atomic-level flatness and thickness control.

[0049] Sp2: Provides an ion implantation mask. The mask is opaque at the position corresponding to the core light-emitting channel 3 of the future chip, and transparent at the position corresponding to the wide bandgap mixing region of the future chip. The ion implantation mask used in Sp2 has a specially treated semi-transparent structure with blurred contour edges in the region corresponding to the junction of the core light-emitting channel 3 and the gradient bandgap buffer protection layer 4, in order to form a laterally gradient impurity ion concentration distribution.

[0050] After the semiconductor stack growth is completed, a 300-nanometer-thick layer of silicon nitride is first deposited on the wafer surface by plasma-enhanced chemical vapor deposition, and a 1.5-micrometer-thick layer of photoresist is then spin-coated on top of it. Subsequently, a stepper lithography machine and a specially made grayscale mask with a grayscale gradient pattern on the edge are used for precise exposure. After development, the photoresist is partially removed and used as a mask. The pattern is then transferred to the underlying silicon nitride layer by reactive ion etching, ultimately forming a high-hardness ion implantation mask with blurred window edge contours. This mask is ingeniously designed to completely cover the area corresponding to the future core light-emitting channel 3 and expose the area of ​​the future gradient bandgap buffer protection layer 4.

[0051] Sp3: Selective, low-dose impurity ion implantation is performed on the semiconductor stacked structure 2 using an ion implantation mask, so that the impurity ions are implanted only into the region where the gradient bandgap buffer protection layer 4 is to be formed, while the region where the core light-emitting channel 3 is to be formed is not implanted. The impurity ions implanted in Sp3 are electrically neutral atoms selected from boron atoms, fluorine atoms and phosphorus atoms. The ion implantation in Sp3 is tilted angle implantation, and the implantation direction has a preset angle with the surface normal of the semiconductor stacked structure 2, in order to control the scattering range of impurity ions in the lateral direction, so as to assist in the formation of a transition region with a gradual bandgap.

[0052] A wafer with a mask is fed into an ion implanter. Neutral, low-atomic-weight ions such as boron (B) are selected to avoid unnecessary electrical doping of the semiconductor. The implantation energy (30-100 kiloelectron volts) and implantation dose (1 x 10⁻⁶) are set. 13 Up to 1x10 15 The implantation energy (ions / cm²) determines the penetration depth of the impurities, while the dosage determines the degree of subsequent phase mixing. To create a more uniform lateral gradient, tilted implantation can be used, for example, implanting the ion beam at a 7-degree angle to the wafer normal.

[0053] Sp4: After removing the mask, the entire chip wafer undergoes a low-temperature rapid thermal annealing process. This annealing causes the quantum dots in the impurity-injected region to mix with the barrier material, forming a wide-bandgap mixing region. Meanwhile, the region without impurity injection retains the original quantum dot structure, forming the core light-emitting channel 3. The set temperature of the low-temperature rapid thermal annealing in Sp4 is higher than the activation temperature required for impurity-induced atomic phase mixing, while being lower than the thermal degradation temperature at which the quantum dot material suffers structural damage.

[0054] After the mask is stripped, the wafer is fed into a rapid thermal annealing apparatus. In an atmosphere filled with high-purity nitrogen and trace amounts of phosphine (to protect the surface of indium phosphide), the wafer is heated from room temperature to the set annealing temperature (650 to 750 degrees Celsius) at an extremely fast rate (100-200 degrees Celsius / second) and held for 30 to 90 seconds, followed by rapid cooling. This brief and precise thermal shock is sufficient to activate atomic phase mixing in the implanted region, but not enough to destroy the quantum dot structure in the unimplanted region.

[0055] Sp5: On the semiconductor stacked structure 2 after phase mixing is completed, subsequent ridge waveguide etching, insulating layer filling, electrode fabrication and passivation processes are performed. In the ridge waveguide etching process in Sp5, the etching depth is precisely controlled to ensure that the two sidewalls of the finally formed ridge waveguide are completely located within the wide gap mixing region formed by atomic phase mixing.

[0056] After the aforementioned core steps, the wafer possesses a built-in protective structure. Subsequent processes are similar to standard semiconductor laser processes, including inductively coupled plasma dry etching to form the ridge waveguide, plasma-enhanced chemical vapor deposition to fill the silicon dioxide insulating layer, chemical mechanical polishing for global planarization, and fabrication of the top titanium-platinum-gold electrodes through electron beam evaporation and lift-off processes. In the ridge waveguide etching operation, inductively coupled plasma dry etching technology is used to etch the shape of the ridge waveguide onto the wafer surface. The etching depth is precisely controlled to ensure the ridge's integrity. The sidewalls fall within the already formed "wide bandgap hybrid region". In the insulating layer filling and planarization operation, silicon dioxide is deposited using plasma-enhanced chemical vapor deposition technology, and then the surface is smoothed by chemical mechanical polishing. In the electrode fabrication operation, multilayer metals (titanium / platinum / gold) are deposited by photolithography, electron beam evaporation and magnetron sputtering. Finally, electrodes and pads with precise patterns are formed by a lift-off process. In the back electrode and dicing operation, after the wafer is thinned, N-type ohmic contact electrodes are deposited on the back side. Finally, independent laser chips are formed by dicing and dicing. Specific Implementation Example 3:

[0058] like Figures 1 to 3 As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0059] The preparation method steps will be broken down in detail below:

[0060] Sp1: Epitaxial growth;

[0061] On an N-type indium phosphide substrate 1, a semiconductor stack structure 2 was atomically precisely grown. The equipment used was a CRIUS II-L type metal-organic chemical vapor deposition (MOCVD) system manufactured by AIXTRON GmbH, Germany. The source materials were trimethylindium, trimethylgallium, high-purity arsine, high-purity phosphine, diluted silane for N-type doping, and diethylzinc for P-type doping.

[0062] Indium phosphide substrate 1 was fed into the reaction chamber through the sample introduction chamber and baked at 650 degrees Celsius for 10 minutes in a hydrogen atmosphere to remove surface oxides. The temperature was then lowered to 600 degrees Celsius to begin growing the lower cladding and lower waveguide confinement layer. The temperature was then lowered to 480 degrees Celsius to grow the active region of the indium arsenide quantum dot array. An alternating power supply growth mode was adopted, i.e., the phosphine gas flow was turned off during quantum dot growth and the arsenine gas flow was turned off during barrier layer growth to form a steep interface. The temperature was then raised again to 600 degrees Celsius to complete the growth of the upper waveguide confinement layer and upper cladding. The entire growth process was monitored in real time by an in-situ laser reflection monitoring system. The thickness of each layer was accurately determined by the interference fringes of the reflected signal. After growth, samples were taken for high-resolution X-ray diffraction testing. The sharpness and spacing of the satellite peaks indicated extremely high crystal quality and periodicity. At the same time, the surface was examined by atomic force microscopy, and its root mean square roughness should be less than 0.2 nanometers.

[0063] Sp2 and Sp3: Selective impurity injection;

[0064] A specific dose of boron ions is precisely implanted into a preset buffer protection layer region, and its lateral concentration distribution presents a preset gradient. The equipment used is ASML's TWINSCAN NXT series deep ultraviolet (DUV) lithography machine and Applied Materials' Varian VIISta HCP type ion implanter. The materials used are high-hardness silicon nitride thin film and special grayscale lithography mask.

[0065] 300 nm silicon nitride was deposited on an epitaxial wafer. After spin-coating photoresist, exposure was performed using a grayscale mask. This mask achieved a continuous light intensity variation of 10% to 90% on the stripes of the corresponding transition region through a sub-resolution chromium dot array. After development and etching, an implantation window with a smooth ramp edge was formed on the silicon nitride. The wafer with the silicon nitride mask was loaded into an ion implanter. To suppress channeling effects, the wafer stage was tilted 7 degrees and rotated 22.5 degrees. The implantation energy of boron-11 ions was set to 85 kEV, and the implantation dose was 6 x 10^13 ions per square centimeter. The energy of electron volts ensures that the peak boron ion concentration is precisely located at the center of the multilayer quantum dot stack. A dose of 6 x 10^13 is a key parameter for achieving a 60 nm blue shift. Tilting and rotation are used to deflect the incident direction of the ion beam off the main axis of the lattice, entering an "amorphous" implantation mode, thereby obtaining a predictable and highly repeatable implantation profile. On the same batch of test wafers, destructive testing is performed using secondary ion mass spectrometry (SIMS). The measured boron atom concentration distribution curve with depth must match the simulation results of TRIM software based on the Monte Carlo algorithm within a 10% error range.

[0066] Sp4: Low-temperature rapid thermal annealing;

[0067] The atomic phase mixing of the injection region is activated in the shortest possible time while protecting the quantum dot structure of the core light-emitting channel 3 to the maximum extent. The equipment is AnnealSys' AS-One Rapid Thermal Annealing (RTA) system, and the atmosphere is high-purity nitrogen and a mixture of phosphine and nitrogen with a volume fraction of 5%.

[0068] The wafer is placed on a graphite support and placed into a nitrogen-filled quartz furnace. The program is started, raising the temperature from room temperature to 710 degrees Celsius at a rate of 150 degrees Celsius per second. At the plateau temperature of 710 degrees Celsius, it is precisely held for 60 seconds, during which time phosphine is continuously introduced. After the holding period, the power to the heating lamp is immediately cut off, and the wafer is rapidly cooled with nitrogen. The combination of 710 degrees Celsius and 60 seconds constitutes a precise "thermal budget," providing sufficient energy-time to drive the migration of lattice vacancies induced by boron ions, thereby achieving atomic phase mixing. Shorter times or lower temperatures result in insufficient mixing; longer times or higher temperatures cause the quantum dots in the unimplanted regions to begin thermal decomposition, affecting device performance. The core judgment method is a full-wafer scan of the micro-area photoluminescence spectrum (μ-PL). The wavelength blue shift distribution map must meet the following requirements: the blue shift in the core luminescent channel 3 region is less than 5 nanometers, the blue shift in the wide bandgap mixing region is between 55 and 65 nanometers, and the transition region shows a smooth gradient change. Any wafer with abnormal spots or inhomogeneity will be judged as unqualified.

[0069] Sp5: Subsequent component processing;

[0070] The final device is fabricated on the wafer with the built-in protection structure already formed, using the Cobra series inductively coupled plasma dry etching (ICP-RIE) machine from Oxford Instruments and the Delta series plasma enhanced chemical vapor deposition (PECVD) machine from SPTS.

[0071] The ridge waveguide etching employed a chlorine / methane / hydrogen-based etching formulation. The etching depth was monitored in real-time using a laser interferometer, automatically stopping when the target depth of 2.2 micrometers was reached. After etching, the cross-section was examined using a scanning electron microscope, confirming that the ridge's sidewall steepness was greater than 88 degrees and its position fell within the wide bandgap mixing region defined by photoluminescence spectroscopy, with an alignment error of less than 0.1 micrometers. Insulating layer filling and electrode fabrication were completed using standard PECVD, chemical mechanical polishing (CMP), electron beam evaporation, and lift-off processes. Four-probe stage and transmission line model (TLM) testing ensured that the contact resistivity of the P-electrode was less than 1 x 10⁻⁵ ohms per square centimeter. Specific Implementation Example 4:

[0073] like Figures 1 to 3 As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0074] This experiment aims to systematically verify the unique advantages of this application in solving problems related to interface defects, mechanical stress, and electrical stability by comparing three groups of tunable laser chips manufactured using different processes.

[0075] This experiment will prepare three different sets of tunable laser chips, each containing at least 20 representative samples to ensure the statistical validity of the data:

[0076] Existing technology comparison group (Group A): On an N-type indium phosphide substrate, a semiconductor stack structure containing a quantum dot array is grown by metal-organic chemical vapor deposition. Inductively coupled plasma dry etching technology is used to directly etch the semiconductor stack into a ridge waveguide structure. Plasma-enhanced chemical vapor deposition technology is used to deposit silicon nitride as an external passivation layer and fill it on both sides of the ridge waveguide to complete the fabrication of the top Ti / Pt / Au metal electrode and the back N electrode. In traditional manufacturing processes, chip performance depends on the external passivation layer, but sidewall etching defects cannot be eliminated, and stress problems are prominent. This group of samples is used to represent the problems existing in traditional technologies.

[0077] The simplified comparison group (Group B) is the same as Group A. A semiconductor stacked structure is grown, and a simple, grayscale-free mask is used for high-dose, uniform boron ion implantation. The implantation area covers both sides of the future ridge waveguide. A low-temperature rapid thermal annealing is performed to completely mix the quantum dots in the implanted area, forming a uniform wide bandgap mixing region, but without forming a gradient bandgap transition region. The ridge waveguide is etched, and the etching depth is precisely controlled within the wide bandgap mixing region to ensure that the sidewalls are located within the built-in passivation layer. The insulating layer filling and electrode fabrication are then completed. This group of chips has a built-in atomic phase mixing passivation layer, which effectively reduces the defects introduced by etching. However, it lacks a gradient structure, and the effects of stress buffering and smoothing carrier confinement are limited. This group of samples is used to demonstrate the effectiveness of the built-in passivation itself.

[0078] This innovative approach (Group C) is similar to Groups A and B, growing a semiconductor stacked structure and using a grayscale mask for selective, low-dose boron ion implantation. The implanted region has a gradually changing concentration distribution at its edges. A low-temperature rapid thermal annealing process is then performed, causing a gradual phase mixing in the implanted region to form a complete gradient bandgap buffer protection layer. Inductively coupled plasma etching (ICP-C) is used, with precise control over the etching depth to ensure that the sidewalls of the ridge waveguide are completely within the built-in wide bandgap mixing region. Insulating layer filling and electrode fabrication are then completed. This group of chips is fabricated entirely according to the innovative approach of this application, possessing a gradient bandgap buffer protection layer that integrates defect passivation, carrier confinement, and stress buffering, theoretically offering the superior performance. This group of samples is used to demonstrate the superiority of the complete innovative approach.

[0079] Experimental equipment list: Microscopic needle bending stage (with temperature control module), semiconductor parameter analyzer (such as Keithley 2400 series source meter), high-precision optical power meter, spectrometer, high-temperature oven, electrostatic discharge (ESD) tester;

[0080] Detailed testing steps:

[0081] Step 1: Initial Performance Testing: Place the chip sample on a bending stage, precisely contact the P and N electrodes with a probe, and inject current using a source meter in a stepwise manner (e.g., from 0mA to 50mA in 1mA steps). Simultaneously use an optical power meter and a spectrum analyzer to record the output optical power, voltage, and spectrum corresponding to each current point. Plot the optical power-current (LI) and voltage-current (VI) curves based on the data, and record the threshold current (VI). ), slope efficiency and output wavelength;

[0082] Step Two: Accelerated Aging Test: Place the three sets of chips in a high-temperature oven set at 85°C, and provide each chip with a high-stress current (3× The oven is continuously powered on, and every 24 hours, a representative portion of the chips is removed from the oven for initial performance testing in step one. The change in threshold current is recorded, and the test continues until the threshold current growth rate reaches the set threshold or the oven runs for 1000 hours. The change curve of threshold current over time is recorded.

[0083] Step 3: Thermal Stability Test: Place the chip back on the bending stage and, using the temperature control module, gradually increase the chip temperature from 25°C to 85°C (measurement every 10°C). At each temperature point, maintain the injected current at 1.5 × Record the threshold current and center wavelength at each temperature point, and calculate the characteristic temperature based on the recorded data. and wavelength shift rate;

[0084] Step 4: Electrostatic Discharge (ESD) Test: Place a portion of the chips from the three groups on the ESD test bench. Using a human body model (HBM) electrostatic discharge tester, start with a low voltage (500V) and gradually apply electrostatic pulses to the chips. Immediately after each electrostatic discharge, perform LIV characteristic tests and record the changes in threshold current and leakage current. Continuously increase the electrostatic voltage until the chip performance shows a significant decline (threshold current increases sharply) or complete failure. Record the maximum electrostatic voltage that each group of chips can withstand.

[0085] The table below shows the performance data of the three sets of chips in the above comparative experiment and the analysis of the underlying technical reasons:

[0086] ;

[0087] Based on the initial threshold current data, the chips in groups B and C exhibited lower initial threshold currents, indicating that the built-in passivation layer effectively reduced leakage current and improved carrier injection efficiency in the early stages of chip manufacturing, fundamentally solving the leakage current problem. Based on the threshold current growth rate data after aging, it can be seen that the threshold current growth rate is a key indicator for measuring chip lifespan. Group A, due to sidewall defects caused by etching, experienced rapid aging. Groups B and C, due to their built-in atomic phase mixing protective layers, fundamentally eliminated these defects, thus significantly reducing the aging rate. Group C performed best, with its gradient structure further optimizing carrier confinement, enabling the chip to maintain extremely high stability even under long-term high-stress operation. Based on the characteristic temperature data... The higher the value, the better the chip's thermal stability; Group A has a lower value. The values ​​indicate that the quantum dot lattice is susceptible to thermal stress. The built-in stress compensation layers in groups B and C effectively protect the quantum dot lattice structure, making its performance insensitive to temperature changes. The gradient structure of group C provides a smooth stress buffer, which is more effective than the single mixing region of group B, achieving the highest performance. This solves the mechanical stress problem. According to the wavelength drift rate data, the lower the wavelength drift rate, the better the chip's thermal stability. This indicator reflects the thermo-optic effect of the chip material. Group A has lattice deformation due to stress concentration, and its refractive index is more sensitive to temperature changes. The built-in structures of Groups B and C effectively buffer thermal stress. The gradient structure of Group C shows the best effect in this regard, ensuring the stability of the chip's output wavelength at different temperatures. According to the maximum electrostatic voltage data, the higher the maximum electrostatic voltage, the stronger the antistatic capability. Group A has electric field concentration due to defects in the insulating layer and sidewalls, which leads to breakdown. The built-in wide-bandgap buffer protection layer of Groups B and C provides stronger electrical isolation and electric field dispersion capabilities. The smooth transition structure of Group C further avoids electric field concentration, enabling it to withstand higher electrostatic voltage impacts without failure.

[0088] The above experiments clearly demonstrate the innovative advantages of this solution:

[0089] Aging test results show that the threshold current growth rate of the innovative group (Group C) of this invention is less than 3%, which is far better than the more than 20% of the traditional technology group (Group A). ​​This directly proves that the built-in atomic phase mixed passivation layer of this invention eliminates the interface defects introduced by etching from the source. These defects are the root cause of leakage current and aging of traditional chips. This invention completely solves this problem through the "in-situ generation" protective layer, fundamentally extending the life and reliability of the chip.

[0090] Thermal stability test results show that the innovative group (Group C) has a characteristic temperature as high as 75K and the lowest wavelength drift rate. This indicates that the chip's performance remains very stable under extreme temperature changes. This is attributed to the unique "stress spring" effect of the gradient bandgap buffer layer, which buffers the thermal stress between materials step by step, protects the quantum dot lattice from deformation, ensures the stability of light-emitting properties, and fundamentally solves the problems of performance degradation and physical damage caused by thermal stress.

[0091] Electrostatic discharge (ESD) test results show that the innovation group (Group C) can withstand an electrostatic voltage of over 2000V, far exceeding the lower than 1000V of the traditional technology group (Group A). ​​This result strongly proves that the built-in protective layer of this invention is not only physically continuous, but also forms a smooth and efficient potential barrier electrically. It effectively disperses the electric field and avoids the concentration of the electric field at sharp boundaries or defects, thereby greatly improving the chip's antistatic and anti-electrical breakdown capabilities. Specific Implementation Example 5:

[0093] like Figures 1 to 3 As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0094] To further verify the feasibility of the technical solution in this application, the following case study is provided:

[0095] Case 1: High-speed coherent optical communication system: In fiber optic communication backbone networks, coherent communication technology is required to transmit massive amounts of data. This technology requires light sources with extremely high linewidth (narrow to sub-megahertz), extremely low noise, and stable operating conditions. More importantly, in WDM (wavelength division multiplexing) systems, multiple lasers need to be precisely locked to different ITU (International Telecommunication Union) standard wavelengths and be able to be quickly tuned according to network requirements. Traditional distributed feedback (DFB) lasers or lasers with external cavities (EC) will experience wavelength drift due to changes in operating current and ambient temperature during long-term operation. If DF-etched DFB lasers are used, defects in the active region sidewalls will lead to increased leakage current, thereby reducing lifespan and requiring frequent replacement. At the same time, their tuning range is limited and cannot meet the requirements of future WDM systems for higher integration.

[0096] Using the tunable laser chip of this application, integrated into a coherent optical communication module, engineers set the chip's operating current to the optimal point and precisely lock the chip at the ITU standard wavelength of 193.1 THz (approximately 1552.52 nm) through tuning electrodes. Due to the presence of the gradient bandgap buffer protection layer, the chip's threshold current aging rate is extremely slow, ensuring stable operation for several years without replacement. Simultaneously, its built-in stress compensation structure allows the chip to achieve a higher characteristic temperature. The wavelength drift is minimal when the computer room temperature fluctuates, ensuring communication continuity. When switching to another wavelength (193.0 THz) is required, the controller injects a preset micro-current into the tuning electrode. Through the Joule heating effect, the waveguide refractive index of the chip is finely adjusted, allowing the laser wavelength to be precisely switched to the target value. Because this chip has a wider tuning gain spectrum, it can cover a larger tuning range, providing convenience for future network upgrades. This chip solves the problems of poor reliability and narrow tuning range of traditional solutions, providing a longer lifespan, more stable, and more flexible high-performance light source for coherent optical communication.

[0097] Case Study 2: LiDAR System: In the fields of autonomous driving and industrial robotics, LiDAR systems construct 3D maps of the environment by emitting laser beams and receiving reflected light. To improve resolution and anti-interference capabilities, high-power, narrow-pulse semiconductor laser arrays capable of rapidly switching between different wavelengths are required. LiDAR systems typically operate in harsh outdoor environments with drastic temperature variations. In such environments, the emission wavelength of traditional lasers drifts significantly due to temperature changes, leading to inaccurate reception of reflected light and affecting ranging accuracy. Furthermore, to improve resolution, multiple lasers are needed, but the characteristics of each laser array differ, making it difficult to guarantee consistency in mass production.

[0098] Integrating the tunable laser chip array (typically 1x4 or 1x8) of this application into a LiDAR transmitter module addresses the challenge of ambient temperatures varying from -40°C to 60°C during vehicle startup and operation. The stress compensation layer within the chip effectively mitigates the mechanical stress caused by temperature changes, resulting in a high characteristic temperature (…). The characteristics ensure the stability of the threshold current and emitted wavelength. The LiDAR control system can guarantee accurate ranging without complex temperature compensation circuitry. The LiDAR system can be configured to operate on multiple different wavelengths. When one wavelength is interfered with by other LiDARs or ambient light, the control system can immediately switch the laser to another clean wavelength through the tuning electrode, thereby ensuring data accuracy. This chip has a wide gain spectrum, making this wavelength switching simple and fast. Due to the strict control of "low-temperature rapid thermal annealing" and "micro-area photoluminescence spectroscopy" in the chip manufacturing process, the performance consistency of each chip is ensured, which greatly simplifies the calibration and integration process of the LiDAR system. This chip provides an ideal light source for LiDAR systems with high thermal stability, anti-interference, and easy mass production, fundamentally improving the reliability of applications such as autonomous driving.

[0099] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A tunable laser chip integrating a quantum dot array, characterized in that, The tunable laser chip includes a substrate (1) and a semiconductor stack structure (2) grown thereon, the semiconductor stack structure (2) comprising, in the lateral direction: The core light-emitting channel (3) located in the center is composed of quantum dots and barrier materials that maintain the original epitaxial structure; And a gradient bandgap buffer protection layer (4) integrated with the core light-emitting channel (3), which is formed on both sides of the core light-emitting channel (3); The gradient bandgap buffer protection layer (4) is a semiconductor alloy region formed by atomic phase mixing of the quantum dots and the barrier material. Its bandgap gradually increases from the adjacent core light-emitting channel (3) outwards and forms a continuous single crystal structure with the core light-emitting channel (3). The gradient bandgap buffer protective layer (4) is further divided laterally into: The bandgap gradient transition region adjacent to the core light-emitting channel (3) has a gradient distribution in the degree of mixing between quantum dots and barrier materials; And a wide-bandgap mixing region located outside the bandgap gradient transition region, in which quantum dots and barrier materials are completely mixed.

2. The tunable laser chip with integrated quantum dot array according to claim 1, characterized in that: The wide-bandgap hybrid region is a quaternary and quinary semiconductor alloy, whose lattice constant and thermal expansion coefficient are between the quantum dot material and the barrier material of the core light-emitting channel (3).

3. The tunable laser chip with integrated quantum dot array according to claim 1, characterized in that: The tunable laser chip also includes a tuning electrode (5) disposed above the semiconductor stacked structure (2), and the gradient bandgap buffer protection layer (4) serves as an electrical isolation layer and a thermal stress buffer layer between the tuning electrode (5) and the core light-emitting channel (3).

4. A method for fabricating a tunable laser chip with an integrated quantum dot array according to any one of claims 1-3, characterized in that: The specific method for fabricating the tunable laser chip is as follows: Sp1: A semiconductor stack structure (2) containing a multilayer quantum dot array is epitaxially grown on a substrate (1). Sp2: Provide an ion implantation mask, wherein the mask is an opaque area at the position corresponding to the core light-emitting channel (3) of the future chip, and a transparent area at the position corresponding to the wide bandgap mixing region of the future chip; Sp3: Selective, low-dose impurity ion implantation is performed on the semiconductor stacked structure (2) through the ion implantation mask, so that the impurity ions are implanted only into the region where the gradient bandgap buffer protection layer (4) is pre-formed, while the region where the core light-emitting channel (3) is pre-formed is not implanted. Sp4: After removing the mask, the entire chip wafer is subjected to a low-temperature rapid thermal annealing process. This annealing causes the quantum dots in the impurity-injected region to mix with the barrier material to form the wide bandgap mixing region, while the region without impurity injection retains the original quantum dot structure to form the core light-emitting channel (3). Sp5: On top of the completed phase-mixed semiconductor stacked structure (2), subsequent ridge waveguide etching, insulating layer filling, electrode fabrication and passivation processes are performed.

5. The method for fabricating a tunable laser chip with an integrated quantum dot array according to claim 4, characterized in that: The impurity ions injected into Sp3 are one of boron atoms, fluorine atoms, and phosphorus atoms.

6. The method for fabricating a tunable laser chip with an integrated quantum dot array according to claim 4, characterized in that: The ion implantation mask used in Sp2 has a specially treated, contour-blurred semi-transparent structure in the region corresponding to the junction of the core light-emitting channel (3) and the gradient bandgap buffer protection layer (4) to form a laterally gradient impurity ion concentration distribution.

7. The method for fabricating a tunable laser chip with an integrated quantum dot array according to claim 4, characterized in that: The set temperature for the low-temperature rapid thermal annealing in Sp4 is higher than the activation temperature required for the quantum dots and barrier material to mix in the injected impurity region, while being lower than the thermal degradation temperature at which the quantum dots suffer structural damage.

8. The method for fabricating a tunable laser chip with an integrated quantum dot array according to claim 4, characterized in that: The ridge waveguide etching process in Sp5 has its etching depth precisely controlled to ensure that the two sidewalls of the final ridge waveguide are completely located within the wide gap mixing region formed by atomic phase mixing.

9. The method for fabricating a tunable laser chip with an integrated quantum dot array according to claim 4, characterized in that: The ion implantation in Sp3 is at an angle, with the implantation direction having a preset angle with the surface normal of the semiconductor stack (2) to control the scattering range of impurity ions in the lateral direction, so as to help form the bandgap gradient transition region.

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