Power tube current limiting circuit and switching power supply

Abstract

The invention provides a power tube current limiting circuit and a switching power supply, the circuit comprises a current limiting module, a target power tube, a current detection module and a negative feedback control module which are connected in sequence, and the negative feedback control module switches a working state when the current detection module detects that the output current of the target power tube is greater than a preset value; when the negative feedback control module is in a first state, the negative feedback control module and the current limiting module do not influence each other, and when the negative feedback control module is in a second state, the negative feedback control module and the current limiting module establish a negative feedback loop, and the current limiting module outputs a target working current to a target power tube. The target working current is the output current when the negative feedback control module is in the second state. According to the invention, overcurrent of the power tube can be prevented, and the working continuity of the whole circuit is not affected.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a power tube current limiting circuit and a switching power supply. Background Art

[0002] High-power circuits containing power transistors are widely used in fields requiring efficient energy control, such as power conversion, motor drive, and power management. To prevent overcurrent from damaging the power transistors and the load system, these circuits typically require integrated protection mechanisms.

[0003] However, the core protection method of mainstream protection solutions is mostly to quickly shut down the power tube, which will cause discontinuous circuit operation, causing problems such as power outages, signal interruptions and intermittent equipment operation, thereby reducing system stability and energy efficiency, damaging operating accuracy and dynamic response, and accelerating the aging and failure of power tubes and related components. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the present invention provides a power tube current limiting circuit and a switching power supply, which solve the problem in the prior art of achieving overcurrent protection by quickly shutting down the power tube, resulting in discontinuous circuit operation.

[0005] According to an embodiment of the present invention, a first aspect provides a power tube current limiting circuit, comprising a current limiting module, a target power tube, a current detection module, and a negative feedback control module connected in sequence, wherein the current detection module is connected to the control terminal of the target power tube, and the negative feedback control module is also connected to the current limiting module;

[0006] Wherein, one end of the current limiting module, the current detection module, the negative feedback control module and the input end of the target power tube are connected to the power supply voltage, and the other end of the current limiting module, the current detection module, the negative feedback control module and the output end of the target power tube are grounded;

[0007] The negative feedback control module switches the working state when the current detection module detects that the output current of the target power tube is greater than a preset value; when the negative feedback control module is in a first state, the negative feedback control module and the current limiting module do not affect each other; when the negative feedback control module is in a second state, the negative feedback control module and the current limiting module establish a negative feedback loop, and the current limiting module outputs a target working current to the target power tube, and the target working current is the output current of the negative feedback control module when it is in the second state.

[0008] Optionally, the negative feedback control module includes a voltage divider unit, a current mirror unit and a current control unit, the reference branch of the current mirror unit is connected to the voltage divider unit, the voltage divider unit is connected to the current detection module, and the output branch of the current mirror unit is connected to the current control unit;

[0009] Among them, when the current control unit is turned off, the negative feedback control module is in the first state; when the current limiting module is turned on, the negative feedback control module is in the second state; the current limiting module mirrors the target operating current output by the current control unit to the target power tube.

[0010] Optionally, a buffer is further included, wherein the gate of the buffer is connected to the current limiting module, the source of the buffer is connected to the control end of the target power tube, and the drain of the buffer is connected to the output end of the target power tube; the source of the buffer is connected to a fixed bias current, and the drain of the buffer is grounded.

[0011] Optionally, the target power tube is any one of MOSFET, IGBT, and GaN HEMT.

[0012] Optionally, the current limiting module includes a first MOS transistor and a second MOS transistor;

[0013] The sources of the first MOS transistor and the second MOS transistor are connected to the power supply voltage, the drain of the first MOS transistor is connected to the source of the buffer and the control end of the target power transistor, the drain of the second MOS transistor is connected to the gate of the buffer, and the gates of the first MOS transistor and the second MOS transistor are connected to the negative feedback control module.

[0014] Optionally, the first MOS transistor and the second MOS transistor are PMOS transistors.

[0015] Optionally, the current detection module includes a third MOS transistor, a gate of the third MOS transistor is connected to the control terminal of the target power transistor, a drain of the third MOS transistor is grounded, and a source of the third MOS transistor is connected to the negative feedback control module;

[0016] The third MOS tube is a PMOS tube.

[0017] Optionally, the negative feedback control module includes fourth to tenth MOS transistors and first to fifth resistors, wherein the fourth and sixth MOS transistors are reference branches of a current mirror unit, the fifth and seventh MOS transistors are output branches of the current mirror unit, the first, second, and third resistors are voltage dividers, and the eighth, ninth, fifth, and tenth MOS transistors are current control units.

[0018] One end of the first resistor, one end of the fourth resistor, and the source of the eighth MOS transistor are connected to the power supply voltage; the other end of the first resistor is connected to the current detection module and one end of the second resistor, the other end of the second resistor is connected to the source of the fourth MOS transistor, the drain of the fourth MOS transistor is connected to the source of the sixth MOS transistor, the source of the sixth MOS transistor is connected to one end of the third resistor, and the other end of the third resistor is grounded; the other end of the fourth resistor is connected to the source of the fifth MOS transistor, the drain of the fifth MOS transistor is connected to the source of the seventh MOS transistor, the drain of the seventh MOS transistor is grounded, and the drain of the ninth MOS transistor is connected to the other end of the fourth resistor. One end of the transistor is connected to the source of the fifth MOS transistor, the gate of the ninth MOS transistor is connected to the drain of the seventh MOS transistor, and the source of the ninth MOS transistor is grounded; the drain of the eighth MOS transistor is connected to the drain of the tenth MOS transistor, the source of the tenth MOS transistor is connected to one end of the fifth resistor, and the other end of the fifth resistor is grounded; the gate of the fourth MOS transistor is connected to the gate of the fifth MOS transistor and one end of the third resistor, the gate of the sixth MOS transistor is connected to the gate of the seventh MOS transistor and the other end of the third resistor, the gate of the eighth MOS transistor is connected to the current limiting circuit, and the gate of the tenth MOS transistor is connected to the source of the ninth MOS transistor.

[0019] Optionally, the fourth to eighth MOS transistors are PMOS transistors, and the ninth and tenth MOS transistors are NMOS transistors.

[0020] A second aspect provides a switching power supply, comprising the power tube current limiting circuit as described above.

[0021] The technical principle of the present invention is: the negative feedback control module switches the working state when the current detection module detects that the output current of the target power tube is greater than the preset value; when the negative feedback control module is in the first state, the negative feedback control module and the current limiting module do not affect each other; when the negative feedback control module is in the second state, the negative feedback control module and the current limiting module establish a negative feedback loop, and the current limiting module outputs the target working current to the target power tube.

[0022] Compared to the prior art, the present invention has the following beneficial effects: the current through the target power transistor is limited by the current limiting module. In particular, when the feedback control circuit is in the second state, a negative feedback loop is established with the negative feedback control module to control the target power transistor with the target operating current, limiting the target power transistor to the operating point when the second state is triggered. Based on this, the present invention can prevent overcurrent in the power transistor without affecting the operational continuity of the overall circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1This is a schematic diagram of the structure of a power tube current limiting circuit according to an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the structure of a power tube current limiting circuit according to an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the structure of a power tube current limiting circuit according to an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the structure of a power tube current limiting circuit according to an embodiment of the present invention;

[0027] Figure 5 Schematic diagram of the circuit structure of a power tube current limiting circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is further described below with reference to the accompanying drawings and embodiments.

[0029] like Figure 1 As shown, an embodiment of the present invention provides a power tube current limiting circuit, comprising a current limiting module 10, a target power tube 20, a current detection module 30, and a negative feedback control module 40. The current limiting module 10, the target power tube 20, the current detection module 30, and the negative feedback control module 40 are connected in sequence, with the current detection module 30 connected to the control terminal of the target power tube 20, and the negative feedback control module 40 also connected to the current limiting module 10. The detailed operating process of this embodiment is as follows: the negative feedback control module 40 switches to a different operating state when the current detection module 30 detects that the output current of the target power tube 20 is greater than a preset value. When the negative feedback control module 40 is in a first state, the negative feedback control module 40 and the current limiting module 10 do not affect each other. When the negative feedback control module 40 is in a second state, the negative feedback control module 40 and the current limiting module 10 establish a negative feedback loop, and the current limiting module 10 outputs a target operating current to the target power tube 20. The target operating current is the output current when the negative feedback control module 40 is in the second state. Since the current limiting module 10 limits the current passing through the target power tube 20, especially when the feedback control circuit is in the second state, a negative feedback loop is established with the negative feedback control module 40 to control the target power tube 20 with the target operating current, thereby limiting the target power tube 20 to the operating point when the second state is triggered. Therefore, the embodiment of the present invention can prevent overcurrent of the power tube without affecting the operating continuity of the entire circuit.

[0030] like Figure 2As shown, an embodiment of the present invention provides a component structure of the negative feedback control module 40 to achieve different working states, namely a first state and a second state, according to the output of the current detection module 30, and work in conjunction with the current limiting module 10 in the second state to limit the current passing through the target power tube 20 to prevent the target power tube 20 from overcurrent.

[0031] See also Figure 2 The negative feedback control module 40 includes a voltage divider unit 41, a current mirror unit 42, and a current control unit 43. The connections between these components are as follows: the reference branch of the current mirror unit 42 is connected to the voltage divider unit 41, the voltage divider unit 41 is connected to the current detection module 30, and the output branch of the current mirror unit 42 is connected to the current control unit 43. In a specific application, when the current control unit 43 is turned off, the negative feedback control module 40 is in the first state, and the negative feedback control module 40 and the current limiting module 10 do not affect each other.

[0032] When the current control unit 43 is turned on, the negative feedback control module 40 is in the second state. The negative feedback control module 40 establishes a negative feedback loop with the current limiting module 10. The current limiting module 10 can mirror the output of the current control unit 43, that is, the target operating current. The current limiting module 10 drives the target power tube 20 according to the target operating current and limits the current of the target power tube to the operating point when the current control unit 43 is turned on.

[0033] It should be noted that the target power tube 20 in the embodiment of the present invention can be any one of MOSFET, IGBT, and GaN HEMT. Figures 1 to 5 The target power tube 20 is a P-type MOSFET. Based on this, the control end of the target power tube 20 is the gate of the eleventh MOS tube M11 in the figure, the input end of the target power tube 20 is the source of the eleventh MOS tube M11 in the figure, and the output end of the target power tube 20 is the drain of the eleventh MOS tube M11.

[0034] based on Figure 1 and Figure 2 The current limiting module 10 of the present invention also provides another structure including a buffer 50, wherein the buffer 50 is a PMOS transistor, and in the accompanying drawings, it is the twelfth MOS transistor M12. Figure 3 As shown, Figure 1 As a basis, the gate of the buffer 50 is connected to the current limiting module 10, the source of the buffer 50 is connected to the control end of the target power tube 20, and the drain of the buffer 50 is connected to the output end of the target power tube 20; the source of the buffer 50 is connected to the fixed bias current, and the drain of the buffer 50 is grounded.

[0035] In practical applications, the primary pole of a power circuit is located at the output node, and the secondary pole is located at the gate node of the power transistor. Since power transistors are generally large, the primary pole and secondary pole are very close to each other. Therefore, in this embodiment of the present invention, a buffer 50 is added to isolate the current limiting module 10 from the target power transistor 20, and impedance transformation is performed to split the original secondary pole into two new high-frequency poles, thereby reducing phase lag in the low-frequency band and improving circuit stability.

[0036] For example, if Figure 2 Based on the structure of the buffer 50, Figure 4 The working principle and function of the buffer 50 are the same as those in the above embodiment, and will not be described in detail here.

[0037] like Figure 5 As shown, the embodiment of the present invention shows the detailed implementation structure of the current limiting module 10.

[0038] See also Figure 5 The current limiting module 10 includes a first MOS transistor M1 and a second MOS transistor M2. The connections between these components are as follows: the sources of the first MOS transistor M1 and the second MOS transistor M2 are connected to the power supply voltage; the drain of the first MOS transistor M1 is connected to the source of the buffer 50 and the control terminal of the target power transistor 20; the drain of the second MOS transistor M2 is connected to the gate of the buffer 50; and the gates of the first MOS transistor M1 and the second MOS transistor M2 are connected to the negative feedback control module 40. In a preferred implementation, the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors.

[0039] It should be noted that, based on the above-described current limiting module 10, the first MOS transistor M1 is used to adjust the gate voltage of the target power transistor 20, and the second MOS transistor M2 is used to match the first MOS transistor M1, further stabilizing the gate-source voltage of the buffer 50. When negative feedback is triggered, that is, when the negative feedback control module 40 is in the second state, a negative feedback loop is formed with the negative feedback control module 40. The drain currents of the first MOS transistor M1 and the second MOS transistor M2 are both mirrored to the output current of the negative feedback control module 40, that is, the target operating current. By controlling the target power transistor 20 with this target operating current, the target power transistor 20 can be limited to the operating point when the second state is triggered, thereby stabilizing the gate voltage of the target power transistor 20.

[0040] See also Figure 5The current detection module 30 includes a third MOS transistor M3. The gate of the third MOS transistor M3 is connected to the control terminal of the target power transistor 20, the drain of the third MOS transistor M3 is grounded, and the source of the third MOS transistor M3 is connected to the negative feedback control module 40. In a preferred implementation, the third MOS transistor M3 is a PMOS transistor. In a specific application, the current detection module 30 proportionally samples the current flowing through the target power transistor 20 and uses I P3 represents the sampling current of the current detection module 30, the sampling current I P3 and the current I flowing through the target power tube 20 OUT The relationship is as follows:

[0041]

[0042] Where, (W / L) P3 is the width-to-length ratio of the third MOS transistor M3, (W / L) P11 is the width-to-length ratio of the eleventh MOS transistor M11 , that is, the target power transistor 20 .

[0043] See also Figure 5The negative feedback control module 40 includes fourth to tenth MOS transistors M4 to M10, and first to fifth resistors R1 to R5. The fourth MOS transistor M4 and the sixth MOS transistor M6 serve as reference branches of the current mirror unit 42, the fifth MOS transistor M5 and the seventh MOS transistor M7 serve as output branches of the current mirror unit 42, the first resistor R1, the second resistor R2, and the third resistor R3 serve as a voltage divider unit 41, and the eighth MOS transistor M8, the ninth MOS transistor M9, the fifth resistor R5, and the tenth MOS transistor M10 serve as a current control unit 43. The connection relationship of the above-mentioned parts is as follows: one end of the first resistor R1, one end of the fourth resistor R4, and the source of the eighth MOS transistor M8 are connected to the power supply voltage; the other end of the first resistor R1 is connected to the current detection module 30 and one end of the second resistor R2, the other end of the second resistor R2 is connected to the source of the fourth MOS transistor M4, the drain of the fourth MOS transistor M4 is connected to the source of the sixth MOS transistor M6, the source of the sixth MOS transistor M6 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is grounded; the other end of the fourth resistor R4 is connected to the source of the fifth MOS transistor M5, the drain of the fifth MOS transistor M5 is connected to the source of the seventh MOS transistor M7, the drain of the seventh MOS transistor M7 is grounded, and the drain of the ninth MOS transistor M9 is connected to the The other end of the fourth resistor R4 is connected to the source of the fifth MOS transistor M5, the gate of the ninth MOS transistor M9 is connected to the drain of the seventh MOS transistor M7, and the source of the ninth MOS transistor M9 is grounded; the drain of the eighth MOS transistor M8 is connected to the drain of the tenth MOS transistor M10, the source of the tenth MOS transistor M10 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is grounded; the gate of the fourth MOS transistor M4 is connected to the gate of the fifth MOS transistor M5 and one end of the third resistor R3, the gate of the sixth MOS transistor M6 is connected to the gate of the seventh MOS transistor M7 and the other end of the third resistor R3, the gate of the eighth MOS transistor M8 is connected to the current limiting circuit, and the gate of the tenth MOS transistor M10 is connected to the source of the ninth MOS transistor M9. In a preferred implementation, the fourth to eighth MOS transistors M4 to M8 are PMOS transistors, and the ninth and tenth MOS transistors M9 and M10 are NMOS transistors.

[0044] It should be noted that, based on the above-mentioned negative feedback control module 40, the common end of the first resistor R1 and the second resistor R2 serves as the input end of the negative feedback control module 40. When the ninth MOS transistor M9 and the tenth MOS transistor M10 are turned on, the current limiting module 10 is turned on, and the negative feedback control module 40 is in the second state. At this time, the current limiting module 10 and the negative feedback control module 40, mainly together with the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, and the fifth resistor R5 of the current limiting module 10, form a negative feedback loop. As a result, the drain currents of the first MOS transistor M1 and the second MOS transistor M2 in the current limiting module 10 are the same as the drain current of the eighth MOS transistor M8 at this time. Since the first MOS transistor M1 is used to adjust the gate voltage of the target power transistor 20, the embodiment of the present invention can limit the operating point of the target power transistor 20 to the operating point when the second state is triggered, that is, the operating point when the ninth MOS transistor M9 is turned on. This means that when the current passing through the target power transistor 20 increases to a level that can turn on the ninth MOS transistor M9, the first MOS transistor M1, the second MOS transistor M2, the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, and the fifth resistor R5 form a negative feedback loop, and the drain currents of the first MOS transistor M1 and the second MOS transistor M2 are both the drain current of the eighth MOS transistor M8 at this time. Since the eighth MOS transistor M8 is an NMOS transistor, a constant current output is achieved. Therefore, the output current of the target power transistor 20 is also stable as the gate voltage of the target power transistor 20 is stable, thereby achieving the purpose of current limiting.

[0045] based on Figure 5 The complete workflow of the embodiment of the present invention is as follows: in the initial state, the first MOS transistor M1 and the second MOS transistor M2 of the current limiting module 10 do not form a loop with the negative feedback control module 40 and do not affect each other. Then, the current detection module 30 samples the target power transistor 20, and the negative feedback control module 40 obtains the sampled current output by the current detection module 30. At this time, the current IBIAS1 flowing through the fourth MOS transistor M4, the sixth MOS transistor M6, and the third resistor R3 is equal to the current flowing through the fifth MOS transistor M5 and the seventh MOS transistor M7, and is equal to half of the current flowing through the ninth MOS transistor M9. The conduction voltage of the ninth MOS transistor M9 is pre-designed so that when the voltage V across the first resistor R1 is equal to R1 Gradually increase to I R3 ≧3I R2 When the gate of the ninth MOS tube M9 is pulled high, the ninth MOS tube M9 starts to work, and at the same time the gate of the tenth MOS tube M10 is pulled high, the tenth MOS tube M10 starts to work, and a current is generated in the branch where the tenth MOS tube M10 and the fifth resistor R5 are located. The current flows through the eighth MOS tube M8, generating V GSP8, provided to the gates of the first MOS transistor M1 and the second MOS transistor M2. After the first MOS transistor M1 and the second MOS transistor M2 obtain the bias current, a negative feedback loop is formed. Based on the current mirror structure with the first MOS transistor M1 and the second MOS transistor M2, a stable drain current is output, thereby stabilizing the V of the buffer 50. GS , indirectly stabilize the gate voltage V of the target power tube 20 G , so when the current detection module 30 detects that the load current increases again, I R3 ≧3I R2 When the output current of the power tube no longer changes, the current of the power tube is limited, thus achieving current limitation and overcurrent protection.

[0046] Another embodiment of the present invention further provides a switching power supply, comprising the power tube current limiting circuit described above.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A power tube current limiting circuit, characterized in that: It includes a current limiting module, a target power tube, a current detection module, and a negative feedback control module connected in sequence, wherein the current detection module is connected to the control end of the target power tube, and the negative feedback control module is also connected to the current limiting module; Wherein, one end of the current limiting module, the current detection module, the negative feedback control module and the input end of the target power tube are connected to the power supply voltage, and the other end of the current limiting module, the current detection module, the negative feedback control module and the output end of the target power tube are grounded; The negative feedback control module switches the working state when the current detection module detects that the output current of the target power tube is greater than a preset value; when the negative feedback control module is in a first state, the negative feedback control module and the current limiting module do not affect each other; when the negative feedback control module is in a second state, the negative feedback control module and the current limiting module establish a negative feedback loop, and the current limiting module outputs a target working current to the target power tube, and the target working current is the output current of the negative feedback control module when it is in the second state.

2. The power tube current limiting circuit according to claim 1, wherein: The negative feedback control module includes a voltage dividing unit, a current mirror unit and a current control unit, wherein the reference branch of the current mirror unit is connected to the voltage dividing unit, the voltage dividing unit is connected to the current detection module, and the output branch of the current mirror unit is connected to the current control unit; Among them, when the current control unit is turned off, the negative feedback control module is in the first state; when the current limiting module is turned on, the negative feedback control module is in the second state; the current limiting module mirrors the target operating current output by the current control unit to the target power tube.

3. The power tube current limiting circuit according to claim 1 or 2, characterized in that: It also includes a buffer, the gate of the buffer is connected to the current limiting module, the source of the buffer is connected to the control end of the target power tube, and the drain of the buffer is connected to the output end of the target power tube; the source of the buffer is connected to a fixed bias current, and the drain of the buffer is grounded.

4. The power tube current limiting circuit according to claim 3, wherein: The target power tube is any one of MOSFET, IGBT, and GaN HEMT.

5. The power tube current limiting circuit according to claim 3, wherein: The current limiting module includes a first MOS transistor and a second MOS transistor; The sources of the first MOS transistor and the second MOS transistor are connected to the power supply voltage, the drain of the first MOS transistor is connected to the source of the buffer and the control end of the target power transistor, the drain of the second MOS transistor is connected to the gate of the buffer, and the gates of the first MOS transistor and the second MOS transistor are connected to the negative feedback control module.

6. The power tube current limiting circuit according to claim 4, wherein: The first MOS transistor and the second MOS transistor are PMOS transistors.

7. The power tube current limiting circuit according to claim 3, wherein: The current detection module includes a third MOS transistor, the gate of the third MOS transistor is connected to the control end of the target power transistor, the drain of the third MOS transistor is grounded, and the source of the third MOS transistor is connected to the negative feedback control module; The third MOS tube is a PMOS tube.

8. The power tube current limiting circuit according to claim 3, wherein: The negative feedback control module includes fourth to tenth MOS transistors and first to fifth resistors, wherein the fourth and sixth MOS transistors are reference branches of the current mirror unit, the fifth and seventh MOS transistors are output branches of the current mirror unit, the first, second, and third resistors are voltage dividers, and the eighth, ninth, fifth, and tenth MOS transistors are current control units; One end of the first resistor, one end of the fourth resistor, and the source of the eighth MOS transistor are connected to the power supply voltage; the other end of the first resistor is connected to the current detection module and one end of the second resistor, the other end of the second resistor is connected to the source of the fourth MOS transistor, the drain of the fourth MOS transistor is connected to the source of the sixth MOS transistor, the source of the sixth MOS transistor is connected to one end of the third resistor, and the other end of the third resistor is grounded; the other end of the fourth resistor is connected to the source of the fifth MOS transistor, the drain of the fifth MOS transistor is connected to the source of the seventh MOS transistor, the drain of the seventh MOS transistor is grounded, and the drain of the ninth MOS transistor is connected to the other end of the fourth resistor. One end of the transistor is connected to the source of the fifth MOS transistor, the gate of the ninth MOS transistor is connected to the drain of the seventh MOS transistor, and the source of the ninth MOS transistor is grounded; the drain of the eighth MOS transistor is connected to the drain of the tenth MOS transistor, the source of the tenth MOS transistor is connected to one end of the fifth resistor, and the other end of the fifth resistor is grounded; the gate of the fourth MOS transistor is connected to the gate of the fifth MOS transistor and one end of the third resistor, the gate of the sixth MOS transistor is connected to the gate of the seventh MOS transistor and the other end of the third resistor, the gate of the eighth MOS transistor is connected to the current limiting circuit, and the gate of the tenth MOS transistor is connected to the source of the ninth MOS transistor.

9. The power tube current limiting circuit according to claim 8, wherein: The fourth MOS transistor to the eighth MOS transistor are PMOS transistors, and the ninth MOS transistor and the tenth MOS transistor are NMOS transistors.

10. A switching power supply, characterized in that: The invention comprises a power tube current limiting circuit as claimed in any one of claims 1 to 9.

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