Capacitance isolation type driving circuit based on SiC MOSFET

Abstract

The invention discloses a capacitance isolation type driving circuit based on a SiC MOSFET, and the driving circuit comprises an on-off keying modulation circuit, the output end of the on-off keying modulation circuit is connected with the input end of a third-order differential isolation transmission circuit, and the output end of the third-order differential isolation transmission circuit is connected with the input end of a frequency-selective amplifier circuit. And the output end of the frequency selective amplifier circuit is connected with the input end of the demodulation circuit. According to the capacitance isolation type driving circuit based on the SiC MOSFET, a third-order differentiating circuit and an isolation capacitor are combined, the rapid response and frequency selection characteristics of the differentiating circuit to high-frequency signals are accurately utilized, input signals are optimized, and the signal coupling efficiency is enhanced; and meanwhile, through a unique circuit topology design, interference signals generated by common-mode transient electric stress are effectively suppressed, the anti-interference capability of the system is greatly enhanced, and the bottleneck of the traditional design in the aspect of common-mode transient immunity is successfully broken through.

Description

Technical Field

[0001] The present invention belongs to the technical field of isolation drive circuits and relates to a capacitor isolation drive circuit based on SiC MOSFET. Background Art

[0002] With the urgent demand for high efficiency, high power density, and high-frequency operation in electric vehicles, photovoltaic inverters, high-end power systems, and other fields, SiC MOSFETs (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors) are gradually replacing traditional silicon-based devices with their outstanding characteristics such as high breakdown voltage, fast switching speed, and low on-resistance, becoming a key component in the next generation of power electronics systems. However, SiC MOSFETs are prone to generating strong common-mode interference signals when operating under high dV / dT (rate of change of voltage with respect to time) conditions. Furthermore, the voltage range, turn-on and turn-off time requirements, and interference immunity required for SiC MOSFET gate drives are significantly higher than those of traditional silicon devices. This places stringent requirements on the driver chip's common-mode transient immunity (CMTI), pulse width consistency, and transmission delay performance. Therefore, designing an isolated driver chip with high common-mode transient immunity, low latency, low power consumption, small pulse width distortion, and stability and reliability has become the key to ensuring system performance.

[0003] In summary, the existing technology has the problem of low common-mode transient immunity of SiC MOSFET drive circuits. Summary of the Invention

[0004] The purpose of the present invention is to provide a capacitive isolation drive circuit based on SiC MOSFET, which solves the problem of low common-mode transient immunity of SiC MOSFET drive circuits in the prior art.

[0005] The technical solution adopted by the present invention is a capacitive isolation drive circuit based on SiC MOSFET, including an on-off keying modulation circuit, the output end of the on-off keying modulation circuit is connected to the input end of a third-order differential isolation transmission circuit, the output end of the third-order differential isolation transmission circuit is connected to the input end of a frequency-selective amplifier circuit, and the output end of the frequency-selective amplifier circuit is connected to the input end of a demodulation circuit.

[0006] The present invention is also characterized in that: The on-off keying modulation circuit includes a first differential comparator, the output of the first differential comparator is connected to the input of an AND gate NAND1, the output of the AND gate NAND1 is connected to the input of a first inverter, the output of the first inverter is connected to the input of a second inverter, and the output of the second inverter is connected to the input of a third inverter; the sizes of the first inverter, the second inverter, and the third inverter increase in sequence.

[0007] The on-off keying modulation circuit further includes a second differential comparator, wherein the output of the second differential comparator is connected to the input of an AND gate NAND2, the output of the AND gate NAND2 is connected to the input of a fourth inverter, the output of the fourth inverter is connected to the input of a fifth inverter, and the output of the fifth inverter is connected to the input of a sixth inverter; the sizes of the fourth, fifth, and sixth inverters increase in sequence. The input terminals of the AND gates NAND1 and NAND2 are connected to the control voltage signal V IN .

[0008] The third-order differential isolation transmission circuit includes capacitors C ISO1 ,capacitance C ISO1 The upper plate is connected to the output of the third inverter, and the capacitor C ISO1 The lower plate and capacitor C ISO2 The upper plate of the capacitor is connected to C ISO2 The lower plate and resistor R 0 one end, capacitor C 0 one end connected, resistor R 0The other end is grounded, the capacitor C 0The other end of the resistor R 1 one end, capacitor C 1 one end connected to the resistor R 1The other end is grounded, the capacitor C 1The other end of the resistor R 2. Connect one end.

[0009] The third-order differential isolation transmission circuit includes capacitors C ISO3 ,capacitance C ISO3 The upper plate is connected to the output of inverter No. 6, and the capacitor C ISO3 The lower plate and capacitor C ISO4 The upper plate of the capacitor is connected to C ISO4 The lower plate and resistor R 3 one end, capacitorC 2 one end connected to the resistor R 3The other end is grounded, the capacitor C 2The other end of the resistor R 4 one end, capacitor C 3 one end connected to the resistor R 4The other end is grounded, the capacitor C 3The other end of the resistor R 5. Connect one end.

[0010] The frequency selective amplifier circuit includes a transistor M N3 , transistor M N3 The source and resistor R 2 Keep away from the ungrounded end and capacitor C 1. Stay away from resistors R 2 one end, resistor R 8 one end connected to the resistor R 8The other end is grounded, transistor M N3 The gate of transistor M N1 The gate of transistor M N1 The drain of transistor M N3 The drain of transistor M N2 The source connection; Transistor M N1 The gate of transistor M N1 The drain of transistor M N1 The gate of transistor M N1 The drain and bias current source I bias1 One end is connected to the bias current source I bias1 The other end is connected to the power supply VDD, transistor M N1 The source of transistor M N5 The source connection; Transistor M N2 The gate of transistor M N4 The gate connection of transistor M N2 The drain of transistor M P1 The drain of transistor M P0 Gate, resistor R 7 one end connected to the resistor R 7The other end and the capacitor C 5 one end connected to the capacitor C 5. The other end is connected to the power supply VDD; Transistor M P1 The source of transistor M is connected to the power supply VDD. P1 The gate and capacitance C 5. Keep away from the power supply VDD end and resistor R 7 Keep away from transistor M N2 One end is connected; Transistor M P0 The source of transistor M is connected to the power supply VDD. P0 The gate and capacitance C a One end connected, capacitor C a The other end is connected to transistor M P3 The drain of transistor M N7 The drain of transistor M P0 The drain and capacitance C b One end, transistor M N0 Drain, resistance R 6 one end connected; Transistor M N0 The gate and resistor R 6 Keep away from transistor M P0 One end, capacitor C 4 One end is connected to the capacitor C 4 The other end is grounded, transistor M N0 The source is grounded.

[0011] The frequency selective amplifier circuit also includes a transistor M N5 , transistor M N5 The source and resistor R 5Keep away from the ungrounded end and capacitor C 3. Stay away from resistors R 4 one end, resistor R 9 one end connected to the resistor R 9The other end is grounded, transistor M N5 The gate of transistor M N6 The gate of transistor M N6 The drain of transistor M N5 The drain of transistor M N4 The source connection; Transistor M N6 The gate of transistor M N6 The drain of transistor M N6 The gate of transistor M N6 The drain and bias current source I bias2 One end is connected to the bias current source I bias2 The other end is connected to the power supply VDD, transistor M N6 The source of transistor M N3 The source connection; Transistor M N4 The drain of transistor M P2 The drain of transistor M P3 Gate, resistor R 10 One end connected to the resistor R10 The other end and the capacitor C 6 one end connected to the capacitor C 6The other end is connected to the power supply VDD; Transistor M P2 The source of transistor M is connected to the power supply VDD. P2 The gate and capacitance C 6 Keep away from the power supply VDD end, resistor R 10 Keep away from transistor M N4 One end is connected; Transistor M P3 The source of transistor M is connected to the power supply VDD. P3 The gate and capacitance C b One end connected, capacitor C b The other end is connected to transistor M P0 The drain of transistor M N0 The drain of transistor M P3 The drain and capacitance C a One end, transistor M N7 Drain, resistance R 11 One end is connected; Transistor M N7 The gate and resistor R 11 Stay away from transistor M P3 One end, capacitor C 7 One end is connected to the capacitor C 7 The other end is grounded, transistor M N7 The source is grounded.

[0012] Transistor M P0 Source, bias current source I bias1 Connect one end of the power supply VDD and the capacitor C 5 is connected to one end of the power supply VDD, transistor M P1 The source of transistor M P2 The source, capacitance C 6 is connected to one end of the power supply VDD and the bias current source I bias2 Connect one end of the power supply VDD to the transistor M P3 The source connection; capacitance C 4 ground one end, transistor M N0 Source, resistor R 8 ground one end, resistor R 9 ground one end, transistor M N7 The source, capacitance C 7 Connect one end to the ground.

[0013] The demodulation circuit includes capacitors C 8 and capacitors C 9. Capacitor C 8 One end and the resistor R 11 Keep away from capacitors C 7 one end, transistor M N7 The drain of transistor M P3 Drain, capacitance C a is far away from transistor M P0 One end connected, capacitor C 8The other end of the resistor R 15 One end, transistor M N12 The gate connection; capacitance C 9 one end and the resistor R 6. Keep away from capacitors C 4 one end, transistor M N0 The drain of transistor M P0 Drain, capacitance C b Keep away from transistor M P3 One end connected, capacitor C 9The other end of the resistor R 16 One end, transistor M N13 The gate connection; Transistor M N12 The drain of transistor M N13 The drain of transistor M P10 The drain of transistor M P10 The gate of transistor M P11 The gate connection of transistor M N12 The source of transistor M N10 The source of transistor M N13 The source of transistor M N11 The drain connection; resistance R 15 Keep away from capacitors C 8 one end, resistor R 16 Keep away from capacitors C 9 one end, transistor M P7 Drain, resistance R 14 One end connected to the resistor R 14 The other end is grounded; Transistor M P10 The drain of transistor M P10 The gate connection of transistor M P10The source of transistor M is connected to the power supply VDD. P11 The source of transistor M is connected to the power supply VDD. P11 The drain of transistor M N14 The drain connection; Transistor M N10 The drain of transistor M P9 The drain of transistor M P9 The gate of transistor M P8 The gate connection of transistor M N10 The gate of transistor M P6 Drain, resistance R 12 One end connected to the resistor R 12 The other end of the resistor R 13 One end connected to the resistor R 13 The other end is grounded; Transistor M P8 The gate of transistor M P9 The gate connection of transistor M P8 The source of transistor M P9 The source of transistor M is connected to the power supply VDD. P8 The drain of transistor M N9 The drain of transistor M N9 The gate connection; Transistor M N14 The source of transistor M is grounded. N14 The gate of transistor M N9 The gate of transistor M N9 The drain of transistor M P8 The drain of transistor M N9 The source is grounded; Transistor M N11 The gate and control voltage signals V b1 Connection, transistor M N11 The source is grounded; Transistor M P7 The source of transistor M is connected to the power supply VDD. P7 The gate of transistor M P6 The gate of transistor M P5 The gate of transistor M P4 The gate, bias current source I bias3 One end is connected to the bias current source I bias3 The other end is grounded; Transistor M P6 The source of transistor M is connected to the power supply VDD. P6The drain and resistance R 12 Stay away from resistors R 13 One end, transistor M N10 The gate connection; Transistor M P5 The source of transistor M is connected to the power supply VDD. P5 The drain of transistor M N8 The gate of transistor M N8 The drain connection; Transistor M P4 The source of transistor M is connected to the power supply VDD. P4 The drain of transistor M P4 The gate, bias current source I bias3 The ungrounded end is connected; Transistor M N8 The drain of transistor M N8 The gate connection of transistor M N8 The source is grounded.

[0014] Transistor M P4 The source of transistor M P5 The source of transistor M P6 The source of transistor M P7 The source of transistor M P8 The source of transistor M P9 The source of transistor M P10 The source of transistor M P11 The source connection; Bias current source I bias3 Ground one end, transistor M N8 Source, resistor R 13 Ground one end, resistor R 14 Ground one end, transistor M N9 The source of transistor M N11 The source of transistor M N14 source connection.

[0015] The beneficial effects of the present invention are: based on the analysis of the impact of common-mode transient electrical stress on the transmitter and receiver of the capacitive isolation chip, the present invention proposes an innovative isolation transmission structure based on a third-order differential circuit as a capacitive isolation solution. The structure combines the third-order differential circuit with the isolation capacitor, and accurately utilizes the fast response and frequency selection characteristics of the differential circuit to high-frequency signals to optimize the input signal and enhance the signal coupling efficiency; at the same time, through the unique circuit topology design, the interference signal generated by the common-mode transient electrical stress is effectively suppressed, the system's anti-interference ability is greatly enhanced, and the bottleneck of traditional design in common-mode transient immunity is successfully broken through; the present invention can improve the system's common-mode transient immunity performance by several times, greatly increasing the reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 1 is a system circuit diagram of a SiC MOSFET-based capacitive isolation drive circuit according to the present invention; Figure 2 This is a schematic diagram of the structure of an on-off keying modulation circuit for generating a carrier signal in the present invention; Figure 3 This is a schematic diagram of the structure of a third-order differential isolation transmission circuit for eliminating common-mode noise current in the present invention; Figure 4 This is a schematic diagram of the structure of a frequency-selective amplifier circuit for amplifying a carrier signal in the present invention; Figure 5 It is a schematic diagram of the structure of a demodulation circuit for demodulating a carrier signal into a level signal in the present invention.

[0017] In the figure, 1. On-off keying modulation circuit; 2. Third-order differential isolation transmission circuit; 3. Frequency-selective amplifier circuit; 4. Demodulation circuit. DETAILED DESCRIPTION

[0018] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] Example 1 This embodiment proposes a capacitive isolation drive circuit based on SiC MOSFET, such as Figure 1 As shown, it includes an on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected to the input end of the third-order differential isolation transmission circuit 2, the output end of the third-order differential isolation transmission circuit 2 is connected to the input end of the frequency selection amplifier circuit 3, and the output end of the frequency selection amplifier circuit 3 is connected to the input end of the demodulation circuit 4.

[0020] Example 2 This embodiment proposes a capacitive isolation drive circuit based on SiC MOSFET, such as Figure 1As shown, it includes an on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected to the input end of the third-order differential isolation transmission circuit 2, the output end of the third-order differential isolation transmission circuit 2 is connected to the input end of the frequency selection amplifier circuit 3, and the output end of the frequency selection amplifier circuit 3 is connected to the input end of the demodulation circuit 4.

[0021] Combine Figure 2 As shown, the on-off keying modulation circuit 1 includes a first differential comparator, the output of the first differential comparator is connected to the input of the AND gate NAND1, the output of the AND gate NAND1 is connected to the input of the first inverter, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the third inverter; the sizes of the first inverter, the second inverter, and the third inverter are increased in sequence. The on-off keying modulation circuit 1 also includes a second differential comparator, the output of the second differential comparator is connected to the input of the AND gate NAND2, the output of the AND gate NAND2 is connected to the input of the fourth inverter, the output of the fourth inverter is connected to the input of the fifth inverter, and the output of the fifth inverter is connected to the input of the sixth inverter; the sizes of the fourth inverter, the fifth inverter, and the sixth inverter are increased in sequence; the inputs of the AND gates NAND1 and NAND2 are connected to the control voltage signal V IN .

[0022] Example 3 This embodiment proposes a capacitive isolation drive circuit based on SiC MOSFET, such as Figure 1 As shown, it includes an on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected to the input end of the third-order differential isolation transmission circuit 2, the output end of the third-order differential isolation transmission circuit 2 is connected to the input end of the frequency selection amplifier circuit 3, and the output end of the frequency selection amplifier circuit 3 is connected to the input end of the demodulation circuit 4.

[0023] Combine Figure 2As shown, the on-off keying modulation circuit 1 includes a first differential comparator, the output of the first differential comparator is connected to the input of the AND gate NAND1, the output of the AND gate NAND1 is connected to the input of the first inverter, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the third inverter; the sizes of the first inverter, the second inverter, and the third inverter are increased in sequence. The on-off keying modulation circuit 1 also includes a second differential comparator, the output of the second differential comparator is connected to the input of the AND gate NAND2, the output of the AND gate NAND2 is connected to the input of the fourth inverter, the output of the fourth inverter is connected to the input of the fifth inverter, and the output of the fifth inverter is connected to the input of the sixth inverter; the sizes of the fourth inverter, the fifth inverter, and the sixth inverter are increased in sequence; the inputs of the AND gates NAND1 and NAND2 are connected to the control voltage signal V IN .

[0024] Combine Figure 3 As shown, the third-order differential isolation transmission circuit 2 includes capacitors C ISO1 ,capacitance C ISO1 The upper plate is connected to the output of the third inverter, and the capacitor C ISO1 The lower plate and capacitor C ISO2 The upper plate of the capacitor is connected to C ISO2 The lower plate and resistor R 0 one end, capacitor C 0 one end connected, resistor R 0The other end of the capacitor is grounded. C 0The other end of the resistor R 1 one end, capacitor C 1 one end connected to the resistor R 1The other end is grounded, the capacitor C 1The other end of the resistor R 2 one end is connected. The third-order differential isolation transmission circuit 2 includes capacitor C ISO3 ,capacitance C ISO3 The upper plate is connected to the output of inverter No. 6, and the capacitor C ISO3 The lower plate and capacitor C ISO4 The upper plate of the capacitor is connected to C ISO4 The lower plate and resistor R 3 one end, capacitor C 2 one end connected to the resistor R3The other end is grounded, the capacitor C 2The other end of the resistor R 4 one end, capacitor C 3 one end connected to the resistor R 4The other end is grounded, the capacitor C 3The other end of the resistor R 5. Connect one end.

[0025] Example 4 This embodiment proposes a capacitive isolation drive circuit based on SiC MOSFET, such as Figure 1 As shown, it includes an on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected to the input end of the third-order differential isolation transmission circuit 2, the output end of the third-order differential isolation transmission circuit 2 is connected to the input end of the frequency selection amplifier circuit 3, and the output end of the frequency selection amplifier circuit 3 is connected to the input end of the demodulation circuit 4.

[0026] Combine Figure 2 As shown, the on-off keying modulation circuit 1 includes a first differential comparator, the output of the first differential comparator is connected to the input of the AND gate NAND1, the output of the AND gate NAND1 is connected to the input of the first inverter, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the third inverter; the sizes of the first inverter, the second inverter, and the third inverter are increased in sequence. The on-off keying modulation circuit 1 also includes a second differential comparator, the output of the second differential comparator is connected to the input of the AND gate NAND2, the output of the AND gate NAND2 is connected to the input of the fourth inverter, the output of the fourth inverter is connected to the input of the fifth inverter, and the output of the fifth inverter is connected to the input of the sixth inverter; the sizes of the fourth inverter, the fifth inverter, and the sixth inverter are increased in sequence; the inputs of the AND gates NAND1 and NAND2 are connected to the control voltage signal V IN .

[0027] Combine Figure 3 As shown, the third-order differential isolation transmission circuit 2 includes capacitors C ISO1 ,capacitance C ISO1 The upper plate is connected to the output of the third inverter, and the capacitor C ISO1 The lower plate and capacitor C ISO2 The upper plate of the capacitor is connected to C ISO2 The lower plate and resistor R 0 one end, capacitor C 0 one end connected, resistor R 0The other end of the capacitor is grounded. C0The other end of the resistor R 1 one end, capacitor C 1 one end connected to the resistor R 1The other end is grounded, the capacitor C 1The other end of the resistor R 2 one end is connected. The third-order differential isolation transmission circuit 2 includes capacitor C ISO3 ,capacitance C ISO3 The upper plate is connected to the output of inverter No. 6, and the capacitor C ISO3 The lower plate and capacitor C ISO4 The upper plate of the capacitor is connected to C ISO4 The lower plate and resistor R 3 one end, capacitor C 2 one end connected to the resistor R 3The other end is grounded, the capacitor C 2The other end of the resistor R 4 one end, capacitor C 3 one end connected to the resistor R 4The other end is grounded, the capacitor C 3The other end of the resistor R 5. Connect one end.

[0028] Combine Figure 4 As shown, the frequency selection amplifier circuit 3 includes a transistor M N3 , transistor M N3 The source and resistor R 2 Keep away from the ungrounded end and capacitor C 1. Stay away from resistors R 2 one end, resistor R 8 one end connected to the resistor R 8The other end is grounded, transistor M N3 The gate of transistor M N1 The gate of transistor M N1 The drain of transistor M N3 The drain of transistor M N2 The source of transistor M N1 The gate of transistor M N1 The drain of transistor M N1 The gate of transistor M N1 The drain and bias current source I bias1 One end is connected to the bias current source I bias1 The other end is connected to the power supply VDD, transistor M N1 The source of transistor M N5 The source of transistor M N2 The gate of transistor MN4 The gate connection of transistor M N2 The drain of transistor M P1 The drain of transistor M P0 Gate, resistor R 7 one end connected to the resistor R 7The other end and the capacitor C 5 one end connected to the capacitor C 5The other end is connected to the power supply VDD; transistor M P1 The source of transistor M is connected to the power supply VDD. P1 The gate and capacitance C 5. Keep away from the power supply VDD end and resistor R 7 Keep away from transistor M N2 One end is connected to transistor M P0 The source of transistor M is connected to the power supply VDD. P0 The gate and capacitance C a One end connected, capacitor C a The other end is connected to transistor M P3 The drain of transistor M N7 The drain of transistor M P0 The drain and capacitance C b One end, transistor M N0 Drain, resistance R 6 one end connected to transistor M N0 The gate and resistor R 6 Keep away from transistor M P0 One end, capacitor C 4 One end is connected to the capacitor C 4 The other end is grounded, transistor M N0 The source is grounded.

[0029] Example 5 This embodiment proposes a capacitive isolation drive circuit based on SiC MOSFET, such as Figure 1 As shown, it includes an on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected to the input end of the third-order differential isolation transmission circuit 2, the output end of the third-order differential isolation transmission circuit 2 is connected to the input end of the frequency selection amplifier circuit 3, and the output end of the frequency selection amplifier circuit 3 is connected to the input end of the demodulation circuit 4.

[0030] Combine Figure 2As shown, the on-off keying modulation circuit 1 includes a first differential comparator, the output of the first differential comparator is connected to the input of the AND gate NAND1, the output of the AND gate NAND1 is connected to the input of the first inverter, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the third inverter; the sizes of the first inverter, the second inverter, and the third inverter are increased in sequence. The on-off keying modulation circuit 1 also includes a second differential comparator, the output of the second differential comparator is connected to the input of the AND gate NAND2, the output of the AND gate NAND2 is connected to the input of the fourth inverter, the output of the fourth inverter is connected to the input of the fifth inverter, and the output of the fifth inverter is connected to the input of the sixth inverter; the sizes of the fourth inverter, the fifth inverter, and the sixth inverter are increased in sequence; the inputs of the AND gates NAND1 and NAND2 are connected to the control voltage signal V IN .

[0031] Combine Figure 3 As shown, the third-order differential isolation transmission circuit 2 includes capacitors C ISO1 ,capacitance C ISO1 The upper plate is connected to the output of the third inverter, and the capacitor C ISO1 The lower plate and capacitor C ISO2 The upper plate of the capacitor is connected to C ISO2 The lower plate and resistor R 0 one end, capacitor C 0 one end connected, resistor R 0The other end of the capacitor is grounded. C 0The other end of the resistor R 1 one end, capacitor C 1 one end connected to the resistor R 1The other end is grounded, the capacitor C 1The other end of the resistor R 2 one end is connected. The third-order differential isolation transmission circuit 2 includes capacitor C ISO3 ,capacitance C ISO3 The upper plate is connected to the output of inverter No. 6, and the capacitor C ISO3 The lower plate and capacitor C ISO4 The upper plate of the capacitor is connected to C ISO4 The lower plate and resistor R 3 one end, capacitor C 2 one end connected to the resistor R3The other end is grounded, the capacitor C 2The other end of the resistor R 4 one end, capacitor C 3 one end connected to the resistor R 4The other end is grounded, the capacitor C 3The other end of the resistor R 5. Connect one end.

[0032] Combine Figure 4 As shown, the frequency selection amplifier circuit 3 includes a transistor M N3 , transistor M N3 The source and resistor R 2 Keep away from the ungrounded end and capacitor C 1. Stay away from resistors R 2 one end, resistor R 8 one end connected to the resistor R 8The other end is grounded, transistor M N3 The gate of transistor M N1 The gate of transistor M N1 The drain of transistor M N3 The drain of transistor M N2 The source of transistor M N1 The gate of transistor M N1 The drain of transistor M N1 The gate of transistor M N1 The drain and bias current source I bias1 One end is connected to the bias current source I bias1 The other end is connected to the power supply VDD, transistor M N1 The source of transistor M N5 The source of transistor M N2 The gate of transistor M N4 The gate connection of transistor M N2 The drain of transistor M P1 The drain of transistor M P0 Gate, resistor R 7 one end connected to the resistor R 7The other end and the capacitor C 5 one end connected to the capacitor C 5The other end is connected to the power supply VDD; transistor M P1 The source of transistor M is connected to the power supply VDD. P1 The gate and capacitance C 5. Keep away from the power supply VDD end and resistor R 7 Keep away from transistor M N2 One end is connected to transistor M P0 The source of transistor M is connected to the power supply VDD. P0 The gate and capacitance Ca One end connected, capacitor C a The other end is connected to transistor M P3 The drain of transistor M N7 The drain of transistor M P0 The drain and capacitance C b One end, transistor M N0 Drain, resistance R 6 one end connected to transistor M N0 The gate and resistor R 6 Keep away from transistor M P0 One end, capacitor C 4 One end is connected to the capacitor C 4 The other end is grounded, transistor M N0 The source is grounded.

[0033] The frequency selective amplifier circuit 3 further includes a transistor M N5 , transistor M N5 The source and resistor R 5Keep away from the ungrounded end and capacitor C 3. Stay away from resistors R 4 one end, resistor R 9 one end connected to the resistor R 9The other end is grounded, transistor M N5 The gate of transistor M N6 The gate of transistor M N6 The drain of transistor M N5 The drain of transistor M N4 The source of transistor M N6 The gate of transistor M N6 The drain of transistor M N6 The gate of transistor M N6 The drain and bias current source I bias2 One end is connected to the bias current source I bias2 The other end is connected to the power supply VDD, transistor M N6 The source of transistor M N3 The source of transistor M N4 The drain of transistor M P2 The drain of transistor M P3 Gate, resistor R 10 One end connected to the resistor R 10 The other end and the capacitor C 6 one end connected to the capacitor C 6 The other end is connected to the power supply VDD; transistor M P2 The source of transistor M is connected to the power supply VDD.P2 The gate and capacitance C 6 Keep away from the power supply VDD end, resistor R 10 Keep away from transistor M N4 One end is connected to transistor M P3 The source of transistor M is connected to the power supply VDD. P3 The gate and capacitance C b One end connected, capacitor C b The other end is connected to transistor M P0 The drain of transistor M N0 The drain of transistor M P3 The drain and capacitance C a One end, transistor M N7 Drain, resistance R 11 One end is connected to transistor M N7 The gate and resistor R 11 Stay away from transistor M P3 One end, capacitor C 7 One end is connected to the capacitor C 7 The other end is grounded, transistor M N7 The source of transistor M is grounded. P0 Source, bias current source I bias1 Connect one end of the power supply VDD and the capacitor C 5 is connected to one end of the power supply VDD, transistor M P1 The source of transistor M P2 The source, capacitance C 6 is connected to one end of the power supply VDD and the bias current source I bias2 Connect one end of the power supply VDD to the transistor M P3 The source connection of the capacitor C 4 ground one end, transistor M N0 Source, resistor R 8 ground one end, resistor R 9 ground one end, transistor M N7 The source, capacitance C 7 Connect one end to the ground.

[0034] Example 6 This embodiment proposes a capacitive isolation drive circuit based on SiC MOSFET, such as Figure 1As shown, it includes an on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected to the input end of the third-order differential isolation transmission circuit 2, the output end of the third-order differential isolation transmission circuit 2 is connected to the input end of the frequency selection amplifier circuit 3, and the output end of the frequency selection amplifier circuit 3 is connected to the input end of the demodulation circuit 4.

[0035] Combine Figure 2 As shown, the on-off keying modulation circuit 1 includes a first differential comparator, the output of the first differential comparator is connected to the input of the AND gate NAND1, the output of the AND gate NAND1 is connected to the input of the first inverter, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the third inverter; the sizes of the first inverter, the second inverter, and the third inverter increase in sequence.

[0036] The on-off keying modulation circuit 1 also includes a second differential comparator, the output of the second differential comparator is connected to the input of the AND gate NAND2, the output of the AND gate NAND2 is connected to the input of the fourth inverter, the output of the fourth inverter is connected to the input of the fifth inverter, and the output of the fifth inverter is connected to the input of the sixth inverter; the sizes of the fourth inverter, the fifth inverter, and the sixth inverter increase in sequence; the inputs of the AND gates NAND1 and NAND2 are connected to the control voltage signal V IN .

[0037] Combine Figure 3 As shown, the third-order differential isolation transmission circuit 2 includes capacitors C ISO1 ,capacitance C ISO1 The upper plate is connected to the output of the third inverter, and the capacitor C ISO1 The lower plate and capacitor C ISO2 The upper plate of the capacitor is connected to C ISO2 The lower plate and resistor R 0 one end, capacitor C 0 one end connected, resistor R 0The other end is grounded, the capacitor C 0The other end of the resistor R 1 one end, capacitor C 1 one end connected to the resistor R 1The other end is grounded, the capacitor C 1The other end of the resistor R 2. Connect one end.

[0038] The third-order differential isolation transmission circuit 2 includes capacitors C ISO3 ,capacitance CISO3 The upper plate is connected to the output of inverter No. 6, and the capacitor C ISO3 The lower plate and capacitor C ISO4 The upper plate of the capacitor is connected to C ISO4 The lower plate and resistor R 3 one end, capacitor C 2 one end connected to the resistor R 3The other end is grounded, the capacitor C 2The other end of the resistor R 4 one end, capacitor C 3 one end connected to the resistor R 4The other end is grounded, the capacitor C 3The other end of the resistor R 5. Connect one end.

[0039] Combine Figure 4 As shown, the frequency selection amplifier circuit 3 includes a transistor M N3 , transistor M N3 The source and resistor R 2 Keep away from the ungrounded end and capacitor C 1. Stay away from resistors R 2 one end, resistor R 8 one end connected to the resistor R 8The other end is grounded, transistor M N3 The gate of transistor M N1 The gate of transistor M N1 The drain of transistor M N3 The drain of transistor M N2 The source of transistor M N1 The gate of transistor M N1 The drain of transistor M N1 The gate of transistor M N1 The drain and bias current source I bias1 One end is connected to the bias current source I bias1 The other end is connected to the power supply VDD, transistor M N1 The source of transistor M N5 The source of transistor M N2 The gate of transistor M N4 The gate connection of transistor M N2 The drain of transistor M P1 The drain of transistor M P0 Gate, resistor R 7 one end connected to the resistor R 7The other end and the capacitor C 5 one end connected to the capacitor C5The other end is connected to the power supply VDD; transistor M P1 The source of transistor M is connected to the power supply VDD. P1 The gate and capacitance C 5. Keep away from the power supply VDD end and resistor R 7 Keep away from transistor M N2 One end is connected to transistor M P0 The source of transistor M is connected to the power supply VDD. P0 The gate and capacitance C a One end connected, capacitor C a The other end is connected to transistor M P3 The drain of transistor M N7 The drain of transistor M P0 The drain and capacitance C b One end, transistor M N0 Drain, resistance R 6 one end connected to transistor M N0 The gate and resistor R 6 Keep away from transistor M P0 One end, capacitor C 4 One end is connected to the capacitor C 4 The other end is grounded, transistor M N0 The source is grounded.

[0040] The frequency selective amplifier circuit 3 further includes a transistor M N5 , transistor M N5 The source and resistor R 5Keep away from the ungrounded end and capacitor C 3. Stay away from resistors R 4 one end, resistor R 9 one end connected to the resistor R 9The other end is grounded, transistor M N5 The gate of transistor M N6 The gate of transistor M N6 The drain of transistor M N5 The drain of transistor M N4 The source of transistor M N6 The gate of transistor M N6 The drain of transistor M N6 The gate of transistor M N6 The drain and bias current source I bias2 One end is connected to the bias current source I bias2 The other end is connected to the power supply VDD, transistor M N6 The source of transistor M N3 The source of transistor M N4The drain of transistor M P2 The drain of transistor M P3 Gate, resistor R 10 One end connected to the resistor R 10 The other end and the capacitor C 6 one end connected to the capacitor C 6 The other end is connected to the power supply VDD; transistor M P2 The source of transistor M is connected to the power supply VDD. P2 The gate and capacitance C 6 Keep away from the power supply VDD end, resistor R 10 Keep away from transistor M N4 One end is connected to transistor M P3 The source of transistor M is connected to the power supply VDD. P3 The gate and capacitance C b One end connected, capacitor C b The other end is connected to transistor M P0 The drain of transistor M N0 The drain of transistor M P3 The drain and capacitance C a One end, transistor M N7 Drain, resistance R 11 One end is connected to transistor M N7 The gate and resistor R 11 Stay away from transistor M P3 One end, capacitor C 7 One end is connected to the capacitor C 7 The other end is grounded, transistor M N7 The source of transistor M is grounded. P0 Source, bias current source I bias1 Connect one end of the power supply VDD and the capacitor C 5 is connected to one end of the power supply VDD, transistor M P1 The source of transistor M P2 The source, capacitance C 6 is connected to one end of the power supply VDD and the bias current source I bias2 Connect one end of the power supply VDD to the transistor M P3 The source connection of the capacitor C 4 ground one end, transistor M N0 Source, resistor R 8 ground one end, resistor R 9 ground one end, transistor M N7 The source, capacitance C7 Connect one end to the ground.

[0041] Combine Figure 5 As shown, the demodulation circuit 4 includes capacitors C 8 and capacitors C 9. Capacitor C 8 One end and the resistor R 11 Keep away from capacitors C 7 one end, transistor M N7 The drain of transistor M P3 Drain, capacitance C a is far away from transistor M P0 One end connected, capacitor C 8The other end of the resistor R 15 One end, transistor M N12 Gate connection of capacitor C 9 one end and the resistor R 6. Keep away from capacitors C 4 one end, transistor M N0 The drain of transistor M P0 Drain, capacitance C b Keep away from transistor M P3 One end connected, capacitor C 9The other end of the resistor R 16 One end, transistor M N13 The gate of transistor M N12 The drain of transistor M N13 The drain of transistor M P10 The drain of transistor M P10 The gate of transistor M P11 The gate connection of transistor M N12 The source of transistor M N10 The source of transistor M N13 The source of transistor M N11 Drain connection of the resistor R 15 Keep away from capacitors C 8 one end, resistor R 16 Keep away from capacitors C 9 one end, transistor M P7 Drain, resistance R 14 One end connected to the resistor R 14 The other end is grounded; transistor M P10 The drain of transistor M P10 The gate connection of transistor M P10 The source of transistor M is connected to the power supply VDD.P11 The source of transistor M is connected to the power supply VDD. P11 The drain of transistor M N14 The drain of transistor M N10 The drain of transistor M P9 The drain of transistor M P9 The gate of transistor M P8 The gate connection of transistor M N10 The gate of transistor M P6 Drain, resistance R 12 One end connected to the resistor R 12 The other end of the resistor R 13 One end connected to the resistor R 13 The other end is grounded; transistor M P8 The gate of transistor M P9 The gate connection of transistor M P8 The source of transistor M P9 The source of transistor M is connected to the power supply VDD. P8 The drain of transistor M N9 The drain of transistor M N9 The gate connection of transistor M N14 The source of transistor M is grounded. N14 The gate of transistor M N9 The gate of transistor M N9 The drain of transistor M P8 The drain of transistor M N9 The source of transistor M is grounded; N11 The gate and control voltage signals V b1 Connection, transistor M N11 The source of transistor M is grounded; P7 The source of transistor M is connected to the power supply VDD. P7 The gate of transistor M P6 The gate of transistor M P5 The gate of transistor M P4 The gate, bias current source I bias3 One end is connected to the bias current source I bias3 The other end is grounded; transistor M P6 The source of transistor M is connected to the power supply VDD. P6 The drain and resistance R 12 Stay away from resistors R 13 One end, transistor M N10 The gate of transistor MP5 The source of transistor M is connected to the power supply VDD. P5 The drain of transistor M N8 The gate of transistor M N8 The drain of transistor M P4 The source of transistor M is connected to the power supply VDD. P4 The drain of transistor M P4 The gate, bias current source I bias3 The ungrounded end is connected; transistor M N8 The drain of transistor M N8 The gate connection of transistor M N8 The source is grounded.

[0042] Transistor M P4 The source of transistor M P5 The source of transistor M P6 The source of transistor M P7 The source of transistor M P8 The source of transistor M P9 The source of transistor M P10 The source of transistor M P11 Source connection of bias current source I bias3 Ground one end, transistor M N8 Source, resistor R 13 Ground one end, resistor R 14 Ground one end, transistor M N9 The source of transistor M N11 The source of transistor M N14 source connection.

[0043] The on-off keying modulation circuit 1 of the present invention is used to generate a carrier signal and output a differential signal with strong driving capability. V 1+ and differential signals V 1- The third-order differential isolation transmission circuit 2 is used to eliminate the influence of common-mode noise current on the frequency-selective amplifier circuit 3 and output a carrier signal with high common-mode transient immunity. V 2+ and carrier signal V 2- ; The frequency selective amplifier circuit 3 is used to convert the carrier signal V 2+ and carrier signal V 2- Amplify the amplified differential signal V 3+ and differential signals V 3-Demodulation circuit 4 is used to demodulate the amplified differential signal. V 3+ and differential signals V 3- Demodulated into a level signal, that is, the output signal V O .

[0044] The on-off keying modulation circuit 1 includes two differential comparators, AND gates NAND1 and NAND2, and three inverters of increasing sizes. The on-off keying modulation circuit 1 mixes and modulates the input PWM signal with the high-frequency signal generated by the oscillator. When the input is high, the on-off keying modulation circuit 1 modulates it into a carrier signal with the same frequency as the oscillator, and transmits it to the lower plate of the isolation capacitor on the transmitter side; when the input is low, no carrier signal is output from the transmitter. The differential comparator converts the oscillation signal into an oscillation signal with the input power supply voltage of the transmitter as a high level. When the input signal PWM is high, the AND gates NAND1 and NAND2 normally transmit the full-swing signal output by the differential comparator; the output stage of the on-off keying modulation circuit 1 is composed of inverters of increasing sizes, thereby increasing the current capacity of the output differential signal with the shortest delay. Finally, the on-off keying modulation circuit 1 outputs a differential signal with strong driving capability. V 1+ and V 1- .

[0045] Capacitors in the third-order differential isolation transmission circuit 2 module C ISO1 ,capacitance C ISO2 ,capacitance C ISO3 ,capacitance C ISO4 It is an isolation capacitor with a very small capacitance of only tens of fF. C 0. Capacitor C 1. Capacitor C 2. Capacitor C 3 is a low-voltage capacitor with a larger capacitance value, and the resistor R 0. Resistance R 1. Resistors R 2. Resistance R 3. Resistors R 4. Resistors R 5 is a low voltage resistor. VDD is the positive pole of the power supply, and GND represents the ground, i.e., the zero potential point. In practical applications, the third-order differential circuit can be equivalent to the first-order differential circuit. The differential signal with strong driving capability output by the on-off keying modulation circuit 1 V 1+ and differential signals V 1-Connected to capacitors C ISO1 ,capacitance C ISO3 The upper plate of the capacitor. C ISO1 ,capacitance C ISO2 and capacitors C ISO3 ,capacitance C ISO4 Signal transmission is carried out by using the dynamically changing electric field between the two plates of the isolation capacitor. Metal is used as the plate material of the capacitor, and silicon dioxide is used as the dielectric insulation layer in the middle of the capacitor. The insulation layer plays the role of isolation and voltage resistance. When transient electrical stress occurs, a common-mode current proportional to the rate of change of the transient voltage will be generated on the isolation capacitor. Low-voltage capacitors and low-voltage resistors are used to eliminate the influence of common-mode current on the frequency-selective amplifier of the subsequent drive circuit receiver. When common-mode current is generated, the current will produce a voltage drop on the resistor. R 0 and resistance R 3. The moment the voltage changes, the capacitor C 0 and capacitor C 2 will also generate a displacement current. The current in the upper branch resistance R 0. Resistance R 1 and the resistance of the lower branch R 3. Resistors R 4 produces a voltage drop, and at the same time the capacitance of the upper branch C 1, the displacement current is induced in the resistor R 2 produces a voltage drop, and the capacitance of the lower branch C 3. The displacement current induced on the resistor R 5. Due to the capacitance C 0. Capacitor C 1. Capacitor C 2. Capacitor C 3. The capacitance is large relative to the isolation capacitor, and when the rising and falling edges of the signal input from the transmitter are very steep and can be regarded as a step signal, the input square wave signal is the differential signal. V 1+ and differential signals V 1- The capacitance at the rising and falling edges C 0 and capacitor C 1. Capacitor C 2 and capacitor C 3 can be regarded as a short circuit. In order to reduce the impact of common mode current on the transmitter and improve the common mode transient immunity of the transmitter, and to reduce the area, the isolation capacitor size is only tens of fF. This makes the isolation capacitor and resistor R 0. Resistance R3 is very small, so the resistance R 0. Resistance R The voltage on 3 will stabilize in a very short time, and the capacitor will C 0. Capacitor C 2 will no longer generate displacement current, similarly capacitor C 1. Capacitor C 3. No displacement current will be generated above, which will eventually cause the resistor to R 2. Resistance R The voltage generated on 5 will recover in a very short time. C 0. Capacitor C 2 and resistor R 1. Resistors R 4 reduced Figure 3 middle V 2+ Point and V 2- The time constant of the two points makes the voltage of the two points recover faster. In summary, it can be understood that when common-mode transient electrical stress occurs, the common-mode noise current generated on the isolation capacitor basically only flows through the resistor R 0 and resistance R 3. The third-order differential isolation transmission circuit 2 finally outputs a carrier signal with high common-mode transient immunity. V 2+ and carrier signal V 2- .

[0046] The frequency selective amplifier circuit 3 includes a two-stage amplifier in cascade connection, which is used to convert the carrier signal V 2+ and carrier signal V 2- The amplified signal is then passed to the demodulation circuit 4 for demodulation. V 2+ and carrier signal V 2- Connect transistor M N3 and transistor M N5 The source of the bias current source I bias1 and bias current source I bias2 Through transistor M N1 and transistor M N6 Provide a constant current to the branch where resistors R8 and R9 are located, ensuring that transistor M N3 and transistor M N5 The first stage of the two-stage amplifier uses a common-gate structure amplifier, and the transistor M N1 and transistor M N6 Use diode connection to connect through resistorsR 8 and resistor R 9 is a transistor M N3 With transistor M N5 Provides gate bias voltage. R 7. Capacitor C 5. Transistor M P1 and resistors R 10 ,capacitance C 6. Transistor M P2 They respectively form active inductor structures, generating a zero point and two poles for the circuit, and realizing the peak gain near the carrier frequency. The second stage adopts the structure of common source amplifier. In order to reduce the influence of Miller effect, capacitor neutralization technology is used to offset Miller capacitance. C a The two ends of the transistor M are connected P0 The gate and transistor M P3 Drain, capacitance C b The two ends of the transistor M are connected P3 The gate and transistor M P0 The drain of the second stage is used to achieve capacitor neutralization. The second stage load adopts the same method as the first stage, using resistors, capacitors and transistors to form an active inductor to achieve the peak amplification of the second stage. The two stages are cascaded to achieve a large amplification capacity, and finally output the amplified carrier signal. V 3+ and carrier signal V 3- .

[0047] The demodulation circuit 4 includes a current comparator, which switches the transistor M N12 and transistor M N13 The current of transistor M N9 The current is compared with the current of the transistor M, copied by the current mirror, and finally passes through the transistor M N14 With transistor M P11 The output signal is determined by the current capability V O The state is used to amplify the carrier signal V 3+ and carrier signal V 3- Restore to level signal. VDD is the positive pole of power supply, GND is grounding, bias current source I bias3 Through the current mirror transistor M P4 To the subsequent transistor M P5 , transistor M P6 and transistor M P7 The branch provides a constant current and ensures its opening. V 3+and carrier signal V 3- Connect capacitors separately C 10 ,capacitance C 11 The upper plate of transistor M P6 and resistors R 12 ,resistance R 13 is transistor M N10 The gate bias provides a threshold voltage V TH , transistor M P7 and resistors R 14 is transistor M N12 and transistor M N13 Provides static bias voltage V CM ,resistance R 15 and capacitors C 10 With resistor R 16 and capacitors C 9 respectively form two high-pass filters to filter out the DC voltage of the differential signal output by the frequency-selective amplifier. V b1 is the bias voltage, N11 Provides stable gate voltage to enable it to work in the saturation region as a current source. Ensure the MOS tube threshold voltage during circuit design. V TH Greater than the common mode voltage V CM , while transistor M N10 The aspect ratio of transistor M N12 The width-to-length ratio is twice that of transistor M. N12 and transistor M N13 The width-to-length ratio is equal, so that under static conditions, that is, when there is no carrier signal, the tail current source transistor M N11 The current basically flows through transistor M N10 , and transistor M N12 and transistor M N13 Almost working in the cut-off region, at this time, after the current mirror copy, the transistor M N14 Turn on, transistor M P11 Shutdown, so that the output signal V O It is low level in static state. When the receiver receives the differential carrier signal, the frequency selective amplifier amplifies the signal into a differential signal. V 3+ and differential signals V3- , the amplified amplitude is much larger than the threshold voltage V TH , transistor M N12 and transistor M N13 Alternately conducting, the tail current source transistor M N11 The current only flows through transistor M N12 and transistor M N13 The transistor M N10 Basically no current flows through, and the same is copied by the current mirror, transistor M P11 Turn on, transistor M N14 Shutdown, the output signal V O Pulled to a high level, that is, when the input PWM signal is high, the transmitter transmits a carrier signal, and the receiver amplifies the carrier signal and demodulates it to restore the high-level signal.

[0048] This paper analyzes the timing and form of common-mode transient electrical stress and proposes a SiC MOSFET capacitor-isolated drive circuit to improve the chip's common-mode transient immunity. The isolation capacitor and third-order RC differential circuit couple and filter the common-mode noise current, eliminating its impact on the receiver's frequency-selective amplifier, effectively improving the system's CMTI performance and reliability. The isolated drive circuit in this invention has a high transient stress resistance capability, ensuring that the driver chip can function normally and meet the required common-mode transient immunity even when transient electrical stress exceeds the chip's common-mode transient immunity during power device switching.

Claims

1. A capacitive isolation drive circuit based on SiC MOSFET, characterized in that: The invention comprises an on-off keying modulation circuit (1), wherein the output end of the on-off keying modulation circuit (1) is connected to the input end of a third-order differential isolation transmission circuit (2), the output end of the third-order differential isolation transmission circuit (2) is connected to the input end of a frequency-selective amplifier circuit (3), and the output end of the frequency-selective amplifier circuit (3) is connected to the input end of a demodulation circuit (4).

2. The SiC MOSFET-based capacitive isolation drive circuit according to claim 1, wherein: The on-off keying modulation circuit (1) comprises a first differential comparator, the output end of the first differential comparator is connected to the input end of an AND gate NAND1, the output end of the AND gate NAND1 is connected to the input end of a first inverter, the output end of the first inverter is connected to the input end of a second inverter, and the output end of the second inverter is connected to the input end of a third inverter; the sizes of the first inverter, the second inverter, and the third inverter are increased in sequence.

3. The SiC MOSFET-based capacitive isolation drive circuit according to claim 2, wherein: The on-off keying modulation circuit (1) further comprises a second differential comparator, the output end of the second differential comparator is connected to the input end of the AND gate NAND2, the output end of the AND gate NAND2 is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the input end of the fifth inverter, and the output end of the fifth inverter is connected to the input end of the sixth inverter; the sizes of the fourth inverter, the fifth inverter, and the sixth inverter are increased in sequence; The input terminals of the AND gates NAND1 and NAND2 are connected to a control voltage signal V IN .

4. The SiC MOSFET-based capacitive isolation drive circuit according to claim 3, characterized in that: The third-order differential isolation transmission circuit (2) includes a capacitor C ISO1 , the capacitor C ISO1 The upper plate is connected to the output of the third inverter, and the capacitor C ISO1 The lower plate and capacitor C ISO2 The upper plate of the capacitor is connected to C ISO2 The lower plate and resistor R 0 one end, capacitor C 0 one end is connected, the resistor R 0 The other end is grounded, the capacitor C 0The other end of the resistor R 1 one end, capacitor C 1 one end is connected to the resistor R 1 The other end is grounded, the capacitor C 1The other end of the resistor R 2. Connect one end.

5. The SiC MOSFET-based capacitive isolation drive circuit according to claim 4, characterized in that: The third-order differential isolation transmission circuit (2) includes a capacitor C ISO3 , the capacitor C ISO3 The upper plate is connected to the output of inverter No. 6, and the capacitor C ISO3 The lower plate and capacitor C ISO4 The upper plate of the capacitor is connected C ISO4 The lower plate and resistor R 3 one end, capacitor C 2 one end is connected to the resistor R 3 The other end is grounded, the capacitor C 2The other end of the resistor R 4 one end, capacitor C 3 one end is connected to the resistor R 4The other end is grounded, the capacitor C 3The other end of the resistor R 5. Connect one end.

6. The SiC MOSFET-based capacitive isolation drive circuit according to claim 5, characterized in that: The frequency selective amplifier circuit (3) includes a transistor M N3 , the transistor M N3 The source and resistor R 2 Keep away from the ungrounded end and capacitor C 1. Stay away from resistors R 2 one end, resistor R 8 one end is connected to the resistor R 8 The other end is grounded, the transistor M N3 The gate of transistor M N1 The gate of transistor M N1 The drain of the transistor M is connected N3 The drain of transistor M N2 The source connection; The transistor M N1 The gate of transistor M N1 The drain of the transistor M is connected N1 The gate of transistor M N1 The drain and bias current source I bias1 One end is connected to the bias current source I bias1 The other end is connected to the power supply VDD, the transistor M N1 The source of transistor M N5 The source connection; The transistor M N2 The gate of transistor M N4 The gate of the transistor M is connected N2 The drain of transistor M P1 The drain of transistor M P0 Gate, resistor R 7 one end is connected to the resistor R 7The other end and the capacitor C 5 one end is connected to the capacitor C 5. The other end is connected to the power supply VDD; The transistor M P1 The source of the transistor M is connected to the power supply VDD. P1 The gate and capacitance C 5. Keep away from the power supply VDD end and resistor R 7 Keep away from transistor M N2 One end is connected; The transistor M P0 The source of the transistor M is connected to the power supply VDD. P0 The gate and capacitance C a One end is connected to the capacitor C a The other end is connected to transistor M P3 The drain of transistor M N7 The drain of the transistor M is connected P0 The drain and capacitance C b One end, transistor M N0 Drain, resistance R 6 one end connected; The transistor M N0 The gate and resistor R 6 Keep away from transistor M P0 One end, capacitor C 4 one end is connected to the capacitor C 4 The other end is grounded, the transistor M N0 The source is grounded.

7. The SiC MOSFET-based capacitive isolation drive circuit according to claim 6, wherein: The frequency selective amplifier circuit (3) further includes a transistor M N5 , the transistor M N5 The source and resistor R 5Keep away from the ungrounded end and capacitor C 3. Stay away from resistors R 4 one end, resistor R 9 one end is connected to the resistor R 9 The other end is grounded, the transistor M N5 The gate of transistor M N6 The gate of transistor M N6 The drain of the transistor M is connected N5 The drain of transistor M N4 The source connection; The transistor M N6 The gate of transistor M N6 The drain of the transistor M is connected N6 The gate of transistor M N6 The drain and bias current source I bias2 One end is connected to the bias current source I bias2 The other end is connected to the power supply VDD, the transistor M N6 The source of transistor M N3 The source connection; The transistor M N4 The drain of transistor M P2 The drain of transistor M P3 Gate, resistor R 10 One end is connected to the resistor R 10 The other end and the capacitor C 6 one end is connected to the capacitor C 6The other end is connected to the power supply VDD; The transistor M P2 The source of the transistor M is connected to the power supply VDD. P2 The gate and capacitance C 6 Keep away from the power supply VDD end, resistor R 10 Keep away from transistor M N4 One end is connected; The transistor M P3 The source of the transistor M is connected to the power supply VDD. P3 The gate and capacitance C b One end is connected to the capacitor C b The other end is connected to transistor M P0 The drain of transistor M N0 The drain of the transistor M is connected P3 The drain and capacitance C a One end, transistor M N7 Drain, resistance R 11 One end is connected; The transistor M N7 The gate and resistor R 11 Stay away from transistor M P3 One end, capacitor C 7 one end is connected to the capacitor C 7 The other end is grounded, the transistor M N7 The source is grounded.

8. The SiC MOSFET-based capacitive isolation drive circuit according to claim 7, characterized in that: The transistor M P0 Source, bias current source I bias1 Connect one end of the power supply VDD and the capacitor C 5 is connected to one end of the power supply VDD, transistor M P1 The source of transistor M P2 The source, capacitance C 6 is connected to one end of the power supply VDD and the bias current source I bias2 Connect one end of the power supply VDD to the transistor M P3 The source connection; The capacitor C 4 ground one end, transistor M N0 Source, resistor R 8 ground one end, resistor R 9 ground one end, transistor M N7 The source, capacitance C 7 Connect one end to the ground.

9. The SiC MOSFET-based capacitive isolation drive circuit according to claim 8, characterized in that: The demodulation circuit (4) includes a capacitor C 8 and capacitors C 9. The capacitor C 8 One end and the resistor R 11 Keep away from capacitors C 7 one end, transistor M N7 The drain of transistor M P3 Drain, capacitance C a is far away from transistor M P0 One end is connected to the capacitor C 8The other end of the resistor R 15 One end, transistor M N12 The gate connection; The capacitor C 9 one end and the resistor R 6. Keep away from capacitors C 4 one end, transistor M N0 The drain of transistor M P0 Drain, capacitance C b Keep away from transistor M P3 One end is connected to the capacitor C 9The other end of the resistor R 16 One end, transistor M N13 The gate connection; The transistor M N12 The drain of transistor M N13 The drain of transistor M P10 The drain of transistor M P10 The gate of transistor M P11 The gate of the transistor M is connected N12 The source of transistor M N10 The source of transistor M N13 The source of transistor M N11 The drain connection; The resistor R 15 Keep away from capacitors C 8 one end, resistor R 16 Keep away from capacitors C 9 one end, transistor M P7 Drain, resistance R 14 One end is connected to the resistor R 14 The other end is grounded; Transistor M P10 The drain of transistor M P10 The gate of the transistor M is connected P10 The source of the transistor M is connected to the power supply VDD. P11 The source of the transistor M is connected to the power supply VDD. P11 The drain of transistor M N14 The drain connection; The transistor M N10 The drain of transistor M P9 The drain of transistor M P9 The gate of transistor M P8 The gate of the transistor M is connected N10 The gate of transistor M P6 Drain, resistance R 12 One end is connected to the resistor R 12 The other end of the resistor R 13 One end is connected to the resistor R 13 The other end is grounded; The transistor M P8 The gate of transistor M P9 The gate of the transistor M is connected P8 The source of transistor M P9 The source of the transistor M is connected to the power supply VDD. P8 The drain of transistor M N9 The drain of transistor M N9 The gate connection; The transistor M N14 The source of the transistor M is grounded. N14 The gate of transistor M N9 The gate of transistor M N9 The drain of transistor M P8 The drain of the transistor M is connected N9 The source is grounded; The transistor M N11 The gate and control voltage signals V b1 connected, the transistor M N11 The source is grounded; The transistor M P7 The source of the transistor M is connected to the power supply VDD. P7 The gate of transistor M P6 The gate of transistor M P5 The gate of transistor M P4 The gate, bias current source I bias3 One end is connected to the bias current source I bias3 The other end is grounded; The transistor M P6 The source of the transistor M is connected to the power supply VDD. P6 The drain and resistance R 12 Stay away from resistors R 13 One end, transistor M N10 The gate connection; The transistor M P5 The source of the transistor M is connected to the power supply VDD. P5 The drain of transistor M N8 The gate of transistor M N8 The drain connection; The transistor M P4 The source of the transistor M is connected to the power supply VDD. P4 The drain of transistor M P4 The gate, bias current source I bias3 The ungrounded end is connected; The transistor M N8 The drain of transistor M N8 The gate of the transistor M is connected N8 The source is grounded.

10. The SiC MOSFET-based capacitive isolation drive circuit according to claim 9, characterized in that: The transistor M P4 The source of transistor M P5 The source of transistor M P6 The source of transistor M P7 The source of transistor M P8 The source of transistor M P9 The source of transistor M P10 The source of transistor M P11 The source connection; The bias current source I bias3 Ground one end, transistor M N8 Source, resistor R 13 Ground one end, resistor R 14 Ground one end, transistor M N9 The source of transistor M N11 The source of transistor M N14 source connection.

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