Low-overhead digital calibration method for offset error of high-precision low-delay analog-to-digital converter

Abstract

The invention discloses a high-precision low-delay analog-to-digital converter offset error low-overhead digital calibration method, and relates to the technical field of integrated circuit design, and the method comprises the steps: obtaining a bit weight matrix and an error vector according to the output of an analog-to-digital converter; amplifying the bit weight matrix to obtain a minimum segment matrix; performing least square on the error vector according to the minimum segment matrix to obtain a calibration weight vector; and calibrating the output of the analog-to-digital converter according to the minimum segment matrix and the calibration weight vector. According to the invention, the position weight matrix is amplified to obtain the minimum segment matrix, the minimum segment calibration is realized based on the minimum segment matrix, and the calibration precision is improved by increasing the number of calibration weights.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a high-precision, low-delay analog-to-digital converter offset error low-overhead digital calibration method. Background Art

[0002] Analog-to-Digital Converter (ADC) bit weight calibration is a technique used to compensate for ADC errors and improve accuracy. It is primarily used to correct bit weight deviations in converters such as successive approximation analog-to-digital converters (SAR ADCs), capacitive digital-to-analog converters (CDACs), and current-steering DACs (digital-to-analog converters). These deviations are typically caused by process mismatches, parasitic effects, or environmental factors, severely impacting the ADC's linearity and effective number of bits.

[0003] Bit weight calibration can only perform linear calibration for capacitor mismatch errors. Due to the presence of parasitic capacitance, capacitor mismatch errors are nonlinear. Therefore, traditional bit weight calibration has difficulty calibrating nonlinear errors caused by parasitic capacitance. Bit weight calibration usually relies on accurate estimation of the mismatch error of each bit capacitor in the analog-to-digital converter to generate effective calibration weights, thereby achieving accurate correction of the ADC output. However, in the actual calibration process, due to thermal noise interference and the limitations of process and device physical characteristics, error estimation is difficult to be completely accurate, resulting in certain deviations in the bit weight calibration results. Summary of the Invention

[0004] To address the above-mentioned problems in the prior art, the present invention provides a high-precision, low-latency, low-overhead digital calibration method for offset error of analog-to-digital converters. The technical problem to be solved by the present invention is achieved through the following technical solutions: The present invention provides a high-precision, low-latency, low-overhead digital calibration method for offset error of an analog-to-digital converter, comprising: Step 1: Obtain the bit weight matrix and error vector based on the output of the analog-to-digital converter; Step 2: Expand the bit weight matrix to obtain a minimum segment matrix; Step 3: performing least squares multiplication on the error vector according to the minimum segmentation matrix to obtain a calibration weight vector; Step 4: Calibrate the output of the analog-to-digital converter according to the minimum segment matrix and the calibration weight vector.

[0005] In one embodiment of the present invention, step 1 includes: Step 1.1: Sampling the binary digital code vector output by the analog-to-digital converter to obtain a bit weight matrix; Step 1.2: Perform sinusoidal fitting on the actual decimal output code vector of the analog-to-digital converter to estimate the ideal decimal output code vector of the analog-to-digital converter, and obtain the error vector based on the actual decimal output code vector and the ideal decimal output code vector.

[0006] In one embodiment of the present invention, the bit weight matrix is ​​expressed as: ; in, is the number of samples taken, is the number of bits of the analog-to-digital converter, For the The binary code vector of samples, , , For the The first of the binary digital code vectors of samples digit code.

[0007] In one embodiment of the present invention, the error vector is expressed as: ; in, is the error vector, is the actual decimal output code vector, is the ideal decimal output code vector.

[0008] In one embodiment of the present invention, step 2 includes: Step 2.1: Invert the column vector of the most significant bit in the bit weight matrix according to the binary bit to obtain the corresponding transformed column vector; Step 2.2: Combine the transformed column vector with the bit weight matrix to obtain the minimum segment matrix.

[0009] In one embodiment of the present invention, the minimum segment matrix is ​​expressed as: ; in, is the minimum piecewise matrix, is the transformation column vector, is the bit weight matrix, , is the column vector of the most significant bits in the bit weight matrix.

[0010] In one embodiment of the present invention, in step 3, the calibration weight vector is expressed as: ; in, is the calibration weight vector, is the minimum piecewise matrix, is the error vector, Represents matrix transpose.

[0011] In one embodiment of the present invention, in step 4, the output of the analog-to-digital converter is calibrated according to the following formula: ; in, is the calibrated decimal output code vector, is the actual decimal output code vector, is the minimum piecewise matrix, is the calibration weight vector.

[0012] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a high-precision, low-latency, low-overhead digital calibration method for offset errors of analog-to-digital converters. The method amplifies a bit weight matrix to obtain a minimum segmentation matrix, and implements minimum segmentation calibration based on the minimum segmentation matrix. The present invention improves the accuracy of calibration by increasing the number of calibration weights. The increase in calibration weights can more accurately estimate the nonlinear part of the capacitor mismatch model, because the increase in calibration weights makes the linear estimate closer to the nonlinear error, thereby achieving more accurate calibration. Increasing the calibration weights can also reduce the error in estimating the mismatched capacitance, thereby improving the accuracy of calibration.

[0013] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of a low-overhead digital calibration method for offset error of a high-precision, low-latency analog-to-digital converter provided by an embodiment of the present invention; Figure 2 is a flowchart of ADC error calibration using minimum segment calibration and bit weight calibration according to an embodiment of the present invention; Figure 3 The embodiment of the present invention provides a spectrum comparison diagram of uncalibrated, bit weighted and minimum segmented calibration; Figure 4It is a histogram of the signal-to-noise-and-distortion ratio (SNDR) and the spurious dynamic range (SFDR) before and after calibration using the method of the present invention in Monte Carlo simulation. DETAILED DESCRIPTION

[0015] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of a high-precision, low-latency, low-overhead digital calibration method for offset error of an analog-to-digital converter proposed in accordance with the present invention, in conjunction with the accompanying drawings and specific implementation methods.

[0016] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0017] The present invention provides a high-precision, low-latency, low-overhead digital calibration method for offset errors in analog-to-digital converters (ADCs). This method significantly improves calibration results by adding a small amount of calibration weights. Specifically, the method significantly improves the accuracy of ADC error calibration by improving the matrix structure in the bit-weighted calibration method and introducing a small amount of additional calibration weights. This method effectively enhances the accuracy and robustness of the calibration results while maintaining low computational complexity. The method can improve the calibration accuracy of various ADC error calibration methods, such as those based on least-squares sinusoidal fitting, filtering, and least-squares optimization. Furthermore, the method is applicable to both ADCs with binary and non-binary weight structures, demonstrating strong versatility and adaptability.

[0018] See Figure 1 , Figure 1 is a schematic diagram of a low-overhead digital calibration method for offset error of a high-precision, low-latency analog-to-digital converter provided by an embodiment of the present invention, such as Figure 1 As shown, the low-overhead digital calibration method for offset error of a high-precision, low-latency analog-to-digital converter according to an embodiment of the present invention includes the following steps: Step 1: Obtain the bit weight matrix and error vector based on the output of the analog-to-digital converter.

[0019] Optionally, step 1 includes: Step 1.1: Sample the binary digital code vector output by the analog-to-digital converter to obtain a bit weight matrix.

[0020] In this embodiment, the number of samples is , the number of bits of ADC , then the bit weight matrix composed of the sampling samples is expressed as: ; in, is the number of samples taken, is the number of bits of the analog-to-digital converter, For the The binary code vector of samples, , , For the The first of the binary digital code vectors of samples digit code, It is usually represented by binary 0 and 1.

[0021] The matrix form of the bit weight matrix can be expressed as: .

[0022] Step 1.2: Perform sinusoidal fitting on the actual decimal output code vector of the analog-to-digital converter to estimate the ideal decimal output code vector of the analog-to-digital converter. Obtain an error vector based on the actual decimal output code vector and the ideal decimal output code vector.

[0023] In this embodiment, the actual decimal output code vector of the ADC obtained by sampling is defined as , , , Indicates the The actual decimal output code of the sampling is .

[0024] The default input sinusoidal signal has a much higher accuracy than the ADC resolution, so the decimal output code vector of the ADC in the ideal case can be As an ideal sinusoidal signal, we can use the actual decimal output code vector of the ADC to calculate the Perform sinusoidal fitting to estimate the corresponding ideal decimal output code vector , It can be expressed as: , Indicates the The ideal decimal output code of the subsample is .

[0025] The error vector is the difference between the actual decimal output code vector of the ADC and the ideal decimal output code vector of the ADC. In this embodiment, the error vector is expressed as: ; in, is the error vector, is the actual decimal output code vector, is the ideal decimal output code vector.

[0026] Error vector It can be expressed as: , ,in ， Indicates the The error extracted from the samples.

[0027] It can be understood that the actual decimal output code vector of the ADC and bit weight matrix The following are the switches: ; in, is the weight vector of ADC, , , Indicates the weights, , if it is a binary ADC, then .

[0028] Step 2: Expand the bit weight matrix to obtain the minimum segmentation matrix.

[0029] Optionally, step 2 includes: Step 2.1: Invert the most significant column vector in the bit weight matrix according to the binary bit to obtain the corresponding transformed column vector; In this embodiment, let the transformation column vector be , specifically, , , To transform the bit weight matrix in D M-1 The 0 in the equation becomes 1 and the 1 in the equation becomes 0. , , is the bit weight matrix The column vector of the most significant bit (MSB) in . in is 1, then the corresponding in Is 0, on the contrary, if in is 0, then the corresponding in is 1.

[0030] You can do this by Perform linear transformation to obtain : .

[0031] Step 2.2: Combine the transformed column vector with the bit weight matrix to obtain the minimum segmentation matrix.

[0032] In this embodiment, the minimum segment matrix is ​​expressed as: ; in, is the minimum piecewise matrix, is the transformation column vector, is the bit weight matrix, , is the column vector of the most significant bits in the bit weight matrix.

[0033] For example, an 8-bit ADC outputs 12 decimal digital codes. , taking binary weight as an example, the corresponding bit weight matrix and the minimum segmentation matrix obtained after expansion As shown below: .

[0034] Step 3: Perform least squares on the error vector according to the minimum segmentation matrix to obtain the calibration weight vector.

[0035] In this embodiment, the calibration weight vector is expressed as: ; in, is the calibration weight vector, is the minimum piecewise matrix, is the error vector, Represents matrix transpose.

[0036] Calibration weight vector It can be expressed as: ,in, Representative The calibration weight corresponding to the bit, , represents the added calibration weight, in That is the calibration weight vector corresponding to the bit weight calibration .

[0037] Step 4: Calibrate the output of the analog-to-digital converter based on the minimum segmentation matrix and the calibration weight vector.

[0038] In this embodiment, the output of the analog-to-digital converter is calibrated according to the following formula: ; in, is the calibrated decimal output code vector, is the actual decimal output code vector, is the minimum piecewise matrix, is the calibration weight vector.

[0039] In practical applications, after the calibration weight vector is stored and locked, the ADC output can be calibrated directly in the subsequent sampling process. The corresponding minimum segmentation matrix is ​​obtained through the ADC output. , using the minimum segmentation matrix and the calibration weight vector The decimal output code vector of the ADC After calibration, the ADC decimal output code vector after calibration can be obtained. , , , Indicates the The decimal output code of the ADC after calibration.

[0040] The present invention provides a high-precision, low-latency, low-overhead digital calibration method for offset errors in analog-to-digital converters. By amplifying the bit weight matrix to obtain a minimum segmentation matrix, minimum segmentation calibration is performed based on this minimum segmentation matrix. Compared with existing bit weight calibration methods, the present invention offers the following advantages: (1) Traditional bit weight calibration methods can usually only compensate for linear errors caused by capacitor mismatch, and the calibration accuracy is significantly limited when facing nonlinear error models. The minimum segment calibration method proposed in this invention can more accurately approximate the nonlinear part of the capacitor mismatch error, thereby effectively correcting the nonlinear error source. In this way, the overall calibration accuracy of the ADC is significantly improved, which is particularly suitable for application scenarios in high-resolution ADC systems that require high error control accuracy.

[0041] (2) Traditional bit weight calibration typically relies on an accurate estimation of the capacitor mismatch error for each bit in the ADC in order to generate the corresponding calibration weights, thereby effectively correcting the ADC output. However, in the actual calibration process, due to thermal noise interference and the influence of device physical limitations, it is impossible to achieve a completely accurate estimation of the capacitor mismatch error, which leads to a certain error in the calibration weights. By introducing additional calibration weights, the present invention can compensate for the uncertainty in the error estimation to a certain extent, effectively improving the overall calibration accuracy.

[0042] Furthermore, the effects of the method of the present invention are illustrated by using specific examples. The minimum segment calibration method is applied to ADC error calibration based on least squares sine fitting, and the results are compared with the calibration results obtained by the same method using bit weight calibration.

[0043] See Figure 2 , Figure 2 This is a flowchart of ADC error calibration using minimum segment calibration and bit weight calibration provided by an embodiment of the present invention, wherein the left figure is a flowchart of ADC error calibration based on least squares sine fitting using minimum segment calibration, and the right figure is a flowchart of ADC error calibration based on least squares sine fitting using bit weight calibration.

[0044] like Figure 2 As shown in FIG, the ADC error calibration based on least square sine fitting with minimum segment calibration includes the following steps: S1: Make the high-precision signal source generate: the signal amplitude is Amp, the signal frequency is f in A single-tone sinusoidal signal is generated, and the high-precision single-tone sinusoidal signal is input into the ADC; S2: Quantize the input signal through the ADC for a period of time to obtain the ADC output digital code vector and bit weight matrix ; S3: Since the default input sinusoidal signal has a much higher accuracy than the ADC resolution, the ADC output under ideal conditions can be As an ideal sinusoidal signal, we can use the actual decimal output code vector of the ADC to calculate the Perform sinusoidal fitting to estimate the corresponding ideal decimal output code vector ; S4: By calculation Get the error vector ; S5: For bit weight matrix Amplify to get the minimum segmentation matrix ,make ,in , ,in To transform the bit weight matrix in The 0 in becomes 1, and the 1 becomes 0; , , is the bit weight matrix The column vector of the most significant bits (MSB) in . Perform linear transformation to obtain , and then and bit weight matrix Combining them, we can get the minimum segmentation matrix ; .

[0045] S6: For the error vector Perform least squares to obtain the calibration weight vector ; .

[0046] S7: After the calibration weight vector is stored and locked, the ADC output can be calibrated directly in the subsequent sampling process. The corresponding minimum segmentation matrix is ​​obtained through the ADC output. , using the minimum segmentation matrix and the calibration weight vector The actual decimal output code vector of the ADC After calibration, the decimal output code vector of the ADC can be obtained. , , , It can be expressed as: , Indicates the The decimal output code of the ADC after calibration.

[0047] like Figure 2 As shown in FIG, the ADC error calibration based on least square sine fitting with bit weight calibration includes the following steps: S1: Make the high-precision signal source generate: the signal amplitude is Amp, the signal frequency is f in The high-precision single-tone sinusoidal signal is input into the ADC; S2: Quantize the input signal through the ADC for a period of time to obtain the ADC output digital code vector and bit weight matrix ; S3: Since the default input sinusoidal signal has a much higher accuracy than the ADC resolution, the ADC output under ideal conditions can be As an ideal sinusoidal signal, we can use the actual decimal output code vector of the ADC to calculate the Perform sinusoidal fitting to estimate the corresponding ideal decimal output code vector ; S4: By calculation Get the error vector ; S5: For the error vector Perform least squares to obtain the calibration weight vector ; ; in, , Representative The calibration weight corresponding to the bit, .

[0048] S6: After the calibration weights are stored and locked, the ADC output can be calibrated directly in the subsequent sampling process. The corresponding bit weight matrix is ​​obtained through the ADC output. , using the bit weight matrix and the calibration weight vector The actual decimal output code vector of the ADC After calibration, the calibrated decimal output code vector can be obtained , , , , Indicates the The decimal output code of the ADC after calibration.

[0049] The proposed minimum segment calibration method was simulated and verified in MATLAB. The simulation object was a 24-bit SAR ADC. The calibration performance was evaluated under the following conditions: a relative error of 5% per unit capacitance, a sampling sequence length of 1024, and a calibration bit number of 15 bits. The sampling frequency was set during the simulation. f s = 2MHz, input signal frequency f in = 68.4 kHz. The traditional bit weight calibration method and the minimum segment calibration method proposed in this invention were respectively applied to the ADC error correction process based on least squares sine fitting to compare the performance difference between the two in terms of calibration accuracy.

[0050] See Figure 3 , Figure 3 The embodiment of the present invention provides a spectrum comparison diagram of uncalibrated, bit weighted and minimum segmented calibration. Figure 3As shown in the figure, in the uncalibrated state, the system achieves a signal-to-noise ratio (SNR) of 103.9 dB, a signal-to-noise and distortion ratio (SNDR) of 103.8 dB, an effective number of bits (ENOB) of 17.0 bits, a spurious dynamic range (SFDR) of 110.6 dB, and a total harmonic distortion (THD) of -125.4 dB. After bit weight calibration, the SNR improves to 123.4 dB, the SNDR to 123.3 dB, the ENOB to 20.2 bits, the SFDR to 140.2 dB, and the THD to -139.0 dB. Minimum segment calibration further improves performance, achieving an SNR of 137.6 dB, an SNDR of 137.6 dB, an ENOB of 22.6 bits, an SFDR of 150.8 dB, and a further reduction of THD to -162.1 dB. These results demonstrate that the proposed minimum segment calibration method significantly outperforms traditional calibration techniques and offers significant advantages in improving the overall performance of the analog-to-digital converter.

[0051] See Figure 4 and Table 1, Figure 4 The histograms of SNDR and SFDR before and after calibration in Monte Carlo simulation are shown in Table 1. The histograms of SNDR and SFDR before and after calibration in Monte Carlo simulation are shown in Table 1.

[0052] Table 1

[0053] Figure 4 Table 1 shows the histograms and statistical parameters of the SNDR and SFDR before and after bit weight calibration and minimum segment calibration, after 2000 Monte Carlo simulations under the above conditions. Compared to the uncalibrated state, the average SNDR improved by 19.35 dB and 34.63 dB, and the SFDR improved by 24.2 dB and 39.62 dB, respectively, with bit weight calibration and minimum segment calibration. Simulation results show that compared to bit weight calibration, minimum segment calibration improves SNDR and SFDR by 15.28 dB and 15.42 dB, respectively. Furthermore, the standard deviations of SNDR and SFDR with minimum segment calibration are significantly lower than with bit weight calibration. In summary, minimum segment calibration has superior calibration capabilities compared to bit weight calibration, and the ADC is more stable after calibration.

[0054] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the element.

[0055] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0056] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A high-precision, low-latency, low-overhead digital calibration method for offset error of analog-to-digital converters, characterized in that: include: Step 1: Obtain the bit weight matrix and error vector based on the output of the analog-to-digital converter; Step 2: Expand the bit weight matrix to obtain a minimum segment matrix; Step 3: performing least squares multiplication on the error vector according to the minimum segmentation matrix to obtain a calibration weight vector; Step 4: Calibrate the output of the analog-to-digital converter according to the minimum segment matrix and the calibration weight vector.

2. The high-precision, low-latency, low-overhead digital calibration method for offset error of an analog-to-digital converter according to claim 1, characterized in that: The step 1 comprises: Step 1.1: Sampling the binary digital code vector output by the analog-to-digital converter to obtain a bit weight matrix; Step 1.2: Perform sinusoidal fitting on the actual decimal output code vector of the analog-to-digital converter to estimate the ideal decimal output code vector of the analog-to-digital converter, and obtain the error vector based on the actual decimal output code vector and the ideal decimal output code vector.

3. The high-precision, low-latency, low-overhead digital calibration method for offset error of an analog-to-digital converter according to claim 2, characterized in that: The bit weight matrix is ​​expressed as: ； in, is the number of samples taken, is the number of bits of the analog-to-digital converter, For the The binary code vector of samples, , , For the The first of the binary digital code vectors of samples digit code.

4. The high-precision, low-latency, low-overhead digital calibration method for offset error of an analog-to-digital converter according to claim 2, wherein: The error vector is expressed as: ； in, is the error vector, is the actual decimal output code vector, is the ideal decimal output code vector.

5. The high-precision, low-latency, low-overhead digital calibration method for offset error of an analog-to-digital converter according to claim 1, wherein: The step 2 includes: Step 2.1: Invert the column vector of the most significant bit in the bit weight matrix according to the binary bit to obtain the corresponding transformed column vector; Step 2.2: Combine the transformed column vector with the bit weight matrix to obtain the minimum segment matrix.

6. The high-precision, low-latency, low-overhead digital calibration method for offset error of an analog-to-digital converter according to claim 5, characterized in that: The minimum segmentation matrix is ​​expressed as: ； in, is the minimum piecewise matrix, is the transformation column vector, is the bit weight matrix, , is the column vector of the most significant bits in the bit weight matrix.

7. The high-precision, low-latency, low-overhead digital calibration method for offset error of an analog-to-digital converter according to claim 1, characterized in that: In step 3, the calibration weight vector is expressed as: ； in, is the calibration weight vector, is the minimum piecewise matrix, is the error vector, Represents matrix transpose.

8. The high-precision, low-latency, low-overhead digital calibration method for offset error of an analog-to-digital converter according to claim 1, characterized in that: In step 4, the output of the analog-to-digital converter is calibrated according to the following formula: ； in, is the calibrated decimal output code vector, is the actual decimal output code vector, is the minimum piecewise matrix, is the calibration weight vector.

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