Method and apparatus for frequency response characteristic measurement

Abstract

The application relates to the technical field of electric digital data processing and provides a method and device for frequency response characteristic measurement. The method comprises the following steps: generating, by an analog waveform generator, a corresponding analog time-domain waveform as an analog input waveform of an input signal according to digital logic of the input signal received by an input node of a device to be measured, and obtaining, by a time-domain waveform collector, an output waveform of an output signal at an output node; when the output signal is a second electric signal, calculating, by a processor, a frequency response characteristic of the device based on the analog input waveform and a waveform of the second electric signal; and when the output signal is a first optical signal, performing, by the processor, a waveform adjustment operation according to the analog input waveform so as to obtain a third electric signal, and then calculating the frequency response characteristic. In this way, the frequency response characteristic of an on-chip equalizer is obtained, which is beneficial to the miniaturized design, high integration and low power consumption of a chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electric digital data processing, and in particular to a method and device for frequency response characteristic measurement. BACKGROUND

[0002] In the technical field of high-speed digital communication, high-speed optical communication, high-speed transmission interface, optical interconnection, etc., for example, data center, high-performance server, cloud computing, artificial intelligence, etc., data transmission and data processing between different nodes and different machines are involved, which may need to frequently amplify or attenuate signals in order to match the difference between the front and rear circuits, and may also need to adjust the frequency components in the electrical signal to offset the influence of the code interference caused by the transmission channel, such as printed circuit board (PCB) and cable, so as to improve the error-free transmission distance of the system. For example, the frequency response characteristics of the transmission channel can be corrected by an equalizer to reduce code interference and provide compensation, which helps to restore signal amplitude, rise time and fall time. With the shrinking of chip size and the improvement of integration, modules such as equalizers are generally integrated inside the chip, for example, deployed inside the die as part of the functional chip, so that the integrated circuit providing a specific function may include an equalizer with equalization function or similar functional modules for adjusting the frequency components of the electrical signal. In addition, in high-speed optical communication systems and data center optical interconnection applications, the system frequency response characteristics of the electrical-to-optical conversion may also be involved. The electrical signal adjusted by the equalizer is converted into an optical signal and output. In use, the equalizer or similar functional module may be affected by, for example, device aging, loss, etc., which may cause the performance to deviate from the design target, thereby affecting the compensation effect and signal transmission performance. Therefore, it is necessary to obtain the frequency domain characteristics and frequency response characteristics of the equalizer or similar functional module and evaluate them, which can provide a reference for adjusting the configuration and device calibration. For example, US patent US8934598B2 discloses an integrated equalizer and clock data recovery circuit, and the equalizer and clock / data recovery system are contained in a single package.

[0003] However, because equalizers or similar functional modules are integrated inside a chip or as part of an integrated circuit, it is difficult to obtain their frequency response characteristics by connecting test equipment such as a vector network analyzer (VNA) to the input and output terminals. This is because the output of an equalizer or similar functional module is generally located outside the chip. For example, electrical signals can be obtained through corresponding pins, or the output terminal can be located by analyzing the circuit structure and obtaining electrical signals through probes, or the output optical signal can be measured by connecting a VNA to the output terminal. However, the input terminal is generally located inside the chip, such as in an on-chip equalizer. Therefore, it is difficult to directly obtain electrical signals through pins, and it is also difficult to locate suitable probe positions by analyzing the circuit structure. Although it is possible to measure the time-domain performance of the input and output terminals of the entire chip or the entire integrated circuit including the equalizer, this measurement yields a joint frequency response characteristic for the entire chip or integrated circuit. It is difficult to distinguish the frequency response characteristics of the internal equalizer from those of other modules, which is not conducive to accurately obtaining the frequency response characteristics of the equalizer. US Patent 7688887B2 discloses a variable gain equalizer for applying variable gain to an input signal to generate an equalized output signal. It also discloses a phase and pattern detector circuit coupled to the variable gain equalizer in a feedback loop for identifying high-frequency data patterns in the equalized output signal and comparing these patterns with a clock signal to detect high-frequency phase errors. However, US Patent 7688887B2 requires the deployment of additional feedback loops and detector circuitry in the chip to detect high-frequency phase errors. This means additional circuit area and increased hardware costs, and it is not conducive to reducing overall power consumption.

[0004] To address these challenges, this application proposes a method and apparatus for measuring frequency response characteristics, which not only achieves accurate acquisition of the frequency response characteristics of the equalizer but also effectively handles situations where the input of the equalizer is located inside the chip, such as acquiring the frequency response characteristics of an on-chip equalizer. Furthermore, it eliminates the need to deploy additional feedback loops and detection circuits into the chip, which is beneficial for chip miniaturization, high integration, and low power consumption. Summary of the Invention

[0005] In a first aspect, this application provides a method for measuring frequency response characteristics. The method includes: generating a simulated time-domain waveform corresponding to the digital logic of the input signal received by the input node of the device under test (DUT) using a simulated waveform generator; and obtaining an output waveform of an output signal at the output node of the DUT using a time-domain waveform acquisition device. The input signal is a wide-frequency-range wave packet signal including multiple frequency components, the wave packet signal including a test pattern, the test pattern being consecutive identical digital segments with a preset segment length. The input signal is a first electrical signal, and the output signal is a second electrical signal or a first optical signal. When the output signal is the second electrical signal, the processor calculates the frequency response characteristics of the DUT based on the simulated input waveform and the waveform of the second electrical signal. When the output signal is the first optical signal, the processor performs waveform adjustment on the output waveform of the output signal based on the simulated input waveform to convert the first optical signal into a third electrical signal. Then, the processor calculates the frequency response characteristics of the DUT based on the simulated input waveform and the waveform of the third electrical signal.

[0006] The first aspect of this application sets requirements on the composition of the input signal, specifying that the input signal is a wave packet signal with a wide frequency range including multiple frequency components. Furthermore, it sets requirements on the code pattern of the input signal, specifying that the wave packet signal includes a test code pattern, and that the test code pattern is a series of identical digital segments with a preset segment length. Through optimized design of the input signal, a high-order system transfer function matching the frequency response characteristics of the device under test can be derived using digital processing algorithms, thus improving computational accuracy. Using a simulation waveform generator, a simulated time-domain waveform corresponding to the digital logic of the input signal is generated as a simulation of the input signal without the need for actual acquisition of the time-domain waveform of the input node. The input waveform, and the actual time-domain waveform of the output node were acquired through a time-domain waveform acquisition device. The output waveform of the output signal was obtained at the output node of the device under test. Finally, the frequency domain transfer function was analyzed by using the simulated input waveform of the input signal and the output waveform of the output signal. The first optical signal was converted into a third electrical signal by using waveform adjustment operation, and the frequency response characteristics of the electro-optical system were calculated. The frequency response characteristics of the equalizer were accurately obtained, which can effectively deal with the situation where the input of the equalizer is located inside the chip, such as obtaining the frequency response characteristics of the on-chip equalizer. Moreover, it does not require the deployment of additional feedback loops and detection circuits into the chip, which is beneficial to the miniaturization design, high integration and low power consumption of the chip.

[0007] In one possible implementation of the first aspect of this application, the amplitudes of at least two of the plurality of frequency components are inconsistent, or the amplitudes of the plurality of frequency components are the same.

[0008] In one possible implementation of the first aspect of this application, the test code includes a pseudo-random binary sequence.

[0009] In one possible implementation of the first aspect of this application, the consecutive identical digital segments having a preset segment length correspond to the low-frequency portion of the plurality of frequency components, and the low-frequency portion of the plurality of frequency components corresponding to the consecutive identical digital segments having a preset segment length is used to calculate the gain ratio or compression ratio of the device under test.

[0010] In one possible implementation of the first aspect of this application, the device under test includes an equalizer and a driver, wherein the equalizer is a continuous-time linear equalizer, a pre-emphasis equalizer, or a de-emphasis equalizer.

[0011] In one possible implementation of the first aspect of this application, the driver is based on current-mode logic or low-voltage differential signaling.

[0012] In one possible implementation of the first aspect of this application, the frequency response characteristics of the device under test indicate the equalization value and Nyquist frequency of the equalizer.

[0013] In one possible implementation of the first aspect of this application, when the output signal is the second electrical signal, the processor calculates the frequency response characteristics of the device under test based on the simulated input waveform and the waveform of the second electrical signal, including: performing differential processing on the first electrical signal and the second electrical signal using the simulated input waveform and the waveform of the second electrical signal to obtain a first differential electrical signal, wherein the differential mode component of the first differential electrical signal is used to calculate the frequency response characteristics of the device under test.

[0014] In one possible implementation of the first aspect of this application, the method further includes: inputting the first electrical signal into a plurality of system transfer functions to obtain a plurality of reference output electrical signals corresponding one-to-one with the plurality of system transfer functions; then, performing differential processing on the first electrical signal and the plurality of reference output electrical signals to obtain a plurality of reference differential electrical signals corresponding one-to-one with the plurality of reference output electrical signals; by comparing the differential mode components of the first differential electrical signal and the differential mode components of the plurality of reference differential electrical signals respectively, using an error function for iteration, selecting the system transfer function with the smallest error from the plurality of system transfer functions, and using the selected system transfer function with the smallest error to calculate the frequency response characteristics and system bandwidth of the device under test.

[0015] In one possible implementation of the first aspect of this application, when the output signal is the first optical signal, the processor performs waveform adjustment on the output waveform of the output signal according to the simulated input waveform to convert the first optical signal into the third electrical signal. Then, the processor calculates the frequency response characteristics of the device under test based on the simulated input waveform and the waveform of the third electrical signal, including: performing differential processing on the first electrical signal and the third electrical signal using the simulated input waveform and the waveform of the third electrical signal to obtain a second differential electrical signal, wherein the differential mode component of the second differential electrical signal is used to calculate the frequency response characteristics of the device under test.

[0016] In one possible implementation of the first aspect of this application, the method further includes: inputting the first electrical signal into a plurality of system transfer functions to obtain a plurality of reference output electrical signals corresponding one-to-one with the plurality of system transfer functions; then, performing differential processing on the first electrical signal and the plurality of reference output electrical signals to obtain a plurality of reference differential electrical signals corresponding one-to-one with the plurality of reference output electrical signals; by comparing the differential mode component of the second differential electrical signal and the differential mode component of each of the plurality of reference differential electrical signals respectively, using an error function for iteration, selecting the system transfer function with the smallest error from the plurality of system transfer functions, and using the selected system transfer function with the smallest error to calculate the frequency response characteristics and system bandwidth of the device under test.

[0017] In one possible implementation of the first aspect of this application, the error function is a function of the number of poles and zeros of the system transfer function, and the model characteristics of each of the plurality of system transfer functions include delay alignment time, rise time, fall time, and amplitude variation.

[0018] In one possible implementation of the first aspect of this application, when the output signal is the first optical signal, the processor performs the waveform adjustment operation on the output waveform of the output signal according to the simulated input waveform to convert the first optical signal into the third electrical signal. This includes: determining the average value of the waveform corresponding to the first optical signal; then subtracting the average value of the waveform corresponding to the first optical signal from the average value of the waveform corresponding to the first optical signal; and then performing the waveform alignment operation in the waveform adjustment operation according to the waveform corresponding to the first electrical signal.

[0019] In one possible implementation of the first aspect of this application, the wave packet form of the wave packet signal is determined according to the data format of the test code pattern, the consecutive identical digital segments are the reference for the amplitude adjustment operation in the waveform adjustment operation, and the consecutive identical digital segments are constant 0 segments or constant 1 segments.

[0020] In one possible implementation of the first aspect of this application, the device under test is deployed at the receiving end, and the input node corresponds to the output node of the recovered signal; or, the device under test is deployed at the transmitting end, and the input node corresponds to the output node of the transmitted signal sequence.

[0021] Secondly, this application provides an apparatus for measuring frequency response characteristics. The apparatus includes: a simulated waveform generator, configured to generate a simulated time-domain waveform corresponding to the digital logic of an input signal received by an input node of a device under test (DUT) as a simulated input waveform of the input signal; a time-domain waveform acquisition unit, configured to obtain an output waveform of an output signal at an output node of the DUT, wherein the input signal is a wave packet signal with a wide frequency range including multiple frequency components, the wave packet signal includes a test code pattern, the test code pattern being consecutive identical digital segments with a preset segment length, the input signal being a first electrical signal, and the output signal being a second electrical signal or a first optical signal; and a processor, configured to calculate the frequency response characteristics of the DUT based on the simulated input waveform and the waveform of the second electrical signal when the output signal is the second electrical signal, and to perform a waveform adjustment operation on the output waveform of the output signal based on the simulated input waveform when the output signal is the first optical signal, so as to convert the first optical signal into a third electrical signal, wherein the processor is further configured to calculate the frequency response characteristics of the DUT based on the simulated input waveform and the waveform of the third electrical signal.

[0022] The second aspect of this application sets requirements on the composition of the input signal, specifying that the input signal is a wave packet signal with a wide frequency range including multiple frequency components. Furthermore, it sets requirements on the code pattern of the input signal, specifying that the wave packet signal includes a test code pattern, and that the test code pattern is a series of identical digital segments with a preset segment length. Through optimized design of the input signal, a high-order system transfer function matching the frequency response characteristics of the device under test can be derived using digital processing algorithms, thus improving computational accuracy. Using a simulation waveform generator, a simulated time-domain waveform corresponding to the digital logic of the input signal is generated as a simulation of the input signal without the need for actual acquisition of the time-domain waveform of the input node. The input waveform, and the actual time-domain waveform of the output node were acquired through a time-domain waveform acquisition device. The output waveform of the output signal was obtained at the output node of the device under test. Finally, the frequency domain transfer function was analyzed by using the simulated input waveform of the input signal and the output waveform of the output signal. The first optical signal was converted into a third electrical signal by using waveform adjustment operation, and the frequency response characteristics of the electro-optical system were calculated. The frequency response characteristics of the equalizer were accurately obtained, which can effectively deal with the situation where the input of the equalizer is located inside the chip, such as obtaining the frequency response characteristics of the on-chip equalizer. Moreover, it does not require the deployment of additional feedback loops and detection circuits into the chip, which is beneficial to the miniaturization design, high integration and low power consumption of the chip. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A flowchart illustrating a method for measuring frequency response characteristics provided in an embodiment of this application;

[0025] Figure 2 A schematic diagram of a device for measuring frequency response characteristics provided in an embodiment of this application;

[0026] Figure 3 A schematic diagram illustrating a device under test deployed at a receiving end, as provided in an embodiment of this application;

[0027] Figure 4 A schematic diagram illustrating a device under test deployed at a transmitting end, as provided in an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0029] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0030] It should be understood that in the description of this application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first," "second," etc., unless otherwise stated, are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0031] Figure 1 This is a flowchart illustrating a method for measuring frequency response characteristics, provided as an embodiment of this application. Figure 1 As shown, the method includes the following steps.

[0032] Step S101: Using a simulation waveform generator, a simulated time-domain waveform corresponding to the digital logic of the input signal received by the input node of the device under test is generated as the simulated input waveform of the input signal, based on the digital logic of the input signal received by the input node of the device under test. Then, using a time-domain waveform acquisition device, the output waveform of the output signal is obtained at the output node of the device under test. The input signal is a wide-frequency-range wave packet signal including multiple frequency components. The wave packet signal includes a test code pattern, which is a series of identical digital segments with a preset segment length. The input signal is a first electrical signal, and the output signal is a second electrical signal or a first optical signal.

[0033] Step S103: When the output signal is the second electrical signal, the processor calculates the frequency response characteristics of the device under test based on the simulated input waveform and the waveform of the second electrical signal.

[0034] Step S105: When the output signal is the first optical signal, the processor adjusts the output waveform of the output signal according to the simulated input waveform to convert the first optical signal into a third electrical signal. Then, the processor calculates the frequency response characteristics of the device under test based on the simulated input waveform and the waveform of the third electrical signal.

[0035] Figure 1The method shown for measuring frequency response characteristics can be applied in technical fields such as high-speed digital communication, high-speed optical communication, high-speed transmission interfaces, and optical interconnects, including applications such as data centers, high-performance servers, cloud computing, and artificial intelligence. It utilizes a simulation waveform generator, a time-domain waveform acquisition unit, and a processor to calculate the frequency response characteristics of the device under test (DUT). The DUT can be an equalizer or a similar functional module for adjusting the frequency components of an electrical signal. In some embodiments, the DUT can be used in applications such as high-speed optical communication systems and data center optical interconnects, involving the frequency response characteristics of electro-optical systems, for example, where an equalizer-adjusted electrical signal is converted into an optical signal and output. In some embodiments, the DUT can be integrated into a chip or as part of an integrated circuit, meaning that it is difficult to obtain the frequency response characteristics of the DUT by connecting test equipment such as a vector network analyzer (VNA) to both the input and output ends. The device under test (DUT) is deployed between its upstream and downstream circuits. This may involve data transmission and processing between different nodes and machines. Frequent signal amplification or attenuation may be necessary to match the differences between upstream and downstream circuits. Adjustments to the frequency components of the electrical signal may also be needed to counteract inter-symbol interference (ISI) caused by the signal transmission path, such as printed circuit boards (PCBs) and cables, thereby improving the error-free transmission distance. During use, the equalizer or similar functional modules within the DUT may deviate from their design performance due to factors such as component aging and wear, affecting compensation effectiveness and signal transmission performance. Therefore, it is necessary to acquire and evaluate the frequency domain characteristics and frequency response of the equalizer or similar functional modules in real time and repeatedly to provide a reference for configuration adjustments and equipment calibration. However, the input terminal or input node of the device under test may be located inside the chip, or it may be difficult to accurately locate by analyzing the circuit structure, such as an on-chip equalizer. This means that it is difficult to obtain the input electrical signal on the input node through the corresponding pin or probe. In contrast, the output terminal or output node of the device under test can generally obtain the output electrical signal through the pin or probe, or the output optical signal can be measured by connecting a VNA to the output terminal.While it's possible to measure the time-domain performance of the entire chip or the entire integrated circuit including the device under test (DUT) and therefore its internal equalizer, this measurement yields a joint frequency response characteristic for the entire chip or integrated circuit. It's difficult to distinguish the DUT's frequency response characteristics from other modules; for example, it might be difficult to differentiate the DUT's frequency response characteristics from those of the preceding or following circuits. This hinders the accurate acquisition of the equalizer's frequency response characteristics. Furthermore, while deploying additional feedback loops and detector circuits may enable real-time detection of high-frequency phase errors in the DUT, this necessitates additional circuit area and increases hardware costs. It also doesn't reduce overall power consumption, thus failing to meet the requirements for chip miniaturization, high integration, and low power consumption.

[0036] See Figure 1In step S101, a simulated time-domain waveform corresponding to the digital logic of the input signal received by the input node of the device under test (DUT) is generated by a simulated waveform generator as the simulated input waveform of the input signal. Additionally, an output waveform of the output signal is obtained at the output node of the DUT using a time-domain waveform acquisition device. In some embodiments, the input node of the DUT may be located inside a chip or is difficult to accurately locate by analyzing the circuit structure. Therefore, it is difficult to directly acquire the time-domain waveform of the input signal using a acquisition device. For example, the DUT may be an on-chip equalizer, or it may be integrated inside a die as part of the die's physical layer. Although it is difficult to directly acquire the time-domain waveform or time-domain effect diagram of the input signal received by the input node, the digital logic of the input signal received by the input node can be determined, for example, the timing diagram of the high level (generally corresponding to digital logic 1 in a digital circuit) and low level (generally corresponding to digital logic 0 in a digital circuit) on the input node can be determined. It should be understood that, depending on the specific circuit design requirements, voltage levels can be set to represent binary "1" and "0". Generally, a high level corresponds to digital logic 1, and a low level corresponds to digital logic 0; conversely, in some cases, a high level can correspond to digital logic 0, and a low level to digital logic 1. Furthermore, different definitions and standards for voltage levels can be set, such as different logic level standards. By determining the digital logic of the input signal received by the input node of the device under test (DUT), and then combining the corresponding logic level standards and the correspondence between high and low levels and digital logic, a timing diagram reflecting the high and low level changes can be determined based on the digital logic of the input signal. Thus, a simulated time-domain waveform corresponding to the digital logic of the input signal is generated using a simulated waveform generator as the simulated input waveform of the input signal. Without needing to actually acquire the time-domain waveform of the input node, an approximate time-domain waveform, i.e., a simulated time-domain waveform corresponding to the digital logic of the input signal, can be generated based on the digital logic of the input signal received by the input node. Additionally, the output waveform of the output signal is obtained at the output node of the DUT using a time-domain waveform acquisition device, thus actually acquiring the time-domain waveform of the output node. As can be seen, the input node is equivalent to a virtual node because it is not necessary to actually acquire the virtual waveform of the input node. The input node is used to better indicate the digital logic of the input signal. In other words, the reference for subsequent processes is not the time-domain waveform of the actual acquired input node, but the simulated time-domain waveform generated by the simulated waveform generator that corresponds to the digital logic of the input signal, and thus serves as the simulated input waveform of the input signal for subsequent processes.Output nodes are actual physical nodes. For example, the output waveform can be obtained through pins, or it can be accurately located by analyzing the circuit structure and then obtained through probes. Alternatively, it can be measured by connecting a vector network analyzer to measure the output optical signal. The time-domain waveform of the actual acquired output node may be either an electrical signal or an optical signal, serving as a reference for subsequent processes. Similarly, the simulated input waveform of the input signal (i.e., the simulated time-domain waveform generated by the simulated waveform generator corresponding to the digital logic of the input signal), and the output waveform of the output signal actually acquired by the time-domain waveform acquisition device, serve as references for subsequent processes. Through waveform comparison and analysis in subsequent processes, the frequency response characteristics of the device under test (DUT) can be calculated. When the DUT includes an equalizer and a driver, the calculated frequency response characteristics are the combined frequency response characteristics of the equalizer and driver. When the DUT includes an equalizer, a driver, and optoelectronic devices, the calculated frequency response characteristics are the combined frequency response characteristics of the equalizer, driver, and optoelectronic devices. In some embodiments, the internal signal compensation method of the device under test can adopt a variety of technical means, and can also be combined with whether the device under test is deployed at the signal transmitting end or the signal receiving end to adopt the corresponding signal compensation method, such as continuous-time linear equalizer (CTLE), feed-forward equalizer (FFE), decision feedback equalizer (DFE), and pre-emphasis and de-emphasis.

[0037] Continue reading Figure 1The input signal is a wave packet signal with a wide frequency range including multiple frequency components. The wave packet signal includes a test code pattern, which is a continuous identical digit (CID) segment with a preset segment length. The input signal is a first electrical signal, and the output signal is a second electrical signal or a first optical signal. As described above, the simulated input waveform of the input signal, i.e., the simulated time-domain waveform corresponding to the digital logic of the input signal generated by the simulated waveform generator, and the output waveform of the output signal actually acquired by the time-domain waveform acquisition device, serve as reference benchmarks for subsequent processes. Through waveform comparison and analysis in subsequent processes, the frequency response characteristics of the device under test can be calculated. Therefore, by using a wave packet signal with a wide frequency range including multiple frequency components as the input signal, and by specifically designing the code pattern of the wave packet signal, i.e., requiring the wave packet signal to include a test code pattern and the test code pattern to be a continuous identical digit segment with a preset segment length, the frequency response characteristics of the device under test can be calculated. Thus, by inputting the optimized input signal to the device under test (DUT), and assuming no significant change between the frequency ranges of the input and output signals, the frequency domain transfer function can be analyzed using digital processing algorithms based on the simulated input waveform and the output waveform. This includes deriving the higher-order system transfer function corresponding to the frequency response characteristics of the DUT, calculating equalization values ​​(e.g., gain ratio or compression ratio), and determining peak, equalization, and Nyquist frequencies. Clock and data recovery (CDR) circuits and waveform shaping circuits can cause significant changes between the frequency ranges of the input and output signals, affecting the calculation of the DUT's frequency response characteristics. Therefore, DUTs generally do not include clock and data recovery or waveform shaping circuits internally to ensure minimal changes between the input and output frequency ranges. Thus, in the absence of internal devices or circuits such as clock data recovery circuits or waveform shaping circuits in the device under test (DUT) that would cause significant variations between the frequency range of the input signal and the frequency range of the output signal, a wave packet signal with multiple frequency components over a wide frequency range can be used as the input signal. Furthermore, a test code pattern consisting of consecutive identical digital segments of a preset length can be inserted into the input signal. This allows for the use of digital processing algorithms to construct a high-order system transfer function corresponding to the frequency response characteristics of the DUT, thereby enabling frequency domain transfer function analysis.In some embodiments, the input signal can be generated using a pseudo-random sequence, such as a pseudo-random binary sequence (PRBS), or other random generation algorithms, to produce a binary code sequence of 0s and 1s with random characteristics. This means that the digital logic of the input signal has certain random characteristics, as long as it meets the requirements of a wide-frequency-range wave packet signal with multiple frequency components and the test code pattern requirements of consecutive identical digital segments with a preset segment length. The wave packet signal includes multiple frequency components, that is, at least two different frequency components. The amplitudes of these multiple frequency components may be consistent or inconsistent. Therefore, influenced by multiple frequency components, this means that the time-domain waveform of the input signal (if it can be actually acquired) has the characteristic of irregular amplitude changes. As mentioned above, the input node is equivalent to a virtual node, which is actually impossible to measure or too difficult to measure. Therefore, a simulation waveform generator is used to generate a simulated time-domain waveform corresponding to the digital logic of the input signal, and the code pattern requirements of the input signal are optimized by using a wide-frequency-range wave packet signal with multiple frequency components. The time-domain waveform is actually acquired at the output node. When the device under test (DUT) exhibits electrical signal-to-electrical signal transmission characteristics, the time-domain waveform acquired at the output node is the time-domain waveform of the electrical signal. Conversely, when the DUT exhibits electrical signal-to-optical signal transmission characteristics, the time-domain waveform acquired at the output node is the time-domain waveform of the optical signal. The specific configurations of the DUT's front-end and back-end circuits can be flexibly adjusted according to actual needs. When the DUT is deployed at the receiving end, the front-end circuit can be the clock data recovery circuit within the chip, and the input node of the DUT can be the node where the clock data recovery circuit outputs the recovered signal. When the DUT is deployed at the transmitting end, the front-end circuit can be a signal sequence generator, and the input node of the DUT can be the output node of the transmitted signal sequence generated by the signal sequence generator.

[0038] Continue reading Figure 1The input signal is a first electrical signal, and the output signal is a second electrical signal or a first optical signal. In some embodiments, the device under test (DUT) may have electrical signal-to-electrical signal transmission characteristics. For example, the DUT may internally include an equalizer and a driver, which means that the output waveform of the output signal obtained at the output node of the DUT by the time-domain waveform acquisition device is the time-domain waveform of the electrical signal. In step S103, when the output signal is the second electrical signal, the processor calculates the frequency response characteristics of the DUT based on the simulated input waveform and the waveform of the second electrical signal. Thus, using a wide-frequency-range wave packet signal including multiple frequency components as the input signal, and utilizing the test code pattern included in the wave packet signal as continuous identical digital segments with a preset segment length, and through a simulated waveform generator, generating a simulated time-domain waveform corresponding to the digital logic of the input signal as the simulated input waveform of the input signal without actually acquiring the time-domain waveform of the input node, and through a time-domain waveform acquisition device, actually acquiring the time-domain waveform of the output node, obtaining the output waveform of the output signal at the output node of the device under test, and finally, using the simulated input waveform of the input signal and the output waveform of the output signal, performing frequency domain transfer function analysis based on digital processing algorithms, and deriving the higher-order system transfer function corresponding to the frequency response characteristics of the device under test. In this way, the frequency response characteristics of the equalizer are accurately obtained, effectively handling situations where the equalizer input is located inside the chip, such as obtaining the frequency response characteristics of an on-chip equalizer, without needing to deploy additional feedback loops and detection circuits into the chip, which is beneficial for chip miniaturization, high integration, and low power consumption.

[0039] Continue reading Figure 1The input signal is a first electrical signal, and the output signal is a second electrical signal or a first optical signal. In some embodiments, the device under test (DUT) may have electrical signal to optical signal transmission characteristics, for example, the DUT may include an equalizer, a driver, and optoelectronic devices. This allows the electrical signal, after being adjusted by the equalizer, to be finally converted into an optical signal and output. This means that the output waveform of the output signal obtained by the time-domain waveform acquisition device at the output node of the DUT is the time-domain waveform of the optical signal. In step S105, when the output signal is the first optical signal, the processor adjusts the output waveform of the output signal according to the simulated input waveform to convert the first optical signal into a third electrical signal. Then, the processor calculates the frequency response characteristics of the DUT based on the simulated input waveform and the waveform of the third electrical signal. Thus, a wide-frequency-range wave packet signal including multiple frequency components is used as the input signal, and the test code pattern included in the wave packet signal is a series of identical digital segments with a preset segment length. Furthermore, a simulated time-domain waveform corresponding to the digital logic of the input signal is generated as the simulated input waveform of the input signal using a simulated waveform generator, without the need to actually acquire the time-domain waveform of the input node. Additionally, the time-domain waveform of the output node is actually acquired using a time-domain waveform acquisition device, obtaining the output waveform of the output signal at the output node of the device under test. Here, the output signal is the first optical signal, therefore the output waveform of the output signal is the time-domain waveform of the first optical signal. The simulated input waveform of the input signal is a simulated digital waveform generated based on the digital logic of the input signal; therefore, the simulated input waveform of the input signal cannot be directly analyzed and compared with the time-domain waveform of the first optical signal. Therefore, when the output signal is the first optical signal, the processor performs a waveform adjustment operation on the output waveform of the output signal according to the simulated input waveform, thus converting the first optical signal into a third electrical signal. Then, based on the simulated input waveform and the waveform of the third electrical signal, the frequency response characteristics of the device under test are calculated. Thus, based on digital processing algorithms, the frequency domain transfer function is analyzed, and the higher-order system transfer function corresponding to the frequency response characteristics of the device under test is derived. This achieves accurate acquisition of the equalizer's frequency response characteristics, effectively addressing situations where the equalizer's input is located inside the chip, such as acquiring the frequency response characteristics of an on-chip equalizer. Furthermore, it eliminates the need to deploy additional feedback loops and detection circuits within the chip, which is beneficial for chip miniaturization, high integration, and low power consumption.

[0040] Continue reading Figure 1Optimizing the input signal is crucial for calculating the frequency response characteristics of the device under test (DUT). Specifically, requirements are set for the input signal's composition, limiting it to a wide-frequency-range wave packet signal comprising multiple frequency components. Furthermore, requirements are set for the input signal's code pattern, specifying that the wave packet signal includes a test code pattern, and that the test code pattern consists of consecutive identical digital segments of a predetermined segment length. Thus, the amplitude distribution of the multiple frequency components in the input signal follows a certain pattern, such as having consistent or inconsistent amplitudes, ultimately forming a wide-frequency-range wave packet signal. The wave packet signal corresponding to the input signal is input to the DUT from the input node and then output to the outside of the DUT via the output node. Therefore, during its transmission within the DUT, the frequency components of the wave packet signal may be adjusted, for example, amplified or attenuated. This means that the multiple frequency components included in the wave packet signal undergo an overall change in the frequency domain due to their transmission within the DUT. Therefore, by inputting a wide-frequency-range wave packet signal containing multiple frequency components into the device under test (DUT), and obtaining the corresponding output signal, this conversion process from input to output signal is influenced by the internal components and circuits of the DUT, which adjust the frequency components of the signal. For example, it is affected by the internal signal compensation functions of the DUT (e.g., pre-emphasis, de-emphasis, equalization, etc.). Thus, by utilizing the changes between the input and output signals, digital processing algorithms can be used to deduce the information about the frequency response characteristics of the DUT carried by these changes. This allows for the derivation of a higher-order system transfer function (SFC) that matches the frequency response characteristics of the DUT, which can be used for configuration adjustments, equipment calibration, and other applications. Here, the digital processing algorithm used to derive the higher-order SFC that matches the frequency response characteristics of the DUT can employ any suitable algorithm model and principle. For example, an error convergence algorithm can be used to select the SFC with the smallest error from multiple SFCs. Alternatively, the error function can be defined as a function of the number of poles and zeros, and then iterative and adaptive algorithms can be used to screen for the SFC with the smallest error. Another example is the use of digital fitting algorithms to approximate a suitable SFC model. Furthermore, considering that the input signal is limited to a wave packet signal with a wide frequency range and multiple frequency components, this means that, from the perspective of time domain analysis, the time-domain waveform of the input signal (if it is assumed that it can be actually acquired at the input node) has irregular amplitude variations, and the distribution of the peaks and troughs of the time-domain waveform of the input signal may also be irregular.Therefore, the digital processing algorithm used to derive the higher-order system transfer function (STF) that matches the frequency response characteristics of the device under test (DUT) does not compare rise and fall times in the time domain. Instead, it determines the overall changes in rise and fall times in the frequency domain. This leverages the key design requirement that the input signal is a wave packet signal with multiple frequency components over a wide frequency range. By deriving the higher-order STF with the minimum error, it characterizes the overall changes in rise and fall times in the frequency domain. Furthermore, the digital processing algorithm for deriving the higher-order STF that matches the frequency response characteristics of the DUT can consider other factors in the changes between the input and output signals, besides the changes in rise and fall times, thereby improving calculation accuracy. These factors include amplitude variations and delay alignment.

[0041] Continue reading Figure 1As mentioned above, by utilizing the changes between the input and output signals, digital processing algorithms can be used to deduce the information about the frequency response characteristics of the device under test (DUT) carried by these changes. This allows for the derivation of a higher-order system transfer function (STU) that matches the DUT's frequency response characteristics. Specifically, by leveraging the key design requirement that the input signal is a wide-frequency-range wave packet signal with multiple frequency components, instead of comparing rise and fall times in the time domain, the overall changes in rise and fall times are determined in the frequency domain. This allows for the derivation of a higher-order STU with minimal error, thus characterizing the overall rise and fall time changes in the frequency domain. Therefore, compared to inputting a signal with only a single frequency component and then changing that single frequency component for frequency scanning, using a wide-frequency-range wave packet signal with multiple frequency components as the input signal to the DUT allows for a more precise control over the amplitude distribution of the multiple frequency components. Furthermore, these multiple frequency components are pre-designed and do not change with the scanning mode. Here, the wave packet form of the wide-frequency-range wave packet signal with multiple frequency components is determined based on the data format of the input signal's code. As mentioned above, requirements are set for the code pattern of the input signal, specifying that the wave packet signal includes a test code pattern, and that the test code pattern is a series of identical digital segments with a preset segment length. For example, a constant 0 segment or a constant 1 segment is a series of identical digital segments with a preset segment length. The input signal can be generated using a pseudo-random sequence, such as a pseudo-random binary sequence, or other random generation algorithms, to produce a binary code sequence of 0s and 1s with random characteristics. The wave packet form is determined according to the specific pseudo-random code data format used by the algorithm that generates the input signal; for example, a constant 0 or constant 1 segment in that data format is used as a reference to adjust the amplitude. The advantage of this design is that, considering the irregular amplitude variation of the time-domain waveform of the input signal (assuming it can be actually acquired at the input node), and the irregular distribution of the peaks and troughs of the time-domain waveform of the input signal, the design requirements of the input signal code pattern, namely, the test code pattern with consecutive identical digital segments of a preset segment length, are utilized. For example, by utilizing the mechanism of consecutive identical digital segments of the pseudo-random binary sequence itself, multiple consecutive identical codewords may appear, such as nine consecutive constant 0 segments or 23 consecutive constant 1 segments. This can serve as a benchmark for waveform comparison and analysis.It should be noted that the input signal is a wave packet signal with a wide frequency range and multiple frequency components. Therefore, the test code pattern of consecutive identical digital segments with a preset segment length included in the wave packet signal corresponds to the low-frequency part of the multiple frequency components in the wave packet signal. Therefore, using the test code pattern of consecutive identical digital segments with a preset segment length as a reference is equivalent to using the low-frequency part of the wave packet signal to derive the equalization value of the device under test (DUT), such as the gain ratio or compression ratio. This allows for amplitude adjustment to improve the accuracy of the final calculation of the frequency response characteristics of the DUT. Furthermore, the DUT may include optoelectronic devices, such as devices that convert electrical signals into optical signals, like optical emitting devices. When the DUT includes optoelectronic devices, it means that the output signal is the first optical signal. Therefore, the output waveform of the output signal is the time-domain waveform of the first optical signal. The simulated input waveform of the input signal is a simulated digital waveform generated based on the digital logic of the input signal. Therefore, the simulated input waveform of the input signal cannot be directly analyzed and compared with the time-domain waveform of the first optical signal. By utilizing the processor's internal algorithm, the first optical signal can be converted into a third electrical signal through waveform adjustment operations. For example, waveform alignment can be achieved by removing the DC component. The frequency response characteristics of the device under test can then be calculated by using the changes between the first and third electrical signals. Therefore, it can be applied to scenarios that require a large number of optoelectronic devices, such as optical interconnects in data centers.

[0042] In short, Figure 1The method for measuring frequency response characteristics, as shown, imposes requirements on the composition of the input signal, limiting it to a wave packet signal with a wide frequency range including multiple frequency components. It also imposes requirements on the code pattern of the input signal, limiting the wave packet signal to include a test code pattern, where the test code pattern consists of consecutive identical digital segments with a preset segment length. Through optimized design of the input signal, a high-order system transfer function matching the frequency response characteristics of the device under test can be derived using digital processing algorithms, thus improving computational accuracy. Furthermore, by using a simulation waveform generator, a simulated time-domain waveform corresponding to the digital logic of the input signal is generated as the input signal without the need for actual acquisition of the time-domain waveform of the input node. The simulated input waveform and the actual time-domain waveform of the output node were acquired using a time-domain waveform acquisition device. The output waveform of the output signal was obtained at the output node of the device under test. Finally, the frequency domain transfer function was analyzed using the simulated input waveform and the output waveform of the output signal. The first optical signal was converted into a third electrical signal using waveform adjustment operations, and the frequency response characteristics of the electro-optical system were calculated. The frequency response characteristics of the equalizer were accurately obtained, which can effectively deal with the situation where the input of the equalizer is located inside the chip, such as obtaining the frequency response characteristics of the on-chip equalizer. Moreover, it does not require the deployment of additional feedback loops and detection circuits into the chip, which is beneficial to the miniaturization design, high integration and low power consumption of the chip.

[0043] Figure 2 This is a schematic diagram of a device for measuring frequency response characteristics, provided as an embodiment of this application. Figure 2As shown, the device includes: a simulated waveform generator A201, a time-domain waveform acquisition unit A203, and a processor A205. The simulated waveform generator A201 generates a simulated time-domain waveform corresponding to the digital logic A220 of the input signal received at the input node A212 of the device under test (DUT) A210, serving as the simulated input waveform A222 of the input signal. The time-domain waveform acquisition unit A203 obtains the output waveform A224 of the output signal at the output node A214 of the DUT A210. The input signal is a wave packet signal with a wide frequency range including multiple frequency components, and the wave packet signal includes a test code pattern, which is a series of identical digital segments with a preset segment length. The input signal is a first electrical signal, and the output signal is a second electrical signal or a first optical signal. The processor A205 calculates the frequency response characteristics of the DUT A210 based on the simulated input waveform A222 and the waveform of the second electrical signal when the output signal is the second electrical signal. The processor A205 is further configured to, when the output signal is the first optical signal, perform a waveform adjustment operation on the output waveform A224 of the output signal according to the simulated input waveform A222, so as to convert the first optical signal into a third electrical signal. The processor A205 is also configured to calculate the frequency response characteristics of the device under test A210 based on the simulated input waveform A222 and the waveform of the third electrical signal. Figure 2 The diagram also schematically illustrates the pre-amplifier circuit A280 and the post-amplifier circuit A282 relative to the device under test (DUT) A210. It should be understood that the pre-amplifier circuit A280 and the post-amplifier circuit A282 are only used to illustrate possible pre-amplifier circuit relationships for the DUT A210. Depending on the specific deployment of the DUT A210 and the chip design objectives, the pre-amplifier circuit A280 and the post-amplifier circuit A282 can each correspond to different functional modules, sub-circuits, and devices. The specific configuration of the pre-amplifier circuit A280 and the post-amplifier circuit A282 of the DUT A210 can be flexibly adjusted according to actual needs. For example, when the DUT A210 is deployed at the receiving end, the pre-amplifier circuit A280 of the DUT A210 can be the clock data recovery circuit inside the chip, and the input node A212 of the DUT A210 can be the node where the clock data recovery circuit outputs the recovered signal. For example, when the device under test (DUT) A210 is deployed at the transmitting end, the front-end circuit A280 of DUT A210 can be a signal sequence generator, and the input node A212 of DUT A210 can be the output node of the transmitted signal sequence generated by the signal sequence generator. The back-end circuit A282 of DUT A210 can correspond to chip pins, output modules, etc., depending on the specific application requirements.

[0044] Figure 2The apparatus shown for measuring frequency response characteristics imposes requirements on the composition of the input signal, limiting it to a wave packet signal with a wide frequency range including multiple frequency components. Furthermore, it imposes requirements on the code pattern of the input signal, limiting the wave packet signal to include a test code pattern, where the test code pattern consists of consecutive identical digital segments with a preset segment length. Through optimized design of the input signal, a high-order system transfer function matching the frequency response characteristics of the device under test (DUT) A210 can be derived using digital processing algorithms, improving computational accuracy. Using a simulation waveform generator A201, a simulated time-domain waveform corresponding to the digital logic A220 of the input signal is generated as the simulated input waveform A, without requiring actual acquisition of the time-domain waveform of the input node A212. 222, and, through the time-domain waveform acquisition unit A203, the time-domain waveform of the output node A214 was actually acquired, and the output waveform A224 of the output signal was obtained at the output node A214 of the device under test A210. Finally, using the simulated input waveform A222 of the input signal and the output waveform A224 of the output signal, the frequency domain transfer function analysis was realized; the first optical signal was converted into a third electrical signal by using waveform adjustment operation, and the frequency response characteristics of the electro-optical system were calculated; the frequency response characteristics of the equalizer were accurately obtained, which can effectively deal with the situation where the input end of the equalizer is located inside the chip, such as obtaining the frequency response characteristics of the on-chip equalizer, and there is no need to deploy additional feedback loops and detection circuits into the chip, which is beneficial to the miniaturization design, high integration and low power consumption of the chip.

[0045] Figure 3 This is a schematic diagram illustrating a device under test (DUT) deployed at a receiving end, as provided in an embodiment of this application. Figure 3As shown, the device for measuring frequency response characteristics includes: a simulated waveform generator B301, a time-domain waveform acquisition unit B303, and a processor B305. The simulated waveform generator B301 generates a simulated time-domain waveform corresponding to the digital logic B320 of the input signal received at the input node B312 of the device under test (DUT) B310, serving as the simulated input waveform B322 of the input signal. The time-domain waveform acquisition unit B303 obtains the output waveform B324 of the output signal at the output node B314 of the DUT B310. The input signal is a wide-frequency-range wave packet signal including multiple frequency components, and the wave packet signal includes a test code pattern, which is a series of identical digital segments with a preset segment length. The input signal is a first electrical signal, and the output signal is a second electrical signal or a first optical signal. Processor B305 is configured to, when the output signal is the second electrical signal, calculate the frequency response characteristics of the device under test B310 based on the simulated input waveform B322 and the waveform of the second electrical signal. Processor B305 is further configured to, when the output signal is the first optical signal, perform a waveform adjustment operation on the output waveform B324 of the output signal according to the simulated input waveform B322, so as to convert the first optical signal into a third electrical signal. Processor B305 is also configured to calculate the frequency response characteristics of the device under test B310 based on the simulated input waveform B322 and the waveform of the third electrical signal. Figure 3 The diagram also shows a clock data recovery circuit B380 as a pre-stage circuit relative to the device under test (DUT) B310, and a post-stage circuit B382 relative to the DUT B310. When the DUT B310 is deployed at the receiving end, the pre-stage circuit of the DUT B310 can be the on-chip clock data recovery circuit B380, and the input node B312 of the DUT B310 can be the node where the clock data recovery circuit B380 outputs the recovered signal. It should be understood that the clock data recovery circuit B380 and the circuit with waveform shaping function may cause a large variation between the frequency range of the input signal and the frequency range of the output signal. Therefore, Figure 3The clock data recovery circuit B380 in the diagram serves as a pre-amplifier for the device under test (DUT) B310; that is, the clock data recovery circuit B380 is not internal to the DUT B310. Thus, since the DUT B310 lacks internal components such as the clock data recovery circuit B380 or waveform shaping circuits that would cause significant variations between the input and output signal frequency ranges, a wide-frequency-range wave packet signal with multiple frequency components is used as the input signal. A test code pattern with consecutive identical digital segments of a preset length inserted into the input signal allows for the construction of a high-order system transfer function corresponding to the frequency response characteristics of the DUT B310 using digital processing algorithms, thereby enabling frequency domain transfer function analysis. The subsequent stage circuit B382 of the DUT B310 can correspond to components such as chip pins or output modules, depending on the specific application requirements.

[0046] Figure 3 The apparatus shown for measuring frequency response characteristics imposes requirements on the composition of the input signal, limiting it to a wave packet signal with a wide frequency range including multiple frequency components. Furthermore, it imposes requirements on the code pattern of the input signal, limiting the wave packet signal to include a test code pattern, where the test code pattern consists of consecutive identical digital segments with a preset segment length. Through optimized design of the input signal, a high-order system transfer function matching the frequency response characteristics of the device under test (DUT) B310 can be derived using digital processing algorithms, improving calculation accuracy. Using a simulation waveform generator B301, a simulated time-domain waveform corresponding to the digital logic B320 of the input signal is generated as the simulated input waveform B of the input signal without the need for actual acquisition of the time-domain waveform of the input node B312. 322, and, through the time-domain waveform acquisition unit B303, the time-domain waveform of the output node B314 was actually acquired, and the output waveform B324 of the output signal was obtained at the output node B314 of the device under test B310. Finally, using the simulated input waveform B322 of the input signal and the output waveform B324 of the output signal, the frequency domain transfer function analysis was realized; the first optical signal was converted into a third electrical signal by using waveform adjustment operation, and the frequency response characteristics of the electro-optical system were calculated; the frequency response characteristics of the equalizer were accurately obtained, which can effectively deal with the situation where the input end of the equalizer is located inside the chip, such as obtaining the frequency response characteristics of the on-chip equalizer, and there is no need to deploy additional feedback loops and detection circuits into the chip, which is beneficial to the miniaturization design, high integration and low power consumption of the chip.

[0047] Figure 4 This is a schematic diagram illustrating a device under test (DUT) deployed at a transmitting end, as provided in an embodiment of this application. Figure 4As shown, the device for measuring frequency response characteristics includes: a simulated waveform generator C401, a time-domain waveform acquisition unit C403, and a processor C405. The simulated waveform generator C401 generates a simulated time-domain waveform corresponding to the digital logic C420 of the input signal received at the input node C412 of the device under test (DUT) C410, serving as the simulated input waveform C422 of the input signal. The time-domain waveform acquisition unit C403 obtains the output waveform C424 of the output signal at the output node C414 of the DUT C410. The input signal is a wide-frequency-range wave packet signal including multiple frequency components, and the wave packet signal includes a test code pattern, which is a series of identical digital segments with a preset segment length. The input signal is a first electrical signal, and the output signal is a second electrical signal or a first optical signal. Processor C405 is used to calculate the frequency response characteristics of the device under test (DUT) C410 based on the simulated input waveform C422 and the waveform of the second electrical signal when the output signal is the second electrical signal. Processor C405 is also used to perform waveform adjustment on the output waveform C424 of the output signal according to the simulated input waveform C422 when the output signal is the first optical signal, so as to convert the first optical signal into a third electrical signal. Processor C405 is also used to calculate the frequency response characteristics of the DUT C410 based on the simulated input waveform C422 and the waveform of the third electrical signal. When the DUT C410 is deployed at the transmitting end, the front-end circuit of the DUT C410 can be a signal sequence generator C480, and the input node C412 of the DUT C410 can be the output node of the transmitted signal sequence generated by the signal sequence generator C480. The back-end circuit C482 of the DUT C410 can correspond to chip pins, output modules, etc., depending on the specific application requirements.

[0048] Figure 4The apparatus shown for measuring frequency response characteristics imposes requirements on the composition of the input signal, limiting it to a wave packet signal with a wide frequency range including multiple frequency components. Furthermore, it imposes requirements on the code pattern of the input signal, limiting the wave packet signal to include a test code pattern, where the test code pattern consists of consecutive identical digital segments with a preset segment length. Through optimized design of the input signal, a high-order system transfer function matching the frequency response characteristics of the device under test (DUT) C410 can be derived using digital processing algorithms, improving computational accuracy. Using a simulation waveform generator C401, a simulated time-domain waveform corresponding to the digital logic C420 of the input signal is generated as the simulated input waveform C, without requiring actual acquisition of the time-domain waveform of the input node C412. 422, and, through the time-domain waveform acquisition unit C403, the time-domain waveform of the output node C414 was actually acquired, and the output waveform C424 of the output signal was obtained at the output node C414 of the device under test C410. Finally, using the simulated input waveform C422 of the input signal and the output waveform C424 of the output signal, the frequency domain transfer function analysis was realized; the first optical signal was converted into a third electrical signal by using waveform adjustment operation, and the frequency response characteristics of the electro-optical system were calculated; the frequency response characteristics of the equalizer were accurately obtained, which can effectively deal with the situation where the input end of the equalizer is located inside the chip, such as obtaining the frequency response characteristics of the on-chip equalizer, and there is no need to deploy additional feedback loops and detection circuits into the chip, which is beneficial to the miniaturization design, high integration and low power consumption of the chip.

[0049] See Figure 1 , Figure 2 , Figure 3 as well as Figure 4 This application provides a method and apparatus for measuring frequency response characteristics, applicable to situations where the device under test (DUT) is deployed at the receiving or transmitting end. It can be applied in technical fields such as high-speed digital communication, high-speed optical communication, high-speed transmission interfaces, and optical interconnects, including applications such as data centers, high-performance servers, cloud computing, and artificial intelligence. It achieves accurate acquisition of the frequency response characteristics of the DUT, such as the combined frequency response characteristics of the equalizer and driver within the DUT, or the combined frequency response characteristics of the equalizer, driver, and optoelectronic devices within the DUT. It can flexibly adapt to various situations in the front-end and back-end circuits, effectively addressing the problem of the input node of the DUT being located inside the chip or difficult to accurately locate. Furthermore, it eliminates the need to deploy additional feedback loops and detection circuits into the chip, which is beneficial for chip miniaturization, high integration, and low power consumption.

[0050] In one possible implementation, at least two of the plurality of frequency components have inconsistent amplitudes, or the amplitudes of the plurality of frequency components are identical. Requirements are imposed on the composition of the input signal, defining it as a wave packet signal with a wide frequency range comprising multiple frequency components. Furthermore, requirements are imposed on the code pattern of the input signal, defining the wave packet signal as including a test code pattern, and the test code pattern as consecutive identical digital segments with a preset segment length. Thus, the amplitude distribution of the plurality of frequency components in the input signal follows a certain pattern, for example, having consistent or inconsistent amplitudes, ultimately forming a wave packet signal with a wide frequency range. The wave packet signal corresponding to the input signal is input to the device under test (DUT) from the input node and then output to the outside of the DUT via the output node. Therefore, during the transmission of the wave packet signal within the DUT, the frequency components of the wave packet signal may be adjusted, for example, amplified or attenuated. This means that the plurality of frequency components included in the wave packet signal undergo an overall change in the frequency domain due to the transmission process within the DUT. Therefore, by inputting a wide-frequency-range wave packet signal containing multiple frequency components into the device under test (DUT), a corresponding output signal is obtained. This conversion process from input signal to output signal is influenced by the internal devices and circuits of the DUT, which adjust the frequency components in the signal. For example, it is affected by the internal signal compensation functions of the DUT (such as pre-emphasis, de-emphasis, equalization, etc.). Thus, by utilizing the changes between the input and output signals, digital processing algorithms can be used to deduce the information about the frequency response characteristics of the DUT carried by the changes between the input and output signals. Furthermore, a higher-order system transfer function matching the frequency response characteristics of the DUT can be derived for configuration adjustment, equipment calibration, and other purposes. Therefore, the wave packet signal corresponding to the input signal may adopt the same amplitude design at different frequency points, that is, the amplitudes of the multiple frequency components are the same, or it may adopt the different amplitude design at different frequency points, that is, the amplitudes of at least two of the multiple frequency components are inconsistent. This means that the amplitude distribution of the multiple frequency components in the wave packet signal is flexible. It is possible to adopt a design where the amplitudes of the frequency components are consistent or inconsistent, and ultimately it is still possible to achieve the design goal of deriving a high-order system transfer function that matches the frequency response characteristics of the device under test.Therefore, unlike the frequency scanning method that uses an input signal with a single frequency component and changes that single frequency component, this frequency scanning method generally uses a bit error rate tester (BERT) and a pseudo-random binary sequence (PRBS) to compare data and calculate the bit error rate. Therefore, signals of the same amplitude are generally used at different frequency points. In contrast, the method and apparatus for measuring frequency response characteristics provided in the specific embodiments and implementation methods of this application use a wave packet signal with a wide frequency range and multiple frequency components as the input signal. Signals of the same or different amplitudes can be used at different frequency points, which provides better flexibility in the composition of the input signal and is conducive to its widespread application.

[0051] In one possible implementation, the test code pattern includes a pseudo-random binary sequence. The input signal can be generated using a pseudo-random sequence such as a pseudo-random binary sequence (PRBS), or other random generation algorithms, to produce a binary code sequence of 0s and 1s with random characteristics. This means that the digital logic of the input signal has certain random characteristics, as long as it meets the requirements of a wide frequency range wave packet signal with multiple frequency components and the requirements of a test code pattern with consecutive identical digital segments of a preset segment length. The wave packet form is determined according to the specific pseudo-random code data format used by the algorithm that generates the input signal; for example, a constant 0 or constant 1 segment in that data format is used as a reference to adjust the amplitude. The advantage of this design is that, considering the irregular amplitude variation of the time-domain waveform of the input signal (assuming it can be actually acquired at the input node), and the irregular distribution of the peaks and troughs of the time-domain waveform of the input signal, the design requirements of the input signal code pattern, namely, the test code pattern with consecutive identical digital segments of a preset segment length, are utilized. For example, by utilizing the mechanism of consecutive identical digital segments of the pseudo-random binary sequence itself, multiple consecutive identical codewords may appear, such as nine consecutive constant 0 segments or 23 consecutive constant 1 segments. This can serve as a benchmark for waveform comparison and analysis. It should be noted that the input signal is a wave packet signal with a wide frequency range and multiple frequency components. Therefore, the test code pattern of consecutive identical digital segments with a preset segment length included in the wave packet signal corresponds to the low-frequency part of the multiple frequency components in the wave packet signal. Therefore, using the test code pattern of consecutive identical digital segments with a preset segment length as a reference is equivalent to using the signal of the low-frequency part of the wave packet signal to derive the equalization value of the device under test, such as deriving the gain ratio or compression ratio. In this way, the accuracy of the final calculation of the frequency response characteristics of the device under test can be improved by adjusting the amplitude.

[0052] In one possible implementation, the consecutive identical digital segments with a preset segment length correspond to the low-frequency portion of the plurality of frequency components, and the low-frequency portion of the plurality of frequency components corresponding to the consecutive identical digital segments with the preset segment length is used to calculate the gain ratio or compression ratio of the device under test. As mentioned above, by utilizing the changes between the input and output signals, digital processing algorithms can be used to deduce the information about the frequency response characteristics of the device under test carried by the changes between the input and output signals, and thus derive a higher-order system transfer function that matches the frequency response characteristics of the device under test. Specifically, taking advantage of the key design requirement that the input signal is a wave packet signal with a wide frequency range and multiple frequency components, instead of comparing the rise and fall times in the time domain, the overall changes in rise and fall times are determined in the frequency domain, deriving a higher-order system transfer function with the smallest error, thereby characterizing the overall changes in rise and fall times in the frequency domain. Therefore, compared to inputting a signal with only a single frequency component and then changing that single frequency component for frequency scanning, inputting a wave packet signal with a wide frequency range and multiple frequency components as the input signal to the device under test (DUT) allows for amplitude distribution of the multiple frequency components within the wave packet signal to follow a certain pattern. Furthermore, these multiple frequency components are pre-designed and do not change with the scanning mode. Here, the wave packet form of the wide frequency range wave packet signal with multiple frequency components is determined based on the data format of the input signal's code pattern. As mentioned above, requirements are imposed on the input signal's code pattern, limiting the wave packet signal to include a test code pattern, and stating that the test code pattern is a series of identical digital segments with a preset segment length. For example, a constant 0 segment or a constant 1 segment is a series of identical digital segments with a preset segment length. The input signal can be generated using a pseudo-random sequence, such as a pseudo-random binary sequence, or other random generation algorithms to produce a binary code sequence of 0s and 1s with random characteristics. The wave packet form is determined based on the specific pseudo-random code data format used by the algorithm that generates the input signal; for example, a constant 0 or constant 1 segment from that data format is used as a reference to adjust the amplitude. The advantage of this design is that, considering the irregular amplitude variation of the time-domain waveform of the input signal (assuming it can be actually acquired at the input node), and the irregular distribution of the peaks and troughs of the time-domain waveform of the input signal, the design requirements of the input signal code pattern, namely, the test code pattern with consecutive identical digital segments of a preset segment length, are utilized. For example, by utilizing the mechanism of consecutive identical digital segments of the pseudo-random binary sequence itself, multiple consecutive identical codewords may appear, such as nine consecutive constant 0 segments or 23 consecutive constant 1 segments. This can serve as a benchmark for waveform comparison and analysis.It should be noted that the input signal is a wave packet signal with a wide frequency range and multiple frequency components. Therefore, the test code pattern of consecutive identical digital segments with a preset segment length included in the wave packet signal corresponds to the low-frequency part of the multiple frequency components in the wave packet signal. Therefore, using the test code pattern of consecutive identical digital segments with a preset segment length as a reference is equivalent to using the signal of the low-frequency part of the wave packet signal to derive the equalization value of the device under test, such as deriving the gain ratio or compression ratio. In this way, the accuracy of the final calculation of the frequency response characteristics of the device under test can be improved by adjusting the amplitude.

[0053] In one possible implementation, the device under test (DUT) includes an equalizer and a driver. The equalizer is a continuous-time linear equalizer, a pre-emphasis equalizer, or a de-emphasis equalizer. The internal signal compensation method of the DUT can employ various techniques, and the appropriate signal compensation method can be chosen based on whether the DUT is deployed at a signal transmitter or receiver. Examples include continuous-time linear equalizers (CTLE), feed-forward equalizers (FFE), decision-feedback equalizers (DFE), and pre-emphasis and de-emphasis. In some embodiments, the driver is based on current-mode logic or low-voltage differential signaling. Thus, the driver can employ various driving methods and differential signaling techniques, such as current-mode logic (CML) and low-voltage differential signaling (LVDS), which helps to provide beneficial effects such as low noise and low power consumption.

[0054] In one possible implementation, the frequency response characteristics of the device under test (DUT) indicate the equalization value and Nyquist frequency of the equalizer. Thus, by inputting the optimized input signal to the DUT, and assuming no significant change between the frequency range of the input and output signals, the frequency domain transfer function can be analyzed using digital processing algorithms based on the simulated input waveform and the output waveform. This includes deriving the higher-order system transfer function corresponding to the frequency response characteristics of the DUT, calculating the equalization value (e.g., gain ratio or compression ratio), and determining, for example, the peak frequency, equalization frequency, and Nyquist frequency.

[0055] In one possible implementation, when the output signal is the second electrical signal, the processor calculates the frequency response characteristics of the device under test based on the simulated input waveform and the waveform of the second electrical signal, including: performing differential processing on the first electrical signal and the second electrical signal using the simulated input waveform and the waveform of the second electrical signal to obtain a first differential electrical signal, wherein the differential mode component of the first differential electrical signal is used to calculate the frequency response characteristics of the device under test. Thus, using a wide-frequency-range wave packet signal including multiple frequency components as the input signal, and utilizing the test code pattern included in the wave packet signal as continuous identical digital segments with a preset segment length, and through a simulated waveform generator, generating a simulated time-domain waveform corresponding to the digital logic of the input signal as the simulated input waveform of the input signal without actually acquiring the time-domain waveform of the input node, and through a time-domain waveform acquisition device, actually acquiring the time-domain waveform of the output node, obtaining the output waveform of the output signal at the output node of the device under test, and finally, using the simulated input waveform of the input signal and the output waveform of the output signal, performing frequency domain transfer function analysis based on digital processing algorithms, and deriving the higher-order system transfer function corresponding to the frequency response characteristics of the device under test. In this way, the frequency response characteristics of the equalizer are accurately obtained, effectively handling situations where the equalizer input is located inside the chip, such as obtaining the frequency response characteristics of an on-chip equalizer, without needing to deploy additional feedback loops and detection circuits into the chip, which is beneficial for chip miniaturization, high integration, and low power consumption. Furthermore, differential processing can better capture the rise time, fall time, and level changes of the time-domain waveform of the electrical signal. The differential mode component of the first differential electrical signal obtained by differential processing reflects the change of the second electrical signal relative to the first electrical signal. In this way, the frequency response characteristics of the device under test can be calculated using the information of the change, and the frequency domain transfer function can be analyzed based on digital processing algorithms.

[0056] In some embodiments, the method further includes: inputting the first electrical signal into multiple system transfer functions to obtain multiple reference output electrical signals corresponding one-to-one with the multiple system transfer functions; then, performing differential processing on the first electrical signal and the multiple reference output electrical signals to obtain multiple reference differential electrical signals corresponding one-to-one with the multiple reference output electrical signals; by comparing the differential mode components of the first differential electrical signal and the differential mode components of the multiple reference differential electrical signals respectively, iterating using an error function, and selecting the system transfer function with the smallest error from the multiple system transfer functions; the selected system transfer function with the smallest error is used to calculate the frequency response characteristics and system bandwidth of the device under test. Thus, the digital processing algorithm for deriving a high-order system transfer function that matches the frequency response characteristics of the device under test can employ any suitable algorithm model and principle. For example, an error convergence algorithm can be used to select the system transfer function with the smallest error from multiple system transfer functions; another example is that the error function can be set as a function of the number of poles and zeros, and then iterative and adaptive algorithms can be used to filter out the system transfer function with the smallest error; yet another example is that a digital fitting algorithm can be used to approximate and calculate a suitable system transfer model. Here, multiple reference output electrical signals and corresponding reference differential electrical signals are obtained using multiple system transfer functions. Then, by comparing the differential-mode components of the first differential electrical signal and the differential-mode components of each of the multiple reference differential electrical signals, an error function is used for iteration to select the system transfer function with the smallest error from the multiple system transfer functions. In this way, a high-order system transfer function matching the frequency response characteristics of the device under test is efficiently determined through iterative and adaptive algorithms. The error function can be set as a function of the number of poles and zeros.

[0057] In one possible implementation, when the output signal is the first optical signal, the processor adjusts the output waveform of the output signal according to the simulated input waveform to convert the first optical signal into the third electrical signal. Then, the processor calculates the frequency response characteristics of the device under test (DUT) based on the simulated input waveform and the waveform of the third electrical signal. This includes: performing differential processing on the first electrical signal and the third electrical signal using the simulated input waveform and the waveform of the third electrical signal to obtain a second differential electrical signal. The differential-mode component of the second differential electrical signal is used to calculate the frequency response characteristics of the DUT. Since the output signal is the first optical signal, its output waveform is the time-domain waveform of the first optical signal. The simulated input waveform of the input signal is a simulated digital waveform generated based on the digital logic of the input signal. Therefore, the simulated input waveform of the input signal cannot be directly analyzed and compared with the time-domain waveform of the first optical signal. Therefore, when the output signal is the first optical signal, the processor adjusts the output waveform of the output signal according to the simulated input waveform, thus converting the first optical signal into the third electrical signal. Next, based on the simulated input waveform and the waveform of the third electrical signal, the frequency response characteristics of the device under test (DUT) are calculated. Thus, based on digital processing algorithms, the frequency domain transfer function is analyzed, and the higher-order system transfer function corresponding to the frequency response characteristics of the DUT is derived. Furthermore, differential processing can better capture the rise time, fall time, and level changes of the time-domain waveform of the electrical signal. The differential-mode component of the second differential electrical signal obtained through differential processing reflects the change of the third electrical signal relative to the first electrical signal. This change information can be used to calculate the frequency response characteristics of the DUT, and the frequency domain transfer function is analyzed based on digital processing algorithms.

[0058] In some embodiments, the method further includes: inputting the first electrical signal into multiple system transfer functions to obtain multiple reference output electrical signals corresponding one-to-one with the multiple system transfer functions; then, performing differential processing on the first electrical signal and the multiple reference output electrical signals to obtain multiple reference differential electrical signals corresponding one-to-one with the multiple reference output electrical signals; by comparing the differential mode components of the second differential electrical signal and the differential mode components of the multiple reference differential electrical signals respectively, iterating using an error function, and selecting the system transfer function with the smallest error from the multiple system transfer functions; the selected system transfer function with the smallest error is used to calculate the frequency response characteristics and system bandwidth of the device under test. Thus, the digital processing algorithm for deriving a high-order system transfer function that matches the frequency response characteristics of the device under test can employ any suitable algorithm model and principle. For example, an error convergence algorithm can be used to select the system transfer function with the smallest error from multiple system transfer functions; another example is that the error function can be set as a function of the number of poles and zeros, and then iterative and adaptive algorithms can be used to filter out the system transfer function with the smallest error; yet another example is that a digital fitting algorithm can be used to approximate and calculate a suitable system transfer model. Here, multiple reference output electrical signals and corresponding reference differential electrical signals are obtained using multiple system transfer functions. Then, by comparing the differential-mode components of the first differential electrical signal and the differential-mode components of each of the multiple reference differential electrical signals, an error function is used for iteration to select the system transfer function with the smallest error from the multiple system transfer functions. In this way, a high-order system transfer function matching the frequency response characteristics of the device under test is efficiently determined through iterative and adaptive algorithms. The error function can be set as a function of the number of poles and zeros.

[0059] In some examples, the error function is a function of the number of poles and zeros of the system transfer function, and the model characteristics of each of the multiple system transfer functions include the delay alignment time, rise time, fall time, and amplitude variation. Considering that the input signal is limited to a wave packet signal with a wide frequency range and multiple frequency components, this means that, from a time-domain analysis perspective, the time-domain waveform of the input signal (assuming it can be actually acquired at the input node) has irregular amplitude variations, and the distribution of peaks and troughs in the time-domain waveform may also be irregular. Therefore, the digital processing algorithm used to derive a higher-order system transfer function that matches the frequency response characteristics of the device under test does not compare the rise and fall times in the time domain, but rather determines the overall variation of the rise and fall times in the frequency domain. That is, by utilizing the key design requirement that the input signal is a wave packet signal with a wide frequency range and multiple frequency components, the algorithm derives a higher-order system transfer function with the minimum error, thereby characterizing the overall rise and fall time variations in the frequency domain. In addition, digital processing algorithms used to derive high-order system transfer functions that match the frequency response characteristics of the device under test can take into account not only the changes in rise time and fall time, but also other factors in the changes between the input and output signals, thereby improving the calculation accuracy, such as amplitude changes and delay alignment.

[0060] In some embodiments, when the output signal is the first optical signal, the processor performs a waveform adjustment operation on the output waveform of the output signal according to the simulated input waveform to convert the first optical signal into the third electrical signal. This includes: determining the average value of the waveform corresponding to the first optical signal; then, subtracting the average value of the waveform corresponding to the first optical signal from the average value of the waveform corresponding to the first optical signal; and then, performing a waveform alignment operation in the waveform adjustment operation according to the waveform corresponding to the first electrical signal. The device under test may include optoelectronic devices, such as devices that convert electrical signals into optical signals, like light emitting devices. When the device under test includes optoelectronic devices, it means that the output signal is the first optical signal. Therefore, the output waveform of the output signal is the time-domain waveform of the first optical signal. The simulated input waveform of the input signal is a simulated digital waveform generated based on the digital logic of the input signal. Therefore, the simulated input waveform of the input signal cannot be directly analyzed and compared with the time-domain waveform of the first optical signal. Using the processor's internal algorithms, a first optical signal can be converted into a third electrical signal through waveform adjustment operations. For example, waveform alignment can be achieved by removing the DC component. The frequency response characteristics of the device under test (DUT) are then calculated using the changes between the first and third electrical signals. Therefore, this approach can be applied to scenarios requiring a large number of optoelectronic devices, such as optical interconnects in data centers. For instance, the amplitude range of the waveform corresponding to the first electrical signal is from -100 millivolts (mV) to 100 mV, while the amplitude range of the waveform corresponding to the first optical signal is from 300 mW to 500 mW. To perform waveform alignment, the average values ​​of the waveforms can be aligned, i.e., the corresponding average values ​​are subtracted from each of the two original signals. Specifically, the average value of the waveform corresponding to the first optical signal is determined, and then the average value of the waveform corresponding to the first optical signal is subtracted from the average value of the waveform corresponding to the first optical signal. Then, the waveform alignment operation in the waveform adjustment operation is performed based on the waveform corresponding to the first electrical signal. Thus, through waveform adjustment and alignment, and by analyzing the frequency domain transfer function based on digital processing algorithms, the higher-order system transfer function corresponding to the frequency response characteristics of the DUT is derived. In this way, the frequency response characteristics of the equalizer can be accurately obtained, which can effectively deal with the situation where the input of the equalizer is located inside the chip, such as obtaining the frequency response characteristics of the on-chip equalizer. Moreover, there is no need to deploy additional feedback loops and detection circuits into the chip, which is beneficial to the miniaturization design, high integration and low power consumption of the chip.

[0061] In some examples, the wave packet form of the wave packet signal is determined according to the data format of the test code pattern. The consecutive identical digital segments serve as the reference for amplitude adjustment in the waveform adjustment operation, and these consecutive identical digital segments are either constant 0 segments or constant 1 segments. The wave packet form of a wide-frequency-range wave packet signal with multiple frequency components is determined according to the data format of the input signal's code pattern. As mentioned above, requirements are imposed on the input signal's code pattern, limiting the wave packet signal to include a test code pattern, and stating that the test code pattern is a series of consecutive identical digital segments with a preset segment length. For example, constant 0 segments or constant 1 segments are consecutive identical digital segments with a preset segment length. The input signal can be generated using a pseudo-random sequence, such as a pseudo-random binary sequence, or other random generation algorithms, to produce a binary code sequence of 0s and 1s with random characteristics. The wave packet form is determined according to the specific pseudo-random code data format used by the algorithm that generates the input signal; for example, using constant 0 or constant 1 segments in that data format as a reference for amplitude adjustment. The advantage of this design is that, considering the irregular amplitude variation of the time-domain waveform of the input signal (assuming it can be actually acquired at the input node), and the irregular distribution of the peaks and troughs of the time-domain waveform of the input signal, the design requirements of the input signal code pattern, namely, the test code pattern with consecutive identical digital segments of a preset segment length, are utilized. For example, by utilizing the mechanism of consecutive identical digital segments of the pseudo-random binary sequence itself, multiple consecutive identical codewords may appear, such as nine consecutive constant 0 segments or 23 consecutive constant 1 segments. This can serve as a benchmark for waveform comparison and analysis. It should be noted that the input signal is a wave packet signal with a wide frequency range and multiple frequency components. Therefore, the test code pattern of consecutive identical digital segments with a preset segment length included in the wave packet signal corresponds to the low-frequency part of the multiple frequency components in the wave packet signal. Therefore, using the test code pattern of consecutive identical digital segments with a preset segment length as a reference is equivalent to using the signal of the low-frequency part of the wave packet signal to derive the equalization value of the device under test, such as deriving the gain ratio or compression ratio. In this way, the accuracy of the final calculation of the frequency response characteristics of the device under test can be improved by adjusting the amplitude.

[0062] In one possible implementation, the device under test (DUT) is deployed at the receiving end, with the input node corresponding to the output node of the recovered signal; alternatively, the DUT is deployed at the transmitting end, with the input node corresponding to the output node of the transmitted signal sequence. The specific configuration of the front-end and back-end circuits of the DUT can be flexibly adjusted according to actual needs. When the DUT is deployed at the receiving end, the front-end circuit can be a clock data recovery circuit within the chip, and the input node of the DUT can be the node where the clock data recovery circuit outputs the recovered signal. When the DUT is deployed at the transmitting end, the front-end circuit can be a signal sequence generator, and the input node of the DUT can be the output node of the transmitted signal sequence generated by the signal sequence generator.

[0063] Figure 5 This is a schematic diagram of a computing device 500 provided in an embodiment of this application. The computing device 500 includes one or more processors D510, a communication interface 520, and a memory 530. The processors D510, the communication interface 520, and the memory 530 are interconnected via a bus 540. Optionally, the computing device 500 may further include an input / output interface 550, which is connected to input / output devices for receiving user-set parameters, etc. The computing device 500 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-described embodiments of this application; the processor D510 can also be used to implement some or all of the operation steps of the method embodiment in the above-described embodiments of this application. For example, the specific implementation of various operations performed by the computing device 500 can be referred to the specific details in the above embodiments, such as the processor D510 being used to execute some or all of the steps or operations in the above-described method embodiments. For example, in the embodiments of this application, the computing device 500 can be used to implement some or all of the functions of one or more components in the above-described device embodiments. In addition, the communication interface 520 can be used for communication functions necessary to implement the functions of these devices and components, and the processor D510 can be used for processing functions necessary to implement the functions of these devices and components.

[0064] It should be understood that, Figure 5 The computing device 500 may include one or more processors D510, and the multiple processors D510 may collaboratively provide processing power in a parallel connection, a serial connection, a serial-parallel connection, or an arbitrary connection manner; or the multiple processors D510 may form a processor sequence or a processor array; or the multiple processors D510 may be divided into a main processor and an auxiliary processor; or the multiple processors D510 may have different architectures, such as adopting a heterogeneous computing architecture. Furthermore, Figure 5The structural and functional descriptions of the computing device 500 shown are exemplary and non-limiting. In some exemplary embodiments, the computing device 500 may include... Figure 5 The diagram shows more or fewer components, or combinations of some components, or splitting of some components, or different arrangements of components.

[0065] The processor D510 can have various specific implementations. For example, it can include one or more combinations of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a tensor processing unit (TPU), or a data processing unit (DPU). This application does not impose specific limitations on these embodiments. The processor D510 can also be a single-core or multi-core processor. The processor D510 can be a combination of a CPU and hardware chips. These hardware chips can be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The PLDs can be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof. The processor D510 can also be implemented using logic devices with built-in processing logic, such as FPGAs or digital signal processors (DSPs). The communication interface 520 can be a wired interface or a wireless interface, used to communicate with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface can be a cellular network interface or a wireless LAN interface, etc.

[0066] Memory 530 may be non-volatile memory, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Memory 530 may also be volatile memory, which may be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 530 can also be used to store program code and data, so that the processor D510 can call the program code stored in the memory 530 to execute some or all of the operation steps in the above method embodiments, or to execute the corresponding functions in the above device embodiments. Furthermore, the computing device 500 may include, compared to... Figure 5 The number of components displayed may be more or less, or there may be different component configurations.

[0067] Bus 540 can be a Peripheral Component Interconnect Express (PCIe) bus, or an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc. Bus 540 can be divided into address bus, data bus, control bus, etc. In addition to the data bus, bus 540 can also include a power bus, control bus, and status signal bus. However, for clarity,Figure 5 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0068] The methods and devices provided in this application are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, the embodiments, implementation methods, examples, or methods of implementation of the methods and devices can be referred to each other, and repeated details will not be repeated. This application also provides a system comprising multiple computing devices, the structure of each computing device of which can refer to the structure of the computing devices described above. The functions or operations achievable by this system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0069] This application also provides a computer-readable storage medium storing computer instructions. When these computer instructions are executed on a computer device (such as one or more processors), they can implement the method steps described in the above method embodiments. The specific implementation of the above method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0070] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. This application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this application can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0071] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0072] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. The steps in the methods of the embodiments of this application can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A method for measuring frequency response characteristics, characterized in that, The method includes: A simulated waveform generator generates a simulated time-domain waveform corresponding to the digital logic of the input signal received by the input node of the device under test (DUT) as the simulated input waveform of the input signal. A time-domain waveform acquisition device obtains the output waveform of the output signal at the output node of the DUT. The input signal is a wide-frequency-range wave packet signal including multiple frequency components. The wave packet signal includes a test code pattern, which is a series of identical digital segments with a preset segment length. The input signal is a first electrical signal, and the output signal is a second electrical signal. When the output signal is the second electrical signal, the processor calculates the frequency response characteristics of the device under test based on the simulated input waveform and the waveform of the second electrical signal. This includes: performing differential processing on the first electrical signal and the second electrical signal using the simulated input waveform and the waveform of the second electrical signal to obtain a first differential electrical signal. The differential mode component of the first differential electrical signal is used to calculate the frequency response characteristics of the device under test. The method further includes: The first electrical signal is input into multiple system transfer functions to obtain multiple reference output electrical signals that correspond one-to-one with the multiple system transfer functions. Then, the first electrical signal and the multiple reference output electrical signals are differentially processed to obtain multiple reference differential electrical signals that correspond one-to-one with the multiple reference output electrical signals. By comparing the differential-mode components of the first differential electrical signal and the differential-mode components of the plurality of reference differential electrical signals respectively, and using an error function for iteration, the system transfer function with the smallest error is selected from the plurality of system transfer functions. The selected system transfer function with the smallest error is used to calculate the frequency response characteristics and system bandwidth of the device under test.

2. The method according to claim 1, characterized in that, The amplitudes of at least two of the plurality of frequency components are inconsistent, or the amplitudes of the plurality of frequency components are the same.

3. The method according to claim 1, characterized in that, The test code pattern includes a pseudo-random binary sequence.

4. The method according to claim 1, characterized in that, The consecutive identical digital segments with a preset segment length correspond to the low-frequency portion of the plurality of frequency components, and the low-frequency portion of the plurality of frequency components corresponding to the consecutive identical digital segments with a preset segment length is used to calculate the gain ratio or compression ratio of the device under test.

5. The method according to claim 1, characterized in that, The device under test includes an equalizer and a driver. The equalizer is a continuous-time linear equalizer, a pre-emphasis equalizer, or a de-emphasis equalizer.

6. The method according to claim 5, characterized in that, The driver is based on current-mode logic or low-voltage differential signaling.

7. The method according to claim 1, characterized in that, The frequency response characteristics of the device under test indicate the equalization value and Nyquist frequency of the equalizer.

8. A method for measuring frequency response characteristics, characterized in that, The method includes: A simulated waveform generator generates a simulated time-domain waveform corresponding to the digital logic of the input signal received by the input node of the device under test (DUT) as the simulated input waveform of the input signal. A time-domain waveform acquisition device obtains the output waveform of the output signal at the output node of the DUT. The input signal is a wide-frequency-range wave packet signal including multiple frequency components. The wave packet signal includes a test code pattern, which is a series of identical digital segments with a preset segment length. The input signal is a first electrical signal, and the output signal is a first optical signal. When the output signal is the first optical signal, the processor adjusts the output waveform of the output signal according to the simulated input waveform to convert the first optical signal into a third electrical signal. Then, the processor calculates the frequency response characteristics of the device under test based on the simulated input waveform and the waveform of the third electrical signal. This includes: performing differential processing on the first electrical signal and the third electrical signal using the simulated input waveform and the waveform of the third electrical signal to obtain a second differential electrical signal. The differential mode component of the second differential electrical signal is used to calculate the frequency response characteristics of the device under test. The method further includes: The first electrical signal is input into multiple system transfer functions to obtain multiple reference output electrical signals that correspond one-to-one with the multiple system transfer functions. Then, the first electrical signal and the multiple reference output electrical signals are differentially processed to obtain multiple reference differential electrical signals that correspond one-to-one with the multiple reference output electrical signals. By comparing the differential-mode components of the second differential electrical signal and the differential-mode components of the plurality of reference differential electrical signals respectively, and using an error function for iteration, the system transfer function with the smallest error is selected from the plurality of system transfer functions. The selected system transfer function with the smallest error is used to calculate the frequency response characteristics and system bandwidth of the device under test.

9. The method according to claim 8, characterized in that, The error function is a function of the number of poles and zeros of the system transfer function, and the model characteristics of each of the multiple system transfer functions include the delay alignment time, rise time, fall time, and amplitude variation.

10. The method according to claim 8, characterized in that, When the output signal is the first optical signal, the processor adjusts the output waveform of the output signal according to the simulated input waveform to convert the first optical signal into the third electrical signal, including: The average value of the waveform corresponding to the first optical signal is determined. Then, the average value of the waveform corresponding to the first optical signal is subtracted from the amplitude value of the waveform corresponding to the first optical signal. Then, the waveform alignment operation in the waveform adjustment operation is performed according to the waveform corresponding to the first electrical signal.

11. The method according to claim 10, characterized in that, The waveform packet form of the waveform packet signal is determined according to the data format of the test code pattern. The consecutive identical digital segments are the reference for the amplitude adjustment operation in the waveform adjustment operation. The consecutive identical digital segments are either constant 0 segments or constant 1 segments.

12. The method according to claim 1 or 8, characterized in that, The device under test is deployed at the receiving end, and the input node corresponds to the output node of the recovered signal; or, the device under test is deployed at the transmitting end, and the input node corresponds to the output node of the transmitted signal sequence.

13. A device for measuring frequency response characteristics, characterized in that, The device includes: A simulation waveform generator is used to generate a simulated time-domain waveform corresponding to the digital logic of the input signal received by the input node of the device under test, as the simulated input waveform of the input signal. A time-domain waveform acquisition unit is used to obtain the output waveform of the output signal at the output node of the device under test. The input signal is a wave packet signal with a wide frequency range including multiple frequency components. The wave packet signal includes a test code pattern, which is a series of identical digital segments with a preset segment length. The input signal is a first electrical signal, and the output signal is a second electrical signal. The processor is configured to calculate the frequency response characteristics of the device under test based on the simulated input waveform and the waveform of the second electrical signal when the output signal is the second electrical signal. The processor is configured to calculate the frequency response characteristics of the device under test (DUT) based on the simulated input waveform and the waveform of the second electrical signal when the output signal is the second electrical signal. This includes: performing differential processing on the first electrical signal and the second electrical signal using the simulated input waveform and the waveform of the second electrical signal to obtain a first differential electrical signal. The differential-mode component of the first differential electrical signal is used to calculate the frequency response characteristics of the DUT. The processor is also used for: The first electrical signal is input into multiple system transfer functions to obtain multiple reference output electrical signals that correspond one-to-one with the multiple system transfer functions. Then, the first electrical signal and the multiple reference output electrical signals are differentially processed to obtain multiple reference differential electrical signals that correspond one-to-one with the multiple reference output electrical signals. By comparing the differential-mode components of the first differential electrical signal and the differential-mode components of the plurality of reference differential electrical signals respectively, and using an error function for iteration, the system transfer function with the smallest error is selected from the plurality of system transfer functions. The selected system transfer function with the smallest error is used to calculate the frequency response characteristics and system bandwidth of the device under test.

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