Method and system for restoring clock at voip receiving end by fpga

Abstract

The application discloses a method and system for recovering clock at a VOIP receiving end through FPGA, and relates to the field of recovering clock. The method for recovering clock at the VOIP receiving end through FPGA is specifically disclosed as follows: a sending end packs source data transmitted by a falling edge of a source clock into a message and then transmits the message to a receiving end; the receiving end extracts the source data in the message and stores the source data into a receiving buffer; according to the change of the number of data in the receiving buffer, a clock control algorithm is used to output a recovered clock, and the data in the receiving buffer is output through a rising edge of the recovered clock; the clock control algorithm introduces the data transmission rate of the source clock and the maximum network jitter delay. The application can improve the accuracy and stability of clock recovery, solve the influence of the maximum network jitter delay, and reduce the operation scale of the algorithm.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of clock recovery, in particular to a method and system for recovering clock at VOIP receiving end through FPGA. BACKGROUND

[0002] VoIP is the abbreviation of Voice over Internet Protocol, which refers to the transmission of voice signals in the form of data packets in the environment of IP network after compression and packaging. In other words, it is also called Internet phone or IP phone. In VOIP communication, clock synchronization is the key to ensure accurate transmission of voice data. Referring to patent CN111600813A, a multi-mode interconnection interface controller for a converged network is proposed, which can automatically complete link training and rate negotiation, provide message physical layer coding to enhance the versatility and flexibility of the interconnection chip, and at the same time reduce the message penetration delay, which is suitable for the interconnection of data center Ethernet and high-performance computing high-speed network. However, this patent mainly focuses on the optimization of the physical layer, and does not provide a specific solution to the clock recovery problem in VOIP data transmission. Therefore, referring to patent CN108551378A, a method for long-distance transmission of radio frequency signals is disclosed, which comprises the steps of down-converting data, analog-to-digital conversion, low-pass filtering, etc., and adopts time division multiplexing method to form serial data, and finally restores the radio frequency signal at the receiving end. Although this patent proposes an effective data transmission and recovery scheme, it focuses on the long-distance transmission of radio frequency signals, and lacks specific description of the clock recovery technology at the VOIP data transmission end, especially without considering the influence of network delay jitter on clock recovery. And the current market products solve this problem by using adaptive clock recovery algorithm such as jitter prediction and discrete interpolation transformation. This algorithm is complex to implement and requires a large number of operations, which requires a high FPGA hardware resource. Field Programmable Gate Array (FPGA) is an integrated circuit that contains programmable logic blocks and programmable interconnection resources. Its internal structure can be changed through programming after manufacturing to realize specific functions or application requirements. This programmability makes FPGA have high flexibility and customizability in digital circuit design field. Based on the above content, the existing technology has deficiencies in the clock recovery mechanism at the VOIP data transmission end, especially in handling the synchronization problem between the source data clock and the receiving data clock, without effectively considering the influence of maximum network jitter delay. In view of this technical problem, it is necessary to propose a method and system for recovering clock at VOIP receiving end through FPGA, which aims to optimize the clock control algorithm, improve the accuracy and stability of clock recovery, and ensure the high-quality transmission of VOIP data. SUMMARY

[0003] The technical problem to be solved by the present application is that the clock recovery of the VOIP data transmission end fails to effectively consider the influence of the maximum network jitter delay when processing the synchronization between the source data clock and the received data clock, and the purpose is to provide a method and system for recovering the clock at the VOIP receiving end through FPGA, aiming to improve the accuracy and stability of clock recovery by optimizing the clock control algorithm, thereby ensuring the high-quality transmission of VOIP data, solving the influence of the maximum network jitter delay, and reducing the operation scale of the algorithm.

[0004] The present application is implemented by the following technical solutions:

[0005] The method for recovering the clock at the VOIP receiving end through FPGA comprises the following steps:

[0006] The receiving end extracts the source data in the message and stores it in the receiving buffer;

[0007] According to the change of the number of data in the receiving buffer, a recovery clock is output by using a clock control algorithm, and the data in the receiving buffer is output through the rising edge of the recovery clock.

[0008] The clock control algorithm introduces the data transmission rate of the source clock and the maximum network jitter delay.

[0009] The clock control algorithm specifically comprises:

[0010] Based on the weight of the data transmission rate of the source clock and the weight of the maximum network jitter delay, the preset data quantity is calculated according to the message length; it is judged whether the number of data in the receiving buffer reaches the preset data quantity; when it reaches, the data in the receiving buffer is output according to the initial rate value of the recovery clock; and it is recorded as the first data output period.

[0011] According to the change of the number of data in the receiving buffer, a recovery clock is output by using a clock control algorithm, and the data in the receiving buffer is output through the rising edge of the recovery clock.

[0012] It is judged in real time whether the number of remaining data in the receiving buffer is greater than a preset maximum number threshold, if yes, it is judged whether the first data output period is greater than a preset acceleration adjustment time interval of the recovery clock; only when it is greater than the preset acceleration adjustment time interval, the timing of the first data output period is cleared, and the rate value of the recovery clock is increased.

[0013] The clock control algorithm outputs a recovery clock according to the change of the number of data in the receiving buffer, and the data in the receiving buffer is output through the rising edge of the recovery clock.

[0014] If the number of remaining data in the receiving buffer is less than the preset maximum number threshold, it is determined whether the number of remaining data in the receiving buffer is less than the preset minimum number threshold; if yes, it is recorded as a second data output period; it is determined whether the second data output period is greater than a preset deceleration adjustment time interval of the recovery clock; only when yes, the timing of the second data output period is cleared, and the rate value of the recovery clock is reduced.

[0015] The first data output period is timed by a first timer, and the second data output period is timed by a second timer.

[0016] The system for recovering a clock at a VOIP receiving end through an FPGA includes a sending end and a receiving end; the sending end is used for packaging source data transmitted by a falling edge of a source clock into a packet and transmitting the packet to the receiving end; and the receiving end is used for extracting the source data in the packet.

[0017] The receiving end includes a receiving buffer and a clock recovery control module.

[0018] The receiving buffer is used for storing the source data transmitted by the sending end.

[0019] The clock recovery control module is used for outputting a recovery clock according to the change of the number of data in the receiving buffer through a clock control algorithm, and outputting the data in the receiving buffer through the rising edge of the recovery clock.

[0020] The clock control algorithm introduces the data transmission rate of the source clock and the maximum network jitter delay.

[0021] The clock control algorithm specifically includes:

[0022] According to the weight of the data transmission rate of the source clock and the weight of the maximum network jitter delay, a preset data number is calculated according to the length of the packet; it is determined whether the number of data in the receiving buffer reaches the preset data number; when yes, the data in the receiving buffer is output according to the initial rate value of the recovery clock; and it is recorded as a first data output period.

[0023] The sending end comprises a data-to-IP packet module; the receiving end comprises an IP packet data analysis module; source data is transmitted to the data-to-IP packet module through the falling edge of a source clock; the data-to-IP packet module packs the source data into an IP packet and sends the IP packet to the receiving end through a network; and the receiving end extracts the source data in the IP packet through the IP packet data analysis module.

[0024] An electronic device comprises a memory, a processor and a computer program running on the processor, and the processor implements the steps of the method for recovering a clock at a VOIP receiving end through an FPGA when running the computer program.

[0025] A computer readable storage medium stores a computer program, and the computer program implements the steps of the method for recovering a clock at a VOIP receiving end through an FPGA when executed by a processor.

[0026] Compared with the prior art, the present application has the following advantages and beneficial effects:

[0027] The present application provides a method for recovering a clock at a VOIP receiving end through an FPGA, a sending end packs source data transmitted by the falling edge of a source clock into a packet and transmits the packet to a receiving end; the receiving end extracts the source data in the packet and stores the source data in a receiving buffer; a clock control algorithm is used to output a recovered clock according to the change in the number of data in the receiving buffer, and the data in the receiving buffer is output through the rising edge of the recovered clock; the clock control algorithm introduces the weight of the data transmission rate of the source clock and the weight of the maximum network jitter delay. The present application optimizes the clock control algorithm, improves the accuracy and stability of clock recovery, ensures the high-quality transmission of VOIP data, solves the influence of the maximum network jitter delay, makes the recovered clock faster and more stable, and reduces the operation scale of the algorithm, thereby reducing the demand for hardware resources. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor. In the drawings:

[0029] Figure 1 The circuit principle diagram of the method for recovering a clock at a VOIP receiving end through an FPGA in the embodiments of the present application;

[0030] Figure 2 The principle diagram of the clock control algorithm in the embodiments of the present application;

[0031] Figure 3 The circuit principle diagram of the method for recovering clock at a VOIP receiving end through an FPGA is provided in the embodiments of the present application. DETAILED DESCRIPTION

[0032] In order to make the objects, technical solutions and advantages of the present application clearer, further detailed description will be given to the present application in combination with embodiments and drawings, and the schematic embodiments of the present application and the description thereof are only used to explain the present application, but not limit the present application.

[0033] EMBODIMENTS

[0034] As shown in the drawings, the embodiments of the present application provide a method for recovering clock at a VOIP receiving end through an FPGA, a sending end packs source data transmitted by a falling edge of a source clock into a packet and then transmits the packet to a receiving end; Figures 1-3

[0035] The receiving end extracts the source data in the packet and stores the source data into a receiving buffer;

[0036] According to the change of the number of data in the receiving buffer, a clock control algorithm is used to output a recovered clock, and the data in the receiving buffer is output through a rising edge of the recovered clock;

[0037] The clock control algorithm introduces the data transmission rate of the source clock and the maximum network jitter delay.

[0038] The clock control algorithm specifically includes:

[0039] Based on the weight of the data transmission rate of the source clock and the weight of the maximum network jitter delay, a preset data number is calculated according to the length of the packet; whether the number of data in the receiving buffer reaches the preset data number is judged; when the preset data number is reached, the data in the receiving buffer is output according to an initial rate value of the recovered clock; and the first data output period is recorded.

[0040] The clock control algorithm is used to output a recovered clock according to the change of the number of data in the receiving buffer, and the data in the receiving buffer is output through a rising edge of the recovered clock, specifically including:

[0041] The number of remaining data in the receiving buffer is judged in real time, and if the number of remaining data is greater than a preset maximum number threshold, whether the first data output period is greater than a preset acceleration adjustment time interval of the recovered clock is judged; when and only when the first data output period is greater than the preset acceleration adjustment time interval, the timing of the first data output period is cleared, and the rate value of the recovered clock is increased.

[0042] ​The clock control algorithm outputs a recovery clock according to the change of the number of data in the receiving buffer, and the data in the receiving buffer is output through the rising edge of the recovery clock.

[0043] If the number of remaining data in the receiving buffer is less than the preset maximum number threshold, it is determined whether the number of remaining data in the receiving buffer is less than the preset minimum number threshold; if yes, it is recorded as a second data output period; it is determined whether the second data output period is greater than a preset deceleration adjustment time interval of the recovery clock; only when yes, the timing of the second data output period is cleared, and the rate value of the recovery clock is reduced.

[0044] The first data output period is timed by a first timer, and the second data output period is timed by a second timer.

[0045] The system for recovering a clock at a VOIP receiving end through an FPGA includes a sending end and a receiving end; the sending end is used for packaging source data transmitted by a falling edge of a source clock into a packet and transmitting the packet to the receiving end; and the receiving end is used for extracting the source data in the packet.

[0046] The receiving end includes a receiving buffer and a clock recovery control module.

[0047] The receiving buffer is used for storing the source data transmitted by the sending end.

[0048] The clock recovery control module is used for outputting a recovery clock according to the change of the number of data in the receiving buffer through a clock control algorithm, and outputting the data in the receiving buffer through the rising edge of the recovery clock.

[0049] The clock control algorithm introduces the data transmission rate of the source clock and the maximum network jitter delay.

[0050] The clock control algorithm specifically includes:

[0051] According to the weight of the data transmission rate of the source clock and the weight of the maximum network jitter delay, a preset data number is calculated according to the length of the packet; it is determined whether the number of data in the receiving buffer reaches the preset data number; when it reaches, the data in the receiving buffer is output according to the initial rate value of the recovery clock; and it is recorded as a first data output period.

[0052] The sending end comprises a data-to-IP packet module; the receiving end comprises an IP packet data analysis module; source data is transmitted to the data-to-IP packet module through the falling edge of a source clock; the data-to-IP packet module packs the source data into an IP packet and sends the IP packet to the receiving end through a network; and the receiving end extracts the source data from the IP packet through the IP packet data analysis module.

[0053] The embodiment of the application provides a method for recovering a clock in a VOIP data transmission process through an FPGA, specifically, the FPGA dynamically corrects a clock by analyzing the size of data in a data receiving FIFO at a VOIP data receiving end, so that the clock at the receiving end is synchronized with the clock at the sending end. The method can effectively avoid the delay jitter of an IP network and guarantee the stability of the recovered clock. By using the clock recovery control algorithm, the interference of network jitter on clock recovery can be effectively eliminated, the clock can be quickly recovered to a stable state, a large amount of calculation is reduced, and the demand of the algorithm on hardware is reduced.

[0054] As shown in FIG. 1, Figure 1 As shown in FIG. 1, source data DATA is transmitted to a data-to-IP packet module through the falling edge of a source clock CLK, the data-to-IP packet module packs the source data DATA into an IP packet and transmits the IP packet to a receiving end through a network, the receiving end device extracts the source data from the IP packet after receiving the IP packet, and then stores the source data into a receiving buffer RX FIFO. A clock recovery module outputs a recovered clock according to the change of the number of data in the receiving buffer, and outputs the data in the receiving buffer through the rising edge of the recovered clock. When the recovered clock is consistent with the source clock, although the rapid fluctuation of the data in the receiving buffer is caused by the jitter of network delay, the data in the receiving buffer is generally stable. When the recovered clock is inconsistent with the source clock, the data in the receiving buffer will be more and more or less with the accumulation of time. The clock recovery control algorithm excludes the influence of network delay jitter first, and then keeps the number of data in the receiving buffer stable in a relatively long time, so as to synchronize the recovered clock with the source clock. As shown in FIG. 2, Figure 2 As shown in FIG. 2, N represents the total capacity of the receiving buffer, L represents the number of valid source data extracted from a network packet, the preset value X represents a preset data quantity, the threshold value A represents a preset maximum quantity threshold value for determining the threshold value of the data in the receiving buffer becoming more and more, and the threshold value B represents a preset minimum quantity threshold value for determining the threshold value of the data in the receiving buffer becoming more and more less. Figure 3 In the method, the first timer is denoted as cntA, the second timer is denoted as cntB, and the clock rate is denoted as the rate value of the recovered clock.

[0055] In the clock control algorithm of the present application, the preset data quantity X is calculated according to the maximum network jitter delay supported, X = data transmission rate of the source clock * maximum network jitter delay + message length L, the preset acceleration adjustment time interval Ta and the preset deceleration adjustment time interval Tb must be greater than the maximum network jitter delay, the preset maximum quantity threshold A must be greater than X, and the preset minimum quantity threshold B must be less than X. The clock recovery algorithm mainly utilizes that when the recovered clock is equal to the source clock, the data quantity change interval in the receiving buffer is preset value X to X-L when there is no network jitter, and the data quantity change interval in the receiving buffer is preset value X to 0 when there is network jitter. The data quantity in the receiving buffer is greater than the threshold B and less than the threshold A at the beginning in the two processes, and then is less than the threshold B and less than the threshold A, so the second timer cntB will be continuously cleared. Therefore, cntB will not exceed the preset deceleration adjustment time interval Tb, and the clock rate will remain unchanged. When the recovered clock rate value is greater than the source clock, the data accepted by the receiving buffer will be less than the data read out of the receiving buffer every message period, so that the data in the receiving buffer becomes less and less, and further the data quantity change interval in the receiving buffer is always less than the set threshold B. In order to exclude the false judgment that the data quantity in the receiving buffer is less than the set threshold B due to network delay jitter, when the data quantity in the receiving buffer is less than the set threshold B within Tb time, it is determined that the recovered clock rate is too large, and the recovered clock rate needs to be reduced. When the recovered clock rate is less than the source clock, the data accepted by the receiving buffer will be greater than the data read out of the receiving buffer every message period, so that the data in the FIFO becomes more and more, and further the data quantity change interval in the receiving buffer is greater than the set threshold A. Since the network jitter only makes the data quantity in the receiving buffer too small, as long as the data quantity in the receiving buffer is greater than the threshold A, it is determined that the recovered clock is too small, and the recovered clock rate needs to be accelerated. However, in order to prevent the recovered clock adjustment frequency from being too fast and causing the recovered clock to be unstable, a first timer cntA is added, which is cleared every time the recovered clock rate is accelerated, and then continuously timed. When cntA is greater than Ta, the second acceleration adjustment of the recovered clock rate is allowed. The specific implementation steps of the clock control algorithm are as follows:

[0056] 1. Initialize parameters, including the preset data quantity X of the receiving buffer, the preset maximum quantity threshold A, the preset minimum quantity threshold B, the preset acceleration adjustment time interval Ta of the recovered clock, and the preset deceleration adjustment time interval Tb of the recovered clock.

[0057] 2. Read the remaining data quantity in the receiving buffer of the current data reception.

[0058] 3. Determine whether the number of data in the receiving buffer is greater than the preset data number X. If no, jump back to step 2; if yes, start the data output of the receiving buffer and output the data in the receiving buffer according to the initial recovery clock rate.

[0059] 4. Read the number of remaining data in the receiving buffer of the current data reception.

[0060] 5. Determine whether the data in the receiving buffer is empty. If yes, consider that the network has been disconnected, close the data output of the receiving buffer, reset the value of the recovery clock rate of the receiving buffer output to the initial value, and then jump to step 2; if no, execute the next step.

[0061] 6. The first timer cntA accumulates a period of time.

[0062] 7. Determine whether the number of remaining data in the receiving buffer is greater than the preset maximum number threshold A. If yes, execute the next step; if no, directly jump to step 9.

[0063] 8. Determine whether cntA is greater than the preset acceleration adjustment time interval Ta. If yes, clear the first timer cntA, increase the value of the recovery clock rate by one, and jump to step 11; if no, directly jump to step 11.

[0064] 9. Determine whether the number of remaining data in the receiving buffer is less than the preset minimum number threshold B. If yes, the second timer cntB accumulates a period of time, and then execute the next step; if no, clear the second timer cntB and jump to step 11.

[0065] 10. Determine whether cntB is greater than the preset deceleration adjustment time interval Tb. If yes, clear the second timer cntB and decrease the value of the recovery clock rate by one; if no, do not perform any operation.

[0066] 11. Adjust the output corresponding recovery clock according to the value of the rate. After the adjustment is successful, jump to step 4 to perform the cyclic adjustment of the output recovery clock.

[0067] In summary, the embodiment of the present application provides a method and system for recovering clock at a VOIP receiving end through FPGA. The method for recovering clock at a VOIP receiving end through FPGA comprises the following steps: a sending end packs source data transmitted by a falling edge of a source clock into a message and then transmits the message to a receiving end; the receiving end extracts the source data in the message and stores the source data into a receiving buffer; according to the change of the number of data in the receiving buffer, a clock control algorithm is used to output a recovered clock, and the data in the receiving buffer is output through a rising edge of the recovered clock; the clock control algorithm introduces the weight of the data transmission rate of the source clock and the weight of the maximum network jitter delay. The present application optimizes the clock control algorithm, improves the accuracy and stability of clock recovery, ensures the high-quality transmission of VOIP data, solves the influence of the maximum network jitter delay, makes the recovered clock faster and more stable, reduces the operation scale of the algorithm, and thus reduces the demand for hardware resources.

[0068] The above detailed description is further detailed for the purpose of the present application, technical solutions and beneficial effects, and it should be understood that the above description is only a specific embodiment of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for recovering clock at a VOIP receiving end by FPGA, characterized in that, The sending end packs source data transmitted by the falling edge of a source clock into a packet and transmits the packet to a receiving end; The receiving end extracts source data in the packet and stores the source data in a receiving buffer; According to the change of the number of data in the receiving buffer, a clock control algorithm is used to output a recovery clock, and the data in the receiving buffer is output through the rising edge of the recovery clock; the clock control algorithm introduces the data transmission rate of the source clock and the maximum network jitter delay, and specifically includes: Based on the weight of the data transmission rate of the source clock and the weight of the maximum network jitter delay, a preset data quantity is calculated according to the length of the packet; it is judged whether the number of data in the receiving buffer reaches the preset data quantity; when the number of data reaches the preset data quantity, the data in the receiving buffer is output according to the initial rate value of the recovery clock; when the receiving buffer is not empty, a first timer is accumulated by one period of time; when the receiving buffer is empty, the output of the data in the receiving buffer is closed, and the rate value of the recovery clock is reset to the initial rate value; It is judged in real time whether the number of remaining data in the receiving buffer is greater than a preset maximum quantity threshold; if yes, it is judged whether the first timer is greater than a preset acceleration adjustment time interval of the recovery clock; only when the first timer is greater than the preset acceleration adjustment time interval, the timing of the first timer is cleared, and the rate value of the recovery clock is accumulated by one rate unit; If the number of remaining data in the receiving buffer is less than or equal to the preset maximum quantity threshold, it is judged whether the number of remaining data in the receiving buffer is less than a preset minimum quantity threshold; if yes, a second timer is accumulated by one period of time; it is judged whether the second timer is greater than a preset deceleration adjustment time interval of the recovery clock; only when the second timer is greater than the preset deceleration adjustment time interval, the timing of the second timer is cleared, and the rate value of the recovery clock is reduced by one rate unit; if the number of remaining data in the receiving buffer is greater than or equal to the preset minimum quantity threshold, the second timer is cleared.

2. A system for recovering clock at a VOIP receiving end by FPGA, characterized in that, The sending end and the receiving end; the sending end is used for packing source data transmitted by the falling edge of a source clock into a packet and transmitting the packet to the receiving end; the receiving end is used for extracting source data in the packet; The receiving end includes a receiving buffer and a clock recovery control module; The receiving buffer is used for storing source data transmitted by the sending end; The clock recovery control module is used for outputting a recovery clock by a clock control algorithm according to the change of the number of data in the receiving buffer, and outputting data in the receiving buffer through the rising edge of the recovery clock; the clock control algorithm introduces the data transmission rate of the source clock and the maximum network jitter delay, and specifically includes: According to the weight of a data transmission rate of the source clock and the weight of a maximum network jitter delay, a preset data quantity is calculated according to a packet length; whether the data quantity in the receiving buffer reaches the preset data quantity is judged; when the preset data quantity is reached, the data in the receiving buffer is output according to an initial rate value of the recovery clock; when the receiving buffer is not empty, a first timer is accumulated by one period of time; when the receiving buffer is empty, the output of the data in the receiving buffer is closed, and the rate value of the recovery clock is reset to the initial rate value; Real-time judgment is made on whether the quantity of the remaining data in the receiving buffer is greater than a preset maximum quantity threshold; if yes, whether the first timer is greater than a preset acceleration adjustment time interval of the recovery clock is judged; only when the first timer is greater than the preset acceleration adjustment time interval, the timing of the timer is cleared, and the rate value of the recovery clock is accumulated by one rate unit; If the quantity of the remaining data in the receiving buffer is less than or equal to the preset maximum quantity threshold, whether the quantity of the remaining data in the receiving buffer is less than a preset minimum quantity threshold is judged; if yes, a second timer is accumulated by one period of time; whether the second timer is greater than a preset deceleration adjustment time interval of the recovery clock is judged; only when the second timer is greater than the preset deceleration adjustment time interval, the timing of the second timer is cleared, and the rate value of the recovery clock is decreased by one rate unit; if the quantity of the remaining data in the receiving buffer is greater than or equal to the preset minimum quantity threshold, the second timer is cleared.

3. The system for recovering clock at a VOIP receiving end through FPGA according to claim 2, characterized in that, The sending end comprises a data-to-IP packet module; the receiving end comprises an IP packet data analysis module; source data is transmitted to the data-to-IP packet module through a falling edge of a source clock; the data-to-IP packet module packs the source data into IP packets and sends the IP packets to the receiving end through a network; the receiving end extracts the source data in the IP packets through the IP packet data analysis module.

4. An electronic device comprising a memory, a processor, and a computer program running on the processor, characterized in that: The processor executes the computer program to realize the steps of the method for recovering a clock at a VOIP receiving end through an FPGA according to claim 1.

5. A computer readable storage medium storing a computer program, characterized in that: The computer program is executed by the processor to realize the steps of the method for recovering a clock at a VOIP receiving end through an FPGA according to claim 1.

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