Memory, memory preparation method, chip and equipment

Abstract

The invention discloses a memory, a preparation method of the memory, a chip and equipment, and belongs to the technical field of semiconductors. The memory comprises a plurality of layers of memory cell arrays stacked on the substrate along a first direction vertical to the substrate and a plurality of word lines; each layer of memory cell array comprises at least one row of transistors arranged along a second direction parallel to the substrate; grid electrodes of the column of transistors arranged along the first direction are connected to form a word line corresponding to the column of transistors; a grid electrode of the transistor wraps the circumferential side wall of a channel, the channel comprises a supporting layer and a channel layer wrapping the circumferential side wall of the supporting layer, and the material of the channel layer is different from that of the supporting layer. Because the gate wraps the transistor of the channel, the contact area between the gate and the channel is large, and the gate control capability of the transistor is effectively improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a memory, a method for manufacturing a memory, a chip, and a device. Background Art

[0002] With the development of semiconductor technology, more and more applications require data storage through memory. The memory includes transistors, which are used to control the conduction of storage modules for storing charge, thereby controlling the flow of charge into or out of the storage modules, thereby achieving data storage based on the amount of charge stored in the storage modules. Summary of the Invention

[0003] The present invention provides a memory, a method for manufacturing a memory, a chip, and a device that can be used to stack multiple memory cell arrays. The technical solution is as follows:

[0004] In one aspect, an embodiment of the present application provides a memory comprising a plurality of memory cell arrays and a plurality of word lines stacked on a substrate along a first direction perpendicular to the substrate;

[0005] Each layer of the memory cell array includes at least one row of transistors arranged along a second direction parallel to the substrate;

[0006] The gates of a column of transistors arranged along the first direction are connected to form the word line corresponding to the column of transistors;

[0007] The gate of the transistor wraps around the circumferential sidewall of the channel. The channel includes a channel layer supporting and wrapping around the circumferential sidewall of the support layer. The material of the channel layer is different from that of the support layer.

[0008] In one possible implementation, the storage cell array further includes at least one capacitor, the capacitor and the transistor correspond one-to-one, the first source / drain of the transistor is connected to the first electrode plate of the corresponding capacitor; the first electrode plate has a hollow cup-shaped structure, and the hollow cup-shaped structure is arranged in a ring on the outer wall of the second electrode plate of the capacitor.

[0009] In a possible implementation, the second electrode plate of the capacitor includes a first part and a second part, the hollow cup-shaped structure is arranged in an annular manner on the outer wall of the first part, and the second part is arranged in an annular manner on the outer wall of the hollow cup-shaped structure.

[0010] In a possible implementation, the material of the channel layer is a metal oxide material, the electron mobility of the metal oxide material is higher than a first threshold, and the switching current ratio of the metal oxide material is higher than a second threshold.

[0011] In a possible implementation, the metal oxide material includes indium gallium zinc oxide (IGZO).

[0012] In a possible implementation, the memory further includes a plurality of bit lines, and each bit line corresponds one-to-one to a row of transistors included in each layer of the memory cell array;

[0013] The multiple bit lines are arranged at intervals along a first direction perpendicular to the substrate, and each bit line extends along a second direction parallel to the substrate, the second direction is perpendicular to the first direction, and each bit line is respectively connected to the second source / drain of the transistor included in the corresponding memory cell array.

[0014] In a second aspect, a method for preparing a memory is provided, the method comprising:

[0015] providing a substrate for a memory;

[0016] A stacked multi-layer memory cell array and a plurality of word lines are formed on the substrate along a first direction perpendicular to the substrate, each layer of the memory cell array includes at least one row of transistors arranged along a second direction parallel to the substrate, the gates of a column of transistors arranged along the first direction are connected to form the word line corresponding to the column of transistors, the gates of the transistors wrap around the circumferential side walls of the channel, the channel includes a support layer and a channel layer wrapping around the circumferential side walls of the support layer, and the material of the channel layer is different from the material of the support layer.

[0017] In a possible implementation, forming a stacked multi-layer memory cell array and a plurality of word lines on the substrate along a first direction perpendicular to the substrate includes:

[0018] Alternatingly stacking a plurality of initial film layers and a plurality of sacrificial film layers on the substrate along a first direction perpendicular to the substrate to form a stacked structure;

[0019] Etching the stack structure along the first direction to form a plurality of isolation trenches extending along a third direction and spaced apart along the second direction, and forming an isolation layer in the isolation trenches, wherein the third direction is parallel to the substrate and intersects the second direction, and the isolation trenches divide the stack structure into a bit line region extending along the second direction and a transistor region extending along the third direction;

[0020] Etching the isolation layer corresponding to the transistor region in the isolation trench to form a first groove of the stacked structure exposing the transistor region, and etching the region of the support layer where each sacrificial film layer blocks each initial film layer in the stacked structure based on the first groove to expose the support layer;

[0021] A channel material and a gate material are deposited along the exposed supporting layers to wrap around the circumferential sidewalls of the supporting layers to form channels, gates and the plurality of word lines of the transistors.

[0022] In a possible implementation, depositing a channel material and a gate material along each exposed supporting layer to wrap around a circumferential sidewall of each supporting layer to form a channel, a gate, and the plurality of word lines of each transistor includes:

[0023] Depositing a channel material on the circumferential sidewalls of each of the support layers and the sidewalls of the first groove to form an initial channel layer;

[0024] depositing a gate material based on the initial channel layer to form an initial gate layer covering a surface of the initial channel layer;

[0025] Etching the isolation layer in the isolation trench away from the bit line region to form a second groove, wherein the second groove exposes the gate material located on the sidewall of the first groove, and removing the gate material on the sidewall of the first groove and the channel material covered by the gate material;

[0026] The isolation layer of the isolation trench near the bit line area is etched to form a third groove, wherein the third groove exposes the gate material located on the sidewall of the first groove, and the gate material on the sidewall of the first groove and the channel material covered by the gate material are removed. The gates of the transistors on the same layer in the obtained multiple transistors are disconnected, and the gates of the transistors on different layers arranged along the first direction are connected to form corresponding word lines. The gate material exposed by the third groove and the gate material exposed by the second groove are located on both sides of the first groove.

[0027] In a possible implementation, after forming the isolation layer in the isolation trench, the method further includes:

[0028] Etching the stacked structure of the transistor region away from the bit line region along the first direction to form a groove line extending along the first direction, and etching each initial film layer in the stacked structure along the third direction based on the groove line to form a hollow cup-shaped structure between the etched initial film layer and the adjacent sacrificial film layer;

[0029] Depositing a first metal material and an oxidized material to obtain the first metal material attached to the inner wall and the outer wall of the hollow cup-shaped structure, and the oxidized material wrapped by the first metal material;

[0030] etching the first metal material and the oxidized material attached to the outer wall of the hollow cup-shaped structure;

[0031] The oxide material wrapped by the first metal material is etched, and the second metal material and the insulating material are deposited to obtain a first electrode plate and a second electrode plate included in the capacitor. The capacitor and the transistor correspond one to one, and the first source / drain of the transistor is connected to the first electrode plate of the corresponding capacitor. The first metal material forms the first electrode plate, and the second metal material forms the second electrode plate. The first electrode plate has a hollow cup-shaped structure, and the hollow cup-shaped structure is arranged in a ring on the outer wall of the second electrode plate.

[0032] In a possible implementation, the second electrode plate includes a first part and a second part, and the depositing of the second metal material and the insulating material to obtain the first electrode plate and the second electrode plate includes:

[0033] Depositing the insulating material and the second metal material in the gap of the hollow cup-shaped structure formed by the first metal material to obtain a first part formed by the second metal material, wherein the hollow cup-shaped structure is annularly arranged on the outer wall of the first part;

[0034] etching a region of the sacrificial film layer that contacts an outer wall of the hollow cup-shaped structure formed by the first electrode plate to expose the outer wall of the hollow cup-shaped structure formed by the first electrode plate;

[0035] The second metal material and the insulating material are deposited along the exposed outer wall to obtain the second portion arranged in an annular manner around the outer wall of the hollow cup-shaped structure.

[0036] In a possible implementation, the method further includes:

[0037] Etching the bit line region in the stack structure to expose the second source / drain of the transistor;

[0038] Deposition is performed based on the gaps obtained by etching the bit line region to obtain a bit line connecting the second source / drain electrodes of a row of transistors arranged along the second direction;

[0039] A plurality of bit lines are arranged at intervals along a first direction perpendicular to the substrate, and each of the bit lines extends along the second direction.

[0040] In a third aspect, a chip is provided, comprising the memory according to the first aspect or any possible implementation of the first aspect.

[0041] In a fourth aspect, an electronic device is provided, which includes the memory in the first aspect or any possible implementation of the first aspect.

[0042] In a possible implementation, the electronic device further includes a processor, which is coupled to the memory, and the processor is configured to load and execute at least one instruction stored in the memory to enable the electronic device to operate.

[0043] The technical solutions provided by the embodiments of the present application bring at least the following beneficial effects:

[0044] The gate is the control electrode of a transistor. Changing the gate voltage can change the transistor's conductivity. Using a transistor with the gate wrapped around the channel increases the contact area between the gate and the channel, enhancing the gate's control over the transistor's conductivity, enabling better electrical control and reducing leakage current. Due to the large contact area between the gate and the channel, the transistor's gate control capability can control the channel even if the channel length is reduced, and suppress the short channel effect caused by the shortened channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1 This is a schematic diagram of the structure of a memory provided by an embodiment of the present application;

[0047] Figure 2 is a schematic structural diagram of another memory provided in an embodiment of the present application;

[0048] Figure 3 This is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0049] Figure 4 This is a structural diagram of another memory provided in an embodiment of the present application;

[0050] Figure 5 is a flow chart of a method for preparing a memory provided in an embodiment of the present application;

[0051] Figure 6 Schematic diagram of a stack of an initial film layer and a sacrificial film layer provided in an embodiment of the present application;

[0052] Figure 7 Schematic diagram of another stacking of an initial film layer and a sacrificial film layer provided in an embodiment of the present application;

[0053] Figure 8 This is a schematic diagram of etching an initial film layer provided in an embodiment of the present application;

[0054] Figure 9is a schematic diagram of material deposition provided in an embodiment of the present application;

[0055] Figure 10 This is a schematic diagram of etching another initial film layer provided in an embodiment of the present application;

[0056] Figure 11 is a schematic diagram of deposition of a first metal material provided in an embodiment of the present application;

[0057] Figure 12 This is a schematic diagram of preparing a connection end provided in an embodiment of the present application;

[0058] Figure 13 This is a schematic diagram of deposition corresponding to a first electrode plate provided in an embodiment of the present application;

[0059] Figure 14 This is a schematic diagram of etching corresponding to a first electrode plate provided in an embodiment of the present application;

[0060] Figure 15 This is a schematic diagram of deposition corresponding to a second electrode plate provided in an embodiment of the present application;

[0061] Figure 16 This is a schematic diagram of forming a capacitor provided by an embodiment of the present application;

[0062] Figure 17 is a schematic diagram of forming another capacitor provided in an embodiment of the present application;

[0063] Figure 18 This is a schematic diagram of etching corresponding to a transistor provided in an embodiment of the present application;

[0064] Figure 19 This is a deposition diagram corresponding to a transistor provided in an embodiment of the present application;

[0065] Figure 20 is a deposition diagram corresponding to another transistor provided in an embodiment of the present application;

[0066] Figure 21 This is an etching effect diagram provided by an embodiment of the present application;

[0067] Figure 22 This is another etching effect diagram provided in an embodiment of the present application;

[0068] Figure 23 This is a deposition effect diagram provided by an embodiment of the present application;

[0069] Figure 24 This is another deposition effect diagram provided in an embodiment of the present application;

[0070] Figure 25This is an etching schematic diagram provided in an embodiment of the present application;

[0071] Figure 26 This is another etching schematic diagram provided in an embodiment of the present application;

[0072] Figure 27 This is another deposition effect diagram provided in an embodiment of the present application;

[0073] Figure 28 This is a schematic diagram of etching corresponding to a bit line provided in an embodiment of the present application;

[0074] Figure 29 This is a deposition diagram corresponding to a bit line provided in an embodiment of the present application;

[0075] Figure 30 is a plan view of a memory cell array provided in an embodiment of the present application;

[0076] Figure 31 This is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0077] To make the purpose, technical solutions and advantages of this application clearer, the following will further describe the implementation of this application in detail with reference to the accompanying drawings. The terms used in the implementation of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0078] With the development of semiconductor technology, memory array transistors can be arranged in three dimensions through a 3D (3D) stacking structure, so that transistors can be placed close to each other to achieve multi-layer stacking. On the basis of saving area within the plane, the connection length can also be reduced to reduce signal delay.

[0079] An embodiment of the present application provides a memory using a 3D stacking structure. Figure 1 A schematic diagram of the structure of a memory provided in an embodiment of the present application is provided. Figure 1 For the side view of the memory in the x direction, see Figure 1 The memory includes a multi-layer memory cell array 11, which is stacked on a substrate along a first direction perpendicular to the substrate. Figure 1 The xyz coordinate system in is a memory coordinate system established with the structural center of the memory as the coordinate origin. The first direction is the vertical direction perpendicular to the substrate, that is, the z-axis direction in the xyz coordinate system.

[0080] In one possible scenario, a memory cell array includes at least one memory cell for storing data. Each memory cell includes a transistor. The transistor is used to control the flow of charge into or out of the memory module. When the transistor is on, charge can flow into the memory module; when the transistor is off, the charge is fixed in the memory module. The transistor controls the flow of charge into and out of the memory module to store data in the memory module.

[0081] Figure 1 The memory shown in FIG. 1 includes a multi-layer memory cell array 11 , which is stacked on a substrate along a first direction perpendicular to the substrate. The memory cell array 11 includes at least one memory cell, that is, at least one transistor 111 . Figure 1 In the equation, the first direction is the z direction, Figure 1 In the text, "one memory cell array 11 includes one transistor 111" means that when viewed from the side in the x-direction, the transistor 111 is one. However, in practice, a memory cell array 11 stacked in one layer may include any number of transistors 111. A memory cell array 11 may include only one transistor 111 or multiple transistors 111. For example, multiple transistors 111 may be spaced apart along the x-direction. Therefore, when viewed from the side in the x-direction, the multiple transistors 111 overlap to form a single side view. Figure 2 Shows a perspective view of a memory, see Figure 2 , a memory cell array 11 includes three transistors 111 .

[0082] In one possible case, the gate of transistor 111 wraps around the peripheral sidewalls of the channel, see Figure 2 The gate of transistor 111 wraps around the channel of transistor 111. Since the gate wraps around the channel, the gate control capability of transistor 111 is enhanced, providing better electrical control over the channel, thereby reducing leakage current and suppressing short channel effects. Figure 2 In the figure, the circumferential sidewall of the channel refers to the other areas outside the two ends of the channel.

[0083] Exemplarily, the channel of transistor 111 includes a support layer and a channel layer wrapping the circumferential sidewalls of the support layer, and the material of the channel layer is different from the material of the support layer. Optionally, the material of the channel layer is a metal oxide material, the electron mobility of the metal oxide material is higher than the first threshold, and the switching current ratio is higher than the second threshold. The first threshold and the second threshold can be set based on experience and implementation environment. The first threshold and the second threshold can have the same or different values. Since the electron mobility of the channel of transistor 111 is higher than the first threshold and the switching current ratio is higher than the second threshold, that is, the material of the channel layer is a material with high electron mobility and high switching current ratio, the gate control effect is better. Optionally, the metal oxide can be IGZO (Indium Gallium Zinc Oxide). When the metal oxide material is IGZO, the leakage current of transistor 111 is small (the leakage current is less than or equal to 10-15A (amperes)), thereby ensuring the low refresh rate of the dynamic memory.

[0084] It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other oxide materials.

[0085] In one possible case, the memory cell further includes a capacitor as a storage module for storing charge. The capacitor is used to store charge to implement data storage according to the stored charge. Therefore, for a memory cell array 11 including at least one memory cell, as shown in FIG. Figure 3 As shown, the memory cell array 11 further includes at least one capacitor 112 , and the capacitor 112 corresponds to the transistor 111 in a one-to-one manner.

[0086] In one possible implementation, capacitor 112 includes two conductive electrode plates and a dielectric. The electrode plates are typically made of a conductive material, and the dielectric is an insulating material located between the two electrode plates, which can be a solid, liquid, or gas. In this application, the two electrode plates included in capacitor 112 are distinguished as a first electrode plate and a second electrode plate. In some cases, the first electrode plate can also be referred to as an upper plate or an inner plate, and the second electrode plate can be referred to as a lower plate or an outer plate. This embodiment of the application does not limit this.

[0087] Optionally, the first source / drain of transistor 111 is connected to the first electrode plate of the corresponding capacitor 112. Either the source or the drain can be connected to capacitor 112. This means that the present embodiment does not limit whether capacitor 112 is connected to the source or drain of transistor 111; it can be connected to either end of transistor 112. In one possible scenario, the first electrode plate of capacitor 112 forms a hollow cup-shaped structure, and the hollow cup-shaped structure is disposed around the outer wall of the second electrode plate of capacitor 112. Figure 3 (1) and (3) show two memories, and the structures of the capacitors 112 included in the two memories are different. Figure 3 (2) and (4) are schematic diagrams of the structure of capacitor 112. Figure 3 (2) and (4), the structure formed by the first electrode plate of the capacitor 112 is a cup-shaped structure with an open top, and there is a gap in the middle of the cup-shaped structure, and the gap is used to place the second electrode plate and the dielectric.

[0088] Since the first electrode plate forms a hollow cup-shaped structure, the contact surface between the second electrode plate and the first electrode plate includes the side wall surface and the bottom surface of the hollow cup-shaped structure. By increasing the contact surface between the first electrode plate and the second electrode plate, the capacitance of the capacitor 112 is effectively increased.

[0089] Alternatively, the second electrode plate may be Figure 3 As shown in FIG. (2), the inner wall of the first electrode plate may be in contact with the inner wall of the first electrode plate. Figure 3 As shown in FIG. (4), the second electrode plate also contacts the outer wall of the first electrode plate. That is, the second electrode plate includes a first portion and a second portion. On the basis of the hollow cup-shaped structure being arranged in an annular manner on the outer wall of the first portion, the second portion is also arranged in an annular manner on the outer wall of the hollow cup-shaped structure. The inner and outer surfaces of the first and second electrode plates can contact each other, thereby increasing the contact area between the first and second electrode plates and increasing the capacitance of capacitor 112.

[0090] In one possible implementation, see Figure 4 The memory also includes a BL (bit line) 13 and a WL (word line) 12, wherein the word line 12 is used to control the conduction of the transistor, and the bit line 13 serves as a channel for accessing the capacitor 112 included in the memory cell array 11. The capacitor 112 can be read or written by applying a voltage to the bit line 13.

[0091] In one possible case, each bit line 13 corresponds to a row of transistors 111 included in each layer of the memory cell array 11. The plurality of bit lines 13 are spaced apart along a first direction perpendicular to the substrate, and each bit line 13 extends along a second direction parallel to the substrate, the second direction being perpendicular to the first direction. Figure 4The structure diagram shown is a structure diagram observed in the first direction, that is, a structure diagram observed in the z-axis direction. In the first direction, the substrate is blocked by the bit line 13, so Figure 4 The structural shape of the substrate is not shown.

[0092] Figure 4 In the embodiment, the plurality of bit lines 13 are spaced apart along the first direction. Since the plurality of bit lines 13 overlap when viewed in the first direction, Figure 4 The bit line 13 shown in FIG is one. Optionally, the bit line 13 extends along a second direction, which is a direction parallel to the substrate, and the second direction is, for example, the x-axis direction.

[0093] Optionally, each bit line 13 is respectively connected to the second source / drain of the transistor 111 included in the corresponding memory cell array 11. Similar to the connection relationship of the capacitor 112, the embodiment of the present application does not limit whether the bit line 13 is connected to the source or drain of the transistor 111, and it can be any end of the transistor 111. When the capacitor 112 is connected to the source of the transistor 111, the bit line 13 is connected to the drain of the transistor 111. When the capacitor 112 is connected to the drain of the transistor 111, the bit line 13 is connected to the source of the transistor 111. Among them, the first and second before the source / drain are intended to distinguish the two ends of the transistor 111.

[0094] Figure 4 The memory cell array 11 includes three transistors 111, and the second source / drain electrodes of the three transistors 111 are extended and connected to the bit line 13. A single bit line 13 is used to connect multiple transistors 111 included in a row of memory cells in the memory cell array 11. Subsequently, only a voltage needs to be applied to the single bit line 13 to read or write any transistor 111 included in a row of memory cells in the memory cell array 11, making operation convenient.

[0095] Optionally, the word line 12 included in the memory cell array 11 can be formed by connecting the gates of the transistors 111. For example, the gates of a column of transistors 111 arranged along the first direction are connected to form the word line 12 corresponding to the column of transistors 111. Figure 2 , Figure 2 In the embodiment, two layers of memory cell arrays 11 are stacked along a first direction, and the gates of the transistors 111 included in the two layers of memory cell arrays 11 are connected to form a word line 12. In this case, the multiple word lines 12 extend along a first direction perpendicular to the substrate. Based on the bit lines 13 extending along a second direction, since the first direction and the second direction are perpendicular to each other, for example, Figure 1The first direction is the z-axis direction, and the second direction is the x-axis direction. By cross-distributing the word lines 12 and the bit lines 13, cross-addressing of the memory cells included in the memory cell array 11 is achieved. The cross address of a word line 12 and a bit line 13 is the address of a memory cell composed of a transistor 111 and a capacitor 112. In addition, the cross of the word line 12 and the bit line 13 easily realizes multi-layer stacking, thereby reducing the difficulty of stacking the memory cell array 11.

[0096] In summary, the memory provided by the embodiment of the present application uses a transistor with a gate wrapped around a channel, which effectively improves the gate control capability of the transistor. The capacitor used is a cup-shaped structure, so that the first electrode plate has more surfaces in contact with the second electrode plate, increasing the contact area between the electrode plates. By increasing the contact area of ​​the electrode plates, the capacitance is increased. Using IGZO as a channel, the transistor is more conducive to gate control. In addition, the gates of the transistors stacked along the first direction are connected as word lines, and the word lines of the memory are arranged wirelessly, saving the space required for the memory.

[0097] The present invention provides a method for preparing a memory device. Figure 1 、 Figure 2 、 Figure 3 or Figure 4 For any of the memories shown, the flowchart of the method is as follows Figure 5 As shown, it includes steps 501 and 502.

[0098] In step 501, a memory substrate is provided.

[0099] In one possible implementation, the preparation equipment can obtain a substrate that has been prepared, or it can use a substrate preparation process to produce the substrate required for the memory. The substrate preparation process includes but is not limited to steps such as preparing crystals, slicing, grinding, chamfering, etching or polishing. Among them, slicing refers to cutting the crystal into thin slices with a thickness of no more than 1 mm according to the crystal orientation of the crystal. The slices obtained by cutting are also called wafers. Grinding refers to using diamonds of different particle sizes to grind the wafer to the required flatness and roughness. Chamfering is used to round the edges of the wafer to prevent edge chipping and debris during subsequent processing. The purpose of etching is to remove surface processing damage, stress, etc., and to make the wafer have a dense and clean back side. Etching can be performed using a mixed solution of hydrofluoric acid and nitric acid. Polishing is used to remove the damage layer remaining on the processed surface. Mechanical polishing or chemical mechanical polishing can be used to obtain a flat, smooth, damage-free wafer with a certain thickness. The embodiments of the present application do not limit the material of the substrate provided by the preparation equipment. The composition of the substrate can be silicon (Si) or other materials.

[0100] In step 502 , a stacked multi-layer memory cell array and a plurality of word lines are formed on a substrate along a first direction perpendicular to the substrate.

[0101] Exemplarily, a fabrication device can form a multi-layer memory cell array on a substrate using thin film stacking technology. For example, the fabrication device alternately stacks multiple initial film layers and multiple sacrificial film layers on a substrate along a first direction perpendicular to the substrate to form a stacked structure; etches the stacked structure along the first direction to form multiple isolation trenches extending along a third direction and spaced apart in the second direction; and forms an isolation layer within the isolation trenches, wherein the third direction is parallel to the substrate and intersects, for example, perpendicular to, the second direction. The isolation trenches divide the stacked structure into a bit line region extending along the second direction and a transistor region extending along the third direction; and performs etching and deposition processes based on the isolation layer to form transistors and multiple word lines.

[0102] Figure 6 A schematic diagram of a stack of a sacrificial film layer and an initial film layer provided in an embodiment of the present application is shown. Figure 6 In the figure, the black rectangle indicates the substrate. In the process of stacking to form a stacked structure, the preparation device adopts a cross-stack sequence of first stacking a sacrificial film layer on the substrate, then stacking an initial film layer, and then stacking a sacrificial film layer. The number of stacked initial film layers is the same as the number of memory cell arrays included in the memory. The embodiment of the present application does not limit the number of stacked initial film layers, and can be flexibly adjusted based on the number of memory cell arrays to be obtained, and Figure 6 The figures appearing below are also intended to illustrate the process of preparing the memory, rather than to limit the number of initial film layers.

[0103] In one possible case, the sacrificial layer and the initial layer are made of different materials. Figure 7 , Figure 7 A schematic diagram of a preparation process provided in an embodiment of the present application is shown. Figure 7 Shown Figure 6 Front view in x direction, Figure 7 In this process, the substrate is made of silicon, the sacrificial film is made of SiO2 (silicon oxide), and the initial film is made of SiN (silicon nitride). The fabrication equipment deposits a thin film stack of SiN and SiO2 on the Si substrate to form the initial film and the sacrificial film.

[0104] Optionally, after stacking the sacrificial film layer and the initial film layer to obtain a stacked structure, the manufacturing device can perform longitudinal etching on the stacked structure along the first direction, and the longitudinal etching ends at the substrate to obtain multiple isolation trenches. Figure 8 , Figure 8 correspond Figure 6 The cross section of the initial film layer at position A. In fact, the sacrificial film layer will also be longitudinally etched at the same position, and the longitudinal etching runs through the sacrificial film layer and the initial film layer of the stacked structure. Figure 8Four isolation trenches are shown in FIG. 4 , which are spaced apart along the second direction and extend along the third direction. The initial film layer is divided into a bit line region and a transistor region by the isolation trenches. Figure 8 In the embodiment, the bit line region is located on the left side of the initial film layer and extends along the second direction, and the transistor region is located on the right side of the bit line region and extends along the third direction.

[0105] In the case where the memory cell array includes a plurality of devices, such as the above Figure 3 In the embodiment shown, when the memory cell array includes capacitors and transistors, the initial film layer separated by the isolation trench may also include a capacitor region, for example Figure 8 As shown, the capacitance region is located to the right of the initial film layer. In addition, Figure 8 The purpose is to illustrate the distribution of a capacitor region, a bit line region and a transistor region, rather than to limit the positional relationship between the capacitor region, the transistor region and the bit line region. The capacitor region and the bit line region can be as follows: Figure 8 As shown, the bit line region is located on the left and the capacitor region is located on the right. Alternatively, the bit line region is located on the right and the capacitor region is located on the left. This embodiment of the present application does not limit this.

[0106] After etching the isolation trench, the manufacturing equipment can deposit isolation material in the isolation trench to form an isolation layer. Figure 9 As shown, the isolation trenches formed by etching are filled with an isolation material, different from the sacrificial film layer and the initial film layer. This isolation material has a high selective etching ratio and a low-k dielectric constant. The isolation material can be polysilicon (poly) or other materials. The term "low-k material" will be used when describing isolation materials. After the isolation trenches are filled with the low-k material, the fabrication equipment performs CMP (chemical mechanical polishing). Through the synergistic effect of chemical etching and mechanical polishing, the excess material is efficiently removed and nanometer-scale planarization is achieved.

[0107] After depositing the isolation material to form an isolation layer, the manufacturing equipment can perform etching and deposition processes corresponding to forming capacitors, and etching and deposition processes corresponding to forming transistors, respectively, based on the isolation layer. The order of the etching and deposition processes corresponding to the capacitors and transistors is not limited in the present embodiment. The etching and deposition processes corresponding to the capacitors can be performed first, or the etching and deposition processes corresponding to the transistors can be performed first. The following example illustrates the process of forming a memory device by first performing the etching and deposition processes corresponding to the capacitors and then performing the etching and deposition processes corresponding to the transistors.

[0108] Optionally, taking the formation of a capacitor as an example, the preparation equipment etches the stacked structure close to the capacitor area along the first direction to form a groove line extending along the first direction, and etches each initial film layer in the stacked structure along the third direction based on the groove line, and a hollow cup-shaped structure is formed between the etched initial film layer and the adjacent sacrificial film layer; deposits a first metal material and an oxide material to obtain the first metal material attached to the inner wall and outer wall of the hollow cup-shaped structure, and the oxide material wrapped by the first metal material; etches the first metal material and the oxide material attached to the outer wall of the hollow cup-shaped structure; etches the oxide material wrapped by the first metal material, and deposits the second metal material and the insulating material to obtain the first electrode plate and the second electrode plate included in the capacitor, the capacitor and the transistor correspond one to one, the first source / drain of the transistor is connected to the first electrode plate of the corresponding capacitor, the first metal material forms the first electrode plate, the second metal material forms the second electrode plate, the first electrode plate has a hollow cup-shaped structure, and the hollow cup-shaped structure is arranged around the outer wall of the second electrode plate.

[0109] See also Figure 10 , Figure 10 Including three pictures from left to right, corresponding to Figure 6 The cross section at position A, the longitudinal section at position C and the longitudinal section at position B. Figure 10 The preparation equipment first performs longitudinal etching along the first direction, and the etching track is shown as arrow 1. After etching to obtain the groove line, it etches inward along the third direction based on the groove line, and the etching track is shown as arrow 2. Through two etchings, the capacitor area included in the initial film layer is removed to obtain an area for depositing capacitors. The two adjacent sacrificial film layers of the etched initial film layer form a hollow cup-shaped structure. The sacrificial film layers are longer than the initial film layers. Therefore, the sacrificial film layer and the top surface and the side of the groove of the initial film layer serve as the sidewalls of the hollow cup-shaped structure, and the bottom surface of the groove of the initial film layer serves as the bottom surface of the hollow cup-shaped structure. Subsequently, a capacitor of a hollow cup-shaped structure can be deposited based on the hollow cup-shaped structure.

[0110] After etching to obtain a hollow cup-shaped structure, the preparation equipment can start to deposit the capacitor. In one possible case, since there is a connection relationship between the transistor and the capacitor, the preparation equipment can first form the connection terminal between the capacitor and the transistor based on the initial film layer. For example, the preparation equipment deposits TiN (titanium nitride) and metal W (tungsten), and grinds the deposited TiN and W to obtain the following: Figure 11 The structure shown, Figure 11 The left picture is the longitudinal section of position B, and the right picture is the longitudinal section of position C. For the positional relationship between position B, position C and the memory, please refer to Figure 6 After depositing W and TiN, the equipment is used to etch the deposited TiN and W laterally to obtain the following Figure 12 In the structure shown, the etching depth can be set based on experience, and the embodiments of the present application do not limit this.

[0111] The connection terminal between the capacitor and the transistor is formed by first depositing and then etching. In the subsequent process of depositing the capacitor and the transistor, the structure is formed on the basis of the connection terminal, that is, the transistor and capacitor are generated on the left and right sides of the connection terminal respectively, ensuring the connection between the transistor and the connection terminal, and the connection between the capacitor and the connection terminal, thereby ensuring the close connection between the transistor and the capacitor.

[0112] After forming the connection terminal, the manufacturing equipment can form a capacitor based on the connection terminal. Optionally, the manufacturing equipment can first form the first electrode plate of the capacitor based on the groove formed by the sacrificial film layer and the initial film layer. Figure 13 The preparation equipment first deposits the first metal material, and then deposits the oxide material on the basis of the first metal material. Figure 13 In the embodiment, the first metal material is TiN, and the oxidizing material is Al2O3 (aluminum oxide). The aluminum oxide completely wraps the first metal material, and the first metal material can be arbitrarily changed in structure later by the oxidizing material.

[0113] For example, the manufacturing equipment can directly etch the first electrode plate based on the deposited first metal material and the oxide material, or grind the deposited first metal material and the oxide material after deposition to achieve flattening of the film layer formed by the first metal material and the oxide material. Regardless of whether the manufacturing equipment grinds the first metal material and the oxide material, the first metal material can be etched based on the oxide material. Figure 14 The manufacturing equipment etches the first metal material and the oxidized material attached to the outer wall of the sacrificial film layer. The oxidized material leaves the first metal material attached to the inner wall of the sacrificial film layer. The first metal material attached to the inner wall serves as the first electrode plate of the capacitor. The manufacturing equipment then etches away the oxidized material deposited on the inner wall, i.e., the oxidized material included in the first metal material, to obtain the first electrode plate.

[0114] After forming the first electrode plate, the manufacturing equipment can begin to prepare the second electrode plate wrapped by the first electrode plate. In one possible embodiment, the manufacturing equipment deposits an insulating material and a second metal material in the gap of the hollow cup-shaped structure formed by the first metal material. The insulating material is used to form the dielectric, and the second metal material is used to form the second electrode plate. Figure 15 The insulating material shown in the figure is HK (high dielectric constant dielectric) and the second metal material is polysilicon. Since the deposition of the materials is carried out on the surface of the provided film layer, the second metal material and the insulating material are formed not only in the gaps of the first metal material but also on the outer wall of the sacrificial film layer. The excess insulating material and second metal material on the outer wall can be removed by etching by the preparation equipment to obtain Figure 16 The structure shown, Figure 16The left picture is the longitudinal section at position B, and the right picture is the cross section at position A. Figure 16 In the embodiment, the portion formed by polysilicon is the second electrode plate, and multiple inner walls of the first electrode plate are in contact with multiple surfaces of the second electrode plate, thereby effectively increasing the contact area between the first electrode plate and the second electrode plate.

[0115] In one possible scenario, the second electrode plate can also contact the outer wall of the first electrode plate while contacting the inner wall of the first electrode plate. That is, the second electrode plate includes a first portion and a second portion. The second metal material deposited on the inner wall is used to form the first portion, and the hollow cup-shaped structure is arranged around the outer wall of the first portion. Furthermore, the manufacturing equipment further etches the area of ​​the sacrificial film layer that contacts the outer wall of the hollow cup-shaped structure formed by the first electrode plate, exposing the outer wall of the hollow cup-shaped structure formed by the first electrode plate; the second metal material and insulating material are deposited along the exposed outer wall to obtain the second portion arranged around the outer wall of the hollow cup-shaped structure. Figure 16 The area to be etched is shown to be in contact with the outer wall of the first layer, but in fact, there are areas in the stacked multiple sacrificial film layers that are in contact with the outer wall structure of the hollow cup-shaped structure. Figure 17 , Figure 17 The left picture is a longitudinal section at position B, and the right picture is a cross section at position A. The three-dimensional structure diagram of the capacitor including the first part and the second part can be found in Figure 3 In FIG (4), the second electrode plate wrapped by the first electrode plate is the first part, and the second electrode plate wrapping the first electrode plate is the second part.

[0116] Exemplarily, the manufacturing equipment can also perform etching and deposition corresponding to the transistor to form a transistor connected to the capacitor. Optionally, the process of forming the transistor by the manufacturing equipment includes: etching the isolation layer corresponding to the transistor area in the isolation trench to form a first groove of the stacked structure exposing the transistor area, etching the area of ​​the support layer of each initial film layer blocked by each sacrificial film layer in the stacked structure based on the first groove to expose the support layer; depositing the trench material and gate material along the exposed support layers to wrap the circumferential sidewalls of each support layer to form the channel, gate and multiple word lines of each transistor.

[0117] In one possible case, the manufacturing equipment will also deposit an initial film layer on the top surface of the stack structure before performing the etching corresponding to the transistor, for example Figure 18 As shown in the left figure, compared with Figure 17 The right picture, Figure 18 An initial film layer is deposited on the top surface of the sacrificial film layer to facilitate the subsequent deposition of transistors. For example, after the initial film layer is deposited on the top surface, the fabrication equipment can begin etching corresponding to the transistor to expose the supporting layer of the transistor.

[0118] Optionally, the support layer of the transistor may be Figure 8 Since the support layer is blocked by the isolation layer and the sacrificial film layer, the preparation equipment will first etch away the low-k material filled in the isolation trench to obtain Figure 18 The structure shown in the left figure, Figure 18 The left picture corresponds to the cross section at position A, the right picture corresponds to the longitudinal section at position B, and Figure 8 The situation is similar, although Figure 18 While only the initial film layer is etched, the low-k material is etched vertically from top to bottom along a first direction. Therefore, the low-k material filling the sacrificial film layer is also etched. Due to the etching of the low-k material, the area of ​​the sacrificial film layer that obscures the support layer is also exposed. The fabrication equipment can then etch the exposed area of ​​the sacrificial film layer to expose the support layer.

[0119] Figure 18 The support layer of the initial film layer is located on the left side of the capacitor. The length of the support layer is the length of the transistor to be formed. The specific length can be set based on experience. The preparation equipment will block the various parts of the support layer and etch them to reveal the gaps for depositing the transistor. Figure 18 The structure shown.

[0120] In one possible case, the process of preparing a device for depositing and forming a transistor includes: depositing channel material on the circumferential side walls of each support layer and the side walls of the first groove to form an initial channel layer; depositing gate material based on the initial channel layer to form an initial gate layer covering the surface of the initial channel layer; etching the isolation layer away from the bit line area in the isolation groove to form a second groove, the second groove exposing the gate material located on the side walls of the first groove, removing the gate material on the side walls of the first groove and the channel material covered by the gate material; etching the isolation layer near the bit line area of ​​the isolation groove to form a third groove, the third groove exposing the gate material located on the first groove, removing the gate material on the side walls of the first groove and the channel material covered by the gate material, and the gates of the transistors in the same layer of the obtained multiple transistors are disconnected, and the gates of the transistors in different layers arranged along the first direction are connected to form corresponding word lines, and the gate material exposed by the third groove and the gate material exposed by the second groove are located on both sides of the first groove.

[0121] Figure 19 A structural diagram provided in an embodiment of the present application is shown. Figure 19 The left picture corresponds to the cross section at position A, and the right picture corresponds to the longitudinal section at position B. Figure 19 The preparation equipment first deposits the channel material along the sidewalls of the support layer and the first groove to obtain an initial channel layer. The electron mobility of the channel material used is higher than the first threshold and the on-off current ratio is higher than the second threshold. For a description of the channel material, please refer to Figure 1 The channel material described in the embodiment will not be repeated here. Figure 19 As shown, IGZO is used as the channel material to wrap the support layer to form the channel of the transistor. Then, a gate material can be deposited along the initial channel layer to form an initial gate layer covering the surface of the initial channel layer. Figure 19 In the process, after forming the initial channel layer, the preparation equipment will also deposit HK as the insulating material between the gate and the channel, and then deposit IZO (indium zinc oxide) as the gate material on the basis of the insulating material.

[0122] In one possible case, among the multiple transistors formed by deposition, the gates of the transistors located in the same layer are connected. Therefore, the manufacturing equipment will also fill the gaps between the transistors adjacent in the second direction parallel to the substrate with insulating material. The insulating material is used to isolate the transistors adjacent in the second direction. Among them, the insulating material filled with the transistors adjacent in the second direction, that is, the transistors located in the same layer of the memory cell array, is, for example, Figure 19 By filling the insulating material, the gates of transistors on the same layer are separated to disconnect the transistors on the same layer.

[0123] In one possible implementation, during the deposition process, channel material and gate material are also deposited on the sidewalls of the first groove, forming a parasitic channel. The parasitic channel refers to the channel that appears between the source and drain during the transistor manufacturing process. The presence of the parasitic channel will cause current leakage and increase power consumption. Figure 20 , Figure 20 The left picture is the cross section at position A, and the right picture is the longitudinal section at position 1.

[0124] against Figure 20 The two parasitic channels to be removed are not limited in the order of removing the parasitic channels in the present embodiment. The parasitic channel on the left can be removed first, and then the parasitic channel on the right, or the parasitic channel on the right can be removed first, and then the parasitic channel on the left. For example, the preparation equipment first etches the isolation layer close to the capacitor area and away from the bit line area, that is, removes the low-k material filled in the isolation trench, and obtains Figure 21 After that, etching can be continued layer by layer to remove the IGZO film on the sidewall of the first groove, and then remove the HK and IZO in sequence.

[0125] After the parasitic channel on the right is removed, the resulting structure is as follows Figure 22 As shown, the preparation equipment can continue to remove the parasitic channel on the left side. The preparation equipment can be as follows Figure 23 or Figure 24As shown, the oxide material is filled, that is, silicon oxide, and the filled silicon oxide is subjected to CMP, and the silicon oxide is used as a sacrificial material to protect the transistor except the parasitic channel, and the parasitic channel on the left is removed based on the silicon oxide. Figure 23 and Figure 24 The difference lies in the different structures of the capacitors connected to the transistors. Regardless of the capacitors connected to the transistors, the process of removing the parasitic channel is similar. Figure 23 Taking the memory structure shown in FIG. 1 as an example, the etching of the parasitic channel is illustrated.

[0126] Figure 25 The view order of the three pictures on the left, middle and right is the cross section at position A, the longitudinal section at direction 2, and the longitudinal section at direction 1. Figure 25 The preparation equipment removes the low-k material filled on the left side of the transistor near the bit line area to form a third groove. The gate material to be removed on the left side of the first groove is exposed through the third groove. After that, similar to the process of removing the right parasitic channel, the IGZO film, HK and IZO on the sidewall of the first groove are removed in sequence to obtain Figure 26 The structure shown.

[0127] Through the above operations, the device is prepared to form a stacked multi-layer memory cell array, which includes at least one transistor, and the gate of the transistor wraps the channel, and the area wrapped by the gate includes other areas in the channel except the source and drain.

[0128] In one possible scenario, the manufacturing equipment is used to form not only transistors and capacitors, but also bit lines and word lines. For example, in the case where the gates of each transistor wrap around the channel of the transistor, the gates of the transistors arranged along the first direction can be connected to form a word line corresponding to a column of transistors. In this case, the manufacturing equipment also completes the formation of the word line during the process of forming the transistor. Figure 19 In addition to serving as the gate, the IZO deposited by the preparation equipment will also serve as the word line.

[0129] Next, the process of forming the bit lines is introduced. For example, a preparation device etches the bit line area included in the stack structure to expose the second source / drain of the transistor; deposition is performed based on the gaps obtained by etching the bit line area to obtain a bit line connecting the second source / drain of a row of transistors; wherein the multiple bit lines are arranged at intervals along a first direction perpendicular to the substrate, and each bit line extends along a second direction.

[0130] Figure 27-28 An etching process corresponding to a bit line provided in an embodiment of the present application is: Figure 27 and Figure 28The three images on the left, middle and right correspond to the cross section at position A, the longitudinal section in direction 1, and the longitudinal section in direction 2. The preparation equipment first deposits silicon oxide in the etched gap and performs CMP on the deposited silicon oxide to obtain Figure 27 The structure shown in FIG. 1 is then etched along the third direction to silicon nitride. The etching length can be set based on experience. The equipment is prepared to complete the etching corresponding to the bit line. Figure 28 After the structure shown. Figure 27 and Figure 28 The etched portion in the first image on the left is the bit line area of ​​the initial film layer. After etching to expose the second source / drain of the transistor, the fabrication equipment can perform deposition corresponding to the bit line, depositing titanium nitride and tungsten in the gaps formed by etching. The deposited titanium nitride and tungsten are used as the bit line. Figure 29 The structure shown.

[0131] Figure 30 A plan view of a memory cell array provided in an embodiment of the present application, Figure 30 The dimensions of the components included in the memory cell array are marked in FIG. Figure 30 The unit is nm (Nanometer), see Figure 30 The length of the bit line is 50nm, the length of the transistor is 90nm, the width is 70nm, the length of the capacitor is 150-200nm, and the distance between the memory cells included in the same layer of the memory cell array is 120nm. Figure 30 The area occupied by one memory cell array shown is (420 to 470)×190=79,800 to 89,300 square nanometers.

[0132] In summary, the preparation method of the memory provided in the embodiment of the present application, the gate of the prepared transistor wraps the channel, the gate control capability of the transistor is high, and the prepared capacitor has a cup-shaped structure, so that the first electrode plate has more surfaces in contact with the second electrode plate, increasing the contact area between the electrode plates, and increasing the contact area of ​​the electrode plates. The capacitance is increased. Using IGZO as the channel material, the transistor is more conducive to gate control. In addition, the gate of the transistor is used as the word line, and the word line of the memory is prepared wirelessly, which saves the preparation process of the memory, reduces the preparation cost, and improves the preparation efficiency.

[0133] An embodiment of the present application provides a chip, which includes any possible memory described above.

[0134] An embodiment of the present application provides an electronic device, which includes any of the possible memories described above. Exemplarily, the electronic device also includes a processor, which is coupled to the memory and configured to load and execute instructions stored in the memory to operate the electronic device.

[0135] In some implementation scenarios, the electronic device may be a server. Figure 31 15 is a schematic diagram of the structure of a server provided in an embodiment of the present application. The server may vary significantly due to different configurations or performance, and may include one or more processors 1501 and one or more memories 1502. The one or more memories 1502 store at least one computer program, which is loaded and executed by the one or more processors 1501 to enable the server to operate. Of course, the server may also have components such as a wired or wireless network interface, a keyboard, and input / output interfaces for input and output. The server may also include other components for implementing device functions, which are not detailed here.

[0136] In one possible implementation, the electronic device including the memory may be a terminal, such as a smartphone, a tablet computer, a player, a notebook computer, or a desktop computer. The terminal may also be referred to as user equipment, a portable terminal, a laptop terminal, a desktop terminal, or other names.

[0137] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, storage, display, etc.), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the storage cell arrays involved in this application were obtained with full authorization.

[0138] It should be understood that the term "plurality" used herein refers to two or more. "And / or" describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates an "or" relationship between the associated objects.

[0139] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A memory, characterized in that: The memory comprises a plurality of memory cell arrays (11) and a plurality of word lines (12) stacked on the substrate in a first direction perpendicular to the substrate; Each layer of the memory cell array (11) includes at least one row of transistors (111) arranged along a second direction parallel to the substrate; The gates of a column of transistors (111) arranged along the first direction are connected to form the word line (12) corresponding to the column of transistors (111); The gate of the transistor (111) wraps around the circumferential sidewall of the channel, and the channel comprises a support layer and a channel layer wrapping around the circumferential sidewall of the support layer, wherein the material of the channel layer is different from that of the support layer.

2. The memory according to claim 1, wherein: The memory cell array (11) further includes at least one capacitor (112), the capacitor (112) and the transistor (111) corresponding one to one, and the first source / drain of the transistor (111) is connected to the first electrode plate of the corresponding capacitor (112); The first electrode plate has a hollow cup-shaped structure, and the hollow cup-shaped structure is arranged in a ring around the outer wall of the second electrode plate of the capacitor (112).

3. The memory according to claim 2, wherein: The second electrode plate of the capacitor (112) comprises a first part and a second part, the hollow cup-shaped structure is arranged in an annular manner on the outer wall of the first part, and the second part is arranged in an annular manner on the outer wall of the hollow cup-shaped structure.

4. The memory according to any one of claims 1 to 3, characterized in that: The memory further comprises a plurality of bit lines (13), each of the bit lines (13) corresponding one to one with a row of transistors (111) included in each layer of the memory cell array (11); The plurality of bit lines (13) are spaced apart along a first direction perpendicular to the substrate, each bit line (13) extends along a second direction parallel to the substrate, the second direction and the first direction being perpendicular to each other, and each bit line (13) is respectively connected to a second source / drain of a corresponding transistor (111).

5. A method for preparing a memory, characterized in that: The method comprises: providing a substrate for a memory; A stacked multi-layer memory cell array and a plurality of word lines are formed on the substrate along a first direction perpendicular to the substrate, each layer of the memory cell array includes at least one row of transistors arranged along a second direction parallel to the substrate, the gates of a column of transistors arranged along the first direction are connected to form the word line corresponding to the column of transistors, the gates of the transistors wrap around the circumferential side walls of the channel, the channel includes a support layer and a channel layer wrapping around the circumferential side walls of the support layer, and the material of the channel layer is different from the material of the support layer.

6. The method according to claim 5, characterized in that The method comprises forming a stacked multi-layer memory cell array and a plurality of word lines on the substrate along a first direction perpendicular to the substrate, comprising: Alternatingly stacking a plurality of initial film layers and a plurality of sacrificial film layers on the substrate along a first direction perpendicular to the substrate to form a stacked structure; Etching the stack structure along the first direction to form a plurality of isolation trenches extending along a third direction and spaced apart along the second direction, and forming an isolation layer in the isolation trenches, wherein the third direction is parallel to the substrate and intersects the second direction, and the isolation trenches divide the stack structure into a bit line region extending along the second direction and a transistor region extending along the third direction; Etching the isolation layer corresponding to the transistor region in the isolation trench to form a first groove of the stacked structure exposing the transistor region, and etching the region of the support layer where each sacrificial film layer blocks each initial film layer in the stacked structure based on the first groove to expose the support layer; A channel material and a gate material are deposited along the exposed supporting layers to wrap around the circumferential sidewalls of the supporting layers to form channels, gates and the plurality of word lines of the transistors.

7. The method according to claim 6, characterized in that Depositing a channel material and a gate material along each exposed supporting layer to wrap around the circumferential sidewall of each supporting layer to form a channel, a gate and the plurality of word lines of each transistor, comprising: Depositing a channel material on the circumferential sidewalls of each of the support layers and the sidewalls of the first groove to form an initial channel layer; depositing a gate material based on the initial channel layer to form an initial gate layer covering a surface of the initial channel layer; Etching the isolation layer in the isolation trench away from the bit line region to form a second groove, wherein the second groove exposes the gate material located on the sidewall of the first groove, and removing the gate material on the sidewall of the first groove and the channel material covered by the gate material; The isolation layer of the isolation trench near the bit line area is etched to form a third groove, wherein the third groove exposes the gate material located on the sidewall of the first groove, and the gate material on the sidewall of the first groove and the channel material covered by the gate material are removed. The gates of the transistors on the same layer in the obtained multiple transistors are disconnected, and the gates of the transistors on different layers arranged along the first direction are connected to form corresponding word lines. The gate material exposed by the third groove and the gate material exposed by the second groove are located on both sides of the first groove.

8. The method according to claim 6 or 7, characterized in that After forming the isolation layer in the isolation trench, the method further includes: Etching the stacked structure on a side of the transistor region away from the bit line region along the first direction to form a groove line extending along the first direction, and etching each initial film layer in the stacked structure along the third direction based on the groove line to form a hollow cup-shaped structure between the etched initial film layer and the adjacent sacrificial film layer; Depositing a first metal material and an oxidized material to obtain the first metal material attached to the inner wall and the outer wall of the hollow cup-shaped structure, and the oxidized material wrapped by the first metal material; etching the first metal material and the oxidized material attached to the outer wall of the hollow cup-shaped structure; The oxide material wrapped by the first metal material is etched, and the second metal material and the insulating material are deposited to obtain a first electrode plate and a second electrode plate included in the capacitor. The capacitor and the transistor correspond one to one, and the first source / drain of the transistor is connected to the first electrode plate of the corresponding capacitor. The first metal material forms the first electrode plate, and the second metal material forms the second electrode plate. The first electrode plate has a hollow cup-shaped structure, and the hollow cup-shaped structure is arranged on the outer wall of the second electrode plate.

9. The method according to claim 8, characterized in that The second electrode plate includes a first part and a second part, and the deposition of the second metal material and the insulating material to obtain the first electrode plate and the second electrode plate of the capacitor includes: Depositing the insulating material and the second metal material in the gap of the hollow cup-shaped structure formed by the first metal material to obtain a first part formed by the second metal material, wherein the hollow cup-shaped structure is arranged in an annular manner on the outer wall of the first part; etching a region of the sacrificial film layer that contacts an outer wall of the hollow cup-shaped structure formed by the first electrode plate to expose the outer wall of the hollow cup-shaped structure formed by the first electrode plate; The second metal material and the insulating material are deposited along the exposed outer wall to obtain the second portion arranged in an annular manner around the outer wall of the hollow cup-shaped structure.

10. The method according to claim 6 or 7, characterized in that The method further comprises: Etching the bit line region in the stack structure to expose the second source / drain of the transistor; Deposition is performed based on the gaps obtained by etching the bit line region to obtain a bit line connecting the second source / drain electrodes of a row of transistors arranged along the second direction; A plurality of bit lines are arranged at intervals along a first direction perpendicular to the substrate, and each of the bit lines extends along the second direction.

11. A chip, characterized in that: The chip includes the memory according to any one of claims 1-4.

12. An electronic device, characterized in that: The electronic device comprises the memory according to any one of claims 1-4.

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