Preparation method of three-dimensional memory

Abstract

A preparation method of a three-dimensional memory comprises the steps that a first substrate is provided, the first substrate comprises a base, a stacking layer located above the base and a bottom electrode layer located between the stacking layer and the base, a through hole is formed in the stacking layer, and the top of the bottom electrode layer is exposed at the bottom of the through hole; forming a first thin film layer; executing an ion implantation process along the depth direction of the through hole, and modifying the part of the first thin film layer at the bottom of the through hole; executing a first etching process to remove the unmodified first thin film layer on the side wall of the through hole, and reserving the modified first thin film layer at the bottom of the through hole; forming a second thin film layer covering the side wall of the through hole and the modified first thin film layer; and executing a second etching process, performing anisotropic etching on the second thin film layer by taking the modified first thin film layer as a stop layer, removing the part of the second thin film layer located on the modified first thin film layer, and reserving the part of the second thin film layer located on the side wall of the through hole to form a side wall material layer, thereby improving the surface roughness problem of the bottom electrode layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a three-dimensional memory. Background Art

[0002] The structure of three-dimensional memory (also known as 3D memory) consists of multiple alternating layers of conductive lines (plates) and dielectric layers, interspersed with numerous cylindrical electrodes (pillars). A capacitive dielectric layer is formed between the conductive lines and the cylindrical electrodes, forming storage capacitors at these locations.

[0003] Three-dimensional memories usually use the Plate-Last (form the conductor layer later) process, and its specific process is as follows: a bottom electrode layer is prepared on the substrate, and then a stacked layer is prepared on the bottom electrode layer and the substrate, a through hole is formed in the stacked layer, the bottom of the through hole exposes the top of the bottom electrode layer, and a cylindrical electrode is formed in the through hole. The stacked layer is formed by alternating multiple sacrificial layers and dielectric layers. After the cylindrical electrode is prepared, the sacrificial layer is removed by wet etching to form a horizontal groove, and then the horizontal groove is filled to form a conductor layer. In the process of wet etching to remove the sacrificial layer, an excessive etching time is required to completely remove the sacrificial layer, so that the wet etching chemicals will contact the cylindrical electrode for a long time, causing irreparable interface damage to the cylindrical electrode, thereby affecting the electrical characteristics of the storage capacitor. Therefore, after forming the through hole for accommodating the cylindrical electrode and before forming the cylindrical electrode, a protective layer is usually formed on the sidewall of the through hole to protect the cylindrical electrode during the etching of the sacrificial layer. Forming a protective layer on the sidewall of the through hole includes first forming a protective material layer on the sidewall and bottom of the through hole, and then anisotropically dry etching to remove the protective material layer at the bottom of the through hole to expose the bottom electrode layer, so that the cylindrical electrode subsequently formed in the through hole can be electrically connected to the bottom electrode layer.

[0004] In the prior art, when etching to remove the protective material layer at the bottom of the through hole, over-etching may occur, resulting in the surface of the bottom electrode layer being etched and damaged, resulting in various rough surfaces such as but not limited to bird's beaks, affecting the contact quality between the cylindrical electrode and the bottom electrode layer, causing excessive interface impedance and thus generating excessively high electric voltage divider, leading to increased power consumption and severe heat generation of the three-dimensional memory. Summary of the Invention

[0005] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention is not intended to limit the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] In order to solve the existing problems, a first aspect of an embodiment of the present invention provides a method for manufacturing a three-dimensional memory, the method comprising:

[0007] Providing a first substrate, the first substrate comprising a base and a stacked layer located above the base, and a bottom electrode layer located between the stacked layer and the base, wherein the stacked layer comprises a plurality of first material layers and a plurality of second material layers stacked alternately, a through hole being formed in the stacked layer, and a bottom of the through hole exposing a top of the bottom electrode layer;

[0008] forming a first thin film layer, wherein the first thin film layer covers the bottom and sidewalls of the through hole;

[0009] performing an ion implantation process along a depth direction of the through hole to modify a portion of the first thin film layer located on a bottom of the through hole;

[0010] Performing a first etching process to remove the unmodified first thin film layer located on the sidewall of the through hole and retaining the modified first thin film layer located at the bottom of the through hole, wherein the first etching process has etching selectivity between the modified first thin film layer and the unmodified first thin film layer;

[0011] forming a second film layer covering the sidewalls of the through hole and the modified first film layer;

[0012] Performing a second etching process includes anisotropically etching the second film layer using the modified first film layer as a stop layer, removing the portion of the second film layer located on the modified first film layer, and retaining the portion of the second film layer located on the side wall of the through hole to form a sidewall material layer.

[0013] In some embodiments of the present application, the first material layer is a dielectric layer; and the method further includes:

[0014] removing the modified first thin film layer and forming a vertical conductor layer electrically connected to the bottom electrode layer in the remaining space of the through hole;

[0015] The second material layer includes a horizontal conductor layer, or the second material layer includes a sacrificial layer, and the sacrificial layer is replaced with the horizontal conductor layer;

[0016] A storage capacitor is formed between the horizontal conductor layer and the vertical conductor layer; the three-dimensional memory further includes a selection unit, which is used to select the vertical conductor layer.

[0017] In some embodiments of the present application, the sidewall material layer includes a capacitor dielectric layer of a storage capacitor.

[0018] In some embodiments of the present application, the second material layer includes a sacrificial layer, the sidewall material layer includes a through-hole filling material protection layer, and the through-hole filling material protection layer contacts the through-hole sidewall;

[0019] Replacing the sacrificial layer with the horizontal conductor layer includes: removing the sacrificial layer to form a horizontal groove between adjacent first material layers, removing the through-hole filling material protection layer exposed by the horizontal groove, and filling the horizontal groove to form the horizontal conductor layer.

[0020] In some embodiments of the present application, the method further comprises:

[0021] Before performing the second etching process, an etching protection layer is formed on the surface of the second thin film layer, and the etching protection layer is used to protect the portion of the second thin film layer located on the side wall of the through hole during the second etching process.

[0022] In some embodiments of the present application, the first thin film layer further includes a portion formed on top of the stacked layers;

[0023] When the ion implantation process is performed along the depth direction of the through hole, a portion of the first thin film layer located on top of the stacked layers is also modified.

[0024] In some embodiments of the present application, after the first etching process is performed, a portion of the modified first thin film layer located on top of the stacked layers forms an overhang at the through hole opening.

[0025] In some embodiments of the present application, an ion implantation process is performed along a depth direction of the through-hole to modify a portion of the first thin film layer located on the bottom of the through-hole, comprising:

[0026] An ion implantation process is performed to damage or dope a portion of the first thin film layer located on the bottom of the through hole.

[0027] In some embodiments of the present application, the method further comprises:

[0028] Before modifying the portion of the first thin film layer located on the bottom of the through hole, forming an ion implantation sidewall protection layer on the surface of the first thin film layer;

[0029] After modifying the portion of the first thin film layer located on the bottom of the through hole, the ion implantation sidewall protection layer is removed.

[0030] In some embodiments of the present application, the thickness of the ion implantation sidewall protection layer at the through-hole opening is greater than the thickness at the through-hole bottom.

[0031] In some embodiments of the present application, the material of the first thin film layer includes crystalline silicon, and the material of the ion implantation sidewall protection layer includes silicon oxide or silicon nitride.

[0032] In some embodiments of the present application, the thickness of the first film layer at the opening of the through hole is greater than the thickness at the bottom of the through hole.

[0033] In some embodiments of the present application, the thickness of the first thin film layer and the energy of the ion implantation are configured so that ions in the ion implantation process reach the top, middle or bottom layer of the portion of the first thin film layer located on the bottom of the through hole.

[0034] In some embodiments of the present application, the first etching process is a wet etching process;

[0035] After the wet etching process is performed, the first film layer remaining at the bottom of the through hole contacts or does not contact the side wall of the through hole.

[0036] According to the method for fabricating a three-dimensional memory device provided by the present invention, a first thin film layer is first formed to cover the bottom and sidewalls of a through-hole. An ion implantation process is then performed along the depth direction of the through-hole to modify the portion of the first thin film layer located on the bottom of the through-hole. Based on the etching selectivity between the modified first thin film layer and the unmodified first thin film layer, a first etching process is performed to remove the unmodified first thin film layer located on the sidewalls of the through-hole, while retaining the modified first thin film layer located on the bottom of the through-hole. During a second etching process, the second thin film layer is anisotropically etched using the modified first thin film layer as a stop layer to remove the portion of the second thin film layer located on the modified first thin film layer, while retaining the portion of the second thin film layer located on the sidewalls of the through-hole to form a sidewall material layer. As a result, the modified first thin film layer located at the bottom of the through-hole can protect the bottom electrode layer and prevent it from being damaged by over-etching, thereby avoiding various rough surfaces such as, but not limited to, bird's beaks on the bottom electrode layer. This avoids excessive interface impedance between the cylindrical electrode and the bottom electrode layer, which could result in excessive voltage division. This can improve the problems of increased power and severe heat generation in the three-dimensional memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The following drawings of the present invention are incorporated herein as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and the description thereof is used to explain the principle of the present invention.

[0038] In the attached figure:

[0039] Figure 1 A schematic flow chart showing a method for preparing a three-dimensional memory according to a specific embodiment of the present invention is shown;

[0040] Figures 2 to 14D Schematic cross-sectional views of various steps of a method for preparing a three-dimensional memory in a specific embodiment of the present invention are shown. DETAILED DESCRIPTION

[0041] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, certain technical features well known in the art are not described to avoid confusion with the present invention.

[0042] It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0043] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0044] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Therefore, in view of the existence of the technical problems described in the above background technology section, an embodiment of the present invention provides a method for preparing a three-dimensional memory, referring to Figure 1 , the preparation method mainly comprises the following steps:

[0047] In S101, a first substrate is provided, the first substrate including a base and a stacked layer located above the base, and a bottom electrode layer located between the stacked layer and the base, the stacked layer including a plurality of first material layers and a plurality of second material layers stacked alternately, a through hole being formed in the stacked layer, and a bottom of the through hole exposing a top of the bottom electrode layer;

[0048] In S102 , a first thin film layer is formed, where the first thin film layer covers the bottom and sidewalls of the through hole;

[0049] In S103 , an ion implantation process is performed along a depth direction of the through hole to modify a portion of the first thin film layer located on the bottom of the through hole;

[0050] In S104, a first etching process is performed to remove the unmodified first thin film layer located on the sidewall of the through hole, and retain the modified first thin film layer located at the bottom of the through hole, wherein the first etching process has etching selectivity between the modified first thin film layer and the unmodified first thin film layer;

[0051] In S105 , a second thin film layer is formed to cover the sidewalls of the through hole and the modified first thin film layer;

[0052] In S106, a second etching process is performed, including anisotropically etching the second thin film layer using the modified first thin film layer as a stop layer, removing the portion of the second thin film layer located on the modified first thin film layer, and retaining the portion of the second thin film layer located on the side wall of the through hole to form a side wall material layer.

[0053] In the above scheme, a first thin film layer covering the bottom and side walls of the through hole is first formed, and then an ion implantation process is performed along the depth direction of the through hole to modify the portion of the first thin film layer located on the bottom of the through hole. Then, based on the etching selectivity between the modified first thin film layer and the unmodified first thin film layer, a first etching process is performed to remove the unmodified first thin film layer located on the side walls of the through hole, while retaining the modified first thin film layer located at the bottom of the through hole. During the second etching process, the second thin film layer is anisotropically etched with the modified first thin film layer as a stop layer to remove the portion of the second thin film layer located on the modified first thin film layer, while retaining the portion of the second thin film layer located on the modified first thin film layer. The sidewall material layer is formed on the portion of the through-hole sidewall, so that the modified first thin film layer located at the bottom of the through-hole can protect the bottom electrode layer and prevent the bottom electrode layer from being damaged by over-etching, thereby avoiding the appearance of various rough surfaces such as but not limited to bird's beaks on the bottom electrode layer, so that the bottom electrode layer exposed on the upper surface of the through-hole has an extremely flat surface, which provides good planar conditions for the subsequent deposition and dense growth of the vertical conductor layer, thereby avoiding the interface impedance between the vertical conductor layer (also called cylindrical electrode) formed in the through-hole and the bottom electrode layer being too large, thereby generating an excessively high electric voltage divider phenomenon, which can improve the problems of power increase and severe heat generation of the three-dimensional memory.

[0054] Below, reference Figures 2 to 14D The preparation method of the three-dimensional memory of the present application is described in detail.

[0055] First, refer to Figure 2 and Figure 3 A first substrate is provided, comprising a base 101 and a stacked layer 105 located above the base 101, and a bottom electrode layer 102 located between the stacked layer 105 and the base 101. A through hole 106 is formed in the stacked layer 105, and the bottom of the through hole 106 exposes the top of the bottom electrode layer 102. That is, in the depth direction of the through hole 106, the through hole 106 penetrates to the bottom of the stacked layer 105, thereby exposing the top of the bottom electrode layer 102. It will be understood that exposing the top of the bottom electrode layer 102 by the through hole 106 includes extending or not extending into a portion of the depth of the bottom electrode layer 102.

[0056] In some embodiments, the stacked layer 105 includes a plurality of alternating first material layers 104 and a plurality of second material layers 103. The first material layers 104 and the second material layers 103 can be selected in a variety of ways. In some embodiments, the first material layer 104 can be a dielectric layer; the second material layer 103 can be a horizontal conductive layer (substantially parallel to the surface of the substrate 101) or a sacrificial layer. The specific materials of the two layers can be determined based on the preparation process.

[0057] The function of the bottom electrode layer 102 provided on the substrate 101 can be determined according to the specific type of the three-dimensional memory, as described exemplarily below. In some embodiments, the three-dimensional memory may include a DRAM (Dynamic Random Access Memory), the type of which may specifically be a 1TnC (1 transistor corresponds to n capacitors connected in series, n ≥ 1 and is an integer) DRAM, wherein the n capacitors in series are formed by n horizontal electrodes and vertical electrodes passing through the horizontal electrodes. It can be understood that the capacitor also includes a capacitor dielectric layer located between the horizontal electrodes and the vertical electrodes, and a transistor is used as a selection unit, the selection unit is used to select the vertical electrode, the selection unit may also be a selection circuit composed of multiple transistors or other selection circuits, and this application does not make specific limitations, as long as the vertical electrode can be selected, for example, the selection unit is directly electrically connected to the vertical electrode (i.e. Figure 12B The vertical conductor layer 114 in the bottom electrode layer 102 is electrically connected to the bottom electrode layer 102 by the selection unit, or the vertical electrode is electrically connected to the bottom electrode layer 102 via the bottom electrode layer 102, thereby enabling the vertical electrode to be selected by the selection unit. In other embodiments, the three-dimensional memory may include other types of three-dimensional memories. In these three-dimensional memories, it is necessary to form a sidewall material layer with a bottom opening in the through hole penetrating the stacked layers without damaging the bottom electrode layer exposed at the bottom of the through hole.

[0058] In one example, the capacitor dielectric layer includes a ferroelectric material, making the three-dimensional memory a ferroelectric memory. However, the present invention is not limited thereto. In some embodiments, the capacitor dielectric layer can be made of other materials as long as it can store data bits.

[0059] There are many ways to form the through hole 106 in the stacked layer 105. For example, Figure 2 , providing a substrate 101 and a stacked layer 105 located above the substrate 101, and a bottom electrode layer 102 located between the stacked layer 105 and the substrate 101. Figure 3 , a through hole 106 is formed in the stacked layer 105 using processes such as, but not limited to, photolithography and dry etching. The etching process for forming the through hole 106 stops at the upper surface of the bottom electrode layer 102 or partially extends into the bottom electrode layer 102, both of which are situations where the bottom of the through hole 106 exposes the top of the bottom electrode layer 102. The size of the through hole 106, such as the depth and diameter of the through hole 106, can be adjusted according to actual needs. The shape of the through hole 106, such as whether the horizontal cross-section of the through hole 106 is circular, elliptical, polygonal, or bar-shaped, whether the shapes of multiple horizontal cross-sections of the through hole 106 are the same, and whether the shapes of different through holes 106 are the same when there are multiple through holes 106, can be adjusted according to actual needs and are not specifically limited in this application.

[0060] Next, refer to Figure 4 , forming a first thin film layer 107, which covers the bottom and sidewalls of the through-hole 106, that is, the first thin film layer 107 at least covers the bottom and sidewalls of the through-hole 106. In some embodiments, the thickness of the first thin film layer 107 is uniform, but is not limited thereto. The thickness distribution of the first thin film layer 107 can be controlled according to actual needs. The first thin film layer 107 includes a portion formed at the bottom of the through-hole 106, which can be defined as a first portion 1071 of the first thin film layer 107. The first thin film layer 107 also includes a portion formed on the sidewalls of the through-hole 106, which can be defined as a second portion 1072 of the first thin film layer 107. In some embodiments, the first thin film layer 107 also includes a portion formed on the top of the stacked layer 105, which can be defined as a third portion 1073 of the first thin film layer 107. The first thin film layer 107 can be formed by processes such as atomic layer deposition, so that the thickness of the first thin film layer 107 uniformly covers the top of the stacked layer 105, the bottom and side walls of the through hole 106, but is not limited to this. In some embodiments, the process of forming the first thin film layer 107 includes chemical vapor deposition or physical vapor deposition, etc.

[0061] Next, refer to Figures 5A to 5E An ion implantation process is performed along the depth direction of the through-hole 106 to modify the portion of the first thin film layer 107 located at the bottom of the through-hole 106 (first portion 1071). Specifically, the portion of the first thin film layer 107 located at the bottom of the through-hole 106 (first portion 1071) is modified, while the portion of the first thin film layer 107 located at the sidewall of the through-hole 106 (second portion 1072) is not modified. This allows the modified first thin film layer 107 to have an etching selectivity with respect to some or specific etchants compared to the unmodified first thin film layer 107. For example, in the first etching process, the etching rate ratio between the modified first thin film layer 107 and the unmodified first thin film layer 107 is 1:(100-5), thereby facilitating the removal of the unmodified first thin film layer 107 located at the sidewall of the through-hole 106 using a selective etching process.

[0062] Regarding the implementation of the modification, various methods can be used, some of which are described below as examples. For example, performing an ion implantation process along the depth direction of the through-hole 106 to modify the portion of the first thin film layer 107 located at the bottom of the through-hole 106 (the first portion 1071) can include: performing the ion implantation process to damage or dope the portion of the first thin film layer 107 located at the bottom of the through-hole 106 (the first portion 1071). In this embodiment, the portion of the first thin film layer 107 located at the bottom of the through-hole 106 (the first portion 1071) is modified by damage or doping to provide etching selectivity between it and the unmodified first thin film layer 107 for some or specific etchants. It should be noted that damage and doping can exist simultaneously. For example, modification including damage can include both damage and doping, and modification including doping can include both doping and damage. In some embodiments, after the ion implantation causes both damage and doping, thermal annealing is performed to repair the damage caused by the ion implantation, so that the modification only includes doping. In some embodiments, doping is the primary modification that causes the difference in etching rate. In some embodiments, damage is the primary modification that causes the difference in etching rate, and the modified first thin film layer 107 includes the entire thickness up to and including the ion implantation depth. It should also be noted that the modification methods are not limited to the aforementioned damage or doping methods. In addition, other methods that can change the etching rate for certain or specific etchants can also be used.

[0063] In some embodiments, when the first thin film layer 107 further includes a portion (third portion 1073) formed on top of the stacked layer 105, the portion (third portion 1073) of the first thin film layer 107 located on top of the stacked layer 105 is also modified during the ion implantation process along the depth direction of the through hole 106. Thus, during the subsequent first etching process, the modified first thin film layer 107 located on top of the stacked layer 105 can protect the stacked layer 105, preventing the top of the stacked layer 105 from being etched and damaged.

[0064] For example, the ion implantation process may include highly directional ion implantation (most ions are implanted along the depth direction of the through-hole 106) to modify the portion of the first thin film layer 107 located at the top of the stacked layer 105 (third portion 1073) and the portion at the bottom of the through-hole 106 (first portion 1071), while leaving the portion of the first thin film layer 107 located at the sidewall of the through-hole (second portion 1072) unmodified. The modified portion of the first thin film layer 107 located at the top of the stacked layer 105 (third portion 1073) and the portion at the bottom of the through-hole 106 (first portion 1071) may have a changed doping concentration or be damaged, resulting in lattice structure relaxation or even destruction of lattice integrity. This may change the reaction rate during etching, resulting in a significantly different etching selectivity between the modified first thin film layer 107 and the unmodified first thin film layer 107 for some or individual etchants. This allows for the directional removal of the second portion 1072 of the first thin film layer 107 using, for example, wet etching.

[0065] In some embodiments, reference Figure 6 The preparation method may further include: before modifying the portion of the first thin film layer 107 located on the bottom of the through hole 106 (the first portion 1071 ), forming an ion implantation sidewall protection layer 118 on the surface of the first thin film layer 107 .

[0066] In an ideal ion implantation process, the ion implantation direction is well perpendicular to the surface of the substrate 101. However, in the actual implementation process, the ion implantation will be scattered, tilted, etc. to a greater or lesser extent, causing the movement direction of some ions to form an angle with the vertical direction. Although the angle will not be very large (for example, less than 10°), the tilted or scattered implanted ions will cause the first thin film layer 107 located on the side wall of the through hole 106 to be at least partially modified, so that the etching selectivity between the first part 1071 and the second part 1072 in the first etching process is reduced, and the first thin film layer 107 on the side wall cannot be completely removed, that is, there will be residues of the first thin film layer 107 on the side wall of the through hole, which may cause defects in subsequent processes and the final three-dimensional memory.

[0067] In this embodiment, before performing the ion implantation process, an ion implantation sidewall protection layer 118 is first formed on the surface of the first thin film layer 107. When the scattered or tilted implanted ions are incident on the thin film layer on the side wall of the through hole 106, they need to completely penetrate the ion implantation sidewall protection layer 118 before they can be implanted into the first thin film layer 107. It can be understood that the longer the path the implanted ions penetrate in the film layer, the higher the ion energy required. Since the angle α of the scattered or tilted implanted ions relative to the thin film layer on the side wall of the through hole 106 is small (usually α<10°), the path of the ion implantation sidewall protection layer 118 on the side wall of the through hole 106 is longer (such as Figure 6L1 in the figure represents the path length of the scattered or tilted implanted ions penetrating the ion implanted sidewall protection layer 118 on the sidewall of the through-hole 106. When the thickness of the ion implanted sidewall protection layer 106 on the sidewall of the through-hole is d, L1 = d / sinα. When α < 10°, L1 is at least 5.8 times of d. Therefore, it is not easy for the ion implanted sidewall protection layer 118 to penetrate. Therefore, the ion implanted sidewall protection layer 118 has a protective effect on the first thin film layer 107 on the sidewall of the through-hole 106. Most of the ions in the ion implantation process move to the bottom of the through-hole 106 in a direction close to or equal to the vertical direction. The implantation direction of these ions is nearly perpendicular to the angle of the ion implanted sidewall protection layer 118 at the bottom of the through-hole 106, and the path when passing through the ion implanted sidewall protection layer 118 is shorter (e.g. Figure 6 L2 in the figure represents the path length of the ions injected vertically into the bottom of the through-hole 106 and penetrating the ion-implanted sidewall protection layer 118. L2 is the thickness of the ion-implanted sidewall protection layer 118 at the bottom of the through-hole 106, i.e., the ions are injected into the first thin film layer 107 at the bottom of the through-hole 106. The ion-implanted sidewall protection layer 118 is prepared using a common deposition process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Typically, depositing a film layer in a through-hole will result in the deposition thickness on the through-hole sidewall being greater than or equal to the deposition thickness at the through-hole bottom. Therefore, L2 is much smaller than L1, allowing the ion-implanted sidewall protection layer 118 to protect the first thin film layer 107 on the sidewall of the through-hole 106 while not hindering the ion injection into the first thin film layer 107 at the bottom of the through-hole 106. This allows the first thin film layer 107 at the bottom of the through-hole 106 to be modified while minimizing the modification of the first thin film layer 107 on the sidewall of the through-hole 106.

[0068] In an embodiment not shown, the thickness of the ion implantation sidewall protection layer 118 at the bottom of the through hole 106 is thinner than the thickness at the opening of the through hole 106. Thus, for situations where the through hole 106 has a large depth-to-width ratio and the ion implantation energy at the opening of the through hole 106 is higher than that at the bottom of the through hole 106, the first thin film layer 107 near the opening of the through hole 106 can be effectively prevented from being modified by ion implantation, while making it easier for the first thin film layer 107 at the bottom of the through hole 106 to be modified. This further reduces the probability of ion implantation penetrating all film layers on the sidewall of the through hole 106 and entering the stacked layer 105, causing damage. For example, the ion implantation sidewall protection layer 118 can be prepared by a process such as chemical vapor deposition, thereby having a thickness distribution in which it is thicker near the opening of the through hole 106 and thinner at the bottom of the through hole 106. Optionally, the thickness of the ion implantation sidewall protection layer 118 gradually decreases from the opening of the through hole 106 to the bottom of the through hole 106. Moreover, the thickness of the ion implantation sidewall protection layer 118 at the bottom of the through hole 106 is thinner than the thickness at the opening of the through hole 106, which can narrow the opening for ion implantation into the through hole 106, improve the collimation of the ion implantation, and further reduce the modification of the first thin film layer 107 on the side wall of the through hole 106 by ion implantation.

[0069] Of course, when the first thin film layer 107 also covers the top of the stacked layer 105, the ion-implanted sidewall protection layer 118 can also cover the first thin film layer 107 at the top of the stacked layer 105. Therefore, when the ion implantation process is performed, the ions implanted into the thin film layer at the top of the stacked layer 105 can penetrate the ion-implanted sidewall protection layer 118 and be implanted into the first thin film layer 107 at the top of the stacked layer 105 because their implantation direction is substantially perpendicular to the thin film layer at the top of the stacked layer 105, thereby modifying the first thin film layer 107 at the top of the stacked layer 105. It should be noted that even if the portion of the ion-implanted sidewall protection layer 118 covering the top of the stacked layer 105 is thicker than the portion located at the bottom of the through-hole 106, since the ion implantation direction is perpendicular, it is still possible to simultaneously protect the sidewalls of the first thin film layer 107 and implant and modify the third portion 1073 of the first thin film layer 107.

[0070] In some embodiments, after modifying the portion of the first thin film layer 107 located on the bottom of the through hole 106 (the first portion 1071 ), the ion implantation sidewall protection layer 118 may be removed by a process such as, but not limited to, wet etching.

[0071] Regarding the material of the first thin film layer 107, various types of materials can be used. For example, the material of the first thin film layer 107 can include any one or more of single crystal silicon, amorphous silicon, polycrystalline silicon, silicon oxide, and silicon nitride. Of course, in addition to these, the first thin film layer 107 can also be made of other materials, as long as the first material layer 103 and the second material layer 104 in the stacked layer 105 can be removed without damaging them, the first thin film layer 107 can be modified to produce a change in etching rate, and the removal of the modified first thin film layer 107 will not damage the subsequently formed sidewall material layer and the bottom electrode layer 102.

[0072] As a preferred embodiment, the material of the first thin film layer 107 may include crystalline silicon. In this case, the material of the ion implantation sidewall protection layer 118 may include silicon oxide or silicon nitride. The ion implantation sidewall protection layer 118 is simple to prepare and has low process cost, while also achieving the protective effect of the ion implantation sidewall protection layer 118.

[0073] In some embodiments, the ratio of the thickness of the first thin film layer 107 at the bottom of the through-hole 106 to the thickness at the opening of the through-hole 106 is 30%-95%. That is, the thickness of the first thin film layer 107 at the bottom of the through-hole 106 is thinner than the thickness at the opening of the through-hole 106. Preferably, the thickness of the first thin film layer 107 gradually decreases from the opening of the through-hole 106 to the bottom of the through-hole 106. This protects the stacked layer 105 during the ion implantation process, preventing scattered or oblique implanted ions from penetrating the first thin film layer 107 on the sidewalls of the through-hole 106 and damaging the stacked layer 105. The reason for this is similar to that for the ion implantation sidewall protection layer 118 protecting the second portion 1072 of the first thin film layer 107 and will not be further elaborated here. In this embodiment, the large difference in film thickness between the sidewalls and the bottom of the through-hole 106 effectively prevents damage to the stacked layer 105 from ion implantation, thereby improving the electrical performance and yield of the three-dimensional memory device. Moreover, the thickness of the first film layer 107 at the bottom of the through hole 106 is thinner than the thickness at the opening of the through hole 106, which can narrow the opening for ion injection into the through hole 106, improve the collimation of the ion injection, and further reduce the modification of the first film layer 107 on the side wall of the through hole 106 by ion injection.

[0074] The ions used in the ion implantation process can be of various materials. For example, the ions used in the ion implantation process can include any one or more of boron, fluorine, argon, hydrogen, silicon, oxygen, carbon, and nitrogen. However, this is not limited to these ions, as long as they can modify the first thin film layer 107 and create a difference in etching rate.

[0075] Regarding the ion implantation energy during the ion implantation process, it can be adjusted according to the depth of the through hole 106 to ensure that the ions are implanted into the first thin film layer 107 at the bottom of the through hole 106 .

[0076] The ion implantation dose of the ion implantation process can be adjusted according to actual needs, for example, according to the modification degree required to achieve etching selectivity, the thickness of the first thin film layer 107 at the bottom of the through hole 106, etc.

[0077] Regarding the ion implantation angle of the ion implantation process, in a preferred embodiment, it is perpendicular to the surface of the substrate 101. In some embodiments, the ion implantation angle of the ion implantation process is offset by no more than 10° relative to the vertical direction perpendicular to the surface of the substrate 101.

[0078] In some embodiments, reference Figures 5B to 5E The thickness of the first thin film layer 107 and the energy of the ion implantation are configured so that the ions in the ion implantation process reach the top layer, middle layer or bottom layer of the portion (first portion 1071 ) of the first thin film layer 107 located on the bottom of the through hole 106 .

[0079] For example, in some embodiments, reference Figure 5C By adjusting the thickness of first thin film layer 107 and the energy of ion implantation, the ions in the sub-implantation process reach the top layer of the portion of first thin film layer 107 located at the bottom of through-hole 106 (first portion 1071). In other words, in the depth direction, the implanted ions are primarily distributed in the shallow layer of first thin film layer 107 at the bottom of through-hole 106. This prevents the implanted ions from penetrating first thin film layer 107 at the bottom of through-hole 106 and causing damage to bottom electrode layer 102 or other electrical defects.

[0080] In other embodiments, reference Figure 5D By adjusting the thickness of the first thin film layer 107 and the energy of the ion implantation, the ions in the sub-implantation process can reach the middle layer of the portion of the first thin film layer 107 located at the bottom of the through hole 106 (the first portion 1071). In other words, in the depth direction, the implanted ions are mainly distributed in the middle layer of the first thin film layer 107 at the bottom of the through hole 106. This can be achieved by increasing the thickness of the first thin film layer 107, thereby reducing the precision control requirements for the ion implantation energy.

[0081] In other embodiments, reference Figure 5EBy configuring the thickness of the first thin film layer 107 and the energy of the ion implantation, the ions in the sub-implantation process can reach the bottom layer of the portion of the first thin film layer 107 located at the bottom of the through-hole 106 (the first portion 1071). That is, in the depth direction, the implanted ions are mainly distributed at the bottom layer of the first thin film layer 107 at the bottom of the through-hole 106. This can be achieved by increasing the thickness of the first thin film layer 107. Since the first thin film layer 107 at the bottom of the through-hole 106 is thicker, the energy of the ions that penetrate to the bottom of the first thin film layer 107 at the bottom of the through-hole 106 is already very low and will not cause damage to the bottom electrode layer 102, thereby lowering the requirements for the ion implantation energy control accuracy.

[0082] Of course, in other embodiments, reference Figure 5B , by configuring the thickness of the first thin film layer 107 and the energy of ion implantation, the ions in the sub-implantation process can be uniformly distributed in the first thin film layer 107 at the bottom of the through hole 106 in the depth direction. At this time, in the depth direction, the doping concentration of the implanted ions in the first thin film layer 107 at the bottom of the through hole 106 has no difference or basically no difference. Therefore, the first thin film layer 107 at the bottom of the through hole 106 as a whole can have etching selectivity relative to the first thin film layer 107 on the side wall of the through hole 106, and the difficulty of controlling the process of removing the first thin film layer 107 on the side wall of the through hole 106 is reduced. Furthermore, the difficulty of subsequently removing the modified first thin film layer 107 at the bottom of the through hole 106 is also reduced.

[0083] Next, refer to Figure 5A and Figure 7A A first etching process is performed to remove the unmodified first thin film layer 107 located on the sidewalls of the through hole 106, while retaining the modified first thin film layer 107 located at the bottom of the through hole 106. The first etching process has etching selectivity between the modified first thin film layer 107 and the unmodified first thin film layer 107. The first etching process can be selected in various ways. For example, the first etching process can be a wet etching process.

[0084] refer to Figure 7A and Figure 7B After the wet etching process, the first thin film layer 107 remaining at the bottom of the through hole 106 may or may not contact the sidewall of the through hole 106. It should be noted that there are many ways to achieve that the first thin film layer 107 remaining at the bottom of the through hole 106 contacts or does not contact the sidewall of the through hole 106.

[0085] Since the first film layer 107 (the second portion 1072) located on the side wall of the through hole 106 blocks the injected ions of the portion of the first film layer 107 located at the bottom of the through hole 106 and in contact with the side wall of the through hole 106 (the portion of the first portion 1071 in contact with the side wall of the through hole 106) during the ion implantation process, the modification degree of the portion of the first film layer 107 located at the bottom of the through hole 106 and in contact with the side wall of the through hole 106 (the portion of the first portion 1071 in contact with the side wall of the through hole 106) is unmodified or significantly lower than that of the first film layer 107. The modification degree of the portion of the film layer 107 located at the bottom of the through-hole 106 and not in contact with the sidewall of the through-hole 106 (the portion of the first portion 1071 that is not in contact with the sidewall of the through-hole 106) causes the etching rate of the portion of the first film layer 107 located at the bottom of the through-hole 106 and in contact with the sidewall of the through-hole 106 (the portion of the first portion 1071 that is in contact with the sidewall of the through-hole 106) to be faster than the etching rate of the portion of the first film layer 107 located at the bottom of the through-hole 106 and not in contact with the sidewall of the through-hole 106 (the portion of the first portion 1071 that is not in contact with the sidewall of the through-hole 106). Figure 7A , the wet etching process can be controlled to be excessive in duration to completely remove the portion of the first thin film layer 107 located at the bottom of the through hole 106 and in contact with the side wall of the through hole 106 (the portion of the first portion 1071 that contacts the side wall of the through hole 106), so that the first thin film layer 107 remaining at the bottom of the through hole 106 does not contact the side wall of the through hole 106. At this time, the second thin film layer 108 formed subsequently can extend to the gap between the portion of the first thin film layer 107 located at the bottom of the through hole 106 and the side wall of the through hole 106, as shown in FIG. Figure 8 As shown, it is beneficial to the design of smaller devices. Figure 7B Alternatively, the wet etching process may be controlled to be shorter in duration so as not to remove the portion of the first thin film layer 107 that is located at the bottom of the through hole 106 and in contact with the side wall of the through hole 106 (the portion of the first portion 1071 that is in contact with the side wall of the through hole 106), so that the first thin film layer 107 (the first portion 1071) retained at the bottom of the through hole 106 contacts the side wall of the through hole 106. It can be understood that at this time, the first thin film layer 107 retained at the bottom of the through hole includes a modified portion and may also include an unmodified portion.

[0086] The first etching process can employ a variety of etchants. For example, the etchant used in the first etching process can include any one or more of hydrofluoric acid, phosphoric acid, nitric acid, acetic acid, potassium hydroxide, hydrogen peroxide, tetramethylammonium hydroxide, piranha solution, and hydrochloric acid. However, this is not limiting. As long as the etchant can achieve etching selectivity between the modified and unmodified first thin film layer 107 under the etchant conditions and does not damage other structures such as the stacked layers, the etchant will suffice.

[0087] An exemplary implementation is described below:

[0088] The material of the first thin film layer 107 comprises crystalline silicon, and the ions implanted include boron. After the ion implantation, the first thin film layer 107 at the bottom of the through hole 106, i.e., the crystalline silicon, is damaged and doped, forming boron-doped amorphous silicon and thus modified. An HNA (HF / HNO3 / CH3COOH) etchant is used to remove the unmodified first thin film layer 107 without damaging the modified first thin film layer 107, thereby achieving selective etching of the first thin film layer 107. In this case, the materials selected for the bottom electrode layer 102 and the stacked layer 105 in the structural design must have a relatively low etching rate for HNA.

[0089] In some embodiments, reference Figure 7A After the first etching process is performed, the portion of the modified first thin film layer 107 located on the top of the stacked layer 105 (the third portion 1073) forms an overhang 1074 at the opening of the through hole 106. Specifically, the portion of the modified first thin film layer 107 located on the top of the stacked layer 105 and close to the sidewall of the through hole 106 has a protruding portion relative to the sidewall of the through hole 106, and this protruding portion constitutes the overhang 1074. Figure 7A and Figure 8 After the second film layer 108 is formed, the second film layer 108 located on the sidewall of the through hole 106 can be blocked by the overhang 1074 in the depth direction of the through hole 106. Figure 10A Therefore, during the second etching process (anisotropic etching) of the second thin film layer 108, the overhang 1074 can protect the second thin film layer 108 on the side wall of the through hole 106, thereby reducing the degree of damage to the upper part of the side wall material layer 110 during the anisotropic etching of the second thin film layer 108.

[0090] The principle of the formation of the overhang 1074 is that during the ion implantation process, the first film layer 107 located at the top corner of the through hole 106 will be modified, while the first film located on the side wall of the through hole 106 will not be modified. Therefore, after the first etching process is performed, the unmodified first film layer 107 located on the side wall of the through hole 106 is removed, and the modified first film layer 107 located at the corner of the through hole 106 remains, forming an overhang 1074 relative to the side wall of the through hole 106.

[0091] In a preferred embodiment, the thickness of the first thin film layer 107 near the opening of the through hole 106 is greater than the thickness near the bottom of the through hole 106. For example, the ratio of the thickness of the first thin film layer 107 at the bottom of the through hole 106 to the thickness at the opening of the through hole 106 is 30%-95%. This can increase the overhang 1074 and improve the protection effect of the second thin film layer 108 on the sidewalls of the through hole 106 during the second etching process.

[0092] Next, refer to Figure 8, forming a second thin film layer 108 covering the sidewalls of the through hole 106 and the modified first thin film layer 107. The second thin film layer 108 can be formed by processes such as, but not limited to, chemical vapor deposition, physical vapor deposition, or atomic layer deposition, so that the second thin film layer 108 covers the sidewalls of the through hole 106 and the retained modified first thin film layer 107. In a preferred embodiment, the second thin film layer 108 is prepared by an atomic layer deposition process, so that the second thin film layer 108 can be formed in the through hole 106 in a conformal manner and with a uniform thickness. Figure 8 In the illustrated embodiment, the second film layer 108 may cover the modified first film layer 107 located at the top of the stacked layers 105, the modified first film layer 107 located at the bottom of the through-hole 106, or the surface of the overhang 1074 formed at the opening of the through-hole 106 by the portion (third portion 1073) of the modified first film layer 107 located at the top of the stacked layers 105. Obviously, the second film layer 108 is also formed on the sidewalls of the through-hole 106. It is understood that when the unmodified first film layer 107 is still present at the bottom of the through-hole 106, the second film layer 108 also covers the unmodified first film layer 107.

[0093] Next, refer to Figure 8 and Figure 10A , performing a second etching process, the second etching process includes anisotropically etching the second thin film layer 108 with the modified first thin film layer 107 as a stop layer, removing the portion of the second thin film layer 108 located on the modified first thin film layer 107, and retaining the portion of the second thin film layer 108 located on the side wall of the through hole 106 to form a sidewall material layer 110.

[0094] Among them, reference Figure 8 When the second thin film layer 108 also includes a portion covering the modified first thin film layer 107 located on top of the stacked layer 105, during the second etching process, the portion of the second thin film layer 108 covering the modified first thin film layer 107 located on top of the stacked layer 105 is also removed.

[0095] During the anisotropic etching process of the second thin film layer 108 using the modified first thin film layer 107 as the stop layer, when etching to the modified first thin film layer 107, the etching rate decreases and the etching process stops at the modified first thin film layer 107, thereby preventing the bottom electrode layer 102 from being damaged by over-etching, thereby avoiding the appearance of various rough surfaces such as but not limited to bird's beaks on the bottom electrode layer 102.

[0096] For example, after the second etching process is performed, the upper surface of the modified first thin film layer 107 remaining at the bottom of the through hole 106 may be as follows: Figure 10A The flushing shown can also be Figure 10BThe middle area shown is recessed, but it can also be Figure 10C It can be understood that the above structure is caused by at least one of the ion implantation modification, the first etching process and the second etching process.

[0097] In some embodiments, reference Figure 11 The preparation method may further include: removing the modified first thin film layer 107. The specific removal process may utilize the difference in etching selectivity between the sidewall material layer 110 and the modified first thin film layer 107, and adopt a wet selective etching process to remove the modified first thin film layer 107, thereby not damaging the top of the bottom electrode layer 102. Obviously, in the wet etching process, there is etching selectivity between the first thin film layer 107 (including the modified first thin film layer 107, or including the modified and unmodified first thin film layers 107) and the bottom electrode layer 102.

[0098] In some embodiments, reference Figure 12B and Figure 14D The preparation method may further include: forming a vertical conductor layer 114 electrically connected to the bottom electrode layer 102 in the remaining space of the through hole 106 , so that the vertical conductor layer 114 is electrically connected to the bottom electrode layer 102 .

[0099] In some embodiments, reference Figure 12B The second material layer 103 includes a horizontal conductor layer 115 , and the first material layer 104 is a dielectric layer, so that the vertically adjacent horizontal conductor layers 115 in the stacked layer 105 are separated by the dielectric layer therebetween.

[0100] In other embodiments, reference 13A to 13C The second material layer 103 includes a sacrificial layer. After forming the vertical conductor layer 114, the sacrificial layer can be replaced with the horizontal conductor layer 115. The specific replacement method may include: removing the sacrificial layer to form a horizontal groove 119 between adjacent first material layers 104, and filling the horizontal groove 119 to form the horizontal conductor layer 115.

[0101] A capacitor dielectric layer 116 may be formed between the horizontal conductor layer 115 and the vertical conductor layer 114 . The memory cell of the three-dimensional memory may include a storage capacitor including the horizontal conductor layer 115 , the vertical conductor layer 114 and the capacitor dielectric layer 116 therebetween.

[0102] In other embodiments, reference Figure 12B , the vertical conductor layer 114 may include an electrode column 120, and the electrode column 120 may be in direct contact with the sidewall material layer 110 and the bottom electrode layer 102; optionally, referring to Figure 12BThe vertical conductor layer 114 includes an electrode column 120 and a portion located between the electrode column 120 and the electrode layer 113. That is, the vertical conductor layer 114 can be formed as a single layer or multiple layers, wherein the electrode layer 113 and the electrode column 120 can be made of any conductor material, which is not specifically limited in this application. For example, in the process of forming the vertical conductor layer 114, refer to Figure 12A , an electrode material layer 111 covering the bottom of the through hole 106, the sidewall material layer 110, and the top of the stacked layer 105 can be formed first, and then the electrode column material layer 112 is filled. The electrode column material layer 112 fills the remaining space of the through hole 106 and covers the upper surface of the electrode material layer 111 located at the bottom of the stacked layer 105; Figure 12B The electrode material layer 111 and the electrode column material layer 112 outside the through hole 106 are removed by a planarization process such as chemical mechanical polishing to form an electrode layer 113 and an electrode column 120 in the through hole 106. The electrode layer 113 is located between the electrode column 120 and the sidewall material layer 110 and the bottom electrode layer 102 at the bottom of the through hole 106.

[0103] Regarding the sidewall material layer 110 , it may be a single material layer or may include multiple material layers. Some exemplary methods are introduced below.

[0104] In some embodiments, reference 14A to 14D The sidewall material layer 110 may include a capacitor dielectric layer of the storage capacitor. Specifically, the sidewall material layer 110 may include only a capacitor dielectric layer; or it may include a capacitor dielectric layer and other material layers in addition to the capacitor dielectric layer, that is, in this case, the sidewall material layer 110 includes at least two material layers. It should be noted that the capacitor dielectric layer may be a single layer or multiple layers.

[0105] In some embodiments, reference 13A to 13C , the second material layer 103 may include a sacrificial layer, that is, the stacked layer 105 is formed by alternating dielectric layers and sacrificial layers. At this time, the sidewall material layer 110 may include a through-hole filling material protective layer 117, and the through-hole filling material protective layer 117 contacts the sidewall of the through-hole 106. Specifically, the sidewall material layer 110 may be a through-hole filling material protective layer 117, or the through-hole filling material protective layer 117 belongs to a portion of the material layer in the sidewall material layer 110 that is closer to the sidewall of the through-hole 106 (or the stacked layer 105). That is, the through-hole filling material protective layer 117 belongs to the material layer deposited first in the second thin film layer 108. It should be noted that the through-hole filling material protective layer 117 can be a single layer or a multi-layer material layer.

[0106] Exemplary, reference 14A to 14DThe sidewall material layer 110 may include a capacitor dielectric layer 116 and a through-hole filling material protection layer 117. The through-hole filling material protection layer 117 contacts and covers the sidewall of the through-hole 106, while the capacitor dielectric layer 116 covers the through-hole filling material protection layer 117 and is separated from the sidewall of the through-hole 106 by the through-hole filling material protection layer 117.

[0107] At this time, refer to 13A to 14D In the process of replacing the sacrificial layer with the horizontal conductor layer 115 and removing the sacrificial layer to form the horizontal groove 119 between the adjacent first material layers 104, an excessive amount of etching time is required to completely remove the sacrificial layer. The via filling material protection layer 117 can protect the other thin film layers (if any) in the sidewall material layer 110 and the vertical conductor layer 114, thereby preventing the other thin film layers (if any) in the sidewall material layer 110 and the vertical conductor layer 114 from being damaged by etching. After removing the sacrificial layer, the via filling material protection layer 117 exposed by the horizontal groove 119 is also removed. This removal method can be wet etching, etc., and then the horizontal groove 119 is filled to form the horizontal conductor layer 115.

[0108] Exemplary, reference Figure 13C When the sidewall material layer 110 includes a through-hole filling material protective layer 117, when filling the horizontal groove 119 to form the horizontal conductor layer 115, a capacitor dielectric layer 116 can be first formed on the groove wall of the horizontal groove 119, and then the remaining space of the horizontal groove 119 is filled to form the horizontal conductor layer 115, thereby forming a storage capacitor between the horizontal conductor layer 115 and the vertical conductor layer 114.

[0109] Exemplary, reference Figure 14D When the sidewall material layer 110 includes a through-hole filling material protection layer 117 and a capacitor dielectric layer 116, after removing the through-hole filling material protection layer 117 exposed by the horizontal groove 119, the horizontal groove 119 can be directly filled to form a horizontal conductor layer 115, and the capacitor dielectric layer 116 in the sidewall material layer 110 separates the horizontal conductor layer 115 and the vertical conductor layer 114 to form a storage capacitor.

[0110] In some embodiments, reference Figure 9The preparation method may further include: before performing the second etching process, forming an etching protection layer 109 on the surface of the second thin film layer 108. The etching protection layer 109 is used to protect the portion of the second thin film layer 108 located on the sidewall of the through hole 106 during the second etching process, thereby preventing damage to the portion of the second thin film layer 108 located on the sidewall of the through hole 106 during the second etching process, which would cause the surface of the formed sidewall material layer 110 to be etched and damaged. It should be noted that the sidewall material layer 110 in all embodiments including at least one of the above-mentioned capacitor dielectric layer 116 and the through hole filling material protection layer 117 can be combined with the etching protection layer 109 of this embodiment.

[0111] In some embodiments, reference Figure 11 The etch protection layer 109 is removed after the second etching process, that is, before forming the vertical conductor layer 114. Of course, in other embodiments, the etch protection layer 109 can be retained to function as a capacitor dielectric layer or a portion of the vertical conductor layer 114.

[0112] Exemplarily, the three-dimensional memory may further include a selection transistor (not shown in the figure), and the selection transistor and the storage capacitor constitute a storage unit of the three-dimensional memory. The setting method of the selection transistor can be adopted in a variety of ways. For example, the selection transistor can be formed on the substrate 101 and electrically connected to the bottom electrode layer 102, so that the selection transistor can be electrically conductive with the vertical conductor layer 114 through the bottom electrode layer 102. In other embodiments, the selection transistor can be formed on the stacked layer 105 and electrically connected to the vertical conductor layer 114. In other embodiments, the selection transistor can also be formed on a second substrate, and the second substrate is bonded to the first substrate, so that the selection transistor is electrically connected to the vertical conductor layer 114.

[0113] It should be noted that the vertical conductor layer 114 is a conductor extending perpendicular to the surface of the substrate 101 and can be any structure in a three-dimensional memory, such as, but not limited to, a cylindrical structure, a polygonal column structure, a conductive plate, or a conductive plug. Accordingly, the through-hole 106 has a structure compatible with the vertical conductor layer 114. The horizontal conductor layer 115 is a conductor extending parallel to the surface of the substrate 101 and can be any structure in a three-dimensional memory, such as, but not limited to, a conductive line or a conductive plate. The vertical conductors can be distributed one-dimensionally or two-dimensionally on a horizontal plane, and this application does not impose any specific restrictions.

[0114] At this point, the main steps of the method for preparing a three-dimensional memory according to one embodiment of the present invention have been completed. It can be understood that the method of this embodiment includes not only the above steps, but also other necessary steps, which are all included in the scope of the method for preparing a three-dimensional memory according to this embodiment.

[0115] The present invention has been described through the above-described embodiments. However, it should be understood that the above-described embodiments are for illustrative and illustrative purposes only and are not intended to limit the present invention to the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments and that various variations and modifications may be made based on the teachings of the present invention, all of which fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for preparing a three-dimensional memory, characterized in that: include: Providing a first substrate, the first substrate comprising a base and a stacked layer located above the base, and a bottom electrode layer located between the stacked layer and the base, the stacked layer comprising a plurality of first material layers and a plurality of second material layers stacked alternately, a through hole formed in the stacked layer, and a bottom of the through hole exposing a top of the bottom electrode layer; forming a first thin film layer, wherein the first thin film layer covers the bottom and sidewalls of the through hole; performing an ion implantation process along a depth direction of the through hole to modify a portion of the first thin film layer located on a bottom of the through hole; Performing a first etching process to remove the unmodified first thin film layer located on the sidewall of the through hole and retain the modified first thin film layer located at the bottom of the through hole, wherein the first etching process has etching selectivity for the modified first thin film layer and the unmodified first thin film layer; forming a second thin film layer covering the sidewall of the through hole and the modified first thin film layer; Performing a second etching process, including anisotropically etching the second thin film layer using the modified first thin film layer as a stop layer, removing the portion of the second thin film layer located on the modified first thin film layer, and retaining the portion of the second thin film layer located on the side wall of the through hole to form a sidewall material layer.

2. The preparation method according to claim 1, wherein The first material layer is a dielectric layer; and the method further includes: removing the modified first thin film layer and forming a vertical conductor layer electrically connected to the bottom electrode layer in the remaining space of the through hole; The second material layer includes a horizontal conductor layer, or the second material layer includes a sacrificial layer, and the sacrificial layer is replaced with a horizontal conductor layer; A storage capacitor is formed between the horizontal conductor layer and the vertical conductor layer; and the three-dimensional memory further includes a selection unit configured to select the vertical conductor layer.

3. The preparation method according to claim 2, wherein The sidewall material layer comprises a capacitance dielectric layer of the storage capacitor.

4. The preparation method according to claim 2 or 3, wherein The second material layer includes a sacrificial layer, the sidewall material layer includes a through-hole filling material protection layer, and the through-hole filling material protection layer contacts the through-hole sidewall; Replacing the sacrificial layer with a horizontal conductor layer includes: removing the sacrificial layer to form a horizontal groove between adjacent first material layers, removing the through-hole filling material protection layer exposed by the horizontal groove, and filling the horizontal groove to form the horizontal conductor layer.

5. The preparation method according to claim 1, 3 or 4, characterized in that: The method further comprises: Before performing the second etching process, an etching protection layer is formed on the surface of the second thin film layer, and the etching protection layer is used to protect the portion of the second thin film layer located on the side wall of the through hole during the second etching process.

6. The preparation method according to claim 1, wherein The first thin film layer also includes a portion formed on top of the stacked layer; When the ion implantation process is performed along the depth direction of the through hole, a portion of the first thin film layer located on the top of the stacked layer is also modified.

7. The preparation method according to claim 6, wherein After performing the first etching process, a portion of the modified first thin film layer located on top of the stacked layer forms an overhang at the through hole opening.

8. The preparation method according to claim 1, wherein The step of performing an ion implantation process along a depth direction of the through hole to modify a portion of the first thin film layer located on the bottom of the through hole comprises: The ion implantation process is performed so that a portion of the first thin film layer located on the bottom of the through hole is damaged or doped.

9. The preparation method according to claim 1, wherein The method further comprises: Before modifying the portion of the first thin film layer located on the bottom of the through hole, forming an ion implantation sidewall protection layer on the surface of the first thin film layer; After modifying the portion of the first thin film layer located on the bottom of the through hole, the ion implantation sidewall protection layer is removed.

10. The preparation method according to claim 9, characterized in that The thickness of the ion implantation sidewall protection layer at the opening of the through hole is greater than the thickness at the bottom of the through hole.

11. The preparation method according to claim 9, wherein The material of the first thin film layer includes crystalline silicon, and the material of the ion implantation sidewall protection layer includes silicon oxide or silicon nitride.

12. The preparation method according to claim 1 or 6, characterized in that: The thickness of the first film layer at the opening of the through hole is greater than the thickness at the bottom of the through hole.

13. The preparation method according to claim 1, wherein The thickness of the first thin film layer and the energy of the ion implantation are configured so that ions in the ion implantation process reach the top layer, middle layer or bottom layer of the portion of the first thin film layer located on the bottom of the through hole.

14. The preparation method according to claim 1, wherein The first etching process is a wet etching process; After the wet etching process is performed, the first thin film layer remaining at the bottom of the through hole contacts or does not contact the sidewall of the through hole.

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