Manufacturing method of memory device and memory device
By forming a semi-floating gate structure with an island structure in the manufacture of memory devices, the problem of high difficulty in capacitor processing is solved, and the storage density is improved and the cost is reduced.
Patent Information
- Application Number
- CN202410366099.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-27
- Publication Date
- 2025-10-03
AI Technical Summary
In the manufacturing of existing memory devices, especially the capacitors of the basic unit structure 1T1C of DRAM, the processing difficulty and cost are high, which affects the storage density.
An island structure is formed on a semiconductor substrate. A groove is opened on the substrate and a gate insulating layer and a gate are formed in sequence. The semi-floating gate structure is formed by combining etching technology to reduce the size of the semi-floating gate in the direction of the bit line extension.
The storage density is improved and the cost of storage devices is reduced.
Smart Images
Figure CN120751703A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a memory device and the memory device. Background Art
[0002] In the application process of integrated circuits, the performance of various devices will be affected by the dimensions between each layer of material, especially memory devices, because the width dimensions between each layer of material affect the unit size of the device.
[0003] During actual operation, the researchers of this application found that the current memory device manufacturing scheme, especially the manufacturing of memory devices, generally adopts the dynamic random access memory (DRAM) scheme for manufacturing, and its basic unit is composed of 1T1C, that is, a structure of a transistor plus a capacitor. Usually, the capacitor of the corresponding structure is manufactured by means of digging deep grooves to reduce the area occupied by it. However, as the storage density increases, the technical difficulty and cost of capacitor processing increase significantly, affecting the storage density of the memory device. Summary of the Invention
[0004] The main technical problem solved by the present invention is to provide a manufacturing method of a memory device and a memory device, which can effectively improve the storage density of the memory device and reduce the cost.
[0005] To solve the above technical problems, a technical solution adopted in the present application is: providing a method for manufacturing a memory device, comprising: providing a semiconductor base, wherein the semiconductor base includes a substrate, a first dielectric layer and a semiconductor layer formed on the substrate; opening a first groove from the semiconductor layer toward the substrate, and forming a gate insulating layer and a first gate in sequence in the first groove; forming a second gate layer on one side of the first gate, wherein the second gate layer contacts the substrate and the first gate; forming an inter-gate dielectric layer and a third gate layer to cover the second gate layer and the first gate; etching the third gate layer, the inter-gate dielectric layer and the second gate layer at the drain end, and etching the third gate layer, the inter-gate dielectric layer and the semiconductor layer at the source end to form an island structure, wherein the first dielectric layer is the etching end point.
[0006] In one embodiment of the present application, providing a semiconductor base includes: providing a substrate, and forming the first dielectric layer and the second dielectric layer on the substrate; opening a plurality of second grooves from the second dielectric layer toward the substrate, wherein the plurality of second grooves are distributed sequentially along a first direction; forming a shallow trench isolation structure in the plurality of second grooves; removing the second dielectric layer, and forming the semiconductor layer on the first dielectric layer to form the semiconductor base.
[0007] In one embodiment of the present application, after the shallow trench isolation structure is formed in the second groove, providing the semiconductor base further includes: performing a first ion implantation on the substrate to form a first doping type well region in the substrate; removing the second dielectric layer, and performing a second ion implantation on the substrate to form a second doping type well region in the substrate; wherein the first doping type is opposite to the second doping type, and the second doping type well region is located on the first doping type well region.
[0008] In one embodiment of the present application, the step of opening a first groove from the semiconductor layer toward the substrate and sequentially forming a gate insulating layer and a first gate electrode in the first groove includes: opening a plurality of first grooves from the semiconductor layer toward the substrate along a second direction; forming the gate insulating layer in the first groove, wherein the gate insulating layer covers a portion of the substrate exposed by the first groove; and forming the first gate electrode in the first groove in which the gate insulating layer is formed, wherein the first gate electrode is isolated from the substrate by the gate insulating layer.
[0009] In one embodiment of the present application, a second gate layer is formed on one side of the first gate, and the second gate layer contacts the substrate and the first gate, including: forming a contact window at the drain end, the contact window exposing the side wall of the first gate and the substrate; and forming the second gate layer in the contact window.
[0010] In one embodiment of the present application, forming a contact window at the drain end includes: etching at the drain end to form a third groove, wherein the third groove exposes the first dielectric layer and the semiconductor layer; oxidizing the portion of the semiconductor layer exposed by the third groove to form an oxide layer; and removing the oxide layer and the first dielectric layer at the bottom of the third groove to form the contact window.
[0011] In one embodiment of the present application, before forming the inter-gate dielectric layer, it also includes: lowering the height of part of the shallow trench isolation structure to form a first isolation part and a second isolation part, so that the first gate is higher than the height of the first isolation part to form a tooth-like structure.
[0012] In one embodiment of the present application, after the island structure is formed, the third gate layer remaining on the inter-gate dielectric layer serves as the third gate; the second gate layer remaining on one side of the first gate serves as the second gate, and the first gate and the second gate constitute a semi-floating gate structure; and isolation sidewalls are formed on both sides of the island structure.
[0013] To solve the above technical problems, another technical solution adopted in the present application is: providing a storage device, comprising: a substrate, a groove, a first gate, a second gate, a dielectric isolation barrier, an inter-gate dielectric layer and a third gate; the groove extends from the surface of the substrate to the substrate, and a gate insulation layer is formed on the inner wall of the groove; the first gate is filled in the first groove having the gate insulation layer and extends onto the substrate, and the first gate is isolated from the substrate by the gate insulation layer; the second gate is arranged on one side of the first gate and contacts the substrate and the first gate; the dielectric isolation barrier is arranged on the other side of the first gate, wherein the dielectric isolation barrier comprises a semiconductor layer.
[0014] In one embodiment of the present application, the width of the second gate in the second direction is 10 nm-20 nm.
[0015] In one embodiment of the present application, the memory device further includes: an inter-gate dielectric layer and a third gate, the inter-gate dielectric layer covers the second gate, the first gate and the dielectric isolation wall, and the third gate layer covers the inter-gate dielectric layer; wherein the third gate layer, the inter-gate dielectric layer, the second gate and the dielectric isolation wall constitute an island structure.
[0016] In an embodiment of the present application, the memory device further includes: isolation spacers, which are arranged on both sides of the island structure.
[0017] In one embodiment of the present application, it also includes: a shallow trench isolation structure for isolating storage cells in a memory device, the shallow trench isolation structure including a first isolation part and a second isolation part, the first isolation part being arranged in the substrate; wherein the first gate is higher than the first isolation part to form a tooth-like structure.
[0018] In one embodiment of the present application, the semiconductor layer is a polysilicon layer.
[0019] Different from the prior art, the present invention provides a method for manufacturing a memory device, comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes a substrate, a first dielectric layer formed on the substrate, and a semiconductor layer; defining a first groove extending from the semiconductor layer toward the substrate, and sequentially forming a gate insulating layer and a first gate within the first groove; forming a second gate layer on one side of the first gate, wherein the second gate layer contacts the substrate and the first gate; forming an intergate dielectric layer and a third gate layer to cover the second gate layer and the first gate; etching the third gate layer, the intergate dielectric layer, and the second gate layer at the drain end, and etching the third gate layer, the intergate dielectric layer, and the semiconductor layer at the source end to form an island structure, wherein the etching terminates at the first dielectric layer. That is, in the present invention, the first gate is formed within the first groove, which reduces the size of the first gate, thereby reducing the size of the semi-floating gate in the bit line extension direction. This increases the storage density at the same size, thereby reducing the cost of manufacturing a memory device with the same density. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:
[0021] Figure 1 is a flow chart of an embodiment of a method for manufacturing a memory device in the present application;
[0022] Figure 2a This is a schematic structural diagram of a first direction of an embodiment of forming a first dielectric layer and a second dielectric layer on a substrate in this application. Figure 2b This is a schematic structural diagram of a second direction of an embodiment of forming a first dielectric layer and a second dielectric layer on a substrate in the present application;
[0023] Figure 3a This is a schematic diagram of the first direction structure of an embodiment of providing a second groove in the substrate in this application. Figure 3b This is a schematic diagram of the second direction structure of an embodiment of providing a second groove in the substrate in the present application;
[0024] Figure 4a This is a schematic diagram of the first direction structure of an embodiment of forming a shallow trench isolation structure in this application, Figure 4b This is a schematic diagram of the structure in the second direction of an embodiment of forming a shallow trench isolation structure in the present application;
[0025] Figure 5a This is a schematic diagram of the first direction structure of an embodiment of forming a second doped well region in this application. Figure 5bThis is a schematic diagram of the second direction structure of an embodiment of forming a second doped well region in the present application;
[0026] Figure 6a This is a schematic diagram of the first direction structure of an embodiment of forming a semiconductor layer in this application. Figure 6b This is a schematic diagram of the second direction structure of an embodiment of forming a semiconductor layer in this application;
[0027] Figure 7a This is a schematic diagram of the first direction structure of an embodiment of the present application in which the first groove is provided. Figure 7b This is a schematic diagram of the second direction structure of an embodiment of the present application in which a first groove is provided;
[0028] Figure 8a 1 is a schematic diagram of a first direction structure of an embodiment of forming a gate insulating layer and a first gate in this application, Figure 8b This is a schematic diagram of the second direction structure of an embodiment of forming a gate insulating layer and a first gate in the present application;
[0029] Figure 9a This is a schematic diagram of the first direction structure of an embodiment of forming the third groove in this application. Figure 9b This is a schematic diagram of the second direction structure of an embodiment of forming a third groove in this application;
[0030] Figure 10a This is a schematic diagram of the first direction structure of an embodiment of forming a gate oxide layer in this application. Figure 10b This is a schematic diagram of the second direction structure of an embodiment of forming a gate oxide layer in this application;
[0031] Figure 11a This is a schematic structural diagram of the first direction of an embodiment of removing a portion of the gate oxide layer and the gate insulation layer in this application, Figure 11b This is a schematic diagram of the structure in the second direction of an embodiment of the present application in which a portion of the gate oxide layer and the gate insulation layer are removed;
[0032] Figure 12a This is a schematic diagram of the first direction structure of an embodiment of forming the second gate layer in this application. Figure 12b This is a schematic diagram of the second direction structure of an embodiment of forming a second gate layer in this application;
[0033] Figure 13a This is a schematic diagram of the first direction structure of an embodiment of the shallow trench isolation structure in this application. Figure 13b This is a schematic diagram of the structure in the second direction of an embodiment of a shallow trench isolation structure in the present application;
[0034] Figure 14a This is a schematic diagram of the first direction structure of an embodiment of forming an inter-gate dielectric layer and a third gate layer in this application, Figure 14bThis is a schematic diagram of the second direction structure of an embodiment of forming an inter-gate dielectric layer and a third gate layer in the present application;
[0035] Figure 15a This is a schematic diagram of the first direction structure of an embodiment of forming an island structure in this application. Figure 15b This is a schematic diagram of the second direction structure of an embodiment of forming an island structure in this application;
[0036] Figure 16a This is a schematic diagram of the first direction structure of an embodiment of forming an isolation sidewall in this application. Figure 16b This is a schematic diagram of the structure in the second direction of an embodiment of forming an isolation sidewall in this application;
[0037] Figure 17a This is a schematic diagram of the first direction structure of an embodiment of forming a half-floating gate transistor in this application. Figure 17b This is a schematic diagram of the second direction structure of an embodiment of forming a half-floating gate transistor in this application;
[0038] Figure 18 is a top view of the storage device in this application.
[0039] In the accompanying drawings, there are a substrate 100, a second groove 101, a shallow trench isolation structure 102, a first isolation portion 1021, a first doping type well region 110, a second doping type well region 120, a first drain terminal 121, a common source terminal 122, a second drain terminal 123, a gate insulation layer 130, a first dielectric layer 200, a first groove 201, a second dielectric layer 300, a semiconductor layer 400, a third groove 401, a contact window 402, an oxide layer 410, a first gate 500, a second gate layer 600, a second gate 610, an inter-gate dielectric layer 700, a third gate layer 800, a third gate 810, an isolation spacer 900, a first half-floating gate transistor J1, and a second half-floating gate transistor J2. DETAILED DESCRIPTION
[0040] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0041] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.
[0042] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0043] The present application is described in detail below with reference to the accompanying drawings and embodiments.
[0044] The basic unit of dynamic random access memory (DRAM) consists of a 1T1C structure, that is, a transistor plus a capacitor. Capacitors of this structure are usually manufactured by means of deep trenching to reduce the area they occupy. However, as storage density increases, the technical difficulty and cost of capacitor processing increase significantly, affecting the storage density of memory devices.
[0045] Semi-floating gate memory is an alternative concept to DRAM devices. Unlike the usual 1T1C structure, semi-floating gate devices include a floating gate transistor and an embedded tunneling transistor. Writing and erasing operations are performed on the floating gate of the floating gate transistor through the channel of the embedded tunneling transistor.
[0046] Therefore, a method for manufacturing a memory device is provided, which can effectively reduce the size of the half-floating gate in the bit line extension direction, correspondingly improve the storage density at the same size, and further reduce the cost when making memory devices with the same density.
[0047] See also Figure 1 , Figure 1 It is a flow chart of an embodiment of a method for manufacturing a memory device in this application.
[0048] like Figure 1 The method for manufacturing the memory device of the present application includes:
[0049] S10, providing a semiconductor substrate, wherein the semiconductor substrate includes a substrate, a first dielectric layer formed on the substrate, and a semiconductor layer. The provided semiconductor substrate is as follows Figure 6a and Figure 6b shown.
[0050] The operation flow of step S10 in an embodiment is as follows:
[0051] Providing a substrate and forming a dielectric layer on the substrate. In one embodiment, the dielectric layer includes a first dielectric layer and a second dielectric layer.
[0052] The substrate may be any suitable base material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S□SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).
[0053] See also Figure 2a and Figure 2b , Figure 2a This is a schematic structural diagram of a first direction of an embodiment of forming a first dielectric layer and a second dielectric layer on a substrate in this application. Figure 2b This is a schematic structural diagram of the second direction of an embodiment of forming a first dielectric layer and a second dielectric layer on a substrate in the present application.
[0054] The first direction is the wordline extension direction (WL), which is also the X direction, and the second direction is the bitline extension direction (BL), which is also the Y direction. That is, the first direction and the second direction are perpendicular to the same horizontal plane.
[0055] Specifically, if Figure 2a and Figure 2b As shown, a substrate 100 is provided, and a first dielectric layer 200 and a second dielectric layer 300 are sequentially formed on the substrate 100 .
[0056] In some embodiments, the first dielectric layer 200 may be an oxide layer, such as a silicon oxide layer; and the second dielectric layer 300 may be a nitride layer, such as a silicon nitride layer.
[0057] Next, a plurality of second grooves 101 are opened from the second dielectric layer 300 toward the substrate.
[0058] See Figure 3a and Figure 3b , Figure 3a This is a schematic diagram of the first direction structure of an embodiment of providing a second groove in the substrate in this application. Figure 3b This is a schematic diagram of the second direction structure of an embodiment of opening a second groove into the substrate in this application.
[0059] like Figure 3a and Figure 3b As shown, a plurality of second grooves 101 are opened from the second dielectric layer 300 toward the substrate 100 to define a plurality of active areas (AA) on the substrate 110; Figure 3a is a cross-sectional view in the first direction, Figure 3b is a cross-sectional view of the active area in the second direction.
[0060] In some embodiments, a plurality of second grooves 101 are sequentially spaced and distributed along the first direction (X direction), and the bottom of the second groove 101 is higher than the bottom of the substrate 100 , that is, the second groove 101 extends to a portion of the substrate 100 .
[0061] Then, a shallow trench isolation structure is formed in the plurality of second grooves, and a first ion implantation is performed to form a first doping type well region.
[0062] See Figure 4a and Figure 4b , Figure 4a This is a schematic diagram of the first direction structure of an embodiment of forming a shallow trench isolation structure in this application, Figure 4b This is a schematic diagram of the second direction structure of an embodiment of forming a shallow trench isolation structure in this application.
[0063] like Figure 4a and Figure 4b As shown, an isolation material is filled in the second groove 101 to form a shallow trench isolation structure 102, and the surface exposed by the shallow trench isolation structure 102 is chemically mechanically polished to make the surface flat, and then ion implantation is performed on the substrate 100 to form a first doping type well region 110 in the substrate 100, wherein the first doping type well region 110 is away from the top surface and the bottom surface of the substrate 100, and the shallow trench isolation structure 102 extends to the first doping type well region 110; Figure 4a is a cross-sectional view in the first direction, Figure 4b is a cross-sectional view of the active area in the second direction, and the subsequent drawings are based on Figure 4a and Figure 4b Continue manufacturing based on this.
[0064] In some embodiments, the lowest point of the first doping type well region 110 is higher than the lowest point of the substrate 100, and the highest point of the first doping type well region 110 is lower than the highest point of the substrate 100, that is, the first doping type well region is located in the substrate and away from the top surface and bottom surface of the substrate 100.
[0065] In some embodiments, a portion of the shallow trench isolation structure 102 is disposed within the substrate 100 and a portion protrudes from the substrate 100 to define a plurality of active areas (AA) in the substrate 100. The shallow trench isolation structure 102 extends along the second direction and is spaced apart in the first direction.
[0066] After the shallow trench isolation structure 102 is formed, the second dielectric layer 300 is removed, and a second ion implantation is performed to form a second doping type well region.
[0067] See Figure 5a and Figure 5b , Figure 5a This is a schematic diagram of the first direction structure of an embodiment of forming a second doped well region in this application. Figure 5b This is a schematic diagram of the second direction structure of an embodiment of forming a second doped well region in this application.
[0068] like Figure 5a and Figure 5b As shown, the second dielectric layer 300 is removed to expose part of the shallow trench isolation structure 102 and the first dielectric layer 200, and ion implantation is performed on the substrate 100 using the first dielectric layer 200 as a barrier layer to form a second doping type well region 120 on a side of the substrate 100 close to the first dielectric layer 200.
[0069] The second doping type well region 120 is closer to the first dielectric layer 200 than the first doping type well region 110 . From a vertical perspective, the first dielectric layer 200 is on the substrate 100 , and the second doping type well region 120 is above the first doping type well region 110 .
[0070] In some embodiments, the doping types of the first doping type well region 110 and the second doping type well region 120 are different, that is, the doping types of the first doping type well region 110 and the second doping type well region 120 are opposite; for example, the first doping type well region 110 is an N-type doped well region, and the second doping type well region 120 is a P-type doped well region; conversely, the first doping type well region 110 is a P-type doped well region, and the second doping type well region is an N-type doped well region.
[0071] Next, a semiconductor layer 400 is formed to cover the first dielectric layer 200 to form a semiconductor substrate.
[0072] See Figure 6a and Figure 6b , Figure 6a This is a schematic diagram of the first direction structure of an embodiment of forming a semiconductor layer in this application. Figure 6b This is a schematic diagram of the second direction structure of an embodiment of forming a semiconductor layer in this application.
[0073] like Figure 6a and Figure 6b As shown, a semiconductor layer 400 is formed on the first dielectric layer 200 so that the semiconductor layer 400 covers the first dielectric layer 200, and the surface of the semiconductor layer 400 is chemically mechanically polished to expose the shallow trench isolation structure 102 and the surface of the semiconductor layer 400, and to make the surface flat.
[0074] The semiconductor layer 400 may be a polycrystalline material, such as a polycrystalline silicon layer.
[0075] At this point, a semiconductor base is formed, that is, the semiconductor base includes: a substrate 100, a first dielectric layer 200, a semiconductor layer 400, a first doping type well region 110 and a second doping type well region 120 formed in the substrate 100, and a shallow trench isolation structure 102 that penetrates the semiconductor layer 400, the first dielectric layer 200 and a portion of the substrate 100.
[0076] S20 , opening a first groove from the semiconductor layer toward the substrate, and sequentially forming a gate insulating layer and a first gate electrode in the first groove.
[0077] The operation flow of step S20 in an embodiment is as follows:
[0078] A plurality of first grooves are opened along the second direction from the semiconductor layer toward the substrate.
[0079] See Figure 7a and Figure 7b , Figure 7a This is a schematic diagram of the first direction structure of an embodiment of the present application in which the first groove is provided. Figure 7b This is a schematic diagram of the second direction structure of an embodiment of a first groove in this application.
[0080] like Figure 7a and Figure 7bAs shown, a first groove 201 is opened from the semiconductor layer 400 toward the substrate 100 and in the active area between the shallow trench isolation structures 102. That is, the first groove 201 penetrates the semiconductor layer 400, the first dielectric layer 200, and a portion of the substrate 100, such as penetrating the second doping type well region 120 in the substrate 100, so that the first doping type well region 110 is exposed through the first groove 201, and multiple first grooves 201 are isolated in the first direction by the shallow trench isolation structure 102, and the multiple first grooves 201 are spaced apart in the second direction.
[0081] In some embodiments, the second doping type well region 120 in the substrate 100 is divided into a source terminal and a drain terminal by the first groove 201 . Figure 7b As shown, in order to save layout area, the source region is shared by two adjacent transistors, and the first groove can be divided into a common source terminal 122, a first drain terminal 121 and a second drain terminal 123; among which, the source terminal, the drain terminal, the first drain terminal 121, the second drain terminal 123, and the common source terminal 122 indicate that a source region or a drain region will be formed at this end later, and do not represent the specific location where the source and drain regions are formed.
[0082] In some embodiments, in the first direction, a portion of the second doping type well region 120 may remain in the substrate 100 exposed by the first groove 201, and the semiconductor layer 400 and the first dielectric layer 200 are removed to expose a portion of the shallow trench isolation structure 102; wherein, the cross-section of the first groove 201 can be U-shaped, trapezoidal, square, etc., and there can be one or more first grooves, which can be determined according to the actual device structure; for example, the first groove 201 is a U-shaped groove, that is, the U-shaped groove is a groove with a large opening and a small bottom in the portion of the first doping type well region 110.
[0083] Next, a gate insulating layer 130 is formed in the first groove 201 , and a first gate material is filled in the first groove 201 in which the gate insulating layer 130 is formed to form a first gate 500 .
[0084] See Figure 8a and Figure 8b , Figure 8a 1 is a schematic diagram of a first direction structure of an embodiment of forming a gate insulating layer and a first gate in this application, Figure 8b It is a schematic diagram of the second direction structure of an embodiment of forming a gate insulating layer and a first gate in this application.
[0085] like Figure 8a and Figure 8bAs shown, a gate insulating layer 130 is formed in the first groove 201, that is, the gate insulating layer 130 covers the side walls and bottom wall exposed by the first groove 201; then, a first gate material is filled in the first groove 201 formed with the gate insulating layer 130 to form a first gate 500, that is, the first gate 500 covers the gate insulating layer 130 in the first groove 201, and then the surface of the first gate 500 is chemically mechanically polished to make the surface of the first gate 500 smooth; in some embodiments, a gate insulating layer 130 can also be formed on the surface of the semiconductor layer 400, that is, the gate insulating layer 130 covers the inner wall of the first groove 201 and the semiconductor layer 400 outside the first groove 201.
[0086] The gate insulating layer 130 may be made of at least one of silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide and the like.
[0087] In one embodiment, the gate insulating layer 130 is silicon oxide, and the gate insulating layer 130 is formed on the sidewalls and bottom wall of the first groove 201 by thermal oxidation, and the gate insulating layer 130 is formed on the exposed surface of the substrate 100. For example, the gate insulating layer 130 formed in the first direction can also be formed on the exposed surface of the semiconductor layer 400 by thermal oxidation.
[0088] In another embodiment, a gate insulating layer 130 can be formed on the sidewalls and bottom wall of the first groove 201 by a deposition method. At this time, the gate insulating layer 130 is not only located on the exposed substrate surface, but also formed on the exposed surface of the semiconductor layer 400, such as the gate insulating layer 130 formed on the surface of the first groove 201 and the semiconductor layer 400 in the second direction.
[0089] Next, a second gate layer is formed on one side of the first gate.
[0090] S30 , forming a second gate layer on one side of the first gate, wherein the second gate layer contacts the substrate and the first gate.
[0091] The operation process of step S30 in the embodiment may include the following steps:
[0092] A portion of the semiconductor layer and a portion of the gate insulating layer are removed to form a third groove at the drain terminal.
[0093] See Figure 9a and Figure 9b , Figure 9a This is a schematic diagram of the first direction structure of an embodiment of forming the third groove in this application. Figure 9b This is a schematic diagram of the second direction structure of an embodiment of forming a third groove in this application.
[0094] like Figure 9a and Figure 9bAs shown, taking the shared source region of two adjacent transistors as an example, the substrate 100 is divided into a shared source terminal 122, a first drain terminal 121, and a second drain terminal 123 by a first groove 201. The semiconductor layer 400 is etched to remove portions of the gate insulating layer 130 and corresponding portions of the semiconductor layer 400 at the first drain terminal 121 and the second drain terminal 123. The first dielectric layer 200 at corresponding positions may be retained to form a plurality of third grooves 401. That is, the first dielectric layer 200 and the semiconductor layer 400 are exposed through the third grooves 401; the gate insulating layer 130 and the semiconductor layer 400 at the shared source terminal 122 are retained.
[0095] The third groove 401 of the first drain terminal 121 is located on a side of the first drain terminal 121 close to the first groove 201 , and the third groove 401 of the second drain terminal 123 is located on a side of the second drain terminal 123 close to the first groove 201 .
[0096] In some embodiments, processing is required at the first drain terminal 121 and the second drain terminal 123 to etch part of the gate insulation layer 130 and the corresponding semiconductor layer 400 on the first drain terminal 121 and the second drain terminal 123 to form a third groove 401 at the first drain terminal 121 and the second drain terminal 123.
[0097] Next, the exposed semiconductor layer 400 may be oxidized by rapid thermal oxidation (RTO) to form an oxide layer, and an oxide layer is also formed on the exposed first gate 500 at the same time.
[0098] See Figure 10a and Figure 10b , Figure 10a This is a schematic diagram of the first direction structure of an embodiment of forming an oxide layer in this application. Figure 10b It is a schematic diagram of the second direction structure of an embodiment of forming an oxide layer in this application.
[0099] like Figure 10a and Figure 10b As shown, an oxide layer 410 is formed on the first gate 500 by rapid thermal oxidation to cover the first gate 500; and the semiconductor layer 400 exposed by the third groove 401 is oxidized by rapid thermal oxidation (RTO), so that the remaining semiconductor layer 400 at the drain end close to the first gate 500 is completely formed into an oxide layer 410.
[0100] Then, the oxide layer 410 on the sidewall of the third groove 401 and the first dielectric layer 200 at the bottom are removed, so that the substrate is exposed at the bottom of the third groove 401 to form a contact window, and the first gate 500 is exposed on one side of the third groove 401; the oxide layer 410 on the first gate 500 and the gate insulation layer 130 on the semiconductor layer 400 are also removed.
[0101] See Figure 11a and Figure 11b , Figure 11a This is a schematic diagram of the first direction structure of an embodiment of removing the oxide layer in this application. Figure 11b This is a schematic diagram of the second direction structure of an embodiment of removing the oxide layer in this application.
[0102] like Figure 11a and Figure 11b As shown, the oxide layer 410 is removed to expose the first gate 500; and the first dielectric layer 200 at the bottom of the third groove 401 is removed to expose the substrate 100, forming a contact window 402, and exposing the sidewall of the first gate 500 through the contact window.
[0103] In some embodiments, the oxide layer 410 is removed by HF (hydrofluoric acid), and the oxide layer on the sidewall of the third groove 401 , the first dielectric layer 200 at the bottom, and the gate insulating layer 130 on the semiconductor layer 400 are removed.
[0104] Next, a second gate layer 600 is formed in the contact window, and the second gate layer 600 contacts the first gate 500 and the substrate 100 .
[0105] See Figure 12a and Figure 12b , Figure 12a This is a schematic diagram of the first direction structure of an embodiment of forming the second gate layer in this application. Figure 12b This is a schematic diagram of the second direction structure of an embodiment of forming the second gate layer in this application.
[0106] like Figure 12a and Figure 12b As shown, a second gate material is filled in the contact window to form a second gate layer 600 so that the second gate layer 600 contacts the first gate 500 and the substrate 100 , and the exposed surface of the second gate layer 600 is chemically mechanically polished to make its surface flat.
[0107] In some embodiments, the second gate layer 600 may be an epitaxial layer, which is filled into the contact window by epitaxy, and at least the portion where the second gate layer 600 contacts the substrate 100 is made of a single crystal material.
[0108] Next, in some embodiments, before forming the inter-gate dielectric layer 700 , the height of a portion of the shallow trench isolation structure 102 is lowered.
[0109] See Figure 13a and Figure 13b , Figure 13a This is a schematic structural diagram of the first direction of an embodiment of reducing the height of the shallow trench isolation structure in this application. Figure 13bThis is a schematic structural diagram of the second direction of an embodiment of reducing the height of the shallow trench isolation structure in the present application.
[0110] like Figure 13a and Figure 13b As shown, the height of a portion of the shallow trench isolation structure 102 is lowered to form a first isolation portion and a second isolation portion, so that the first gate 500 is higher than the first isolation portion of the shallow trench isolation structure 102, forming a tooth structure. The tooth structure can increase the coupling area between the semi-floating gate and the control gate in the semi-floating gate transistor and improve the coupling rate.
[0111] For example, the shallow trench isolation structure 102 includes a first isolation portion and a second isolation portion, which are spaced apart in the second direction, and the first isolation portion is isolated by the first groove 201, wherein, Figure 13a The shallow trench isolation structure 102 shown is the first isolation portion; the height of the first isolation portion is lowered, that is, the height of the first isolation portion is lower than the height of the first gate 500, and the second isolation portion (not marked in the drawings) protrudes from the substrate 100 and is flush with the semiconductor layer 400; that is, the first isolation portion is arranged in the substrate 100, the second isolation portion protrudes from the substrate 100, the first isolation portion and the second isolation portion are connected in the substrate, and the portion above the substrate only includes the second isolation portion, therefore, the first isolation portion and the second isolation portion are spaced apart in the second direction on the substrate.
[0112] S40 , forming an inter-gate dielectric layer and a third gate layer to cover the second gate layer and the first gate.
[0113] The operation flow of step S40 in an embodiment is as follows:
[0114] An inter-gate dielectric layer is formed on the second gate layer, the first gate and the remaining semiconductor layer, and a third gate layer is formed on the inter-gate dielectric layer.
[0115] See Figure 14a and Figure 14b , Figure 14a This is a schematic diagram of the first direction structure of an embodiment of forming an inter-gate dielectric layer and a third gate layer in this application, Figure 14b This is a schematic diagram of the second direction structure of an embodiment of forming an inter-gate dielectric layer and a third gate layer in this application.
[0116] like Figure 14a and Figure 14b As shown, an inter-gate dielectric layer 700 is formed on the semiconductor layer 400 , the second gate layer 600 and the first gate 500 , and a third gate layer 800 is formed on the inter-gate dielectric layer 700 . The surface of the third gate layer 800 is flat.
[0117] In some embodiments, the inter-gate dielectric layer 700 may be an ON (Oxide-Nitride) structure, that is, the inter-gate dielectric layer 700 may include an oxide layer and a nitride layer, such as a silicon oxide layer and a silicon nitride layer, to form an ON structure; the third gate layer 800 may be a polycrystalline material, such as polycrystalline silicon.
[0118] S50 , etching the third gate layer, the intergate dielectric layer, and the second gate layer at the drain end, and etching the third gate layer, the intergate dielectric layer, and the semiconductor layer at the source end to form an island structure, wherein the first dielectric layer is the etching end point.
[0119] The operation flow of step S50 in an embodiment is as follows:
[0120] Then, an etching process is performed, that is, an etching process is performed on the drain terminal to remove the third gate layer, the intergate dielectric layer, the semiconductor layer and a portion of the second gate layer on the first drain terminal and the second drain terminal, exposing the first dielectric layer and a portion of the substrate;
[0121] The source terminal is etched to remove the third gate layer, the inter-gate dielectric layer and a portion of the semiconductor layer on the common source terminal, exposing the first dielectric layer to form an island structure.
[0122] See Figure 15a and Figure 15b , Figure 15a This is a schematic diagram of the first direction structure of an embodiment of forming an island structure in this application. Figure 15b This is a schematic diagram of the second direction structure of an embodiment of forming an island structure in this application.
[0123] like Figure 15a and Figure 15b As shown, an etching process is performed to remove a portion of the third gate layer 800, a portion of the intergate dielectric layer 700, and a portion of the second gate layer 600 on the first drain terminal 121, so that the substrate 100 of the first drain terminal 121 is exposed; a portion of the third gate layer 800, a portion of the intergate dielectric layer 700, and a portion of the second gate layer 600 on the second drain terminal 123 are removed, so that the substrate 100 of the second drain terminal 123 is exposed; and a portion of the third gate layer 800, a portion of the intergate dielectric layer 700, and a portion of the semiconductor layer 400 on the common source terminal 122 are removed, so that the first dielectric layer 200 in the common source terminal region is exposed.
[0124] During this process, because the stacked layers on the source and drain terminals are made of the same or similar materials, etching can be performed simultaneously on both terminals to form an island structure. Specifically, from top to bottom, the drain terminal requires etching the third gate layer 800, the inter-gate dielectric layer 700, and the second gate layer 600. From top to bottom, the source terminal requires etching the third gate layer 800, the inter-gate dielectric layer 700, and the semiconductor layer 400. Both the second gate layer 600 and the semiconductor layer 400 are made of silicon, so both terminals can be etched simultaneously to form an island structure.
[0125] In some embodiments, the third gate layer 800 remaining on the inter-gate dielectric layer 700 serves as a third gate 810, i.e., a control gate; the second gate layer remaining on one side of the first gate 500 serves as a second gate 610, and the first gate 500 and the second gate 610 constitute a semi-floating gate structure, i.e., the second gate layer remaining at the drain end serves as the second gate 610, and the horizontal line width of the second gate 610 is 10 nm to 20 nm, such as 15 nm; and the first dielectric layer and the semiconductor layer 400 remaining on the other side of the first gate 500 serve as dielectric isolation walls, i.e., the semiconductor layer 400 remaining at the source end and the first dielectric layer 200 serve as dielectric isolation walls, wherein the horizontal width of the semiconductor layer 400 is determined by process errors, for example, the horizontal line width of the dielectric isolation wall can be the same as the line width of the second gate 610.
[0126] In some implementations, the gate insulating layer 130 is retained on a side of the semiconductor layer 400 at the source end close to the first gate 500 . Therefore, this portion of the gate insulating layer 130 can also serve as a part of the dielectric isolation barrier.
[0127] Because the corresponding first dielectric layer 200 is retained on the source terminal at this time, and because the first dielectric layer 200 is an oxide layer, when etching is performed to form an island structure, the etching stop position can be controlled based on the first dielectric layer 200, that is, etching is stopped when the first dielectric layer 200 is reached. Compared with the current technology of multiple etching operations that stop etching by setting an etching time, the present application uses the first dielectric layer as the etching stop point, reduces the etching operation, and can increase the corresponding process window, thereby increasing the feasibility of the process operation and ensuring the density of the device.
[0128] Next, isolation sidewalls are formed on both sides of the island structure.
[0129] See Figure 16a and Figure 16b , Figure 16a This is a schematic diagram of the first direction structure of an embodiment of forming an isolation sidewall in this application. Figure 16b This is a schematic diagram of the second direction structure of an embodiment of forming an isolation sidewall in this application.
[0130] like Figure 16a and 16b As shown, in Figure 15a and Figure 15b On this basis, isolation sidewalls 900 are formed on both sides of the island structure.
[0131] In some embodiments, after the isolation spacer 900 is formed, source and drain ion implantation is performed on the substrate 100 below the outer side of the isolation spacer 900 to form a semi-floating gate transistor.
[0132] See Figure 17a and Figure 17b , Figure 17a This is a schematic diagram of the first direction structure of an embodiment of forming a half-floating gate transistor in this application. Figure 17b This is a schematic diagram of the second direction structure of an embodiment of forming a half-floating gate transistor in this application.
[0133] like Figure 17a and Figure 17b As shown, after the isolation sidewall 900 is formed, source-drain ion implantation is performed on the substrate 100 below the outer side of the isolation sidewall 900 to form a corresponding common source region in the common source terminal 122, a first drain region is formed in the first drain terminal 121, and a second drain region is formed in the second drain terminal 123. That is, source-drain ion implantation is performed on the substrate 100 to form corresponding sources and drains, and the second dielectric layer 200 on the common source terminal 122, the first drain terminal 121, and the second drain terminal 123 is removed.
[0134] After the above steps, a semi-floating gate transistor can be formed on the substrate, such as Figure 17a and Figure 17b The first half-floating gate transistor J1 and the second half-floating gate transistor J2 shown further form a memory cell in the memory device.
[0135] In some embodiments, the line widths of the second gates 610 in the first half-floating gate transistor J1 and the second half-floating gate transistor J2 are consistent, which helps ensure the consistency of the half-floating gate transistors.
[0136] In order to better illustrate the structure of the memory device, a top view of the memory device is provided.
[0137] See Figure 18 , Figure 18 is a top view of the storage device in this application.
[0138] like Figure 18 As shown in the figure, in the first direction, it can be divided into two types of regions, where X1 is the first type of region in the first direction, and X2 is the second type of region in the first direction. The above-mentioned xa figure, as shown in Figure 2a 、 Figure 3a 、 Figure 4aetc. are all cross-sectional views of the first type region X1 in the first direction. The first isolation portion of the shallow trench isolation structure is also located in the first type region X1 in the first direction, and the second isolation portion of the shallow trench isolation structure is located in the second type region X2 in the first direction, that is, the first isolation portion 1021 and the second isolation portion (not marked in the figure) are spaced apart in the second direction, and the first isolation portion 1021 and the AA region are spaced apart in the first direction; in the second direction, it can be divided into two types of regions, wherein Y1 is the first type region in the second direction, and Y2 is the second type region in the second direction. The aforementioned xb figure, as shown Figure 2b 、 Figure 3b 、 Figure 4b etc. are all cross-sectional views of the second type region Y2 in the second direction, corresponding to the first gate in the first groove.
[0139] The present application also relates to a memory device, comprising the aforementioned half-floating gate transistor, see Figure 17a 、 Figure 17b and Figure 18 .
[0140] Specifically, the memory device includes a substrate 100, a groove, a first gate 500, a second gate 610, a dielectric isolation barrier, an inter-gate dielectric layer 700, and a third gate 810. The portion of the first groove 201 in the substrate is defined as a groove, the groove extending from the surface of the substrate 100 toward the substrate 100, and having a gate insulating layer 130 formed on the inner wall of the groove; the first gate 500 is filled in the first groove 201 having the gate insulating layer 130 and extending onto the substrate 100, and the first gate 500 is isolated from the substrate 100 by the gate insulating layer 130; the second gate 610 is disposed on one side of the first gate 500, the second gate 610 is in contact with the substrate 100, and the second gate 610 is also in contact with the first gate 500; and the dielectric isolation barrier is disposed on the other side of the first gate 500, wherein the dielectric isolation barrier comprises a semiconductor layer.
[0141] In some embodiments, the width of the second gate in the second direction is 10 nm-20 nm, for example, 15 nm.
[0142] In some embodiments, the memory device further includes an inter-gate dielectric layer and a third gate, the inter-gate dielectric layer 700 covers the second gate 610, the first gate 500 and the dielectric isolation wall, and the third gate 810 covers the inter-gate dielectric layer 700; wherein, the third gate 810, the inter-gate dielectric layer 700, the second gate 610 and the dielectric isolation wall constitute an island structure.
[0143] In some embodiments, the dielectric isolation barrier includes a first dielectric layer 200 and a semiconductor layer 400, that is, part of the first dielectric layer 200 at the source end and part of the semiconductor layer 400 serve as the dielectric isolation barrier; wherein the first dielectric layer 200 may be polysilicon or silicon oxide, and the semiconductor layer 400 may be a polycrystalline material, such as polysilicon.
[0144] In some embodiments, the source terminal further includes a gate insulating layer 130 , which may also serve as a part of the dielectric isolation barrier. The gate insulating layer 130 in the dielectric isolation barrier covers the sidewalls of the first gate 500 .
[0145] It can be understood that the first gate 500 and the second gate 610 constitute a semi-floating gate of a memory cell in the memory device, and the third gate 810 constitutes a control gate of the memory cell in the memory device.
[0146] In some embodiments, the memory device further includes an isolation sidewall 900, which is arranged on both sides of the island structure of the memory device, that is, on both sides of the memory cell in the memory device. The isolation sidewall 900 covers the second gate 610, the inter-gate dielectric layer 700, the third gate 810 and the dielectric isolation barrier wall exposed on both sides of the memory cell.
[0147] In some embodiments, a first doping type well region 110 and a second doping type well region 120 are formed in the substrate 100, wherein the second doping type well region 120 is located on a side of the substrate 100 close to the second gate 610, and the first doping type well region 110 is located on a side of the second doping type well region 120 away from the second gate 610, and the first doping type well region 110 and the second doping type well region 120 are in contact, that is, the second doping type well region 120 is located on the first doping type well region, and the doping types of the first doping type well region 110 and the second doping type well region 120 are opposite.
[0148] In some embodiments, the substrate 100 also includes a shallow trench isolation structure 102 for isolating storage cells in a memory device, and the shallow trench isolation structure 102 includes a first isolation portion 1021 and a second isolation portion (not marked in the drawings), wherein the first isolation portion 1021 and the second isolation portion are spaced apart from each other in the second direction, and the height of the first isolation portion is lower than the height of the first gate 500, forming a tooth-like structure, and the height of the second isolation portion can be the same as the height of the second gate 610.
[0149] In some embodiments, the number of semi-floating gate transistors in the memory device can be multiple, for example, 2, 3, 4, etc., and the line width of the second gate 610 in different semi-floating gate transistors is 10nm-20nm. The corresponding contact window in the current technology is larger than this value, resulting in the corresponding gate line width being larger than this value. Therefore, the memory device in the present application has a smaller line width than the current technology, reduces the area occupied by the second gate 610 on the doped region, improves the integration density of the memory device, and improves the storage density.
[0150] In the present application, a method for manufacturing a memory device includes: providing a semiconductor base, wherein the semiconductor base includes a substrate, a first dielectric layer and a semiconductor layer formed on the substrate; opening a first groove from the semiconductor layer toward the substrate, and sequentially forming a gate insulating layer and a first gate in the first groove; forming a second gate layer on one side of the first gate, wherein the second gate layer contacts the substrate and the first gate; forming an inter-gate dielectric layer and a third gate layer to cover the second gate layer and the first gate; etching the third gate layer, the inter-gate dielectric layer and the second gate layer at the drain end, and etching the third gate layer, the inter-gate dielectric layer and the semiconductor layer at the source end to form an island structure, wherein the first dielectric layer is the etching end point. By forming the first gate in the first groove through the above method, the size of the first gate can be effectively reduced, thereby reducing the size of the semi-floating gate in the direction of bit line extension. At the same size, the integration density of the memory device is improved, and the storage density is correspondingly increased, thereby reducing the cost when making memory devices with the same density. In addition, a first dielectric layer is formed below the semiconductor layer, so that when subsequently etching into an island structure, the first dielectric layer on the source terminal and the drain terminal is used as the etching end point, and the source terminal and the drain terminal can be etched simultaneously, thereby increasing the feasibility of the manufacturing process and improving manufacturing efficiency.
[0151] The above description is only an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A method for manufacturing a memory device, characterized in that: include: Providing a semiconductor base, wherein the semiconductor base includes a substrate, a first dielectric layer formed on the substrate, and a semiconductor layer; A first groove is formed from the semiconductor layer toward the substrate, and a gate insulating layer and a first gate are sequentially formed in the first groove; forming a second gate layer on one side of the first gate, wherein the second gate layer contacts the substrate and the first gate; forming an inter-gate dielectric layer and a third gate layer to cover the second gate layer and the first gate; The third gate layer, the intergate dielectric layer and the second gate layer at the drain end are etched, and the third gate layer, the intergate dielectric layer and the semiconductor layer at the source end are etched to form an island structure, wherein the first dielectric layer is the etching end point.
2. The method according to claim 1, characterized in that The provision of a semiconductor substrate comprises: Providing a substrate, and forming the first dielectric layer and the second dielectric layer on the substrate; A plurality of second grooves are formed from the second dielectric layer toward the substrate, wherein the plurality of second grooves are sequentially distributed along the first direction; forming shallow trench isolation structures in the plurality of second grooves; The second dielectric layer is removed, and the semiconductor layer is formed on the first dielectric layer to form the semiconductor substrate.
3. The method according to claim 2, characterized in that After forming the shallow trench isolation structure in the second groove, providing the semiconductor substrate further includes: Performing a first ion implantation on the substrate to form a first doping type well region on the substrate; The second dielectric layer is removed, and the substrate is subjected to a second ion implantation to form a second doping type well region in the substrate; wherein the first doping type is opposite to the second doping type, and the second doping type well region is located on the first doping type well region.
4. The method according to claim 1, wherein The method of opening a first groove from the semiconductor layer toward the substrate and sequentially forming a gate insulating layer and a first gate in the first groove includes: Opening a plurality of first grooves along a second direction from the semiconductor layer toward the substrate; forming the gate insulating layer in the first groove, wherein the gate insulating layer covers the portion of the substrate exposed by the first groove; The first gate is formed in the first groove in which the gate insulating layer is formed, wherein the first gate is isolated from the substrate by the gate insulating layer.
5. The method according to claim 1, wherein The step of forming a second gate layer on one side of the first gate, wherein the second gate layer contacts the substrate and the first gate, comprises: forming a contact window at the drain terminal, wherein the contact window exposes the sidewall of the first gate and the substrate; A second gate layer is formed in the contact window.
6. The method according to claim 5, characterized in that The forming of a contact window at the drain terminal includes: Etching at the drain end to form a third groove, wherein the third groove exposes the first dielectric layer and the semiconductor layer; performing oxidation treatment on a portion of the semiconductor layer exposed by the third groove to form an oxide layer; The oxide layer and the first dielectric layer at the bottom of the third groove are removed to form the contact window.
7. The method according to claim 1, characterized in that Before forming the inter-gate dielectric layer, the method further includes: The height of a portion of the shallow trench isolation structure is lowered to form a first isolation portion and a second isolation portion, so that the first gate is higher than the height of the first isolation portion to form a tooth-shaped structure.
8. The method according to claim 1, characterized in that After the island structure is formed, the third gate layer remaining on the inter-gate dielectric layer serves as a third gate; The second gate layer remaining on one side of the first gate serves as the second gate, and the first gate and the second gate form a semi-floating gate structure; Isolation sidewalls are formed on both sides of the island structure.
9. A memory device, characterized in that: include: substrate; a groove extending from the surface of the substrate toward the substrate, and having a gate insulating layer formed on an inner wall of the groove; a first gate electrode filled in the first groove of the gate insulating layer and extending onto the substrate, wherein the first gate electrode is isolated from the substrate by the gate insulating layer; a second gate, disposed on one side of the first gate and in contact with the substrate and the first gate; The dielectric isolation barrier is arranged on the other side of the first gate, wherein the dielectric isolation barrier comprises a semiconductor layer.
10. The memory device according to claim 9, wherein: The width of the second gate in the second direction is 10 nm-20 nm.
11. The memory device according to claim 9, wherein: Also includes: an inter-gate dielectric layer and a third gate, wherein the inter-gate dielectric layer covers the second gate, the first gate and the dielectric isolation barrier, and the third gate layer covers the inter-gate dielectric layer; The third gate layer, the inter-gate dielectric layer, the second gate and the dielectric isolation barrier wall form an island structure.
12. The memory device according to claim 11, wherein: Also includes: Isolation side walls are arranged on both sides of the island structure.
13. The memory device according to claim 9, wherein: Also includes: A shallow trench isolation structure for isolating storage cells in a memory device, the shallow trench isolation structure comprising a first isolation portion and a second isolation portion, the first isolation portion being arranged in the substrate, wherein the first gate is higher than the first isolation portion to form a tooth-like structure.
14. The memory device according to any one of claims 9 to 13, wherein: The semiconductor layer is a polysilicon layer.