Preparation method of flash memory device
By using the ISSG process and diffused plasma nitridation process to infiltrate nitrogen ions and perform thermal annealing in flash memory devices, the read error problem caused by leakage of the ONO film layer is solved, and the reliability and electrical performance of the device are improved.
Patent Information
- Application Number
- CN202510815904.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-17
- Publication Date
- 2025-10-03
AI Technical Summary
Flash memory devices using the 55nm/90nm process nodes experience "0→1" errors during read operations, resulting in failure to read stored information. This is primarily due to slight leakage between the floating gate and the control gate.
The first silicon oxide layer is formed by the ISSG process, and nitrogen ions are infiltrated into it through a diffusion plasma nitridation process. Subsequently, a thermal annealing process is performed to repair the lattice to form a silicon nitride layer and a second silicon oxide layer, thereby enhancing the dielectric properties of the ONO film layer and inhibiting P-type ion diffusion.
The leakage of the ONO film layer is effectively suppressed, the read operation reliability and electrical performance of the flash memory device are improved, and the life of the device is improved.
Smart Images
Figure CN120751704A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a flash memory device. Background Art
[0002] Multiple products using 55nm / 90nm process node flash memory devices exhibit "0→1" errors during read operations (i.e., a stored "0" is mistakenly read as a "1"), resulting in the product being unable to successfully read the stored information.
[0003] Judging from the failure phenomena, all of them are read interference failures caused by long-term pressure on the CG (control gate) end. A weak leakage occurs between the floating gate and the control gate, and the floating gate electrons pass through the ONO film layer, causing the originally stored "0" to be misread as "1", resulting in read failure. Summary of the Invention
[0004] The present application provides a method for preparing a flash memory device, which can solve the problem that the flash memory device fails to read stored information due to leakage of the ONO film layer of the traditional flash memory device.
[0005] The present invention provides a method for manufacturing a flash memory device, comprising:
[0006] Providing a substrate, on which a gate oxide layer and a floating gate layer are sequentially formed;
[0007] forming a first silicon oxide layer by adopting an ISSG process;
[0008] Infiltrating a certain dose of nitrogen ions into the first silicon oxide layer through a diffusion plasma nitridation process;
[0009] performing a thermal annealing process on the semiconductor structure after the diffusion plasma nitridation process;
[0010] forming a silicon nitride layer, wherein the silicon nitride layer covers the first silicon oxide layer;
[0011] A second silicon oxide layer is formed, wherein the second silicon oxide layer covers the silicon nitride layer.
[0012] Optionally, in the method for preparing the flash memory device, the thickness of the first silicon oxide layer is 40 angstroms to 60 angstroms.
[0013] Optionally, in the method for preparing the flash memory device, in the process of infiltrating nitrogen ions into the first silicon oxide layer by the diffusion plasma nitridation process, the dose of the nitrogen ions infiltrated into the first silicon oxide layer is 1E5 atoms / cm 2 ~1E6 atoms / cm 2 .
[0014] Optionally, in the method for preparing the flash memory device, the radio frequency power of the diffused plasma nitridation process is 1800W to 2000W.
[0015] Optionally, in the method for preparing the flash memory device, during the thermal annealing process performed on the semiconductor structure after the diffusion plasma nitridation process, the process temperature is 1050° C. to 1150° C., and the process time is 10s to 30s.
[0016] Optionally, in the method for preparing the flash memory device, the thickness of the silicon nitride layer is 20 angstroms to 60 angstroms.
[0017] Optionally, in the method for preparing the flash memory device, the second silicon oxide layer is formed by a CVD process.
[0018] Optionally, in the method for preparing the flash memory device, the thickness of the second silicon oxide layer is 30 angstroms to 70 angstroms.
[0019] Optionally, in the method for preparing the flash memory device, after forming the second silicon oxide layer, the method for preparing the flash memory device further comprises:
[0020] A control gate layer is formed, where the control gate layer covers the second silicon oxide layer.
[0021] The technical solution of this application has at least the following advantages:
[0022] In the preparation method of the flash memory device provided in the present application, a dense first silicon oxide layer is first generated by the ISSG process, and then nitrogen ions are infiltrated into the first silicon oxide layer by a diffusion plasma nitridation process. Finally, the lattice of the first silicon oxide layer is repaired by a post-nitridation thermal annealing process. The dielectric constant of the first silicon oxide layer after nitridation is greater than that of the first silicon oxide layer in the traditional ONO film layer, which can effectively inhibit P-type ions (such as boron ions, phosphorus ions and other P-type ions) from diffusing from the floating gate layer to the control gate layer, avoiding the problem of ONO film leakage causing the flash memory device to fail to read the stored information, improving the reliability of the read operation of the flash memory device, and improving the electrical performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0024] Figure 1 is a flow chart of a method for preparing a flash memory device according to an embodiment of the present invention;
[0025] Figure 2-Figure 5 Schematic diagram of the semiconductor structure in each process step of preparing a flash memory device according to an embodiment of the present invention;
[0026] The description of the accompanying drawings is as follows:
[0027] 10 - substrate, 20 - gate oxide layer, 30 - floating gate layer, 40 - ONO film layer, 41 - first silicon oxide layer, 42 - silicon nitride layer, 43 - second silicon oxide layer. DETAILED DESCRIPTION
[0028] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0029] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0030] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0031] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0032] The present invention provides a method for preparing a flash memory device. Figure 1 , Figure 1 1 is a flow chart of a method for preparing a flash memory device according to an embodiment of the present invention, wherein the method for preparing a flash memory device comprises:
[0033] First, perform step S1: refer to Figure 2 , Figure 2 1 is a schematic diagram of a semiconductor structure after a floating gate layer is formed according to an embodiment of the present application. A substrate 10 is provided, on which a gate oxide layer 20 and a floating gate layer 30 are sequentially formed.
[0034] Specifically, the substrate 10 includes at least a storage area. In this embodiment, a gate oxide layer 20 and a floating gate layer 30 are sequentially formed on the surface of at least the storage area of the substrate 10 .
[0035] Then, execute step S2: refer to Figure 3 , Figure 3 3 is a schematic diagram of a semiconductor structure after forming a first silicon oxide layer according to an embodiment of the present application. The first silicon oxide layer 41 is formed by adopting an ISSG (in-situ steam oxidation) process.
[0036] In this embodiment, the thickness of the first silicon oxide layer 41 is 40 angstroms to 60 angstroms.
[0037] Next, execute step S3: refer to Figure 4 , Figure 4 Schematic diagram of a semiconductor structure during a diffusion plasma nitridation process according to an embodiment of the present application, wherein a certain dose of nitrogen ions is introduced into the first silicon oxide layer 41 through the diffusion plasma nitridation process.
[0038] Preferably, in the process of infiltrating nitrogen ions into the first silicon oxide layer 41 through the diffusion plasma nitridation process, the dose of nitrogen ions infiltrated into the first silicon oxide layer 41 is 1E5 atoms / cm 2 ~1E6 atoms / cm 2 .
[0039] In this embodiment, the dosage of nitrogen ions implanted into the first silicon oxide layer 41 is 2E5 atoms / cm 2 .
[0040] Preferably, the radio frequency power of the diffusion plasma nitridation process is 1800W to 2000W, the flow rate of the nitrogen gas is 100sccm to 300sccm, and the process time is 15s to 25s.
[0041] The incorporation of nitrogen can increase the dielectric constant (k value) of the first silicon oxide layer. Furthermore, the incorporation of nitrogen can effectively inhibit the diffusion of P-type dopant ions such as boron and phosphorus from the floating gate layer 30 to the control gate layer.
[0042] Furthermore, step S4 is performed: a thermal annealing process is performed on the semiconductor structure after the diffusion plasma nitridation process. The thermal annealing process can promote uniform distribution of nitrogen in the first silicon oxide layer 41 and repair lattice defects of the first silicon oxide layer 41 .
[0043] During the thermal annealing process performed on the semiconductor structure after the diffusion plasma nitridation process, the process temperature is 1050° C. to 1150° C., and the process time is 10s to 30s.
[0044] Then, execute step S5: refer to Figure 5 , Figure 5 3 is a schematic diagram of a semiconductor structure after forming a second silicon oxide layer according to an embodiment of the present application, wherein a silicon nitride layer 42 is formed, and the silicon nitride layer 42 covers the first silicon oxide layer 41 .
[0045] In this embodiment, the thickness of the silicon nitride layer 42 is 20 angstroms to 60 angstroms.
[0046] The first silicon oxide layer 41 after nitridation and after lattice repair by thermal annealing has a stronger resistance to hot carrier degradation and can extend the life of the device.
[0047] Finally, execute step S6: continue to refer to Figure 5 , forming a second silicon oxide layer 43 , wherein the second silicon oxide layer 43 covers the silicon nitride layer 42 , wherein the first silicon oxide layer 41 , the silicon nitride layer 42 and the third silicon oxide layer 43 together constitute an ONO film layer 40 .
[0048] Preferably, the second silicon oxide layer 43 is formed by a CVD process.
[0049] In this embodiment, the thickness of the second silicon oxide layer 43 is 30 angstroms to 70 angstroms.
[0050] In the present application, a dense first silicon oxide layer is first generated by the ISSG process, and then nitrogen ions are infiltrated into the first silicon oxide layer by a diffusion plasma nitridation process, and finally the lattice of the first silicon oxide layer is repaired by a post-nitridation thermal annealing process. The dielectric constant of the first silicon oxide layer after nitridation is greater than that of the first silicon oxide layer in the traditional ONO film layer, which can effectively inhibit the diffusion of P-type ions (such as boron ions, phosphorus ions and other P-type ions) from the floating gate layer to the control gate layer, avoiding the leakage of the ONO film layer, which may cause the flash memory device to fail to read the stored information, thereby improving the reliability of the read operation of the flash memory device and improving the electrical performance of the device.
[0051] Furthermore, after forming the second silicon oxide layer 43 , the method for preparing the flash memory device may further include: forming a control gate layer (not shown), wherein the control gate layer covers the second silicon oxide layer 43 .
[0052] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.
Claims
1. A method for preparing a flash memory device, characterized in that: include: Providing a substrate, on which a gate oxide layer and a floating gate layer are sequentially formed; forming a first silicon oxide layer by adopting an ISSG process; Infiltrating a certain dose of nitrogen ions into the first silicon oxide layer through a diffusion plasma nitridation process; performing a thermal annealing process on the semiconductor structure after the diffusion plasma nitridation process; forming a silicon nitride layer, wherein the silicon nitride layer covers the first silicon oxide layer; A second silicon oxide layer is formed, wherein the second silicon oxide layer covers the silicon nitride layer.
2. The method for preparing a flash memory device according to claim 1, wherein: The thickness of the first silicon oxide layer is 40 angstroms to 60 angstroms.
3. The method for preparing a flash memory device according to claim 1, wherein: In the process of infiltrating nitrogen ions into the first silicon oxide layer through the diffusion plasma nitridation process, the dose of nitrogen ions infiltrated into the first silicon oxide layer is 1E5 atoms / cm 2 ~1E6 atoms / cm 2 .
4. The method for preparing a flash memory device according to claim 1, wherein: The radio frequency power of the diffusion plasma nitriding process is 1800W to 2000W.
5. The method for preparing a flash memory device according to claim 1, wherein: During the thermal annealing process performed on the semiconductor structure after the diffusion plasma nitridation process, the process temperature is 1050° C. to 1150° C., and the process time is 10s to 30s.
6. The method for preparing a flash memory device according to claim 1, wherein: The thickness of the silicon nitride layer is 20 angstroms to 60 angstroms.
7. The method for preparing a flash memory device according to claim 1, wherein: The second silicon oxide layer is formed by a CVD process.
8. The method for preparing a flash memory device according to claim 1, wherein: The thickness of the second silicon oxide layer is 30 angstroms to 70 angstroms.
9. The method for preparing a flash memory device according to claim 1, wherein: After forming the second silicon oxide layer, the method for preparing the flash memory device further includes: A control gate layer is formed, where the control gate layer covers the second silicon oxide layer.