Nonvolatile two-end memory cell and preparation method thereof

Abstract

The invention discloses a nonvolatile two-end memory cell and a preparation method thereof. The nonvolatile two-end storage unit comprises a lower electrode structure, a first electrode structure and a second electrode structure, the first lower electrode layer, the resistive layer and the upper electrode layer are located on the lower electrode structure and stacked from bottom to top; wherein the resistive random access layer is provided with a first interval part which penetrates through the resistive random access layer in the stacking direction, and the resistive random access layer is divided into a first area and a second area by the first interval part; the first lower electrode layer is provided with a second interval part which penetrates through the first lower electrode layer along the stacking direction; the first lower electrode layer is divided into a third region and a fourth region by the second spacing part. According to the invention, the service life and the reliability of the nonvolatile two-end storage unit are effectively improved.

Description

Technical Field

[0001] The present invention relates generally to the field of semiconductors and more particularly to a non-volatile two-terminal memory cell and a method for manufacturing the same. Background Art

[0002] Semiconductor memory devices can be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices lose stored data when power is interrupted, while nonvolatile memory devices do not lose stored data.

[0003] Non-volatile two-terminal memories (NOR Flash or NAND Flash) represent a recent innovation in integrated circuit technology. Unlike non-volatile three-terminal memories (such as NOR Flash or NAND Flash), which control the conductivity between two terminals by controlling a gate terminal, NOR Flash typically comprises a series-connected non-volatile two-terminal memory cell and a gate. Each NOR Flash cell includes a first electrode (e.g., an upper electrode TE), a second electrode (e.g., a lower electrode BE), and a resistive switching layer disposed between the first and second electrodes. NOR Flash applies different electrical signals to the two electrode terminals to control the conductivity state of the resistive switching layer, thereby creating different conductivity states between the two electrode terminals.

[0004] Various non-volatile two-terminal memory technologies (e.g., resistive switching memory, magnetoresistive memory, ferroelectric memory, phase change memory, and conductive bridge memory) have demonstrated compelling advantages over competing technologies in the semiconductor electronics industry. For example, RRAM (Resistive Random Access Memory) is currently used for data writing, reading, and storage. Its advantages include high density, low power consumption, and fast read / write speeds, making it a promising candidate for broad application in data storage.

[0005] However, current non-volatile two-terminal storage units have low reliability and short service life.

[0006] In view of this, there is an urgent need to provide a non-volatile two-terminal memory cell and a preparation method thereof, so as to effectively improve the service life and reliability of the non-volatile two-terminal memory cell. Summary of the Invention

[0007] In order to at least solve one or more of the technical problems mentioned above, the present application proposes a non-volatile two-terminal memory cell and a method for manufacturing the same in multiple aspects.

[0008] In a first aspect, the present application provides a non-volatile two-terminal memory cell, comprising: a lower electrode structure; a first lower electrode layer, a resistive switching layer, and an upper electrode layer stacked from bottom to top on the lower electrode structure; wherein the resistive switching layer has a first spacer extending through the resistive switching layer in a stacking direction, and the resistive switching layer is divided into a first region and a second region by the first spacer; the first lower electrode layer has a second spacer extending through the first lower electrode layer in a stacking direction; and the first lower electrode layer is divided into a third region and a fourth region by the second spacer.

[0009] In some embodiments, the first spacer and the second spacer are filled with a first insulating material.

[0010] In some embodiments, the non-volatile two-terminal memory cell further includes: a first conductive metal layer; the first conductive metal layer is located above the upper electrode layer, and the side of the first conductive metal layer close to the upper electrode layer includes a first protrusion, and the first protrusion is connected to the upper electrode layer.

[0011] In some embodiments, protective layers are provided on both sides of the upper electrode layer; the material of the protective layers is the second insulating material.

[0012] In some embodiments, a resistive switching layer is further provided between two side edges of the upper electrode layer and the protective layer.

[0013] In some embodiments, a center point of the first spacer and a center point of the second spacer are on the same straight line in the stacking direction.

[0014] In some embodiments, the upper electrode layer has a third spacer penetrating the upper electrode layer along the stacking direction; the upper electrode layer is divided into a fifth region and a sixth region by the third spacer.

[0015] In some embodiments, both sides of the fifth region and both sides of the sixth region are provided with a protective layer; the material of the protective layer is the second insulating material.

[0016] In some embodiments, a resistive switching layer is disposed between two side edges of the fifth region and the protective layer; and a resistive switching layer is disposed between two side edges of the sixth region and the protective layer.

[0017] In some embodiments, the non-volatile two-terminal memory cell further includes: a second conductive metal layer and a third conductive metal layer; the second conductive metal layer is located above the fifth region, and the second conductive metal layer includes a second protrusion on a side close to the fifth region, and the second protrusion is connected to the fifth region; the third conductive metal layer is located above the sixth region, and the third conductive metal layer includes a third protrusion on a side close to the sixth region, and the third protrusion is connected to the sixth region.

[0018] In some embodiments, the first spacer, the second spacer, and the third spacer are filled with a first insulating material.

[0019] In some embodiments, a center point of the first spacer, a center point of the second spacer, and a center point of the third spacer are on the same straight line in the stacking direction.

[0020] In some embodiments, the absolute difference between the length of the third region and the length of the fourth region is less than or equal to 1 / 4 of the length of the third region; and / or the absolute difference between the length of the third region and the length of the fourth region is less than or equal to 1 / 4 of the length of the fourth region.

[0021] In some embodiments, the lower electrode structure includes: a second lower electrode layer; a first contact area exists between the second lower electrode layer and the third region; a second contact area exists between the second lower electrode layer and the fourth region; the absolute difference between the length of the first contact area and the length of the second contact area is less than or equal to 1 / 10 of the length of the contact surface between the second lower electrode layer and the third region and the fourth region.

[0022] In a second aspect, the present application provides a method for preparing a non-volatile two-terminal memory cell, the method comprising: providing a lower electrode structure; depositing a first lower electrode layer and a resistive layer on the lower electrode structure in sequence; etching the resistive layer and the first lower electrode layer using a first photoresist layer having an opening as a mask to form a first spacer penetrating the resistive layer on the resistive layer and a second spacer penetrating the first lower electrode layer on the first lower electrode layer; depositing an insulating layer on the etched first structure and etching the insulating layer; wherein the etch stop layer is the resistive layer; depositing an upper electrode layer on the etched second structure and etching the upper electrode layer using the second photoresist layer having an opening as a mask; depositing a protective layer on the etched third structure and etching the deposited fourth structure using the upper electrode layer as an etch stop layer; depositing an insulating layer on the etched fifth structure and etching the sixth structure after the insulating layer is deposited using the third photoresist layer having an opening as a mask and then depositing a first conductive metal layer to obtain the non-volatile two-terminal memory cell.

[0023] In some embodiments, before depositing a protection layer on the etched third structure, the method further includes: depositing a resistive switching layer on the etched third structure.

[0024] In a third aspect, the present application provides a method for preparing a non-volatile two-terminal memory cell, the method comprising: providing a lower electrode structure; depositing a first lower electrode layer, a resistive layer, and an upper electrode layer on the lower electrode structure in sequence; etching the upper electrode layer and the resistive layer using a fourth photoresist layer having an opening as a mask and the first lower electrode layer as an etch stop layer; depositing a protective layer on the etched seventh structure, and etching the deposited eighth structure; wherein the etch stop layer in the hollow area of ​​the eighth structure is the lower electrode structure, and the etch stop layer in the non-hollow area of ​​the eighth structure is the upper electrode layer; forming a first spacer penetrating the resistive layer on the resistive layer; forming a second spacer penetrating the first lower electrode layer on the first lower electrode layer; forming a third spacer penetrating the upper electrode layer on the upper electrode layer; depositing an insulating layer on the etched ninth structure, and etching the tenth structure after the insulating layer is deposited using a fifth photoresist layer having an opening as a mask, depositing a second conductive metal layer and a third conductive metal layer in the etched area to obtain the non-volatile two-terminal memory cell.

[0025] In some embodiments, before depositing a protection layer on the etched seventh structure, the method further includes: depositing a resistive switching layer on the etched seventh structure.

[0026] Through the non-volatile two-terminal memory cell and its fabrication method provided above, the embodiments of the present application form two parallel memory structures on the same lower electrode structure. The two memory structures serve as backups for each other. When one memory structure breaks down, the other memory structure can still operate normally, effectively increasing the service life and reliability of the non-volatile two-terminal memory cell. Furthermore, when voltage is applied to the two electrodes of the non-volatile two-terminal memory cell comprising the two parallel memory structures, the probability of successful forming is increased, making it easier to achieve a stable forming state, thereby improving the electrical performance and stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0028] Figure 1 An example diagram of a non-volatile two-terminal memory cell according to some embodiments of the present application is shown;

[0029] Figure 2 An exemplary diagram of a non-volatile two-terminal storage unit according to some other embodiments of the present application is shown;

[0030] Figure 3 An exemplary flow chart illustrating a method for preparing a non-volatile two-terminal memory cell according to some embodiments of the present application is shown;

[0031] Figures 4A-4K Schematic diagrams of semiconductor cross-sectional structures of some embodiments of the present application are shown;

[0032] Figure 5 An exemplary flow chart showing a method for preparing a non-volatile two-terminal memory cell according to other embodiments of the present application is provided;

[0033] Figures 6A-6F Schematic diagrams of semiconductor cross-sectional structures of other embodiments of the present application are shown. Description of the drawings:

[0035] Lower electrode structure 110; first lower electrode layer 120; resistive switching layer 130;

[0036] Upper electrode layer 140; first spacer 1301; first region 1302;

[0037] Second area 1303; second spacer 1201; third area 1202;

[0038] Fourth region 1203; first conductive metal layer 150; first protrusion 1501;

[0039] Protective layer 160; third spacer 1401; fifth region 1402;

[0040] Sixth region 1403; second conductive metal layer 170; second protrusion 1701;

[0041] A third conductive metal layer 180 ; and a third protrusion 1801 . DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0043] It should be understood that the terms "include" and "comprising" used in the description and claims of this application indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0044] It should also be understood that the terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this specification and claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" as used in this specification and claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0045] As used in this specification and claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0046] The specific implementation of the present application will be described in detail below with reference to the accompanying drawings.

[0047] Traditional non-volatile two-terminal memory cells consist of a memory structure consisting of a connected top electrode (TE), a resistive switching layer (SL), and a bottom electrode (BE). If this structure breaks down during practical use, the non-volatile two-terminal memory cell will become inoperable, severely impacting its reliability and service life.

[0048] In view of this, embodiments of the present application provide a non-volatile two-terminal memory unit to effectively improve the service life and reliability of the non-volatile two-terminal memory unit.

[0049] Figure 1 An exemplary diagram of a non-volatile two-terminal memory cell 100 according to some embodiments of the present application is shown.

[0050] like Figure 1 As shown, the non-volatile two-terminal memory cell 100 includes: a lower electrode structure 110; a first lower electrode layer 120, a resistive layer 130 and an upper electrode layer 140 stacked from bottom to top on the lower electrode structure 110; wherein the resistive layer 130 has a first spacer 1301 that penetrates the resistive layer 130 along the stacking direction, and the resistive layer 130 is divided into a first region 1302 and a second region 1303 by the first spacer 1301; the first lower electrode layer 120 has a second spacer 1201 that penetrates the first lower electrode layer 120 along the stacking direction; the first lower electrode layer 120 is divided into a third region 1202 and a fourth region 1203 by the second spacer 1201.

[0051] For example, in an embodiment of the present application, the above-mentioned non-volatile two-terminal memory unit 100 serves as a data storage unit of a non-volatile two-terminal memory, which can be any one of a resistive random access memory (RRAM) unit, a ferroelectric random access memory (FeRAM) unit, a phase change random access memory (PCRAM) unit, and a magnetoresistive random access memory (MRAM) unit.

[0052] In an embodiment of the present application, the lower electrode structure 110 serves as the basic support structure of the entire non-volatile two-terminal memory cell 100, and is used to carry the various functional layers stacked subsequently. In some embodiments, the lower electrode structure 110 includes a second lower electrode layer, a bottom conductive interconnect layer, and an insulating layer, etc. Among them, the material of the bottom conductive interconnect layer can be a conductive metal material (for example, copper, etc.). The material of the second lower electrode layer can be a metal or a metal compound, for example, tungsten (W), titanium (Ti), titanium nitride (TiN), etc., and this embodiment of the present application does not limit this. In an embodiment of the present application, the lower electrode structure 110 can be prepared by processes such as thin film deposition, photolithography, etching, and chemical mechanical polishing.

[0053] The first lower electrode layer 120 is located on the lower electrode structure 110 and is used to connect the lower electrode structure 110 and the resistive layer 130, providing charge conduction. Its material may include one or a combination of tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), iridium (Ir), and platinum (Pt). Its material may be the same as or different from that of the second lower electrode layer, and this embodiment of the present application does not specifically limit this.

[0054] In the embodiment of the present application, the first lower electrode layer 120 has a second spacer 1201 extending through the first lower electrode layer 120 along the stacking direction (perpendicular to the direction of the layers in the figure). The second spacer 1201 can be formed by processes such as photolithography and etching. In the embodiment of the present application, the second spacer 1201 divides the first lower electrode layer 120 into a third region 1202 and a fourth region 1203. The third region 1202 and the fourth region 1203 are electrically isolated by the second spacer 1201, thereby enabling independent control of the third region 1202 and the fourth region 1203, thereby providing a lower electrode foundation for the regional division of the resistive switching layer 130.

[0055] The resistive switching layer 130 is a key component in achieving the resistive switching function. Applying a voltage changes the resistance state of the resistive switching layer 130 (high resistance state or low resistance state) to enable data storage. In the present embodiment, the material of the resistive switching layer 130 can be a transition metal oxide, such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), etc., but this embodiment is not specifically limited to this.

[0056] In the embodiment of the present application, the resistive layer 130 has a first spacer 1301 that extends through the resistive layer 130 along the stacking direction. This spacer 1301 can also be formed through photolithography and etching processes. The first spacer 1301 divides the resistive layer 130 into a first region 1302 and a second region 1303. The first region 1302 and the second region 1303 are electrically isolated by the first spacer 1301, allowing independent control of the first region 1302 and the second region 1303. Furthermore, the first region 1302 and the second region 1303 can form different resistance states under the action of an electric field, thereby achieving data storage.

[0057] It should be noted that the first spacer 1301 and the second spacer 1201 may be formed by a single photolithography process or by two photolithography processes, which is not specifically limited in the present embodiment. Figure 1 The first spacer 1301 and the second spacer 1201 shown in FIG. 1 are formed by a single photolithography process.

[0058] In the embodiment of the present application, the lengths of the first spacer 1301 and the second spacer 1201 are the same. The specific lengths can be set according to actual process requirements, and the embodiment of the present application does not specifically limit this.

[0059] The top electrode layer 140, located above the resistive layer 130, serves as the top conductive structure of the non-volatile two-terminal memory cell 100. It is primarily used to connect to external circuits and to the resistive layer to form a conductive path. Its material may include tantalum (Ta) or its nitride, titanium (Ti) or its nitride, tungsten (W) or its nitride, ruthenium (Ru), iridium (Ir), and platinum (Pt), or a combination thereof.

[0060] In the embodiment of the present application, the resistive switching layer 130 is divided into a first region 1302 and a second region 1303 by a first spacer 1301, and the first lower electrode structure 110 is divided into a third region 1202 and a fourth region 1203 by a second spacer 1201. This results in two parallel storage structures being formed on the same bottom electrode (i.e., the lower electrode structure 110): a storage structure consisting of the upper electrode layer 140, the first region 1302, and the third region 1202 (referred to as the first storage structure for ease of description), and a storage structure consisting of the upper electrode layer 140, the second region 1303, and the fourth region 1203 (referred to as the second storage structure for ease of description). Consequently, when one of the storage structures (e.g., the first storage structure) breaks down, the other storage structure (the second storage structure) can still operate normally, effectively increasing the service life and reliability of the non-volatile two-terminal storage cell. At the same time, when voltage is applied to the two electrodes of the non-volatile two-terminal memory cell including the two parallel memory structures, the probability of successful forming can be increased, and a stable forming state can be formed more easily, thereby improving the electrical performance and stability of the device.

[0061] As an optional embodiment of the present application, Figure 1 As shown, the first spacer 1301 and the second spacer 1201 are filled with the first insulating material.

[0062] For example, the first insulating material may be silicon dioxide (SiO2), silicon nitride (SiN), etc., which is not specifically limited in the embodiments of the present application. The first spacer 1301 and the second spacer 1201 are filled with the first insulating material, so that the first region 1302 and the second region 1303 are completely isolated by the first insulating material, and the third region 1202 and the fourth region 1203 are also completely isolated by the first insulating material, ensuring electrical isolation of adjacent regions, preventing undesirable conduction of charges at the positions of the first spacer 1301 and the second spacer 1201, ensuring independence between the regions, and maintaining the stable working state and information storage accuracy of the non-volatile two-terminal storage unit 100. At the same time, the first insulating material is also used to support the interlayer and each region to prevent deformation of the device.

[0063] During the specific filling, chemical vapor deposition (CVD) can be used for filling, and the first insulating material can be evenly deposited on the surface of the first spacer 1301, the second spacer 1201 and the entire structure, and then the excess first insulating material on the surface is removed by processes such as chemical mechanical polishing (CMP), so that the first insulating material is only filled in the first spacer 1301 and the second spacer 1201, preventing unnecessary electrical short circuits between the first area 1302 and the second area 1303, and the third area 1202 and the fourth area 1203, thereby improving the structural stability and reliability of the entire non-volatile two-terminal storage unit 100, and avoiding problems such as structural looseness or unstable electrical performance due to the presence of the spacer during subsequent processes or use.

[0064] As an optional embodiment of the present application, Figure 1 As shown, the non-volatile two-terminal memory cell 100 further includes: a first conductive metal layer 150; the first conductive metal layer 150 is located above the upper electrode layer 140, and the side of the first conductive metal layer 150 close to the upper electrode layer 140 includes a first protrusion 1501, and the first protrusion 1501 is connected to the upper electrode layer 140.

[0065] For example, in the embodiment of the present application, the first conductive metal layer 150 is an auxiliary conductive layer located above the upper electrode layer 140. Its material is generally selected from metals with excellent electrical conductivity, such as copper, gold, and silver. In the embodiment of the present application, the first conductive metal layer 150 can be deposited above the upper electrode layer 140 through a process such as physical vapor deposition (PVD) or electroplating. During the deposition process, the deposition thickness and uniformity need to be precisely controlled to ensure that the first conductive metal layer 150 has good electrical conductivity and mechanical adhesion.

[0066] In the embodiment of the present application, the first conductive metal layer 150 includes a first protrusion 1501 on a side close to the upper electrode layer 140, which is connected to the upper electrode layer 140. The first protrusion 1501 is made of the same material as the first conductive metal layer 150 and can be formed together with the first conductive metal layer 150. For details, please refer to the preparation process in the following embodiment, which will not be described here.

[0067] Based on this structure, when the non-volatile two-terminal memory cell 100 is in operation, an operating voltage can be applied to both electrodes. At this point, the first and second storage structures are simultaneously conductive, and the first storage structure is in an operational state. If the first storage structure breaks down, the second storage structure can continue to operate without any additional operation. In this case, the first and second storage structures can also support parallel data storage operations.

[0068] As an optional embodiment of the present application, Figure 1 As shown, protective layers 160 are provided on both sides of the upper electrode layer 140 ; ​​the material of the protective layer 160 is the second insulating material.

[0069] For example, in an embodiment of the present application, the above-mentioned second insulating material can be silicon nitride (SiN), silicon dioxide (SiO2), etc. The second insulating material here can be the same as the first insulating material or different, and the embodiment of the present application does not make specific limitations on this.

[0070] In this embodiment, protective layers 160 are provided on both sides of the top electrode layer 140 to protect the edges of the top electrode layer from interference from the environment and adjacent structures, thereby improving device isolation. Furthermore, a resistive switching layer 130 is provided between the two sides of the top electrode layer 140 and the protective layers 160. This resistive switching layer 130 forms a buffered transition between the insulating protective layer 160 and the conductive electrode layer, preventing breakdown caused by electric field concentration at the electrode edges.

[0071] As an optional embodiment of the present application, the center point of the first spacer 1301 and the center point of the second spacer 1201 are on the same straight line in the stacking direction.

[0072] For example, the center point of the first spacer 1301 and the center point of the second spacer 1201 are in the stacking direction (ie Figure 1 The first and second spacers 1301 and 1201 are aligned in a straight line (in a direction perpendicular to the surface of each layer), meaning the vertical projections of the center points of the first and second spacers 1301 coincide with each other. Precise alignment can be achieved through photolithography. This design ensures structural symmetry between the first lower electrode layer 120 and the resistive switching layer 130, evenly distributing current between the layers and reducing resistance control deviations caused by structural offsets.

[0073] Figure 2 illustrative diagrams of non-volatile two-terminal memory cells 200 according to some other embodiments of the present application are shown.

[0074] As an optional embodiment of the present application, Figure 2 As shown, the upper electrode layer 140 has a third spacer 1401 penetrating the upper electrode layer 140 along the stacking direction; the upper electrode layer 140 is divided into a fifth region 1402 and a sixth region 1403 by the third spacer 1401 .

[0075] Illustratively, in an embodiment of the present application, the upper electrode layer 140 has a third spacer 1401 that penetrates the upper electrode layer 140 along the stacking direction. The third spacer 1401 divides the upper electrode layer 140 into a fifth region 1402 and a sixth region 1403. The fifth region 1402 and the sixth region 1403 can be electrically isolated by the third spacer 1401, so that the fifth region 1402 and the sixth region 1403 can be independently controlled.

[0076] Based on this, in the embodiment of the present application, two parallel storage structures are formed on the same bottom electrode (i.e., the lower electrode structure 110). These are a storage structure consisting of the fifth region 1402, the first region 1302, and the third region 1202 (for ease of description, referred to as the third storage structure), and a storage structure consisting of the sixth region 1403, the second region 1303, and the fourth region 1203 (for ease of description, referred to as the fourth storage structure). Consequently, when one of the storage structures (e.g., the third storage structure) breaks down, the other storage structure (the fourth storage structure) can still operate normally, effectively increasing the service life and reliability of the non-volatile two-terminal storage cell.

[0077] It should be noted that in the embodiment of the present application, the lengths of the first spacer 1301, the second spacer 1201 and the third spacer 1401 are the same. The specific lengths can be set according to actual process requirements, and the embodiment of the present application does not make any specific restrictions on this.

[0078] As an optional embodiment of the present application, Figure 2 As shown, on the premise that the first spacer 1301 and the second spacer 1201 are filled with the first insulating material, the third spacer 1401 is also filled with the first insulating material.

[0079] Exemplarily, the first spacer 1301, the second spacer 1201, and the third spacer 1401 are filled with a first insulating material, completely isolating the first region 1302 from the second region 1303, the third region 1202 from the fourth region 1203, and the fifth region 1402 from the sixth region 1403. This ensures electrical isolation between the first region 1302 and the second region 1303, the third region 1202 from the fourth region 1203, and the fifth region 1402 from the sixth region 1403, preventing undesirable charge conduction at the locations of the first spacer 1301, the second spacer 1201, and the third spacer 1401. This ensures the independence of the regions and maintains the stable operation and information storage accuracy of the non-volatile two-terminal memory cell 100. The first insulating material also serves to support the interlayers and each region, preventing device deformation.

[0080] During the specific filling, chemical vapor deposition (CVD) can be used for filling, and the first insulating material is evenly deposited on the surface of the first spacer 1301, the second spacer 1201, the third spacer 1401 and the entire structure, and then the excess first insulating material on the surface is removed by processes such as chemical mechanical polishing (CMP), so that the insulating material is only filled in the first spacer 1301, the second spacer 1201 and the third spacer 1401, thereby preventing unnecessary electrical short circuits between the first area 1302 and the second area 1303, between the third area 1202 and the fourth area 1203, and between the fifth area 1402 and the sixth area 1403, thereby improving the structural stability and reliability of the entire non-volatile two-terminal storage unit 100, and avoiding problems such as structural looseness or unstable electrical performance due to the presence of the spacer during subsequent processes or use.

[0081] As an optional embodiment of the present application, Figure 2 As shown, both sides of the fifth region 1402 and both sides of the sixth region 1403 are provided with a protective layer 160 ; the material of the protective layer 160 is the second insulating material.

[0082] For example, in the embodiment of the present application, in order to protect the sides of the fifth region 1402 and the sixth region 1403 to avoid damage or adverse conditions such as short circuits during subsequent processes and use, and to ensure the stability and normal functions of the two regions of the upper electrode layer 140, both sides of the fifth region 1402 and both sides of the sixth region 1403 are provided with a protective layer 160. As for the material of the protective layer 160 (i.e., the second insulating material), please refer to the description of the above embodiment and will not be repeated here.

[0083] In addition, a resistive layer 130 is arranged between the two sides of the fifth region 1402 and the protective layer 160; a resistive layer 130 is arranged between the two sides of the sixth region 1403 and the protective layer 160. The resistive layer 130 forms a buffer transition between the insulating layer and the conductive layer, avoiding the breakdown problem caused by the electric field concentration at the electrode edge.

[0084] As an optional embodiment of the present application, Figure 2 As shown, the non-volatile two-terminal memory cell 200 further includes: a second conductive metal layer 170 and a third conductive metal layer 180; the second conductive metal layer 170 is located above the fifth region 1402, and the side of the second conductive metal layer 170 close to the fifth region 1402 includes a second protrusion 1701, and the second protrusion 1701 is connected to the fifth region 1402; the third conductive metal layer 180 is located above the sixth region 1403, and the side of the third conductive metal layer 180 close to the sixth region 1403 includes a third protrusion 1801, and the third protrusion 1801 is connected to the sixth region 1403.

[0085] For example, in an embodiment of the present application, the second conductive metal layer 170 and the third conductive metal layer 180 are auxiliary conductive layers located above the fifth region 1402 and the sixth region 1403, respectively. Through the protrusions on the side close to the corresponding regions (i.e., the second protrusion 1701 and the third protrusion 1801), the fifth region 1402 and the sixth region 1403 are respectively connected, thereby realizing independent electrical connection between the external circuit and different regions of the upper electrode layer 140, which facilitates the control and signal reading of the fifth region 1402 and the sixth region 1403, respectively.

[0086] In the embodiment of the present application, the material of the second conductive metal layer 170 and the material of the third conductive metal layer 180 are generally selected from metals with excellent conductive properties, such as copper, gold, silver, etc., and the embodiment of the present application does not make any specific limitations on this.

[0087] Based on the above structure, in an embodiment of the present application, the third storage structure and the fourth storage structure can be controlled separately, that is, working voltages are applied to the third storage structure and the fourth storage structure respectively. As an optional embodiment of the present application, when the non-volatile two-terminal storage unit 200 is working, working electrodes can be applied to the two electrodes of one of the storage structures (for example, the third storage structure) so that the third storage structure is in a working state, and a lower standby voltage is applied to the other storage structure (i.e., the fourth storage structure) so that the fourth storage structure is in a standby state as a backup for the third storage structure. When the third storage structure breaks down, a working voltage is applied to the fourth storage structure to switch to the fourth storage structure for operation. As another optional embodiment of the present application, when the third storage structure is in a working state, the fourth storage structure can also be in a working state. When the third storage structure breaks down, no additional operation is required, and the fourth storage structure directly performs the operation.

[0088] Furthermore, when the third storage structure and the fourth storage structure are both in the working state, the third storage structure and the fourth storage structure can support parallel data storage operations.

[0089] As an optional embodiment of the present application, the center point of the first spacer 1301 , the center point of the second spacer 1201 , and the center point of the third spacer 1401 are on the same straight line in the stacking direction.

[0090] For example, the center point of the first spacer 1301, the center point of the second spacer 1201, and the center point of the third spacer 1401 in the stacking direction (ie Figure 2 The first, second, and third spacers 1301, 1201, and 1401 are aligned in a straight line (in a direction perpendicular to the surface of each layer). This means that the vertical projections of the center points of the first, second, and third spacers 1301, 1201, and 1401 coincide. Precise alignment can be achieved through photolithography. This design ensures structural symmetry among the first lower electrode layer 120, the resistive switching layer 130, and the upper electrode layer, evenly distributing current between the layers and reducing resistance control deviations caused by structural offsets.

[0091] As an optional embodiment of the present application, the absolute difference between the length of the third region 1202 and the length of the fourth region 1203 is less than or equal to 1 / 4 of the length of the third region 1202; and / or the absolute difference between the length of the third region 1202 and the length of the fourth region 1203 is less than or equal to 1 / 4 of the length of the fourth region 1203.

[0092] For example, in the embodiment of the present application, the length of the third region 1202 and the length of the fourth region 1203 refer to the length of the third region 1202 and the fourth region 1203 perpendicular to the stacking direction ( Figure 1 as well as Figure 2In the embodiment of the present application, by setting the absolute difference between the length of the third region 1202 and the length of the fourth region 1203 to be less than or equal to 1 / 4 of the length of the third region 1202, and / or less than or equal to 1 / 4 of the length of the fourth region 1203, the difference in size between the third region 1202 and the fourth region 1203 is avoided, thereby avoiding the situation where the storage structure composed of the two regions has a large difference, thereby ensuring that the performance of the two storage structures is relatively consistent. If the difference between the two storage structures is too great, it will make it difficult for them to operate under the same conduction voltage Vform, set voltage Vset or reset voltage Vreset conditions in a parallel state, affecting their stability.

[0093] As an optional embodiment of the present application, Figure 1 Or as Figure 2 As shown, the lower electrode structure 110 includes: a second lower electrode layer; a first contact area exists between the second lower electrode layer and the third region 1202; a second contact area exists between the second lower electrode layer and the fourth region 1203; the absolute difference between the length of the first contact area and the length of the second contact area is less than or equal to 1 / 10 of the length of the contact surface of the second lower electrode layer with the third region 1202 and the fourth region 1203.

[0094] For example, in the embodiment of the present application, the length of the first contact region and the length of the second contact region refer to the length of the first contact region and the second contact region perpendicular to the stacking direction ( Figure 1 as well as Figure 2 In the embodiment of the present application, by setting the absolute difference between the length of the first contact region and the length of the second contact region to be less than or equal to 1 / 10 of the length of the contact surface between the second lower electrode layer and the third region 1202 and the fourth region 1203, the contact area between the lower electrode structure 110 and the first lower electrode layer 120 is ensured to be uniform, the difference in contact resistance between the two storage structures is reduced, and the electrical performance consistency of the two storage structures is improved.

[0095] Below Figure 1 The preparation method of the nonvolatile two-terminal memory cell 100 is described as follows:

[0096] Figure 3 A flowchart illustrating a method 300 for preparing a non-volatile two-terminal memory cell according to some embodiments of the present application is shown.

[0097] like Figure 3As shown, the method 300 for preparing a non-volatile two-terminal memory cell includes: step S310: providing a lower electrode structure; step S320: sequentially depositing a first lower electrode layer and a resistive switching layer on the lower electrode structure; step S330: using a first photoresist layer having an opening as a mask, etching the resistive switching layer and the first lower electrode layer to form a first spacer penetrating the resistive switching layer on the resistive switching layer and a second spacer penetrating the first lower electrode layer on the first lower electrode layer; step S340: depositing an insulating layer on the etched first structure and etching the insulating layer; wherein, The etching stop layer is a resistive layer; step S350: depositing an upper electrode layer on the etched second structure, and etching the upper electrode layer using the second photoresist layer with an opening as a mask; step S360: depositing a protective layer on the etched third structure, and etching the deposited fourth structure using the upper electrode layer as an etching stop layer; step S370: depositing an insulating layer on the etched fifth structure, and using the third photoresist layer with an opening as a mask, etching the sixth structure after the insulating layer is deposited, and then depositing the first conductive metal layer to obtain a non-volatile two-terminal storage unit.

[0098] based on Figure 3 The process of the preparation method 300 of the non-volatile two-terminal memory cell is as follows: Figures 4A-4K The schematic diagram of the semiconductor cross-sectional structure is shown, and an exemplary process flow of a method 300 for preparing a non-volatile two-terminal memory cell according to some embodiments of the present application is described in detail.

[0099] like Figure 4A As shown, in step S310, a lower electrode structure 110 is provided. The lower electrode structure 110 can be prepared by a semiconductor process (for example, thin film deposition, photolithography, etching, chemical mechanical polishing, etc.). In an embodiment of the present application, the lower electrode structure 110 may include a second lower electrode layer, a bottom conductive interconnect layer, and an insulating layer, etc. The material of the bottom conductive interconnect layer can be a conductive material (for example, copper). The material of the second lower electrode layer can be a metal or a metal compound, for example, tungsten (W), titanium (Ti), titanium nitride (TiN), etc., which is not limited in the embodiment of the present application.

[0100] like Figure 4BAs shown, in step S320, the first lower electrode layer 120 and the resistive layer 130 are sequentially deposited on the lower electrode structure 110. Specifically, the first lower electrode layer 120 can be first deposited on the lower electrode structure 110 by physical vapor deposition (PVD) or chemical vapor deposition (CVD), and then the resistive layer 130 is continuously deposited on the first lower electrode layer 120. Among them, the deposition thickness of the first lower electrode layer 120 and the deposition thickness of the resistive layer 130 can be set according to actual process requirements, and the embodiment of the present application does not specifically limit this. In addition, the above-mentioned physical vapor deposition (PVD) or chemical vapor deposition (CVD) are conventional deposition techniques, and the embodiments of the present application will not be repeated.

[0101] like Figure 4C As shown, the first photoresist layer in step S330 may include at least one opening, and the position of the opening corresponds to the area to be etched. In the embodiment of the present application, the first photoresist layer can be formed by photolithography spin coating photoresist and exposure and development process. Specifically, the following steps may be included: (1) Photoresist coating: Fix the semiconductor device (i.e., the structure with the first lower electrode layer 120 and the resistive layer 130 deposited) on a spin coater (spin (1) Soft bake: After the photoresist is applied, the semiconductor device is placed in nitrogen and heated to about 80 degrees Celsius to volatilize and remove the organic solvent in the film; (2) Exposure: The pattern on the mask is transferred to the above-mentioned film. Specifically, a stepper is used during exposure to project a light source onto the surface of the semiconductor device through a plurality of lens systems. After the exposure of one wafer area is completed, the stepper moves to the next wafer area for exposure; (3) Development: The exposed photoresist undergoes a chemical reaction in the developer. The photoresist in the non-exposed area is retained, while the photoresist in the exposed area is dissolved. The photoresist pattern left after development will be used as a mask in the subsequent etching and ion implantation processes, thus obtaining the above-mentioned first photoresist layer.

[0102] like Figure 4D As shown, in an embodiment of the present application, the first photoresist layer with an opening is used as a mask and the lower electrode structure 110 is used as an etching stop layer to etch the resistive layer 130 and the first lower electrode layer 120 (for example, wet etching, dry etching, etc.), and the resistive layer 130 and the first lower electrode layer 120 below the opening of the first photoresist layer are removed to form a first spacer 1301 penetrating the resistive layer 130 on the resistive layer 130 and a second spacer 1201 penetrating the first lower electrode layer 120 on the first lower electrode layer 120, thereby obtaining a first structure.

[0103] It should be noted that Figure 4DThe first spacer 1301 and the second spacer 1201 shown are only used as an example, mainly for marking the approximate position of the spacer. In actual production, the first area 1302 and the second area 1303, as well as the third area 1202 and the fourth area 1203 are filled with the first insulating material.

[0104] like Figure 4E-4F As shown, in the above step S340, an insulating layer is first deposited on the etched first structure, filling the first spacer 1301 and the second spacer 1201 and covering the entire surface, thereby completing the filling of the first spacer 1301 and the second spacer 1201. Then, using the resistive layer 130 as an etch stop layer, the insulating layer is etched using a mechanochemical polishing process to ensure that the insulating material in the spacer is flush with the surface of the resistive layer 130, thereby obtaining the second structure.

[0105] like Figure 4G As shown, in step S350, a conductive metal is first deposited on the etched second structure by physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form an upper electrode layer 140. Then, the upper electrode layer 140 is etched using the second photoresist layer with the opening as a mask and the resistive layer 130 as an etch stop layer to form a third structure (i.e., Figure 4H The second photoresist layer is formed in the same manner as the first photoresist layer, and will not be described in detail herein. The pattern of the upper electrode layer 140 is defined by photolithography, and the excess portion is removed by etching, leaving the upper electrode layer 140 of the target shape.

[0106] like Figure 4I As shown, in step S360, a protective layer 160 is deposited on the etched third structure. Optionally, before depositing the protective layer 160, a resistive switching layer 130 (the same material as the main resistive switching layer 130) is first deposited on the etched third structure, and then the protective layer 160 is deposited on the deposited resistive switching layer 130. Finally, the upper electrode layer 140 is used as an etching stop layer to etch the deposited fourth structure to obtain a fifth structure (i.e., Figure 4J The etching method is the same as the etching method mentioned above and will not be described in detail here. In the embodiment of the present application, the protective layer 160 is retained only on the side of the upper electrode layer 140 through the etching process to form an isolation structure.

[0107] like Figure 4KAs shown, in step S370, an insulating layer is deposited on the etched fifth structure. The material of the insulating layer here is the same as the material of the above-mentioned insulating layer. In the embodiment of the present application, the sixth structure after the insulating layer is deposited is etched using the third photoresist layer with an opening as a mask to form a through hole penetrating the insulating layer in the insulating layer, and then the first conductive metal layer 150 is deposited to fill the through hole and cover the surface of the structure to form a first protrusion 1501 at the through hole position, thereby obtaining a non-volatile two-terminal memory cell (i.e. Figure 1 The structure shown in FIG1 is shown in FIG2 , and the entire non-volatile two-terminal memory cell 100 is prepared. The method for forming the third photoresist layer is consistent with the method for forming the first photoresist layer, and will not be repeated here.

[0108] Below Figure 2 The preparation method of the nonvolatile two-terminal memory cell 200 is described as follows:

[0109] Figure 5 A flowchart illustrating a method 500 for fabricating a non-volatile two-terminal memory cell according to some embodiments of the present application is shown.

[0110] like Figure 5 As shown, the preparation method 500 of the non-volatile two-terminal memory cell includes: step S510: providing a lower electrode structure; step S520: depositing a first lower electrode layer, a resistive layer, and an upper electrode layer on the lower electrode structure in sequence; step S530: etching the upper electrode layer and the resistive layer using a fourth photoresist layer having an opening as a mask and the first lower electrode layer as an etch stop layer; step S540: depositing a protective layer on the etched seventh structure and etching the deposited eighth structure; wherein the etch stop layer of the hollowed area of ​​the eighth structure is The lower electrode structure, the etching stop layer in the non-hollow area of ​​the eighth structure is the upper electrode layer; a first spacer penetrating the resistive layer is formed on the resistive layer; a second spacer penetrating the first lower electrode layer is formed on the first lower electrode layer; a third spacer penetrating the upper electrode layer is formed on the upper electrode layer; step S550: depositing an insulating layer on the etched ninth structure, and using the fifth photoresist layer with an opening as a mask, etching the tenth structure after the deposition of the insulating layer, depositing a second conductive metal layer and a third conductive metal layer in the etched area, and obtaining a non-volatile two-terminal storage unit.

[0111] based on Figure 5 The process of preparing the non-volatile two-terminal storage unit is as follows: Figure 4A as well as Figures 6A-6F The schematic diagram of the semiconductor cross-sectional structure is shown, and an exemplary process flow of a method 500 for preparing a non-volatile two-terminal memory cell 200 according to some embodiments of the present application is described in detail.

[0112] like Figure 4AAs shown, in step S510, a lower electrode structure 110 is provided. The composition and preparation process of the lower electrode structure 110 are the same as those of the lower electrode structure 110 in the above step S310. The description of the embodiment of the above step S310 can be referred to and will not be repeated here.

[0113] like Figure 6A As shown, in step S520, a first lower electrode layer 120, a resistive switching layer 130, and an upper electrode layer 140 are sequentially deposited on the lower electrode structure 110. Specifically, physical vapor deposition (PVD) or chemical vapor deposition (CVD) can be used to first deposit the first lower electrode layer 120 on the lower electrode structure 110, then the resistive switching layer 130 is deposited on the first lower electrode layer 120, and finally the upper electrode layer 140 is deposited on the resistive switching layer 130. The deposition thickness of the first lower electrode layer 120, the deposition thickness of the resistive switching layer 130, and the deposition thickness of the upper electrode layer 140 can all be set according to actual process requirements, and are not specifically limited in this embodiment of the present application.

[0114] like Figure 6B As shown, the fourth photoresist layer in step S530 may include at least one opening, the opening corresponding to the area to be etched. In the embodiment of the present application, the method for forming the fourth photoresist layer is the same as the method for forming the first photoresist layer described above. Please refer to the description of the method for forming the first photoresist layer described above, and will not be repeated here.

[0115] like Figure 6C As shown, in an embodiment of the present application, the fourth photoresist layer with an opening is used as a mask and the first lower electrode layer 120 is used as an etching stop layer, and the upper electrode layer 140 and the resistive layer 130 are first etched (for example, wet etching, dry etching, etc.), and the upper electrode layer 140 and the resistive layer 130 below the opening of the fourth photoresist layer are removed to form a first spacer 1301 penetrating the resistive layer 130 on the resistive layer 130 and a third spacer 1401 penetrating the upper electrode layer 140 on the upper electrode layer 140, thereby obtaining a seventh structure.

[0116] In an embodiment of the present application, the upper electrode layer 140 and the resistive layer 130 are etched first without etching the first lower electrode layer 120, so as to avoid the metal of the first lower electrode layer 120 splashing onto the sides of the upper electrode layer 140 and the resistive layer 130 when etching the first lower electrode layer 120, thereby affecting the device performance. Therefore, in an embodiment of the present application, before etching the first lower electrode layer 120, a protective layer 160 is first formed on the sides of the upper electrode layer 140 and the resistive layer 130. For details, please refer to the description of the embodiment below.

[0117] like Figure 6DAs shown, in step S540, a protective layer 160 is deposited on the etched seventh structure. Optionally, before depositing the protective layer 160, a resistive switching layer 130 (the same material as the main resistive switching layer 130) is first deposited on the etched seventh structure. Then, the protective layer 160 is deposited on the deposited resistive switching layer 130 to form a protective layer 160 on both sides of the resistive switching layer 130 and on both sides of the first upper electrode to prevent the metal of the first lower electrode layer 120 from sputtering to the upper electrode layer 140 and the resistive switching layer 130 when etching the first lower electrode layer 120. Finally, for the eighth structure after deposition, its hollow area (i.e. Figure 6D The etch stop layer of the lower electrode structure 110 in the non-hollowed area is the upper electrode layer 140. The eighth structure is etched to form a first spacer 1301 penetrating the resistive layer 130 on the resistive layer 130; a second spacer 1201 penetrating the first lower electrode layer 120 is formed on the first lower electrode layer 120; and a third spacer 1401 penetrating the upper electrode layer 140 is formed on the upper electrode layer 140, thereby forming a ninth structure ( Figure 6E structure shown).

[0118] It should be noted that Figure 6E The first spacer 1301, the second spacer 1201 and the third spacer 1401 shown are only used as an example, mainly for marking the approximate position of the spacers. In actual production, the areas between the first area 1302 and the second area 1303, between the third area 1202 and the fourth area 1203, and between the fifth area 1402 and the sixth area 1403 after the protective layer 160 is deposited are all filled with the first insulating material.

[0119] like Figure 6F As shown, in step S550, an insulating layer is deposited on the etched ninth structure, and the material of the insulating layer here is the same as the material of the above-mentioned insulating layer. In addition, in the embodiment of the present application, the fifth photoresist layer with an opening is used as a mask to etch the tenth structure after the insulating layer is deposited to form two hollow areas in the insulating layer, and both of the hollow areas have a through hole penetrating the insulating layer, and then metal is deposited in the etched area to fill the two hollow areas, so as to form a second conductive metal layer 170 and a third conductive metal layer 180 in the two hollow areas, respectively, and form a second protrusion 1701 and a third protrusion 1801 in the two through holes, respectively, to obtain a non-volatile two-terminal storage unit (i.e. Figure 2 The method for forming the fifth photoresist layer is the same as that for forming the first photoresist layer, and will not be described in detail here.

[0120] Although multiple embodiments of the present application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art can conceive of many changes, modifications, and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The accompanying claims are intended to define the scope of protection of the present application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A non-volatile two-terminal memory cell, characterized in that: include: Lower electrode structure; A first lower electrode layer, a resistive switching layer, and an upper electrode layer are stacked on the lower electrode structure from bottom to top; Among them, the resistive layer has a first spacer portion that penetrates the resistive layer along the stacking direction, and the resistive layer is divided into a first area and a second area by the first spacer portion; the first lower electrode layer has a second spacer portion that penetrates the first lower electrode layer along the stacking direction; the first lower electrode layer is divided into a third area and a fourth area by the second spacer portion.

2. The non-volatile two-terminal memory cell according to claim 1, wherein: The first spacer and the second spacer are filled with a first insulating material.

3. The nonvolatile two-terminal memory cell according to claim 1, wherein: The non-volatile two-terminal memory cell further includes: a first conductive metal layer; the first conductive metal layer is located above the upper electrode layer; a side of the first conductive metal layer close to the upper electrode layer includes a first protrusion, and the first protrusion is connected to the upper electrode layer.

4. The non-volatile two-terminal memory cell according to claim 1, wherein: Both sides of the upper electrode layer are provided with a protective layer; the material of the protective layer is the second insulating material.

5. The non-volatile two-terminal memory cell according to claim 4, wherein: A resistive switching layer is further provided between the two side edges of the upper electrode layer and the protective layer.

6. The non-volatile two-terminal memory cell according to claim 1, wherein: A center point of the first spacer and a center point of the second spacer are on the same straight line in the stacking direction.

7. The non-volatile two-terminal memory cell according to claim 1, wherein: The upper electrode layer has a third spacer that penetrates the upper electrode layer along a stacking direction; the upper electrode layer is divided into a fifth region and a sixth region by the third spacer.

8. The non-volatile two-terminal memory cell according to claim 7, wherein: Both sides of the fifth region and both sides of the sixth region are provided with protective layers; the material of the protective layers is the second insulating material.

9. The non-volatile two-terminal memory cell according to claim 8, wherein: A resistive switching layer is provided between the two side edges of the fifth region and the protective layer; and a resistive switching layer is provided between the two side edges of the sixth region and the protective layer.

10. The non-volatile two-terminal memory cell according to claim 7, wherein: The non-volatile two-terminal memory cell further includes: a second conductive metal layer and a third conductive metal layer; the second conductive metal layer is located above the fifth region, and a side of the second conductive metal layer close to the fifth region includes a second protrusion, and the second protrusion is connected to the fifth region; The third conductive metal layer is located above the sixth region. A side of the third conductive metal layer close to the sixth region includes a third protrusion connected to the sixth region.

11. The non-volatile two-terminal memory cell according to claim 10, wherein: The first spacer, the second spacer, and the third spacer are filled with a first insulating material.

12. The non-volatile two-terminal memory cell according to claim 7, wherein: A center point of the first spacer, a center point of the second spacer, and a center point of the third spacer are on the same straight line in the stacking direction.

13. The non-volatile two-terminal memory cell according to any one of claims 1 to 12, wherein: The absolute difference between the length of the third region and the length of the fourth region is less than or equal to 1 / 4 of the length of the third region; and / or An absolute difference between the length of the third region and the length of the fourth region is less than or equal to 1 / 4 of the length of the fourth region.

14. The non-volatile two-terminal memory cell according to any one of claims 1 to 12, wherein: The lower electrode structure includes: a second lower electrode layer; a first contact area exists between the second lower electrode layer and the third region; a second contact area exists between the second lower electrode layer and the fourth region; the absolute difference between the length of the first contact area and the length of the second contact area is less than or equal to 1 / 10 of the length of the contact surface between the second lower electrode layer and the third region and the fourth region.

15. A method for preparing a non-volatile two-terminal memory cell, characterized in that: The non-volatile two-terminal memory cell is the non-volatile two-terminal memory cell according to any one of claims 1 to 6, and the method comprises: Provide the electrode structure; Depositing a first lower electrode layer and a resistive switching layer in sequence on the lower electrode structure; Using the first photoresist layer having the opening as a mask, etching the resistive layer and the first lower electrode layer to form a first spacer penetrating the resistive layer on the resistive layer and a second spacer penetrating the first lower electrode layer on the first lower electrode layer; Depositing an insulating layer on the etched first structure and etching the insulating layer; wherein the etching stop layer is the resistive switching layer; depositing an upper electrode layer on the etched second structure, and etching the upper electrode layer using the second photoresist layer having the opening as a mask; depositing a protective layer on the etched third structure, and etching the deposited fourth structure using the upper electrode layer as an etch stop layer; An insulating layer is deposited on the etched fifth structure, and the sixth structure after the insulating layer is etched using the third photoresist layer with an opening as a mask, and then a first conductive metal layer is deposited to obtain the non-volatile two-terminal memory cell.

16. The preparation method according to claim 15, characterized in that Before depositing the protection layer on the etched third structure, the method further includes: depositing a resistive switching layer on the etched third structure.

17. A method for preparing a non-volatile two-terminal memory cell, characterized in that: The non-volatile two-terminal memory cell is the non-volatile two-terminal memory cell according to any one of claims 7 to 12, and the method comprises: Provide the electrode structure; Depositing a first lower electrode layer, a resistive switching layer and an upper electrode layer in sequence on the lower electrode structure; Using the fourth photoresist layer with the opening as a mask and the first lower electrode layer as an etching stop layer, etching the upper electrode layer and the resistive layer; Depositing a protective layer on the etched seventh structure, and etching the deposited eighth structure; wherein the etch stop layer in the hollowed-out area of ​​the eighth structure is the lower electrode structure, and the etch stop layer in the non-hollowed-out area of ​​the eighth structure is the upper electrode layer; forming a first spacer penetrating the resistive layer on the resistive layer; forming a second spacer penetrating the first lower electrode layer on the first lower electrode layer; and forming a third spacer penetrating the upper electrode layer on the upper electrode layer; An insulating layer is deposited on the etched ninth structure, and the tenth structure after the insulating layer is etched using the fifth photoresist layer with an opening as a mask, and a second conductive metal layer and a third conductive metal layer are deposited in the etched area to obtain the non-volatile two-terminal memory cell.

18. The preparation method according to claim 17, characterized in that: Before depositing the protection layer on the etched seventh structure, the method further includes: depositing a resistive switching layer on the etched seventh structure.

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