Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors, the preparation method of the semiconductor device comprises the steps that a semiconductor body is formed, the semiconductor body comprises a first surface and a second surface which are oppositely arranged, and a gate structure is formed on the first surface. A stress layer is formed and located on the side, away from the semiconductor body, of the gate structure, and the stress of the material of the stress layer is larger than that of the material of the semiconductor body. And annealing the semiconductor body and the stress layer. And removing the stress layer. A source electrode is formed on the first surface, a drain electrode is formed on the second surface, and the preparation method can improve the electron mobility of the SiC MOSFET.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Stress Memorization Technique (SMT), primarily used in small-scale CMOS devices, is a strained silicon technology designed to improve NMOS electron mobility in 90nm and below process technology. It introduces stress in various directions by depositing and then sacrificing a Si3N4 thin film, significantly improving NMOS electron mobility and, consequently, the drive current. Its advantage lies in the ability to remove the stress film after the entire process flow, without causing any structural changes to the device. Traditional stress layers are made of highly stressed Si3N4. Since SiC itself is highly stressed, the high stress generated by Si3N4 in the SiC surface channel may not achieve the same effect as on Si devices. Summary of the Invention

[0003] The present application provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle for improving the electron mobility of SiC MOSFET.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] An embodiment of the present application provides a method for fabricating a semiconductor device, the method comprising forming a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite each other, the material of the semiconductor body comprising silicon carbide. A gate structure is formed on the first surface. A stress layer is formed, the stress layer being located on a side of the gate structure away from the semiconductor body, the stress of the material of the stress layer being greater than the stress of the material of the semiconductor body. The semiconductor body and the stress layer are annealed to remove the stress layer, and a source electrode is formed on the first surface, and a drain electrode is formed on the second surface.

[0006] In some embodiments, the material of the stress layer includes diamond.

[0007] In some embodiments, the stress layer is formed using a microwave plasma chemical vapor deposition process.

[0008] In some embodiments, a dry etching process is used to remove the stress layer.

[0009] In some embodiments, before forming the stress layer, the preparation method further includes forming a buffer layer, where the buffer layer covers the gate structure.

[0010] In some embodiments, after removing the stress layer, the preparation method further includes removing the buffer layer.

[0011] On the other hand, an embodiment of the present application further provides a semiconductor device prepared by any of the above preparation methods.

[0012] In an embodiment of the present application, a stress layer is formed on the side of the gate structure away from the semiconductor body, and the stress of the material of the stress layer is greater than the stress of the material of the semiconductor body. The semiconductor body and the stress layer are subjected to a spike annealing treatment, and then the stress layer is removed. During annealing, thermal stress and internal stress are generated between the gate structure and the stress layer. These stresses are memorized in the gate structure. The stress transmitted to the channel causes the lattice structure of the semiconductor body to change, thereby affecting the scattering and effective mass of the carriers and improving the electron mobility of the channel. The stress layer is then removed without affecting the original structure of the device.

[0013] On the other hand, an embodiment of the present application further provides a power module including a substrate and a semiconductor device as described in any of the above embodiments, wherein the substrate is used to support the semiconductor device.

[0014] In yet another aspect, embodiments of the present application further provide a power conversion circuit configured for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device according to any of the aforementioned embodiments, the semiconductor device being electrically connected to the circuit board.

[0015] On the other hand, an embodiment of the present application also provides a vehicle, including a load and a power conversion circuit as described in the above embodiment, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0016] The above-mentioned power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0019] Figure 2 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0020] Figures 3 to 11A diagram of the steps for preparing a semiconductor device according to an embodiment of the present application;

[0021] Figure 12 A schematic diagram of the structure of the power module provided in an embodiment of the present application;

[0022] Figure 13 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application;

[0023] Figure 14 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0025] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0026] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0027] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0028] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0029] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0030] Example embodiments are described herein with reference to cross-sectional illustrations that are idealized example drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the example embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the example embodiments.

[0031] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0032] Stress Memorization Technique (SMT), primarily used in small-scale CMOS devices, is a strained silicon technology designed to improve NMOS electron mobility in 90nm and below process technology. It introduces stress in various directions by depositing and then sacrificing a Si3N4 thin film, significantly improving NMOS electron mobility and, consequently, the drive current. Its advantage lies in the ability to remove the stress film after the entire process flow, without causing any structural changes to the device. Traditional stress layers are made of highly stressed Si3N4. Since SiC itself is highly stressed, the high stress generated by Si3N4 in the SiC surface channel may not achieve the same effect as on Si devices.

[0033] In view of the above problems, the present invention provides a semiconductor device. Figure 1 As shown, Figure 1 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application.

[0034] like Figure 1 As shown, the semiconductor device 10 includes a semiconductor body 101, which is configured as a first conductivity type and includes a first surface P1 and a second surface P2 disposed opposite each other. A field oxide layer 106 is disposed on the first surface P1. A gate structure 108 is disposed on the first surface P1, and a source electrode 113 is disposed on the first surface P1. A drain electrode 114 is disposed on the second surface P2. An interlayer dielectric layer 115 is further disposed on the side of the gate structure 108 away from the semiconductor body 101. The interlayer dielectric layer 115 covers the gate structure 108 and is used to isolate and protect the gate structure 108.

[0035] The semiconductor body 101 also includes a silicon carbide substrate 1012 configured as a first conductivity type, a silicon carbide epitaxial layer 1011, a JFET region 116, and a first region 102, a second region 103 configured as a second conductivity type, and a well region 104. A guard ring 105 is also provided outside the well region 104. For example, the first conductivity type is N-type, and the second conductivity type is P-type. Thus, the first region 102, the well region 104, and the semiconductor body 101 form an NPN junction. The gate structure 108, the source 113, and the drain 114 constitute the three electrodes of the semiconductor device 10.

[0036] By transmitting the turn-on voltage to the gate structure 108 , when the semiconductor device 10 is forward-conducting and the operating current is small, the operating current flows from the source 113 through the first region 102 , the well region 104 , the JFET region 116 , the epitaxial layer 1011 and the silicon carbide substrate 1012 to the drain 114 .

[0037] Since the P-type ion concentration in the second region 103 is higher than that in the well region 104, more PN junctions are formed between the second region 103 and the epitaxial layer 1011. When the operating current is large, the operating current flows from the source 113 through the second region 103, the epitaxial layer 1011 and the silicon carbide substrate 1012 to the drain 114, thereby preventing the large operating current from flowing through the well region 104 and protecting the channel in the well region 104.

[0038] The present application also provides a method for preparing a semiconductor device, such as Figure 2 As shown, Figure 2 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application is provided. Figures 3 to 11 A diagram of the steps for preparing a semiconductor device provided in an embodiment of the present application.

[0039] like Figure 2 As shown, the preparation method includes the following steps S10 to S70:

[0040] Step S10: Figure 3 As shown, a semiconductor body 101 of a first conductivity type is formed, and the semiconductor body 101 includes a first surface P1 and a second surface P2 opposite to each other.

[0041] For example, Figure 3As shown, the semiconductor body 101 includes a silicon carbide substrate 1012 and a silicon carbide epitaxial layer 1011. The conductivity type of the semiconductor body 101 is N-type. On the first surface P1 of the semiconductor body 101, a mask is formed by a photolithography process, an ion implantation area is defined, and P+ ion implantation is performed to form a well region 104 and a second region 103. P-type ions are implanted into both the well region 104 and the second region 103, and both have a P-type conductivity. The well region 104 may also be referred to as a "P-type well region (P-well)", and the second region 103 may also be referred to as a "P+ contact region". After that, the mask is removed and a mask is formed again by a photolithography process, an ion implantation area is defined, and N+ ion implantation is performed to form the first region 102 and the JFET region 116. The first region 102 may also be referred to as an "N+ contact region".

[0042] For example, Figure 3 As shown, a guard ring 105 is formed in the epitaxial layer 1011 through a diffusion process, which can improve the voltage resistance of the semiconductor device 10, reduce leakage, and enhance the stability of the device.

[0043] Illustratively, after step S10 and before step S20, the preparation method of the present application further includes the following steps S11 to S12:

[0044] Step S11 : forming a field oxide layer 106 on the first surface P1 .

[0045] Exemplary, reference Figure 3 A field oxide layer 106 can be formed on the side of the first surface P1 away from the semiconductor body 101 using a local oxidation (LOCOS) technique. Field oxide layer 106 is typically made of silicon dioxide (SiO2) because silicon dioxide has good insulation properties and chemical stability. Field oxide layer 106 can provide isolation and improve the reliability of semiconductor device 10.

[0046] Step S12: Figure 3 As shown, a gate insulating layer 107 is formed on the first surface P1.

[0047] For example, Figure 3 As shown, a gate insulating layer 107 is formed on a side of the first surface P1 away from the semiconductor body 101 by using a thermal oxidation method, a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method.

[0048] Step S20: Figure 3 、 Figure 4 As shown, a gate structure 108 is formed on the first surface P1 .

[0049] Exemplary, reference Figure 3 、 Figure 4A polysilicon film is formed on the first surface P1 by chemical vapor deposition (CVD), and the polysilicon film is etched into a desired shape by photolithography and etching processes to form a gate structure 108.

[0050] Illustratively, after step S20 and before step S30, the preparation method of the present application further includes the following step S21:

[0051] Step S21: Figure 5 As shown, a buffer layer 109 is formed, and the buffer layer 109 covers the gate structure 108 .

[0052] For example, Figure 5 As shown, a buffer layer 109 is formed by chemical vapor deposition (CVD) on the side of the gate structure 108 away from the first surface P1. The material of the buffer layer 109 can be SiO2, wherein the buffer layer 109 covers the gate structure 108 and can protect the gate structure 108 from chemical erosion, physical damage or impurity contamination in subsequent process steps.

[0053] Step S30: Figure 6 As shown, a stress layer 110 is formed. The stress layer 110 is located on a side of the gate structure 108 away from the semiconductor body 101 . The stress of the material of the stress layer 110 is greater than the stress of the material of the semiconductor body 101 .

[0054] For example, Figure 6 As shown, the stress layer 110 is formed by microwave plasma chemical vapor deposition (MPCVD).

[0055] For example, the material of the semiconductor body 101 may be silicon carbide, and the material of the stress layer 110 may be diamond, wherein the stress of diamond is greater than the stress of silicon carbide.

[0056] Step S40: Figure 6 As shown, the semiconductor body 101 and the stress layer 110 are annealed.

[0057] For example, after forming the stress layer 110, the semiconductor body 101 and the stress layer 110 are annealed to further improve the performance and reliability of the device. Among them, spike annealing or laser annealing can be selected. The present application adopts spike annealing to anneal the semiconductor body 101 and the stress layer 110. Spike annealing is an important heat treatment step in the semiconductor manufacturing process, which is mainly used to activate doping elements, repair lattice damage, and optimize the electrical properties of the material. When diamond is deposited on the silicon carbide semiconductor body 101 as the stress layer 110, additional stress will be applied to the semiconductor body 101 during the spike annealing process. This stress can change the lattice structure of the semiconductor body 101, thereby affecting its electrical properties. The conditions for spike annealing can refer to the annealing conditions of Si substrate devices in the prior art and will not be described in the present invention.

[0058] Step S50: Figure 6 and Figure 7 As shown, the stress layer 110 is removed.

[0059] For example, Figure 7 As shown, the stress layer 110 is introduced to apply additional stress to the semiconductor body 101 to modify or optimize its performance. However, in subsequent steps of device fabrication, the stress layer 110 is no longer needed. Therefore, to ensure the ultimate performance and reliability of the device, the stress layer 110 must be removed. Dry etching techniques such as plasma or reactive ion etching can be used to remove the stress layer 110 through physical and chemical reactions.

[0060] Illustratively, after step S50 and before step S60, the preparation method of the present application further includes the following steps S51 to S53:

[0061] Step S51: Figure 8 As shown, after removing the stress layer 110 , the preparation method further includes removing the buffer layer 109 .

[0062] For example, Figure 8 As shown, after removing the stress layer 110, the SiO2 buffer layer 109 is removed and cleaned using diluted hydrofluoric acid (DHF), a chemical solution commonly used to remove SiO2. Deionized water or other suitable cleaning agents are then used to clean the surface to remove any DHF solution residue.

[0063] Step S52: Figure 9 As shown, an interlayer dielectric layer 115 is formed, and the interlayer dielectric layer 115 covers the gate structure 108 and the first surface P1 .

[0064] For example, Figure 9As shown, an interlayer dielectric layer 115 is formed on the side of the gate structure 108 away from the first surface P1 using physical vapor deposition (PVD) or chemical vapor deposition (CVD), mainly to isolate the gate structure 108 from the subsequently formed metal layer or other structures, prevent electrical short circuits between them, and ensure the reliability and performance of the semiconductor device.

[0065] Step S53: Figure 10 As shown, a first contact hole D1 is formed in the interlayer dielectric layer 115 , and the first contact hole D1 exposes the first region 102 and the second region 103 .

[0066] For example, Figure 10 As shown, a first contact hole D1 is formed in the interlayer dielectric layer 115 through photolithography and etching processes, such as dry etching or wet etching. The first contact hole D1 exposes the first region 102 and the second region 103. The main function of the first contact hole D1 is to provide an electrical connection path so that the subsequently formed metal interconnect layer can be electrically connected to the first region 102 and the second region 103 through the hole.

[0067] Step S60: Figure 10 As shown, a source electrode 113 is formed on the first surface P1 .

[0068] For example, Figure 10 As shown, a layer of source material, such as aluminum (Al), copper (Cu), nickel (Ni), etc., is deposited on the first surface P1 by sputtering, evaporation, etc. to form a source 113, and the source 113 is in electrical contact with the first region 102 and the second region 103.

[0069] Step S70: Figure 11 As shown, a drain electrode 114 is formed on the second surface P2.

[0070] For example, Figure 11 As shown, a layer of drain material, such as aluminum (Al), copper (Cu), nickel (Ni), etc., is deposited on the second surface P2 by sputtering, evaporation, etc. to form the drain 114.

[0071] In an embodiment of the present application, a stress layer 110 is formed on the side of the gate structure 108 away from the semiconductor body 101, and the stress of the material of the stress layer 110 is greater than the stress of the material of the semiconductor body 101. The semiconductor body 101 and the stress layer 110 are subjected to a spike annealing treatment, and then the stress layer 110 is removed. During annealing, thermal stress and internal stress are generated between the gate structure 108 and the stress layer 110. These stresses are memorized in the gate structure 108. The stress transmitted to the channel causes the lattice structure of the semiconductor body 101 to change, thereby affecting the scattering and effective mass of the carriers and improving the electron mobility of the channel. The stress layer 110 is then removed without affecting the original structure of the device.

[0072] An embodiment of the present application also provides a semiconductor device, which can be manufactured by the manufacturing method described in any of the above embodiments.

[0073] On the other hand, an embodiment of the present application further provides a power module, Figure 12 A schematic diagram of the structure of the power module provided in an embodiment of the present application.

[0074] like Figure 12 As shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments. The substrate 201 is used to support the semiconductor device 10 .

[0075] Illustratively, the power module 200 can function as a power amplifier, a power converter, a power controller, a power management module, or a power regulator. A power amplifier is used to amplify the power of an electrical signal. A power converter is used to convert electrical energy from one form to another. For example, a power converter can be an AC / DC converter or a DC / DC converter. A power controller is used to control the flow of power. A power management module is used to manage the power supply, ensuring stable and efficient distribution of power to different parts of an electronic device. A power regulator is used to adjust the power output to meet the needs of a specific application.

[0076] On the other hand, an embodiment of the present application further provides a power conversion circuit, Figure 13 A schematic diagram of the structure of the power conversion circuit provided in an embodiment of the present application.

[0077] like Figure 13 As shown, the power conversion circuit 300 includes a circuit board 301 and the semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion or power factor correction.

[0078] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce harmonic pollution of the power grid.

[0079] On the other hand, an embodiment of the present application further provides a vehicle, Figure 14 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application.

[0080] like Figure 14 As shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment. The power conversion circuit 300 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 401 to power the load 401.

[0081] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: forming a semiconductor body, the semiconductor body comprising a first surface and a second surface opposite to each other, the material of the semiconductor body comprising silicon carbide; forming a gate structure on the first surface; forming a stress layer, wherein the stress layer is located on a side of the gate structure away from the semiconductor body, and the stress of the material of the stress layer is greater than the stress of the material of the semiconductor body; performing annealing on the semiconductor body and the stress layer; removing the stress layer; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

2. The preparation method according to claim 1, characterized in that The material of the stress layer includes diamond.

3. The preparation method according to claim 1, characterized in that The stress layer is formed by adopting a microwave plasma chemical vapor deposition process.

4. The preparation method according to claim 1, characterized in that The stress layer is removed by using a dry etching process.

5. The preparation method according to claim 1, characterized in that Before forming the stress layer, the preparation method further includes: A buffer layer is formed, where the buffer layer covers the gate structure.

6. The preparation method according to claim 5, characterized in that After removing the stress layer, the preparation method further includes: The buffer layer is removed.

7. A semiconductor device, characterized in that: The method is as described in any one of claims 1 to 6.

8. A power module, characterized in that: include: at least one semiconductor device according to claim 7; A substrate is used to support the semiconductor device.

9. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to claim 7 , wherein the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that: include: A load and a power conversion circuit as claimed in claim 9, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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