Preparation method of high-voltage SiC device with low contact resistance and SiC device
By forming a metal silicon compound between the gate thermal oxidation process and the intermediate oxide layer process, the process complexity and high cost problems when the contact window size is reduced in high-voltage SiC devices are solved, and the preparation of SiC devices with low contact resistance and high electrical performance is achieved.
Patent Information
- Application Number
- CN202510963925.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-14
- Publication Date
- 2025-10-03
AI Technical Summary
In the existing source ohmic contact process of high-voltage SiC devices, metal compounds are only formed at the bottom of the contact window. As a result, when the contact window size is reduced, the difficulty of metal sputtering and annealing reactions increases, the process complexity and cost increase, and the source region cannot effectively reduce the on-resistance.
Between the gate thermal oxidation process and the intermediate oxide layer process, a self-aligned metal silicon compound process is used to form a metal silicon compound at the contact between SiC and the metal, which simplifies the process flow and improves the integrity of the ohmic contact. By forming an ohmic contact of the source before the intermediate oxide layer, the on-resistance of the source region is reduced.
The process flow is simplified, the requirements for high aspect ratio of the equipment are reduced, the cost is reduced, and the static and dynamic electrical performance of the device is improved by expanding the contact area and forming good metal compounds, thereby shortening the production time.
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Figure CN120751719A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of high-voltage SiC devices, and in particular to a method for preparing a high-voltage SiC device with low contact resistance and a SiC device. Background Art
[0002] The common source ohmic contact process for silicon carbide high-voltage MOS devices currently involves the following steps: The source (region) to gate polysilicon is constructed on a SiC epitaxial substrate, followed by growth of an intermediate layer oxide (ILD). The source contact window is then opened using photolithography and dry etching, followed by sputtering of a metal layer (titanium, cobalt, nickel, etc.). This is followed by a low-temperature, rapid temperature ramp annealing process. This forms a preliminary metal-silicon compound at the bottom of the contact window, where the SiC epitaxial layer contacts the metal. Wet etching is then performed to remove any unreacted metal from the intermediate oxide layer and the window sidewalls. This is followed by a high-temperature, rapid temperature ramp annealing process to form an ideal, stable metal-silicon compound, completing the ohmic contact with the source. Finally, the gate lead-out contact window is opened using photolithography and dry etching, followed by sputtering or chemical vapor deposition of tungsten metal to fill the contact window, and then adding a top layer of aluminum-copper (AlCu) to complete the basic MOS device process.
[0003] In the above process, since the metal compound of the ohmic contact is only formed at the bottom of the contact window, the deposition and annealing reaction of the metal compound are limited, which reduces the integrity of the ohmic contact. Especially when the device size continues to shrink, the size of the contact window also continues to shrink accordingly, which will significantly increase the difficulty of metal sputtering, metal removal, and annealing reaction, making it more difficult to achieve a good ohmic contact and increasing the cost of the process. Secondly, because the silicon carbide of the source and the polysilicon of the gate are two different materials, their reaction temperatures to metal compounds are different, so the opening of the contact windows for the two must be performed separately, which increases the process steps and complexity; Moreover, since the metal compound is only formed at the bottom of the contact window, there is no metal compound in other source regions, and the on-resistance of the source cannot be effectively reduced.
[0004] Therefore, a technical solution for preparing a high-voltage SiC device with low contact resistance is needed to solve the above problems. Summary of the Invention
[0005] The present invention aims to provide a method for preparing a high-voltage SiC device with low contact resistance and a SiC device to address the deficiencies in the prior art. The technical problem to be solved by the present invention is achieved through the following technical solutions.
[0006] According to a first aspect of the present application, a method for preparing a high-voltage SiC device with low contact resistance is provided, comprising the following steps: Step 1: Prepare the P-type well region, field oxide layer, source and gate on the SiC epitaxial substrate; Step 2: Using thermal oxidation process, an oxide layer is grown only on the gate surface; Step 3: Using the self-aligned metal-silicon compound process, a metal-silicon compound is formed at the contact point between SiC and metal to complete the ohmic contact of the source; Step 4: growing an intermediate oxide layer, performing photolithography and etching to form a source contact window and a gate contact window; Step 5: Fill the source contact window and the gate contact window with tungsten metal, prepare the upper metal layer, and complete the preparation of the SiC device.
[0007] Preferably, in step 2, the thermal oxidation process is carried out in an environment with a reaction temperature of 700°C-800°C.
[0008] Preferably, the thickness of the oxide layer grown on the gate surface is 10-1000 nanometers.
[0009] Preferably, in step 3, the specific method of forming the metal silicon compound at the contact point between SiC and the metal is: After sputtering the metal layer, a low-temperature rapid temperature rise and fall annealing treatment is performed at 450-550°C to initially form a metal silicon compound; Using wet etching to remove unreacted metal on the polysilicon oxide layer and the field oxide layer; A high-temperature rapid temperature rise and fall annealing process is performed in an environment of 700~950℃ to form a metal silicon compound and complete the ohmic contact of the source.
[0010] Preferably, in the step of sputtering the metal layer, one or more stacks of titanium, cobalt or nickel are used for sputtering.
[0011] Preferably, in step 4, the specific steps are: SiO2 or low-k dielectric is used for deposition until the gate and field oxide layer are covered to form an intermediate oxide layer; After spin coating the photoresist, a mask is used for exposure and development to form a window pattern; A dry etching process is used to open windows to form a source contact window and a gate contact window.
[0012] Preferably, in step 5, the specific method of filling the source contact window and the gate contact window with tungsten metal is: Pre-cleaning: Use Ar⁺ sputter etching or HF vapor treatment to remove residual oxide at the bottom of the contact hole; After sputtering the Ti / TiN stack, tungsten filling was performed using a two-step deposition method; The tungsten metal filling is completed after removing the excess tungsten, Ti or TiN on the surface by chemical mechanical polishing or dry etching.
[0013] Preferably, the specific method for preparing the upper metal layer is: AlCu alloy is deposited by sputtering process, interconnection lines are defined by photolithography on the AlCu alloy and then etched to form conductive lines; Annealing treatment is performed at 400-450°C in an H2 / N2 atmosphere to complete the preparation of the upper metal layer.
[0014] According to a second aspect of the present application, a SiC device is provided, which adopts the above-mentioned method for preparing a high-voltage SiC device with low contact resistance.
[0015] According to a third aspect of the present application, an electronic device is provided, which adopts the above-mentioned SiC device.
[0016] The embodiments of the present invention include the following advantages: The method for fabricating a high-voltage SiC device with low contact resistance provided by the present invention moves the ohmic contact formation process of the metal compound to between the gate thermal oxidation process and the intermediate oxide layer process. This simplifies the process and facilitates the formation of a good metal compound. It also reduces the equipment's requirement for a high aspect ratio, thereby reducing costs. Since the source region has a larger area and good metal compound formation, the on-resistance of the source region will be reduced, and the static and dynamic electrical performance of the device will be improved; Since the ohmic contact of the source region is formed before the intermediate oxide layer, the contact windows of the source region and the gate can be formed at the same time, which simplifies the corresponding processes of photolithography, dry etching and cleaning, and shortens the time for device production. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 This is a flow chart of a method for preparing a high-voltage SiC device with low contact resistance according to the present invention; Figure 2 It is a schematic diagram of the structure in which the P-type well region, field oxide layer, source electrode and gate electrode are prepared in step 1; Figure 3 This is a schematic diagram of the structure after the oxide layer is grown on the surface of the gate polysilicon in step 2; Figure 4 is a schematic diagram of the structure after the ohmic contact is formed in step 3; Figure 5 This is a schematic diagram of the structure after the intermediate oxide layer is produced and the window is opened in step 4. DETAILED DESCRIPTION
[0018] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0019] It should be noted that the above detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this application belongs.
[0020] like Figure 1 As shown, a method for preparing a high-voltage SiC device with low contact resistance in an embodiment of the present application includes the following steps: Step 1: Prepare a P-type well region 110, a field oxide layer 120, a source 130 and a gate 140 on a SiC epitaxial substrate 100; In this step, if Figure 2 As shown, first, a P-type well region 110 is prepared on a SiC epitaxial substrate 100. The specific method is as follows: Ion implantation: Aluminum (Al) or boron (B) is used as a P-type dopant. Al is more suitable for SiC materials due to its higher solid solubility and activation rate. Implantation parameters: The energy range is usually 200–350 keV, and the dose is controlled within 1×10¹³–1×10¹ 4 cm⁻² to form a P-well (P-type well area 110) with a depth of 0.5–1.5 μm; High-temperature activation annealing: Activation of impurities in SiC requires high-temperature treatment (1600–1800°C for 30 minutes) in an inert atmosphere (argon) to repair lattice damage and activate dopant atoms to complete the preparation of the P-type well region 110.
[0021] Then, a field oxide layer 120 is formed on the top of the P-type well region 110 to isolate the device and prevent leakage between electrodes. The specific method is as follows: The SiO2 layer is grown at approximately 400°C using PECVD plasma chemical vapor deposition (PECVD) with a thickness of approximately 500–1000 nm. Photolithography is used to define the isolation area on the SiO2 layer, and the oxide layer in the non-protected area is removed by dry etching (CF4 / CHF3 plasma) or wet etching, ultimately forming a local oxidation isolation (LOCOS) structure.
[0022] The source electrode 130 is prepared as follows: N⁺ injection: Inject nitrogen (N) or phosphorus (P) into the P-well with a concentration of >1×10² 0 cm⁻³, forming a source 130 contact region.
[0023] The gate 140 is prepared as follows: Thermal oxidation growth of a 40–100 nm SiO2 layer (1100–1400°C), or the use of high-k dielectrics (such as Al2O3, HfO2, with a dielectric constant > 20) to enhance capacitance density; Doped polysilicon (300–500 nm thick) was deposited by LPCVD and patterned by photolithography.
[0024] Step 2: Using a thermal oxidation process, an oxide layer 141 is grown only on the surface of the gate 140; In this step, if Figure 3 As shown, a thermal oxidation process is performed in an environment with a reaction temperature of 700° C. to 800° C., and the thickness of the oxide layer 141 grown on the surface of the gate 140 is 100 to 1000 nanometers; By utilizing the difference between the reaction temperature of the gate 140 polysilicon oxidation of 700°C and the reaction temperature of the SiC oxidation of 1000°C, an oxide layer 141 with a thickness of several 100 to several 1000 nanometers is grown on the gate 140 polysilicon surface, without forming an oxide layer on the SiC surface.
[0025] The purpose of using furnace tube hot oxidation (dry oxygen or wet oxygen process) to react with polysilicon to grow oxide layer 141 on the surface of gate 140 has two aspects. First, it protects the gate polysilicon and prevents it from forming a metal-polysilicon compound with subsequent metal; second, it adjusts the distance between the gate and the SiC metal compound. The specific thickness of the oxide layer is adjusted according to the voltage required by the MOS tube.
[0026] Step 3: Using a self-aligned metal-silicon compound process, a metal-silicon compound is formed at the contact point between SiC and the metal to complete the ohmic contact 150 of the source 130; In this step, if Figure 4 As shown, the specific method of forming a metal silicon compound at the contact point between SiC and metal is: The metal layer is sputtered using a stack of one or more of titanium, cobalt, or nickel. After sputtering, a low-temperature rapid temperature annealing process is performed at 450-550°C to initially form a metal-silicon compound. At this point, the oxide layer covering the gate 140 polysilicon blocks the reaction between the metal and the polysilicon. Then, wet etching is used to remove unreacted metal on the polysilicon oxide layer and the field oxide layer 120; A high-temperature rapid temperature rise and fall annealing process is performed in an environment of 700-950° C. to form a metal silicon compound, thereby completing the ohmic contact 150 of the source electrode 130 .
[0027] Step 4: growing an intermediate oxide layer 160, performing photolithography and etching to form a source 130 contact window and a gate 140 contact window; In this step, if Figure 5 As shown, SiO2 or a low-k dielectric is deposited until the gate 140 and the field oxide layer 120 are covered to form an intermediate oxide layer 160; After spin coating the photoresist, a mask is used for exposure and development to form a window pattern; A dry etching process is used to open windows to form a source 130 contact window and a gate 140 contact window.
[0028] Step 5: Fill the source 130 contact window and the gate 140 contact window with tungsten metal, and complete the preparation of the SiC device after preparing the upper metal layer.
[0029] In this step, the specific method of filling the source 130 contact window and the gate 140 contact window with tungsten metal is as follows: Pre-cleaning: Use Ar⁺ sputter etching or HF vapor treatment to remove residual oxide at the bottom of the contact hole; After sputtering the Ti / TiN stack, tungsten filling was performed using a two-step deposition method; The tungsten metal filling is completed after removing the excess tungsten, Ti or TiN on the surface by chemical mechanical polishing or dry etching.
[0030] The specific method for preparing the upper metal layer is: AlCu alloy is deposited by sputtering process, interconnection lines are defined by photolithography on the AlCu alloy and then etched to form conductive lines; Annealing treatment is performed at 400-450°C in an H2 / N2 atmosphere to complete the preparation of the upper metal layer.
[0031] An embodiment of the present application discloses a SiC device, which adopts the above-mentioned method for preparing a high-voltage SiC device with low contact resistance.
[0032] An embodiment of the present application discloses an electronic device using the above-mentioned SiC device.
[0033] The embodiments of the present invention include the following advantages: The method for preparing a high-voltage SiC device with low contact resistance provided by an embodiment of the present invention advances the ohmic contact process formed by the metal compound to between the gate thermal oxidation process and the intermediate oxide layer process.
[0034] The traditional process involves first growing an intermediate oxide layer, then opening a source contact window, and then using a sputtering device to grow an ohmic contact metal at the bottom of the source contact window. The sputtering device faces a high aspect ratio process, so the film thickness grown at the bottom of the contact window is much smaller than that grown at the top of the intermediate oxide layer. The only part that effectively forms an ohmic contact is the portion that contacts the bottom of the SiC, wasting most of the top surface metal. This method simplifies the process and makes it easier to form a good metal compound. It also reduces the equipment's requirement for a high aspect ratio, thereby reducing costs. Since the metal silicon compound is formed before the intermediate oxide layer, the contact area is much larger than the area where the metal silicon compound is formed after the intermediate oxide layer and the contact window. In addition, the metal silicon compound has good formation (i.e., the compound formed by the reaction of titanium, cobalt or nickel with SiC, forming a low metal-SiC contact resistance), which will reduce the on-resistance of the source region and improve the static and dynamic electrical performance of the device. Since the ohmic contact of the source region has been formed before the intermediate oxide layer, the contact windows of the source region and the gate can be completed at the same time, which simplifies the corresponding processes of photolithography, dry etching and cleaning, and shortens the time for device production.
[0035] It should be noted that the terms used herein are intended only to describe specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.
[0036] It should be noted that the terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.
[0037] In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, product, or apparatus.
[0038] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship of a device or feature to other devices or features as shown in the figures. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figures. For example, if the device in the drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be subsequently positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatially relative descriptions used herein are interpreted accordingly.
[0039] In the above detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless the context dictates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be used, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.
[0040] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.
Claims
1. A method for preparing a high-voltage SiC device with low contact resistance, characterized in that: The steps include: Step 1: Prepare the P-type well region, field oxide layer, source and gate on the SiC epitaxial substrate; Step 2: Using thermal oxidation process, an oxide layer is grown only on the gate surface; Step 3: Using the self-aligned metal-silicon compound process, a metal-silicon compound is formed at the contact point between SiC and metal to complete the ohmic contact of the source; Step 4: growing an intermediate oxide layer, performing photolithography and etching to form a source contact window and a gate contact window; Step 5: Fill the source contact window and the gate contact window with tungsten metal, prepare the upper metal layer, and complete the preparation of the SiC device.
2. The method for preparing a high-voltage SiC device with low contact resistance according to claim 1, wherein: In step 2, a thermal oxidation process is performed in an environment with a reaction temperature of 700° C. to 800° C.
3. The method for preparing a high-voltage SiC device with low contact resistance according to claim 2, wherein: The thickness of the oxide layer grown on the gate surface is 10-1000 nanometers.
4. The method for preparing a high-voltage SiC device with low contact resistance according to claim 1, wherein: In step 3, the specific method of forming a metal silicon compound at the contact point between SiC and metal is: After sputtering the metal layer, a low-temperature rapid temperature rise and fall annealing treatment is performed at 450-550°C to initially form a metal silicon compound; Using wet etching to remove unreacted metal on the polysilicon oxide layer and the field oxide layer; A high-temperature rapid temperature rise and fall annealing process is performed in an environment of 700~950℃ to form a metal silicon compound and complete the ohmic contact of the source.
5. The method for preparing a high-voltage SiC device with low contact resistance according to claim 4, characterized in that: In the step of sputtering the metal layer, one or more stacks of titanium, cobalt or nickel are used for sputtering.
6. The method for preparing a high-voltage SiC device with low contact resistance according to claim 1, wherein: In step 4, the specific steps are: SiO2 or low-k dielectric is used for deposition until the gate and field oxide layer are covered to form an intermediate oxide layer; After spin coating the photoresist, a mask is used for exposure and development to form a window pattern; A dry etching process is used to open windows to form a source contact window and a gate contact window.
7. The method for preparing a high-voltage SiC device with low contact resistance according to claim 1, wherein: In step 5, the specific method of filling the source contact window and the gate contact window with tungsten metal is as follows: Pre-cleaning: Use Ar⁺ sputter etching or HF vapor treatment to remove residual oxide at the bottom of the contact hole; After sputtering the Ti / TiN stack, tungsten filling was performed using a two-step deposition method; The tungsten metal filling is completed after removing the excess tungsten, Ti or TiN on the surface by chemical mechanical polishing or dry etching.
8. The method for preparing a high-voltage SiC device with low contact resistance according to claim 1, wherein: The specific method for preparing the upper metal layer is: AlCu alloy is deposited by sputtering process, interconnection lines are defined by photolithography on the AlCu alloy and then etched to form conductive lines; Annealing treatment is performed at 400-450°C in an H2 / N2 atmosphere to complete the preparation of the upper metal layer.
9. A SiC device, characterized in that: A method for preparing a high-voltage SiC device with low contact resistance according to any one of claims 1 to 8.
10. An electronic device, characterized in that: The SiC device according to claim 9 is used.