Low-loss vertical accumulation layer channel conduction type trench MOSFET power device and preparation method thereof

Abstract

The invention discloses a low-loss vertical accumulation layer channel conduction type trench MOSFET power device and a preparation method thereof, and the device comprises a bottom metal layer, cells, a top metal layer, a first conduction type substrate layer, a first conduction type epitaxial layer, a top JFET region, a second conduction type deep well region, a first conduction type source region, and an interlayer medium. And constructing a power device according to design implementation. On-off of a vertical accumulation type conducting channel is controlled through a grid electrode, an electric field is effectively shielded through a second conduction type deep well region, the intensity of a reverse electric field borne by a gate dielectric layer of the device is greatly reduced, and the conduction loss of the device is greatly reduced on the premise that the voltage withstanding level of the device is not affected; meanwhile, the top metal layer and the corresponding first conductive type source region are designed to form ohmic contact to realize single-pole follow current, so that follow current loss is reduced, and the problem of bipolar degradation is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor device structure design and preparation, and in particular to a low-loss vertical accumulation layer channel conduction type trench MOSFET power device and a preparation method thereof. Background Art

[0002] Power MOSFETs (metal oxide semiconductor field-effect transistors), as power switching devices, are now widely used in medium- and high-voltage power electronics applications such as electric vehicles and renewable energy generation due to their high power density, low switching losses, and high operating frequency. Traditional planar-gate power MOSFETs, however, are limited in their lateral topology by the presence of the JFET region, resulting in larger cell sizes. Trench-gate power MOSFETs, on the other hand, offer significant development potential due to their low parasitic resistance and compact cell size. Traditional trench-type inversion layer MOSFETs form a conductive path by applying a gate electric field to induce inversion in the body region. The resulting low inversion layer channel mobility significantly limits the device's current capability and increases conduction losses. Furthermore, traditional trench-type power MOSFETs achieve bipolar freewheeling through body diode conduction, resulting in high freewheeling losses and the susceptibility to bipolar degradation. Integrating Schottky barrier diodes (SBDs) or external anti-parallel SBDs within the cell structure to achieve unipolar freewheeling reduces the chip's active area and complicates the process. Therefore, innovations in device structure are needed to overcome these limitations. Summary of the Invention

[0003] The purpose of the present invention is to propose a low-loss vertical accumulation layer channel conduction type trench MOSFET power device and a preparation method, which can realize vertical accumulation layer channel conduction and unipolar freewheeling, and achieve small cell size, low specific on-resistance and low freewheeling loss without affecting the withstand voltage and gate oxide reliability. The process is simple, the feasibility is high, and the bipolar degradation problem is avoided.

[0004] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0005] In a first aspect, the present invention discloses a low-loss vertical accumulation layer channel conductive type trench MOSFET power device, the device comprising an interlayer dielectric (8), a top metal layer (9), and a bottom metal layer (1), a first conductive type substrate layer (2), a first conductive type epitaxial layer (3), and a plurality of cells arranged in sequence from bottom to top; the structures of the individual cells are identical to each other, and are all distributed on the upper surface of the first conductive type epitaxial layer (3) and extend downward to the interior of the first conductive type epitaxial layer (3) for arrangement; the interlayer dielectric (8) and the top metal layer (9) cover the upper surface of each cell;

[0006] Each cell is provided with a first conductive type JFET layer (10), a first conductive type source region (7) and a first trench on the upper surface of the first conductive type epitaxial layer (3); a gate dielectric layer (5) of a preset thickness is provided on the inner wall of the first trench; a gate material (6) is filled in the inner sidewall of the gate dielectric layer (5); an interlayer dielectric (8) is provided above the gate material to isolate the gate material (6) from the top metal (9); second conductive type deep well regions (4) are provided on both sides of the cell near the upper surface of the first conductive type epitaxial layer (3) and below the first trench; the width of the top of the first trench is smaller than the width of the two sides of the interlayer dielectric (8), and the width of the bottom of the first trench is not greater than the width of the two sides of the second conductive type deep well region (4) below the first trench; the cell structure forms an accumulation layer conductive channel through the first conductive type JFET layer (10) on the outer surface of the first trench sidewall.

[0007] Furthermore, the overall shape of the first groove includes but is not limited to a triangle, a rectangle and a trapezoid.

[0008] Furthermore, the edges on both sides of the first conductive type source region (7) in the cell exceed the edges on both sides of the interlayer dielectric (8), and an ohmic contact is formed between the top metal layer (9) and the first conductive type source region (7).

[0009] Furthermore, the top metal (9) horizontally covers the upper surface of the cell.

[0010] Furthermore, the top metal (9) includes a first metal portion horizontally covering the upper surface of the cell, and a second metal portion and a third metal portion filled in the second grooves on both sides of the cell, and a second conductive type deep well region (4) is wrapped along the outer edges of the second metal portion and the third metal portion.

[0011] Furthermore, the depth of the second grooves on both sides of the cell exceeds the depth of the first groove in the middle of the cell.

[0012] Furthermore, a first conductive type region is constructed below the first trench.

[0013] Furthermore, the second conductive type deep well regions on both sides of the cell are in a stepped shape, and a protrusion is provided on the side of the second conductive type region below the cell facing the first trench.

[0014] Furthermore, the multiple cells are arranged periodically.

[0015] In a second aspect, the present invention discloses a method for preparing a low-loss vertical accumulation layer channel conduction type trench MOSFET power device, the preparation method comprising the following steps:

[0016] S1, taking a first conductive type substrate (2), and forming a first conductive type epitaxial layer (3) above the substrate;

[0017] S2, forming a first conductive type JFET region (4) and a first conductive type source region (7) on the surface of the first conductive type epitaxial layer (3) by an ion implantation process and performing annealing;

[0018] S3, forming a first trench within each first conductivity type source region (7) on the surface of the first conductivity type epitaxial layer (3) by an etching process;

[0019] S4, forming a second conductive type deep well region (4) on both sides of the cell and below the first trench by ion implantation;

[0020] S5, depositing a gate dielectric layer (5) on the inner sidewall of the first trench by a chemical vapor deposition process, depositing a gate electrode (6) on the inner sidewall of the gate dielectric layer (5) by a chemical vapor deposition process, and depositing an oxide layer on the surface and both sides of the gate electrode (6) to form an interlayer dielectric (8);

[0021] S6, forming a top metal layer (9) on the upper surface of the cell using a sputtering process, and making a bottom metal (1) on the other surface of the first conductive type substrate (2).

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] First, the low-loss vertical accumulation layer channel conductive trench MOSFET power device and preparation method of the present invention conducts electricity through the vertical accumulation layer channel formed on the sidewall of the trench under the application of gate bias. Compared with the traditional trench MOSFET that relies on the inversion layer channel for conduction, the conduction loss is greatly reduced.

[0024] Second, the low-loss vertical accumulation layer channel conductive trench MOSFET power device and preparation method of the present invention sets a first conductive type JFET region on the upper surface of the first conductive type epitaxial layer, reduces the vertical accumulation layer channel resistance by increasing the effective carrier concentration, and further reduces the conduction loss.

[0025] Third, the low-loss vertical accumulation layer channel conductive trench MOSFET power device and preparation method of the present invention avoid the reliability problem of the gate dielectric layer at the corner of the bottom of the trench due to the electric field concentration effect by arranging a second conductive type shielding area (4) at the bottom of the trench, and form a JFET area with the second conductive type shielding area at the bottom of the trench by arranging the second conductive type shielding area (4) on both sides of the cell to limit the leakage current in the blocking state to ensure good blocking characteristics of the device.

[0026] Fourth, the low-loss vertical accumulation layer channel conductive type trench MOSFET power device and preparation method of the present invention realizes unipolar freewheeling through ohmic contact between the top metal layer (9) and the first conductive type source region (7), reduces the freewheeling voltage, and thus improves the freewheeling loss. On the one hand, it can avoid the impact of the chip area on the freewheeling of the device by embedding an SBD inside or connecting an external anti-parallel SBD, thereby reducing the system cost; on the other hand, it can avoid the high freewheeling loss, high reverse recovery loss and bipolar degradation caused by the device freewheeling through the internal body diode conduction, thereby improving the efficiency and reliability of the power system.

[0027] Fifth, the low-loss vertical accumulation layer channel conductive trench MOSFET power device and preparation method of the present invention realizes shutdown by applying a negative bias voltage to the gate (6), thereby improving the design flexibility of the power system while reducing the shutdown time and reducing switching losses; at the same time, it can prevent the device from being mis-turned on, effectively improving the stability and reliability of the power system.

[0028] Sixth, the low-loss vertical accumulation layer trench MOSFET power device and its fabrication method of the present invention offer a simple fabrication process and high device feasibility. Compared to traditional trench MOSFET devices, which require complex fabrication processes, the power device proposed in this invention has a relatively simple structure, and the required single-step processes are currently highly mature, ensuring device stability and reliability while maintaining low fabrication costs.

[0029] To sum up, the low-loss vertical accumulation layer channel conduction type trench MOSFET power device and preparation method of the present invention can realize unipolar freewheeling under small cell size and low specific on-resistance conditions, greatly reduce the conduction loss and reverse freewheeling loss of the power device, avoid bipolar degradation problems, improve the economy of the device, and have relatively high reliability and feasibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of a fourth embodiment of a cell in the design of a low-loss power device according to the present invention;

[0031] Figure 2 This is a schematic diagram of a fifth embodiment of a cell in the design of a low-loss power device according to the present invention;

[0032] Figure 3 This is a schematic diagram of a sixth embodiment of a cell in the design of a low-loss power device according to the present invention;

[0033] Figure 4 This is a schematic diagram of a seventh embodiment of a cell in the design of a low-loss power device according to the present invention;

[0034] Figure 5 This is a schematic diagram of an eighth embodiment of a cell in the design of a low-loss power device according to the present invention;

[0035] Figure 6 1 is a schematic diagram of a vertical column embodiment of the cell distribution in a low-loss power device designed according to the present invention;

[0036] Figures 7a to 7c 1 is a schematic diagram of a third embodiment of the present invention for designing a low-loss power device with cell distribution;

[0037] Figure 8 This is the process flow of the second embodiment of the preparation method of the low-loss power device designed by the present invention;

[0038] Figure 9 for Figure 8 State diagram of step S02 in the preparation process of a power device with low loss;

[0039] Figure 10 for Figure 8 State diagram of step S03 in the process of preparing a power device with low loss;

[0040] Figure 11 for Figure 8 State diagram of step S04 in the preparation process of a power device with low loss;

[0041] Figure 12 for Figure 8 State diagram of step S05 in the process of preparing a power device with low loss;

[0042] Figure 13 for Figure 8 State diagram of step S06 in the process of preparing a power device with low loss;

[0043] Figure 14 for Figure 8 State diagram of step S07 in the preparation process of a low-loss power device.

[0044] Among them, 1. bottom metal layer, 2. first conductive type substrate layer, 3. first conductive type epitaxial layer, 4. second conductive type deep well region, 5. gate dielectric layer, 6. gate, 7. first conductive type source region, 8. interlayer dielectric, 9. top metal layer, 10. JFET layer. DETAILED DESCRIPTION

[0045] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

[0046] Although the present invention specifies in the embodiments that the doping type of each region is the first conductivity type or the second conductivity type, those skilled in the art will appreciate that, in other embodiments, the doping type of each region is not limited to the first conductivity type or the second conductivity type specified in the present invention. For example, the first conductivity type and the second conductivity type can be interchanged. The polygons referred to in the present invention may be regular polygons or irregular polygons, and the circles referred to may be perfect circles or imperfect circles.

[0047] Example 1

[0048] The power device of this embodiment includes a bottom metal layer 1, a first conductive type substrate 2, a first conductive type epitaxial layer 3, a second conductive type deep well region 4, a first conductive type source region 7, a gate dielectric layer 5, a gate 6, an interlayer dielectric 8, a top metal layer 9, and a first conductive type JFET region 10. The first conductive type substrate 2 has a first ion doping concentration (e.g., 1×10 19 cm -3 ), the first conductive type epitaxial layer 3 has a second ion doping concentration (for example, 5×10 15 cm -3 ); the first conductive type source region 7 is located on both sides of the gate 6 and the gate dielectric layer 5, and the second conductive type deep well region 4 is respectively located below the gate dielectric layer 5 and on both sides of the cell near the upper surface of the first conductive type epitaxial layer 3; the first conductive type source region 7 has a third doping concentration higher than the second doping concentration (for example, 1×10 19 cm -3 ); the second conductive type deep well region 4 has a fourth ion doping concentration (eg 5×10 18 cm -3 ), the first ion doping concentration may be greater than or equal to the fourth ion doping concentration; the first conductive type JFET region 10 has a fifth doping concentration (e.g., 1×10 16 cm -3 The bottom of the second conductive type deep well region 4 exceeds the bottom of the gate dielectric layer 5, and the length of the excess is not limited to a specific value; the width of the first conductive type source region 7 is greater than the width of both sides of the interlayer dielectric 8.

[0049] It should be pointed out that there are no strict restrictions on the size and shape of the second conductive type deep well region 4 and the depth and shape of the gate trench (first trench). The bottom metal 1 forms an ohmic contact with the lower surface of the first conductive type substrate 2; the top metal 9 forms an ohmic contact with the first conductive type source region 7 and forms an ohmic contact with the second conductive type deep well region 4; in view of the depth of the second conductive type deep well region 4, when the device is in the reverse withstand voltage working state, the electric field peak will be drawn to the depletion layer of the first conductive type epitaxial layer 3 and the second conductive type deep well region 4, away from the gate dielectric layer 5. At the same time, due to the JFET effect formed between the second conductive type deep well region 4, the leakage current is reduced and the gate dielectric layer 5 interface is protected without affecting the conduction loss of the device. The cell structure of the present invention does not set a second conductive type base region, and does not form an inversion layer channel through the surface of the second conductive type base region for conduction. Instead, an accumulation layer conductive channel is formed through the first conductive type JFET layer 10 on the outer surface of the trench sidewall.

[0050] Example 2

[0051] This embodiment provides a method for preparing a low-loss vertical accumulation layer channel conduction type trench MOSFET power device, the preparation method comprising the following steps:

[0052] S01, obtaining a substrate of a first conductive type.

[0053] S02 , forming a first conductive type epitaxial layer on a first conductive type substrate.

[0054] S03, ion implantation: By means of ion implantation, a first conductivity type JFET region and a first conductivity type source region are formed at corresponding positions on the upper surface of the first conductivity type epitaxial layer, and annealing is performed.

[0055] S04, etching to form gate trenches. A corresponding position on the upper surface of the first conductivity type epitaxial layer is bombarded with plasma, such as SF6 or Br2, to form a trench structure. The etching method described in this step is not limited thereto; wet etching or dry etching using other plasma bombardment methods may also be used to achieve the desired effect. The depth of the etched trench is not limited to a specific value.

[0056] S05, ion implantation. Ion implantation is used to form a second conductivity type deep well region below the gate trench and on both sides of the cell and then annealed. The depth is not limited to a specific value, but should ensure that an electric field can be attracted to protect the gate oxide interface.

[0057] S06, using chemical vapor deposition to sequentially deposit a gate dielectric layer, a gate, and an interlayer dielectric, ensuring that the interlayer dielectric can effectively isolate the gate from the top metal layer and that the width of the interlayer dielectric on both sides does not exceed the width of the first conductive type source region on both sides.

[0058] S07: Using a sputtering process, a top metal layer is formed on the top and a bottom metal layer is formed on the bottom. The top metal layer forms an ohmic contact with the upper surface of the first conductive type epitaxial layer, and the bottom metal layer forms an ohmic contact with the lower surface of the first conductive type substrate layer. The materials of the top metal layer 9 and the bottom metal layer 1 include, but are not limited to, titanium, nickel, and molybdenum.

[0059] Compared with the traditional field effect transistor manufacturing process, the low-loss power device manufacturing process provided in this embodiment achieves optimization in terms of forward conduction loss, reverse freewheeling loss, etc. while simplifying the process steps.

[0060] Example 3

[0061] The multiple cells can be arranged separately or periodically. This embodiment provides a power device, the top view of which is a triangle, a quadrilateral, or a hexagon arranged periodically. Figure 7a 、 Figure 7b 、 Figure 7c As shown, the parts framed by dotted lines are the cellular regions described in Example 1.

[0062] Example 4

[0063] The shape of the second conductive type deep well region is not limited to a single shape well region. This embodiment provides another low-loss power device, the cell cross section is as follows Figure 1 Compared with the cell structure described in Example 1, in this embodiment, the second conductivity type deep well regions on both sides of the cell are stepped, and the protruding portions of the second conductivity type region below them enhance the JFET effect between the second conductivity type deep well region below the trench and the second conductivity type deep well regions on both sides of the cell. Therefore, the device can reduce the leakage current in the blocking state without substantially affecting other electrical parameters, thereby increasing the reliability of the device.

[0064] Example 5

[0065] The width of the second conductive type deep well region on both sides of the bottom of the first trench can be consistent with or inconsistent with the width of the first trench, and the bottom edge of the second conductive type deep well region at the bottom of the first trench can be aligned with or not aligned with the bottom edge of the second conductive type deep well region 4 on both sides of the cell. This embodiment provides another low-loss power device, the cell cross section is as follows Figure 2 Compared with the cell structure described in Example 1, in this embodiment, the width of the second conductivity type deep well region on both sides below the first trench exceeds the width of the first trench structure. This not only strengthens the protection of the corners at the bottom of the first trench, but also enhances the JFET effect between the second conductivity type deep well region below the first trench and the second conductivity type deep well regions on both sides of the cell, effectively reducing the electric field concentration effect and leakage current at the corners of the first trench in the blocking state, thereby increasing the reliability of the device.

[0066] Example 6

[0067] This embodiment provides another low-loss power device, the cell cross section of which is as follows: Figure 3 Compared to the cell structure described in Example 1, in this embodiment, a first conductivity type region of a predetermined shape and size is constructed below the first trench. This region effectively prevents the adverse effects of the JFET effect on the on-resistance caused by the second conductivity type deep well region below the first trench and the second conductivity type deep well regions on both sides of the cell in the on-state, further reducing conduction losses without substantially affecting the blocking characteristics and device reliability.

[0068] Example 7

[0069] This embodiment provides another low-loss power device, the cell cross section of which is as follows: Figure 4 Compared to the cellular structure described in Example 1, in this embodiment, the shape of the first trench structure is replaced with a trapezoidal structure. Under this trench shape, the crystal plane where the vertical accumulation layer channel is located can be freely selected, thereby greatly alleviating the increase in conduction loss caused by low channel mobility due to carrier capture by interface states or interface traps. It should be noted that the overall shape of the first trench includes but is not limited to triangle, rectangle, trapezoid, etc.

[0070] Example 8

[0071] The top metal does not necessarily have to completely cover the upper surface of the cell. A groove-shaped top metal structure can be constructed on both sides of the cell, and a second conductivity type deep well region can be constructed along the top metal and deep into the outer edge of the inner part of the cell. This embodiment provides another low-loss power device, whose cell cross section is as follows: Figure 5 The top metal comprises a first metal portion horizontally covering the top surface of the cell, and second and third metal portions filling the second trenches on both sides of the cell. A second conductivity type deep well region is wrapped around the outer edges of the second and third metal portions. The bottom edges of the second conductivity type deep well regions on both sides of the constructed cell may be aligned or not aligned with the bottom edges of the second conductivity type deep well regions below the first trenches.

[0072] Compared with the cell structure described in Example 1, in this embodiment, second trench structures are etched on both sides of the cell and filled with top metal. A second conductive type region of a preset thickness is wrapped around the periphery of the structure. The depth of the second trenches on both sides can exceed the depth of the first trench in the middle of the cell. The second trenches on both sides are used to change the shape of the depletion layer in the blocking state to alleviate the electric field concentration at the bottom corner of the gate trench (first trench), while not exacerbating the JFET effect of the second conductive type deep well region below the first trench and the second conductive type deep well region on both sides of the cell in the on state. In addition, the deeper trenches on both sides are equivalent to reducing the effective epitaxial layer thickness, thereby further reducing the conduction loss, ensuring low conduction loss while achieving high reliability of the device.

[0073] The low-loss vertical accumulation layer channel conductive trench MOSFET power device designed by the present invention obtains a higher channel mobility than the inversion layer channel through the conduction of the vertical accumulation layer channel, and at the same time sets a surface JFET region, thereby greatly reducing the conduction loss of the device; provides a unipolar freewheeling path, reduces the freewheeling loss, and avoids the problem of bipolar degradation; in addition, the present invention is designed to set up a second conductive type deep well region, reduce the leakage current through the JFET effect, and protect the gate dielectric layer by reducing the electric field at the gate dielectric layer; in addition, the device process is simple, with high economic efficiency and high feasibility. In summary, in the design of the present invention, a vertical accumulation layer conductive channel and a unipolar freewheeling path are constructed through a simple process, without affecting the reliability of the device, so that the device has the advantages of low conduction loss, small cell size, low freewheeling loss, no bipolar degradation, high economy and feasibility.

[0074] The applicant has not illustrated all the situations in the specification. Those skilled in the art should know that Figures 1 to 7c Any combination of the innovative points described in the illustrated embodiments should also be understood as the technical solutions or embodiments disclosed in the present invention. Although the innovative points of the present invention such as vertical accumulation layer conduction and unipolar freewheeling have been described and explained above, it should be understood that the technology described in the present invention is also applicable to other power devices with similar structures, and the technology disclosed in the present invention can be used for any appropriate power device. Those skilled in the art can add appropriate areas and structures to the structures shown in the drawings of the present invention specification according to actual needs. Since the present invention can be implemented in various forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the aforementioned details, but should be broadly interpreted within the scope defined by the appended claims. Therefore, all changes and modifications that fall within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A low-loss vertical accumulation layer channel conduction type trench MOSFET power device, characterized in that: The device comprises an interlayer dielectric (8), a top metal layer (9), and a bottom metal layer (1), a first conductive type substrate layer (2), a first conductive type epitaxial layer (3), and a plurality of cells arranged in sequence from bottom to top; the structures of the cells are identical to each other, and are all distributed on the upper surface of the first conductive type epitaxial layer (3) and extend downward to the interior of the first conductive type epitaxial layer (3) for arrangement; the interlayer dielectric (8) and the top metal layer (9) cover the upper surface of each cell; Each cell is provided with a first conductive type JFET layer (10), a first conductive type source region (7) and a first trench on the upper surface of the first conductive type epitaxial layer (3); a gate dielectric layer (5) of a preset thickness is provided on the inner wall of the first trench; a gate material (6) is filled in the inner sidewall of the gate dielectric layer (5); an interlayer dielectric (8) is provided above the gate material to isolate the gate material (6) from the top metal (9); second conductive type deep well regions (4) are provided on both sides of the cell near the upper surface of the first conductive type epitaxial layer (3) and below the first trench; the width of the top of the first trench is smaller than the width of the two sides of the interlayer dielectric (8), and the width of the bottom of the first trench is not greater than the width of the two sides of the second conductive type deep well region (4) below the first trench; the cell structure forms an accumulation layer conductive channel through the first conductive type JFET layer (10) on the outer surface of the first trench sidewall.

2. The low-loss vertical accumulation layer channel conduction type trench MOSFET power device according to claim 1, characterized in that: The overall shape of the first groove includes but is not limited to a triangle, a rectangle and a trapezoid.

3. The low-loss vertical accumulation layer channel conduction type trench MOSFET power device according to claim 1, characterized in that: The edges on both sides of the first conductive type source region (7) in the cell exceed the edges on both sides of the interlayer dielectric (8), and an ohmic contact is formed between the top metal layer (9) and the first conductive type source region (7).

4. The low-loss vertical accumulation layer channel conduction type trench MOSFET power device according to claim 1, characterized in that: The top metal (9) horizontally covers the upper surface of the cell.

5. The low-loss vertical accumulation layer channel conduction type trench MOSFET power device according to claim 1, characterized in that: The top metal (9) includes a first metal portion horizontally covering the upper surface of the cell, and a second metal portion and a third metal portion filled in the second grooves on both sides of the cell, and a second conductive type deep well region (4) is wrapped along the outer edges of the second metal portion and the third metal portion.

6. The low-loss vertical accumulation layer channel conduction type trench MOSFET power device according to claim 5, characterized in that: The depth of the second grooves on both sides of the cell exceeds the depth of the first groove in the middle of the cell.

7. The low-loss vertical accumulation layer channel conduction type trench MOSFET power device according to claim 1, characterized in that: A first conductive type region is constructed below the first trench.

8. The low-loss vertical accumulation layer channel conduction type trench MOSFET power device according to claim 1, characterized in that: The second conductive type deep well regions on both sides of the cell are in a step shape, and a protrusion is provided on the side of the second conductive type region below the cell facing the first trench.

9. The low-loss vertical accumulation layer channel conduction type trench MOSFET power device according to claim 1, characterized in that: The multiple cells are arranged periodically.

10. A method for preparing a low-loss vertical accumulation layer channel conductive type trench MOSFET power device based on any one of claims 1 to 9, characterized in that: The preparation method comprises the following steps: S1, taking a first conductive type substrate (2), and forming a first conductive type epitaxial layer (3) above the substrate; S2, forming a first conductive type JFET region (4) and a first conductive type source region (7) on the surface of the first conductive type epitaxial layer (3) by an ion implantation process and performing annealing; S3, forming a first trench within each first conductivity type source region (7) on the surface of the first conductivity type epitaxial layer (3) by an etching process; S4, forming a second conductive type deep well region (4) on both sides of the cell and below the first trench by ion implantation; S5, depositing a gate dielectric layer (5) on the inner sidewall of the first trench by a chemical vapor deposition process, depositing a gate electrode (6) on the inner sidewall of the gate dielectric layer (5) by a chemical vapor deposition process, and depositing an oxide layer on the surface and both sides of the gate electrode (6) to form an interlayer dielectric (8); S6, forming a top metal layer (9) on the upper surface of the cell using a sputtering process, and making a bottom metal (1) on the other surface of the first conductive type substrate (2).

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