Power semiconductor device and method of manufacturing the same
By adopting an asymmetric trench gate structure and a split gate design in power semiconductor devices, the problem of the gate structure in the existing technology being difficult to simultaneously optimize switching speed and on-resistance is solved, achieving performance improvements in high-voltage and high-current applications.
Patent Information
- Application Number
- CN202410340804.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-25
- Publication Date
- 2025-10-03
AI Technical Summary
The gate structure design of existing power semiconductor devices faces bottlenecks in switching speed and on-resistance in high voltage and high current applications, making it difficult to optimize both simultaneously.
An asymmetric trench gate structure is adopted, including a split gate and gate oxide layers of different thicknesses, combined with a shielding area design to optimize the direction and angle of the channel area, enhance current density and shield strong electric fields.
The breakdown voltage and on-resistance performance of power semiconductor devices are improved, and the switching speed and current density are increased.
Smart Images
Figure CN120751738A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a power semiconductor device, and more particularly to a power semiconductor device having a trench gate structure. Background Art
[0002] With advances in semiconductor technology, the application of metal-oxide-semiconductor field-effect transistors (MOSFETs) is becoming increasingly widespread. Power semiconductors can be used as switches in electronic components. They are used in high-voltage and high-current device designs. The switching speed and on-resistance of power semiconductors are closely related to the design of their gate structure. Summary of the Invention
[0003] A technical aspect of the present disclosure is a power semiconductor device.
[0004] In one embodiment of the present disclosure, a power semiconductor device includes a drain metal, a base layer located on the drain metal, an epitaxial layer located on the base layer, a gate structure, a source / drain doped region, a shielding region, a gate oxide layer, and a source metal located on the epitaxial layer. The epitaxial layer has a first conductivity type. The gate structure is located in the epitaxial layer. The gate structure is asymmetric in the laterally direction. The gate structure includes a first gate and a second gate, and the second gate is located above the first gate. The source / drain doped region is located in the epitaxial layer adjacent to a first side of the second gate. The shielding region is located in the epitaxial layer and at least surrounds the first gate and has a second conductivity type. The gate oxide layer is located between the gate structure and the epitaxial layer.
[0005] In one embodiment, the first gate and the second gate are separated from each other, and the first gate is electrically connected to the source metal.
[0006] In one embodiment, a first center position of the first gate in the transverse direction is offset from a second center position of the second gate in the transverse direction.
[0007] In one embodiment, the power semiconductor device further includes a first gate oxide layer and a second gate oxide layer. The first gate oxide layer is located between the shielding region and the first gate and between the epitaxial layer adjacent to a second side of the second gate and the second gate, wherein the first side and the second side are opposite. The second gate oxide layer is located between the source / drain doped region and the first side of the second gate.
[0008] In one embodiment, the second thickness of the second gate oxide layer is smaller than the first thickness of the first gate oxide layer.
[0009] Another technical aspect of the present disclosure is a method for manufacturing a semiconductor device.
[0010] In one embodiment of the present disclosure, a method for manufacturing a power semiconductor device includes forming an epitaxial layer on a base layer, wherein the epitaxial layer has a first conductivity type; forming a first trench in the epitaxial layer, wherein the first trench has trench sidewalls; implanting the trench sidewalls to form a shielding region, wherein the shielding region has a second conductivity type and surrounds at least a lower portion of the trench sidewalls; forming a source / drain doped region in the epitaxial layer adjacent to an upper portion of the trench sidewalls; forming a second trench so that the second trench is asymmetric in the laterally direction; forming a gate oxide layer in the first trench and the second trench; and forming a gate structure in the first trench and the second trench.
[0011] In one embodiment, forming a second trench so that the second trench is asymmetric in the laterally direction further includes removing the epitaxial layer of the first sidewall located at the upper portion of the trench sidewall to form a third sidewall of the second trench, wherein a first distance from the first sidewall to the second sidewall is less than a second distance from the third sidewall to the second sidewall, the third sidewall is opposite to the second sidewall, and the third sidewall is connected to the first sidewall.
[0012] In one embodiment, forming the gate oxide layer in the first trench and the second trench includes forming a first gate oxide layer in the first trench; and after forming the second trench, forming a second gate oxide layer on a third sidewall of the second trench.
[0013] In one embodiment, forming the gate oxide layer in the first trench and the second trench further includes making the second thickness of the second gate oxide layer smaller than the first thickness of the first gate oxide layer.
[0014] In one embodiment, forming the gate structure in the first trench and the second trench includes forming a first gate oxide layer in the first trench and then forming the first gate in the first gate oxide layer; and forming a second gate oxide layer in the third sidewall of the second trench and then forming the second gate.
[0015] In the above-mentioned embodiment, the semiconductor device with a trench gate structure has a longitudinal channel region to increase the current density. The direction and angle of the channel region can be determined by the sidewall of the trench that accommodates the second gate. By setting a shielding region, the strong electric field in the vertical power semiconductor device can be shielded. By setting gate oxide layers with different thicknesses and setting a split gate, the breakdown voltage can be increased. The present disclosure can integrate the steps of forming a channel region with a specific direction and angle, a gate oxide layer with different thicknesses, and a split gate to optimize the process of the power semiconductor device. The doping concentration and area size of the shielding region can be varied to adjust the on-resistance and breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 FIG. 4 is a cross-sectional view of a power semiconductor device according to an embodiment of the present disclosure.
[0017] Figures 2 to 6 for Figure 1 A cross-sectional view of an intermediate step in a method for manufacturing a power semiconductor device. DETAILED DESCRIPTION
[0018] The following will disclose multiple embodiments of the present invention with the accompanying drawings. For the purpose of clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention.
[0019] Figure 1 FIG1 is a cross-sectional view of a power semiconductor device 100 according to an embodiment of the present disclosure. The power semiconductor device 100 includes a drain metal 110 , a base layer 120 , an epitaxial layer 130 , a gate structure 140 , a source / drain doped region 150 , a shielding region 160 , a gate oxide layer 170 , and a source metal 180 .
[0020] The base layer 120 is located on the drain metal 110, and is, for example, a silicon carbide (SiC) substrate. The epitaxial layer 130 is located on the base layer 120 and has a first conductivity type (N-type). The gate structure 140 is located in the epitaxial layer 130. For example, the power semiconductor device 100 in this embodiment is an N-type metal oxide semiconductor field effect transistor (MOSFET). The base layer 120 is an N-type heavily doped substrate (N+). The doping concentration of the epitaxial layer 130 is lower than the doping concentration of the base layer 120 (N-). The epitaxial layer 130 can serve as a drift region between the source S and the drain D.
[0021] The gate structure 140 is asymmetric in the horizontal direction D1. The gate structure 140 includes a first gate 142 and a second gate 144, with the second gate 144 positioned above the first gate 142. The first gate 142 and the second gate 144 are separated from each other, forming a split gate. The second gate 144 is a gate poly, while the first gate 142 is a shielding electrode electrically connected to the source metal 180. The second width W2 of the second gate 144 is greater than the first width W1 of the first gate 142. The first center position C1 of the first gate 142 in the horizontal direction D1 is offset from the second center position C2 of the second gate 144 in the horizontal direction D1.
[0022] The source / drain doped region 150 is located in the epitaxial layer 130 adjacent to the first side 1442 of the second gate 144. The source / drain doped region 150 includes a source region 152 having a first conductivity type (N+) and a well 154 having a second conductivity type (P). The source region 152, the well 154, and the second gate 144 form a channel region 156. In other words, the power semiconductor device 100 is a semiconductor device having a single-sided trench gate structure.
[0023] The shielding region 160 is located in the epitaxial layer 130 and surrounds at least the first gate 142 and has the second conductivity type (P+). The shielding region 160 includes a first shielding region 162, a second shielding region 164, and a third shielding region 166 that are connected to each other. The shielding region 160 is formed by an implantation step. The first shielding region 162 is formed in the epitaxial layer 130 adjacent to the first side 1422 of the first gate 142, and the second shielding region 164 is formed in the epitaxial layer 130 adjacent to the second side 1424 of the first gate 142. The first shielding region 162 is located below the channel region 156. The third shielding region 166 is formed in the epitaxial layer 130 at the bottom of the first gate 142. In this embodiment, the second shielding region 164 extends into the epitaxial layer 130 adjacent to the second side 1444 of the second gate 144, but the present disclosure is not limited to this.
[0024] Gate oxide layer 170 is located between gate structure 140 and epitaxial layer 130. Source metal 180 is located on epitaxial layer 130. Gate oxide layer 170 includes a first gate oxide layer 172 and a second gate oxide layer 174. First gate oxide layer 172 is located between first shielding region 162, second shielding region 164, third shielding region 166, and first gate 142, and between epitaxial layer 130 and second gate 144 adjacent to second side 1444 of second gate 144. Second gate oxide layer 174 is located between source / drain doped region 150 and first side 1442 of second gate 144. Second gate oxide layer 174 has a second thickness T2 that is less than first thickness T1 of first gate oxide layer 172.
[0025] Since the gate structure 140 is a trench structure, the channel region 156 is oriented vertically rather than horizontally, which increases the density of the gate structure 140 and improves the current density. The shielding region 160 can shield the strong electric field in the vertical power semiconductor device.
[0026] The shielding region 160 may include a plurality of first shielding regions 162. The length and spacing of the first shielding regions 162 may be configured according to actual needs to adjust the on-resistance and breakdown voltage of the power semiconductor device 100.
[0027] Figure 1As shown in FIG, the first side 1442 of the second gate 144 is relatively protruding, so the direction and angle of the channel region 156 are determined by the trench sidewall 190 that accommodates the second gate 144. The trench sidewall 190 includes a first sidewall 192, a second sidewall 194, and a third sidewall 196. The first sidewall 192 is adjacent to the first side 1422 of the first gate 142. The third sidewall 196 is adjacent to the first side 1442 of the second gate 144. The second sidewall 194 is adjacent to both the second side 1424 of the first gate 142 and the second side 1444 of the second gate 144. The third sidewall 196 is opposite the second sidewall 194. The first sidewall 192 is opposite the second sidewall 194. A curved sidewall 198 is defined between the first sidewall 192 and the third sidewall 196. The first sidewall 192 corresponds to the lower portion of the trench sidewall 190, and the third sidewall 196 corresponds to the upper portion of the trench sidewall 190. The second sidewall 194 covers the upper portion and the lower portion of the trench sidewall 190. The slopes of the second sidewall 194 are substantially the same.
[0028] The shielding region 160 at least surrounds the lower portion of the trench sidewall 190. In this embodiment, the second shielding region 164 extends to the upper portion of the trench sidewall 190 and is adjacent to the second sidewall 194. The first shielding region 162 is adjacent to the third sidewall 196.
[0029] A first distance L1 between the first sidewall 192 and the second sidewall 194 in the horizontal direction D1 is less than a second distance L2 between the third sidewall 196 and the second sidewall 194 in the horizontal direction D1. The first gate 142 is accommodated in the first trench TR1, and the second gate 144 is accommodated in the second trench TR2. The first distance L1 is equivalent to the average width of the first trench TR1 accommodating the first gate 142, and the second distance L2 is equivalent to the average width of the second trench TR2 accommodating the second gate 144.
[0030] The vertical projection of the second gate 144 formed in the second trench TR2 on the base layer 120 overlaps with the vertical projection of the first shielding region 162 on the base layer 120. The second trench TR2 is formed by etching the first trench TR1, which will be described in detail later.
[0031] In other embodiments, one of the first shielding region 162, the second shielding region 164, and the third shielding region 166 has a higher doping concentration. In other embodiments, the outer sides of the first shielding region 162 and the second shielding region 164 further include doped regions of the first conductivity type (N-type) (not shown), which are arranged corresponding to the first shielding region 162 and the second shielding region 164. The length, spacing, and interleaving distance of the doped regions of the first conductivity type (N-type) with respect to the first shielding region 162 and the second shielding region 164 can be configured according to actual needs to adjust the on-resistance and breakdown voltage of the power semiconductor device 100.
[0032] Figures 2 to 6 for Figure 1 1 is a cross-sectional view of an intermediate step in a method for manufacturing a power semiconductor device 100. The connection relationship, materials, and functions of the components already described will not be repeated, but will be explained first.
[0033] See Figure 2 The method for manufacturing the power semiconductor device 100 begins by providing an epitaxial layer 130 on a base layer 120. Next, a first trench TR1 is formed in the epitaxial layer 130. The steps of forming the first trench TR1 may include patterning a photoresist layer (not shown), etching a mask layer 200 through the photoresist layer, removing the photoresist layer, and finally etching the epitaxial layer 130. The first trench TR1 is formed by patterning the mask layer 200. The mask layer 200 may be made of, for example, tetraethoxysilane (TEOS). Next, implantation is performed in the first trench TR1 to form a first shielding region 162, a second shielding region 164, and a third shielding region 166 of the second conductivity type (P-type). The method for manufacturing the power semiconductor device 100 continues by forming the source / drain doped regions 150 in the epitaxial layer 130 adjacent to the upper portion of the trench sidewalls 190.
[0034] The manufacturing method of the power semiconductor device 100 continues by forming a first gate oxide layer 172 in the first trench TR1. The first gate oxide layer 172 has a first thickness T1. The first gate oxide layer 172 covers the first sidewall 192, the second sidewall 194, and the bottom of the first trench TR1. In one embodiment, the first gate oxide layer 172 is formed by thermal oxidation at a temperature of 1000 to 1600 degrees Celsius. In another embodiment, the first gate oxide layer 172 is formed by atomic layer deposition (ALD) of silicon dioxide.
[0035] See Figure 3 The manufacturing method of the power semiconductor device 100 continues with filling the polysilicon material 140M in the first trench TR1 (see Figure 2 ) and covers the first gate oxide layer 172 and the mask layer 200. The polysilicon material 140M is formed by a low pressure chemical vapor deposition (LPCVD) process.
[0036] The manufacturing method of the power semiconductor device 100 continues by forming another mask layer 300 on the polysilicon material 140M and patterning the mask layer 300 through the photoresist layer 400. Then, the polysilicon material 140M is patterned through the mask layer 300. The material of the mask layer 300 is the same as that of the mask layer 200.
[0037] See Figure 4The manufacturing method of the power semiconductor device 100 continues with forming the extension structure 146 that electrically connects the polysilicon material 140M to the source metal 180. The photoresist layer 400 is then removed.
[0038] See Figure 5 The manufacturing method of the power semiconductor device 100 continues with etching the polysilicon material 140M (see Figure 3 ) to form the first gate 142. The above steps are equivalent to forming the first gate 142 in the first gate oxide layer 172. The method for manufacturing the power semiconductor device 100 continues by forming a patterned mask layer 200 through the photoresist layer 500. The photoresist layer 500 has a tilt angle θ, so the mask layer 200 after etching also has a tilt angle θ. For example, the tilt angle θ is approximately 15 degrees relative to the vertical direction, but the present disclosure is not limited to this. The photoresist layer 500 and the mask layer 200 determine the shallow trench region R where the second trench TR2 is subsequently formed.
[0039] See Figure 6 The manufacturing method of the power semiconductor device 100 continues with forming the second trench TR2, and making the second trench TR2 asymmetric in the lateral direction D1. The step of forming the second trench TR2 includes: Figure 5 In the shallow trench region R shown in FIG, the epitaxial layer 130 on the first sidewall 192 located above the trench sidewall 190 is removed to form a third sidewall 196. This step is also equivalent to removing a portion of the epitaxial layer 130 located above the first shielding region 162.
[0040] See Figure 1 The manufacturing method of the power semiconductor device 100 continues by forming a second gate oxide layer 174 in the second trench TR2 and removing the photoresist layer 500. The second gate oxide layer 174 is located above the first gate 142 and on the third sidewall 196. The portion of the second gate oxide layer 174 located on the third sidewall 196 has a second thickness T2, which is less than the first thickness T1. By providing gate oxide layers 170 with different thicknesses, the breakdown voltage can be increased.
[0041] The manufacturing method of the power semiconductor device 100 continues by forming a second gate 144 in the second trench TR2. This step may include first forming polysilicon material using a low-pressure chemical vapor deposition (LPCVD) process, and then removing the portion outside the second trench TR2 using etching or chemical mechanical polishing. The direction and angle of the channel region 156 are determined by the third sidewall 196.
[0042] The above steps are equivalent to forming the gate oxide layer 170 in the first trench TR1 and the second trench TR2 and forming the gate structure 140 in the first trench TR1 and the second trench TR2 . Finally, a source metal 180 is formed on the epitaxial layer 130 and the gate structure 140 .
[0043] In summary, a semiconductor device with a trench gate structure makes the channel region vertical, thereby increasing the current density. The direction and angle of the channel region can be determined by the sidewalls of the trench that accommodates the second gate. By providing a shielding region, the strong electric field in the vertical power semiconductor device can be shielded. By providing gate oxide layers with different thicknesses and providing a split gate, the breakdown voltage can be increased. The present disclosure can integrate the steps of forming a channel region with a specific angle, gate oxide layers with different thicknesses, and a split gate to optimize the process of high-power semiconductor devices. The doping concentration and area size of the shielding region can be varied to adjust the on-resistance and breakdown voltage.
[0044] Although the present invention has been disclosed above in terms of embodiments, this is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
[0045]
Explanation of symbols
[0046] 100: Power semiconductor device
[0047] 110: Drain metal
[0048] 120: basal layer
[0049] 130: epitaxial layer
[0050] 140: Gate structure
[0051] 140M: Polysilicon material
[0052] 142: first gate
[0053] 144: Second gate
[0054] 1422,1442: First side
[0055] 1424,1444: Second side
[0056] 146: Extended structure
[0057] 150: Source / drain doping region
[0058] 152: Source region
[0059] 154: Trap
[0060] 156: Channel Area
[0061] 160: Sheltered area
[0062] 162: First sheltered area
[0063] 164: Second sheltered area
[0064] 166: Third Shelter Area
[0065] 170: Gate oxide layer
[0066] 172: first gate oxide layer
[0067] 174: Second gate oxide layer
[0068] 180: Source Metal
[0069] 190: Groove sidewall
[0070] 192: first side wall
[0071] 194: Second side wall
[0072] 196: Third side wall
[0073] 198:Curved sidewall
[0074] 200,300: mask layer
[0075] 400,500: Photoresist layer
[0076] W1: first width
[0077] W2: Second width
[0078] C1: First center position
[0079] C2: Second center position
[0080] T1: First thickness
[0081] T2: Second thickness
[0082] D1: Horizontal
[0083] TR1: First groove
[0084] TR2: Second groove
[0085] L1: First distance
[0086] L2: Second distance
[0087] θ: tilt angle
[0088] R: Shallow trench area.
Claims
1. A power semiconductor device, characterized in that: Include: drain metal; a base layer located on the drain metal; an epitaxial layer located on the base layer and having a first conductivity type; A gate structure located in the epitaxial layer, wherein the gate structure is asymmetric in the laterally direction and comprises a first gate and a second gate, wherein the second gate is located above the first gate; a source / drain doped region located in the epitaxial layer adjacent to the first side of the second gate; a shielding region located in the epitaxial layer and at least surrounding the first gate and having a second conductivity type; a gate oxide layer located between the gate structure and the epitaxial layer; as well as The source metal is located on the epitaxial layer.
2. The power semiconductor device according to claim 1, wherein: The first gate and the second gate are separated from each other, and the first gate is electrically connected to the source metal.
3. The power semiconductor device according to claim 1 or 2, characterized in that: A first center position of the first grid in the horizontal direction is staggered with a second center position of the second grid in the horizontal direction.
4. The power semiconductor device according to claim 1 or 2, characterized in that: Also includes: a first gate oxide layer located between the shielding region and the first gate and between the epitaxial layer adjacent to a second side of the second gate and the second gate, wherein the first side is opposite to the second side; and The second gate oxide layer is located between the source / drain doping region and the first side of the second gate.
5. The power semiconductor device according to claim 4, wherein: The second thickness of the second gate oxide layer is smaller than the first thickness of the first gate oxide layer.
6. A method for manufacturing a power semiconductor device, characterized in that: Include: forming an epitaxial layer on the base layer, wherein the epitaxial layer has a first conductivity type; forming a first trench in the epitaxial layer, wherein the first trench has a trench sidewall; implanting the trench sidewall to form a shielding region, wherein the shielding region has the second conductivity type and surrounds at least a lower portion of the trench sidewall; forming source / drain doped regions in the epitaxial layer adjacent to upper portions of the trench sidewalls; forming a second groove so that the second groove is asymmetric in a transverse direction; forming a gate oxide layer in the first trench and the second trench; as well as A gate structure is formed in the first trench and the second trench.
7. The method for manufacturing a power semiconductor device according to claim 6, wherein: Forming the second trench so that the second trench is asymmetric in the lateral direction further comprises: The epitaxial layer of the first sidewall located at the upper portion of the trench sidewall is removed to form a third sidewall of the second trench, wherein a first distance from the first sidewall to the second sidewall is smaller than a second distance from the third sidewall to the second sidewall, the third sidewall is opposite to the second sidewall, and the third sidewall is connected to the first sidewall.
8. The method for manufacturing a power semiconductor device according to claim 7, wherein: Forming the gate oxide layer in the first trench and the second trench includes: forming a first gate oxide layer in the first trench; and After forming the second trench, a second gate oxide layer is formed in the third sidewall of the second trench.
9. The method for manufacturing a power semiconductor device according to claim 8, wherein: Forming the gate oxide layer in the first trench and the second trench further includes: The second thickness of the second gate oxide layer is made smaller than the first thickness of the first gate oxide layer.
10. The method for manufacturing a power semiconductor device according to claim 8, wherein: Forming the gate structure in the first trench and the second trench includes: After forming the first gate oxide layer in the first trench, forming a first gate in the first gate oxide layer; and After forming the second gate oxide layer in the third sidewall of the second trench, a second gate is formed.