Heterojunction cell and method of manufacturing the same

Abstract

The application belongs to the field of heterojunction cells, and specifically discloses a heterojunction cell and a preparation method thereof. The corresponding area of the grid line electrode is deposited with heavy-doped amorphous silicon, so that the high parasitic absorption, surface dangling bond and interface state density are reduced, and the open voltage and the efficiency of the heterojunction cell are improved. The main technical scheme of the application is as follows: a heterojunction cell, the corresponding area of the grid line electrode on the front surface and the back surface of the N-type silicon substrate is provided with a groove; an intrinsic amorphous silicon layer is provided; a lightly-doped P-type amorphous silicon layer is arranged on the intrinsic amorphous silicon layer on the front surface, a lightly-doped N-type amorphous silicon layer is arranged on the intrinsic amorphous silicon layer on the back surface, a heavily-doped P-type amorphous silicon layer is arranged on the corresponding area of the groove of the lightly-doped P-type amorphous silicon layer, a heavily-doped N-type amorphous silicon layer is arranged on the corresponding area of the groove of the lightly-doped N-type amorphous silicon layer, a transparent conductive oxide layer is arranged on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer respectively, and the grid line electrode is arranged on the transparent conductive oxide layer. The application is mainly used for power generation.

Description

Technical Field

[0001] This invention relates to the field of heterojunction battery technology, and more particularly to a heterojunction battery and its preparation method. Background Technology

[0002] The mainstream heterojunction with intrinsic thin layer (HJT) solar cell consists of an N-type silicon substrate, bifacial intrinsic amorphous silicon layers, bifacial heavily doped amorphous silicon layers (back side N-type amorphous silicon: phosphorus-doped amorphous silicon forming the back surface field, front side P-type amorphous silicon: boron-doped amorphous silicon forming the emitter), bifacial TCO layers, and front and back gate lines. The bifacial heavily doped amorphous silicon layers, together with the bifacial intrinsic amorphous silicon thin films and the silicon substrate, form the pn heterojunction and the back surface field, which is the key structure for photoelectric conversion in HJT cells, effectively separating photogenerated carriers. However, the high doping concentration of N-type and P-type amorphous silicon leads to distortion of the amorphous silicon network structure, forming more dangling bonds, microvoids, and other structural defects, resulting in increased surface recombination and interface state density, as well as high parasitic absorption, ultimately reducing the turn-on voltage and affecting the efficiency of the heterojunction cell. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a heterojunction solar cell and a method for preparing the same, which is used to reduce the surface recombination and interface state density of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer of the heterojunction solar cell, while reducing the parasitic absorption of the film layer.

[0004] To achieve the above objectives, the present invention mainly provides the following technical solutions:

[0005] On one hand, embodiments of the present invention provide a heterojunction solar cell, comprising:

[0006] The N-type silicon substrate includes a front side and a back side, and the gate electrode corresponding areas on the front side and the back side of the N-type silicon substrate are respectively provided with grooves;

[0007] Intrinsic amorphous silicon layers are provided on the front and back sides of the N-type silicon substrate, respectively.

[0008] The P-type doped amorphous silicon layer includes a lightly doped P-type amorphous silicon layer, which is disposed on the intrinsic amorphous silicon layer on the front side.

[0009] The N-type doped amorphous silicon layer includes a lightly doped N-type amorphous silicon layer, which is disposed on the intrinsic amorphous silicon layer on the back side.

[0010] The P-type doped amorphous silicon layer also includes a heavily doped P-type amorphous silicon layer, which is disposed on the lightly doped P-type amorphous silicon layer and located in the corresponding region of the groove.

[0011] The N-type doped amorphous silicon layer also includes a heavily doped N-type amorphous silicon layer, which is disposed on the lightly doped N-type amorphous silicon layer and located in the corresponding region of the groove.

[0012] A transparent conductive oxide layer is disposed on a P-type doped amorphous silicon layer and an N-type doped amorphous silicon layer, respectively.

[0013] The gate electrodes are respectively disposed on the transparent conductive oxide layers on the front and back sides.

[0014] Among them, the intrinsic amorphous silicon layer covers the entire surface of the front and back sides of the N-type silicon substrate, respectively;

[0015] Lightly doped P-type amorphous silicon layers and lightly doped N-type amorphous silicon layers cover the entire surface of the intrinsic amorphous silicon layers on the front and back sides, respectively.

[0016] Transparent conductive oxide layers cover the entire surface of both the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer.

[0017] The thickness of the intrinsic amorphous silicon layer is 1–10 nm.

[0018] The thickness of the lightly doped P-type amorphous silicon layer is the same as that of the heavily doped P-type amorphous silicon layer, and the surface of the P-type doped amorphous silicon layer is planar.

[0019] The thickness of the lightly doped N-type amorphous silicon layer is the same as that of the heavily doped N-type amorphous silicon layer, and the surface of the N-type doped amorphous silicon layer is planar.

[0020] The thickness of the lightly doped P-type amorphous silicon layer is 2–15 nm.

[0021] The thickness of the lightly doped N-type amorphous silicon layer is 2–15 nm;

[0022] The thickness of the heavily doped p-type amorphous silicon layer is 2–15 nm.

[0023] The thickness of the heavily doped N-type amorphous silicon layer is 2–15 nm.

[0024] The doping concentration of the lightly doped p-type amorphous silicon layer is 10. 18 cm -3 ~10 19 cm -3 ;

[0025] The doping concentration of the lightly doped N-type amorphous silicon layer is 10. 18 cm -3 ~1019 cm -3 ;

[0026] The doping concentration of the heavily doped p-type amorphous silicon layer is 10. 20 cm -3 ~10 21 cm -3 ;

[0027] The doping concentration of the heavily doped N-type amorphous silicon layer is 10. 20 cm -3 ~10 21 cm -3 .

[0028] The width of the groove is greater than the width of the gate electrodes on the front and back sides.

[0029] The N-type silicon substrate has a textured surface on both the front and back sides.

[0030] On the other hand, the present invention also provides a method for preparing a heterojunction solar cell, for preparing a heterojunction solar cell as described in any of the above, the method comprising:

[0031] An N-type silicon substrate is provided, and the corresponding areas of the gate electrodes on the front and back sides of the N-type silicon substrate are grooved.

[0032] The N-type silicon substrate after grooving is sequentially subjected to double-sided pre-cleaning, damage layer removal, texturing, and post-cleaning to form a clean texturized silicon wafer surface.

[0033] Intrinsic amorphous silicon layers are deposited on the front and back sides of the texturized N-type silicon substrate;

[0034] A lightly doped P-type amorphous silicon layer is deposited on the surface of the intrinsic amorphous silicon layer on the front side, and a lightly doped N-type amorphous silicon layer is deposited on the surface of the intrinsic amorphous silicon layer on the back side.

[0035] Heavy doped P-type amorphous silicon is deposited on the surface of a lightly doped P-type amorphous silicon layer, and then heavy doped N-type amorphous silicon is deposited on the surface of a lightly doped N-type amorphous silicon layer.

[0036] Remove the heavily doped P-type amorphous silicon in the non-groove region on the surface of the lightly doped P-type amorphous silicon layer, and remove the heavily doped N-type amorphous silicon in the non-groove region on the surface of the lightly doped N-type amorphous silicon layer to form a P-type doped amorphous silicon layer and an N-type doped amorphous silicon layer.

[0037] The surfaces of P-type doped amorphous silicon layers and N-type doped amorphous silicon layers are texturized.

[0038] Transparent conductive oxide layers were deposited on the texturized P-type doped amorphous silicon layer and N-type doped amorphous silicon layer, respectively.

[0039] Gate electrodes are fabricated on transparent conductive oxide layers on the front and back sides.

[0040] The step of grooving the corresponding areas of the gate electrodes on the front and back sides of the N-type silicon substrate is to perform grooving on the corresponding areas of the gate electrodes on the front and back sides of the N-type silicon substrate based on picosecond laser.

[0041] The steps for removing the heavily doped P-type amorphous silicon in the non-groove region on the surface of a lightly doped P-type amorphous silicon layer and the heavily doped N-type amorphous silicon in the non-groove region on the surface of a lightly doped N-type amorphous silicon layer are as follows: the heavily doped P-type amorphous silicon in the non-groove region on the surface of a lightly doped P-type amorphous silicon layer and the heavily doped N-type amorphous silicon in the non-groove region on the surface of a lightly doped N-type amorphous silicon layer are removed by using a reactive ion etching device or a chain etching device, respectively.

[0042] The step of depositing transparent conductive oxide layers on the texturized P-type doped amorphous silicon layer and N-type doped amorphous silicon layer is as follows: transparent conductive oxide layers are deposited on the texturized P-type doped amorphous silicon layer and N-type doped amorphous silicon layer by magnetron sputtering or evaporation.

[0043] The step of fabricating gate electrodes on the transparent conductive oxide layers on the front and back sides is to fabricate gate electrodes on the transparent conductive oxide layers on the front and back sides using a screen printing device.

[0044] Beneficial effects

[0045] The heterojunction solar cell and its fabrication method proposed in this invention involve depositing lightly doped P / N type amorphous silicon on the intrinsic amorphous silicon on both the front and back sides. Heavy doped P-type amorphous silicon is deposited on the front side lightly doped P-type amorphous silicon in the region corresponding to the gate electrode, and heavy doped N-type amorphous silicon is deposited on the back side lightly doped N-type amorphous silicon in the region corresponding to the gate electrode. This method ensures that the gate electrode can normally collect photogenerated carriers and generate current, while reducing the high parasitic absorption caused by the heavy doped P / N type amorphous silicon on both sides, reducing surface dangling bonds and interface state density, increasing the turn-on voltage, and improving the efficiency of the heterojunction solar cell. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the first stage of the fabrication process of a heterojunction battery according to an embodiment of the present invention.

[0047] Figure 2 This is a schematic diagram of the second stage of the fabrication process of a heterojunction battery according to an embodiment of the present invention.

[0048] Figure 3 This is a schematic diagram of the third stage of the fabrication process of a heterojunction battery according to an embodiment of the present invention.

[0049] Figure 4 This is a schematic diagram of the fourth stage of the fabrication process of a heterojunction battery according to an embodiment of the present invention.

[0050] Figure 5 This is a schematic diagram of a heterojunction battery provided in an embodiment of the present invention;

[0051] Figure 6 A flowchart illustrating a method for fabricating a heterojunction solar cell according to an embodiment of the present invention;

[0052] Among them, N-type silicon substrate-100, groove-101, intrinsic amorphous silicon layer-110, lightly doped P-type amorphous silicon layer-120, heavily doped P-type amorphous silicon layer-130, lightly doped N-type amorphous silicon layer-140, heavily doped N-type amorphous silicon layer-150, transparent conductive oxide layer-160, and gate electrode-170. Detailed Implementation

[0053] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description of the specific implementation, structure, features and effects of the heterojunction battery proposed according to the present invention is provided in conjunction with the accompanying drawings and preferred embodiments.

[0054] On the one hand, such as Figure 5 As shown, an embodiment of the present invention provides a heterojunction solar cell, which includes:

[0055] N-type silicon substrate 100, including a front side and a back side, wherein grooves 101 are respectively provided in the corresponding areas of the gate electrode on the front side and the back side of the N-type silicon substrate 100;

[0056] Intrinsic amorphous silicon layer 110 is provided on the front and back sides of the N-type silicon substrate 100, respectively.

[0057] The P-type doped amorphous silicon layer includes a lightly doped P-type amorphous silicon layer 120, which is disposed on the intrinsic amorphous silicon layer 110 on the front side.

[0058] The N-type doped amorphous silicon layer includes a lightly doped N-type amorphous silicon layer 140, which is disposed on the intrinsic amorphous silicon layer 110 on the back side.

[0059] The P-type doped amorphous silicon layer also includes a heavily doped P-type amorphous silicon layer 130, which is disposed on the lightly doped P-type amorphous silicon layer 120 and located in the corresponding region of the groove 101.

[0060] The N-type doped amorphous silicon layer also includes a heavily doped N-type amorphous silicon layer 150, which is disposed on the lightly doped N-type amorphous silicon layer 140 and located in the corresponding region of the groove 101.

[0061] A transparent conductive oxide layer 160 is disposed on a P-type doped amorphous silicon layer and an N-type doped amorphous silicon layer, respectively.

[0062] Gate electrodes 170 are disposed on the transparent conductive oxide layers 160 on the front and back sides, respectively.

[0063] The region corresponding to the gate electrode refers to a portion of the area including the projection region of the gate electrode 170 onto the N-type silicon substrate 100 in a direction perpendicular to the front or back side, i.e., as shown in the figure. Figure 5 In the groove 101, the area opened includes at least the projection area of ​​the gate electrode 170 in the vertical direction on the front or back side. Here, the coverage area of ​​the groove 101 can overlap with the projection area of ​​the gate electrode 170, or the width of the groove 101 can be greater than the width of the gate electrode 170 on the front and back sides, so as to ensure that the gate electrode 170 is better aligned with the heavily doped N-type amorphous silicon layer 150 / heavily doped P-type amorphous silicon layer 130 in the groove 101, and to ensure that the contact resistance between the gate electrode 170 and the transparent conductive oxide layer 160 and the heavily doped N-type amorphous silicon layer 150 / heavily doped P-type amorphous silicon layer 130 does not increase.

[0064] For heterojunction solar cells, the front and back sides adopt a symmetrical distribution structure. For the N-type doped polycrystalline silicon on the back side, if the doping concentration is too high, it will also cause an increase in the dangling bond density on the surface. At the same time, it will also lead to an increase in the interface state density between the N-type doped amorphous silicon and intrinsic amorphous silicon and the N-type silicon substrate 100. The higher N-type doped amorphous silicon layer will also generate more light absorption without generating charge carriers, increasing parasitic absorption, and ultimately reducing the open-circuit voltage, resulting in a decrease in cell efficiency. In the embodiment of this application, a groove 101 is formed in the region of the N-type silicon substrate 100 corresponding to the gate electrode 170, and heavily doped amorphous silicon is introduced in the corresponding regions of the groove 101 on the front and back sides, thereby reducing the interface state density, reducing parasitic absorption, and ensuring the open-circuit voltage and cell efficiency.

[0065] Both the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer are composite two-layer structures. In this application, the surfaces of the lightly doped P-type amorphous silicon layer 120 and the lightly doped N-type amorphous silicon layer 140 are recessed through the groove 101. The heavily doped P-type amorphous silicon layer 130 and the heavily doped N-type amorphous silicon layer 150 are then filled into the groove. After the formation of the heavily doped P-type amorphous silicon layer 130 and the heavily doped N-type amorphous silicon layer 150, the upper surfaces of the P-type and N-type doped amorphous silicon layers are flat. Compared to directly placing the heavily doped amorphous silicon on the corresponding areas of the lightly doped amorphous silicon gate electrodes on the front and back sides (i.e., a protruding heavily doped amorphous silicon configuration), the embedded configuration in this application avoids the need for more transparent conducting oxides (TCOs) to fill areas outside the corresponding areas of the gate electrodes. Since the rare indium element in TCOs is expensive, this application avoids the problem of increasing the overall battery cost due to increased TCO usage.

[0066] The heterojunction solar cell proposed in this invention has lightly doped P / N type amorphous silicon on the intrinsic amorphous silicon on the front and back sides. Heavy doped P type amorphous silicon is deposited on the lightly doped P type amorphous silicon on the front side in the region corresponding to the gate electrode, and heavy doped N type amorphous silicon is deposited on the lightly doped N type amorphous silicon on the back side in the region corresponding to the gate electrode. While ensuring that the gate electrode can normally collect photogenerated carriers to generate current, it reduces the high parasitic absorption caused by the heavy doped amorphous silicon on the front and back sides, reduces the surface dangling bond and interface state density, improves the turn-on voltage, and increases the efficiency of the heterojunction solar cell.

[0067] In one embodiment, an intrinsic amorphous silicon layer 110 covers the entire surface of both the front and back sides of an N-type silicon substrate 100. A lightly doped P-type amorphous silicon layer 120 and a lightly doped N-type amorphous silicon layer 140 cover the entire surface of the intrinsic amorphous silicon layer 110 on both the front and back sides, respectively. A transparent conductive oxide layer 160 covers the entire surface of both the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer.

[0068] In one embodiment, the thickness of the intrinsic amorphous silicon layer 110 is 1–10 nm. An ultrathin intrinsic amorphous silicon layer 110 (ia-Si:H) can minimize light absorption loss while meeting passivation requirements, and simultaneously shorten the carrier transport distance, allowing more photons to penetrate to the intrinsic amorphous silicon layer 110 for absorption and the generation of electron-hole pairs. For example, it can be 1 nm, 3 nm, 5 nm, 8 nm, or 10 nm.

[0069] In one embodiment, the thickness of the lightly doped P-type amorphous silicon layer 120 is the same as the thickness of the heavily doped P-type amorphous silicon layer 130, and the surface of the P-type doped amorphous silicon layer is planar. The thickness of the lightly doped N-type amorphous silicon layer 140 is the same as the thickness of the heavily doped N-type amorphous silicon layer 150, and the surface of the N-type doped amorphous silicon layer is planar, thereby achieving the effect of reducing the amount of total organic carbon (TCO).

[0070] In one embodiment, the thickness of the lightly doped p-type amorphous silicon layer 120 is 2–15 nm. The thickness of the lightly doped n-type amorphous silicon layer 140 is 2–15 nm. The thickness of the heavily doped p-type amorphous silicon layer 130 is 2–15 nm. The thickness of the heavily doped n-type amorphous silicon layer 150 is 2–15 nm. By controlling the thickness of the doped layers within this range, while meeting the requirements for high doping concentration, optical losses can be minimized, carrier transport optimized, recombination losses within the intrinsic amorphous silicon layer 110 reduced, and contact resistance lowered. For example, the thicknesses can be 2 nm, 5 nm, 8 nm, 10 nm, 12 nm, or 15 nm.

[0071] In one embodiment, the doping concentration of the lightly doped p-type amorphous silicon layer 120 is 10. 18 cm -3 ~10 19 cm -3 The lightly doped N-type amorphous silicon layer 140 has a doping concentration of 10. 18 cm -3 ~10 19 cm -3 This ensures a low interface state density between the doped amorphous silicon in the non-gate region and the intrinsic amorphous silicon layer 110, reducing parasitic absorption and guaranteeing open-circuit voltage and cell efficiency. For example, the light doping concentration could be 10... 18 cm -3 20 18 cm -3 50 18 cm -3 80 18 cm -3 10 19 cm -3 .

[0072] The doping concentration of the heavily doped p-type amorphous silicon layer 130 is 10. 20 cm -3 ~10 21 cm -3 The doping concentration of the heavily doped N-type amorphous silicon layer 150 is 10. 20 cm -3 ~10 21 cm -3This, in turn, ensures a reduction in the lateral resistance of the amorphous silicon layer, accelerates carrier transport to the gate region, and optimizes the contact with the TCO, thereby reducing contact resistance. For example, the heavy doping concentration could be 10... 20 cm -3 20 20 cm -3 50 20 cm -3 80 20 cm -3 10 21 cm -3 .

[0073] In one embodiment, both the front and back sides of the N-type silicon substrate 100 have a textured structure, ensuring a textured surface across the entire surface and increasing light absorption. Furthermore, in some embodiments, the surfaces of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer have a textured structure, further increasing light absorption.

[0074] On the other hand, such as Figure 1-6 As shown, the present invention also provides a method for preparing a heterojunction solar cell, used to prepare a heterojunction solar cell as described in any of the above claims, the method comprising:

[0075] S1. Provide an N-type silicon substrate 100, and perform trenching on the corresponding areas of the gate line electrodes on the front and back sides of the N-type silicon substrate 100.

[0076] For example, a groove 101 can be formed by grooving the corresponding areas of the gate electrodes on the front and back sides of the N-type silicon substrate 100 using a picosecond laser. The groove 101 can coincide with the projected area of ​​the gate electrode 700, or its width can be greater than the width of the projected area of ​​the gate electrode 700.

[0077] S2. The N-type silicon substrate 100 after grooving is sequentially pre-cleaned on both sides, the damaged layer is removed, texturing is performed, and post-cleaning is performed to form a clean texturized silicon wafer surface.

[0078] This increases light absorption, forming a shape similar to... Figure 1 The structure shown.

[0079] S3. Deposit intrinsic amorphous silicon layers 110 on the front and back sides of the texturized N-type silicon substrate 100.

[0080] For example, by depositing an intrinsic amorphous silicon layer 110 using a PECVD device, a structure such as... Figure 2 The structure shown.

[0081] S4. A lightly doped P-type amorphous silicon layer 120 is deposited on the surface of the intrinsic amorphous silicon layer 110 on the front side, and a lightly doped N-type amorphous silicon layer 140 is deposited on the surface of the intrinsic amorphous silicon layer 110 on the back side.

[0082] For example, by depositing a lightly doped P-type amorphous silicon layer 120 and a lightly doped N-type amorphous silicon layer 140 using a PECVD device, a structure can be formed as follows: Figure 3 The structure is shown. At this time, the lightly doped P-type amorphous silicon layer 120 and the lightly doped N-type amorphous silicon layer 140 are in a recessed state at the groove 101, depending on the structure of the N-type silicon substrate 100.

[0083] S5. Deposit heavily doped P-type amorphous silicon on the surface of the lightly doped P-type amorphous silicon layer 120, and then deposit heavily doped N-type amorphous silicon on the surface of the lightly doped N-type amorphous silicon layer 140.

[0084] For example, heavily doped P-type amorphous silicon and heavily doped N-type amorphous silicon can be deposited using a PECVD device. After doping, the heavily doped P-type amorphous silicon and heavily doped N-type amorphous silicon are not only present at the corresponding positions of groove 101, but will overflow into the regions not corresponding to groove 101.

[0085] S6. Remove the heavily doped P-type amorphous silicon in the region corresponding to the non-groove 101 on the surface of the lightly doped P-type amorphous silicon layer 120, and remove the heavily doped N-type amorphous silicon in the region corresponding to the non-groove 101 on the surface of the lightly doped N-type amorphous silicon layer 140, to form a P-type doped amorphous silicon layer and an N-type doped amorphous silicon layer.

[0086] For example, by using reactive ion etching or chain etching equipment, the heavily doped P-type amorphous silicon in the region corresponding to the non-recess 101 on the surface of the lightly doped P-type amorphous silicon layer 120 is removed, and the heavily doped N-type amorphous silicon in the region corresponding to the non-recess 101 on the surface of the lightly doped N-type amorphous silicon layer 140 is removed. This forms a heavily doped P-type amorphous silicon layer 130 and a heavily doped N-type amorphous silicon layer 150 only in the recessed region corresponding to the recess 101, thus forming a layer as shown in the image. Figure 4 The structure shown.

[0087] S7. Texturing treatment is performed on the surfaces of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer.

[0088] Compared to the method of directly patterning the area corresponding to the non-gate electrode using reactive ion etching equipment, removing the heavily doped P-type amorphous silicon in the area corresponding to the non-gate electrode, and then directly depositing TCO, this embodiment removes the heavily doped P-type amorphous silicon and heavily doped N-type amorphous silicon corresponding to the non-groove 101 on the front and back sides using reactive ion etching equipment or chain etching equipment, then texturing the front and back sides of the battery, and then depositing TCO and screen printing the gate electrode 700. This avoids the risk that the texturing structure may have been destroyed, ensures the full surface texturing structure, and increases light absorption.

[0089] S8. Deposit transparent conductive oxide layers 160 on the texturized P-type doped amorphous silicon layer and N-type doped amorphous silicon layer, respectively.

[0090] For example, transparent conductive oxide layers 160 are deposited on textured P-type doped amorphous silicon layers and N-type doped amorphous silicon layers respectively by magnetron sputtering or evaporation.

[0091] S9. A gate electrode 170 is fabricated on the transparent conductive oxide layer 160 on the front and back sides.

[0092] For example, gate electrodes 170 are fabricated on the transparent conductive oxide layers 160 on the front and back sides using screen printing equipment. The gate electrodes 170 are metal gate electrodes.

[0093] The method for fabricating a heterojunction solar cell proposed in this invention involves depositing lightly doped P / N type amorphous silicon on the intrinsic amorphous silicon on both the front and back sides. Heavy doped P type amorphous silicon is deposited on the front side lightly doped P type amorphous silicon in the region corresponding to the gate electrode, and heavy doped N type amorphous silicon is deposited on the back side lightly doped N type amorphous silicon in the region corresponding to the gate electrode. This method ensures that the gate electrode can normally collect photogenerated carriers to generate current, while reducing the high parasitic absorption caused by the heavy doped amorphous silicon on both sides, reducing surface dangling bonds and interface state density, increasing the turn-on voltage, and improving the efficiency of the heterojunction solar cell.

[0094] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A heterojunction battery, characterized in that, include: The N-type silicon substrate includes a front side and a back side, and the gate electrode corresponding areas on the front side and the back side of the N-type silicon substrate are respectively provided with grooves; The intrinsic amorphous silicon layer is provided on the front and back sides of the N-type silicon substrate, respectively. The P-type doped amorphous silicon layer includes a lightly doped P-type amorphous silicon layer, which is disposed on the intrinsic amorphous silicon layer on the front side. The N-type doped amorphous silicon layer includes a lightly doped N-type amorphous silicon layer, which is disposed on the intrinsic amorphous silicon layer on the back side. The P-type doped amorphous silicon layer further includes a heavily doped P-type amorphous silicon layer, which is disposed on the lightly doped P-type amorphous silicon layer and located in the region corresponding to the groove. The N-type doped amorphous silicon layer further includes a heavily doped N-type amorphous silicon layer, which is disposed on the lightly doped N-type amorphous silicon layer and located in the region corresponding to the groove. A transparent conductive oxide layer is provided on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer, respectively. Gate electrodes, the gate electrodes being disposed on the transparent conductive oxide layers on the front and back sides respectively; The thickness of the lightly doped P-type amorphous silicon layer is the same as the thickness of the heavily doped P-type amorphous silicon layer, and the surface of the P-type doped amorphous silicon layer is planar. The thickness of the lightly doped N-type amorphous silicon layer is the same as that of the heavily doped N-type amorphous silicon layer, and the surface of the N-type doped amorphous silicon layer is planar.

2. The heterojunction solar cell according to claim 1, characterized in that, The intrinsic amorphous silicon layer covers the entire surface of the front and back sides of the N-type silicon substrate, respectively. The lightly doped P-type amorphous silicon layer and the lightly doped N-type amorphous silicon layer respectively cover the entire surface of the intrinsic amorphous silicon layer on the front and back sides. The transparent conductive oxide layer covers the entire surface of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer, respectively.

3. The heterojunction solar cell according to claim 1, characterized in that, The thickness of the intrinsic amorphous silicon layer is 1–10 nm.

4. The heterojunction solar cell according to claim 1, characterized in that, The thickness of the lightly doped P-type amorphous silicon layer is 2–15 nm. The thickness of the lightly doped N-type amorphous silicon layer is 2–15 nm. The thickness of the heavily doped P-type amorphous silicon layer is 2–15 nm. The thickness of the heavily doped N-type amorphous silicon layer is 2–15 nm.

5. The heterojunction battery according to claim 1, characterized in that, The doping concentration of the lightly doped p-type amorphous silicon layer is 10. 18 cm -3 ~10 19 cm -3 ; The doping concentration of the lightly doped N-type amorphous silicon layer is 10. 18 cm -3 ~10 19 cm -3 ; The doping concentration of the heavily doped p-type amorphous silicon layer is 10. 20 cm -3 ~10 21 cm -3 ; The doping concentration of the heavily doped N-type amorphous silicon layer is 10. 20 cm -3 ~10 21 cm -3 .

6. The heterojunction solar cell according to claim 1, characterized in that, The width of the groove is greater than the width of the gate electrode.

7. The heterojunction solar cell according to claim 1, characterized in that, Both the front and back sides of the N-type silicon substrate have a textured surface.

8. A method for preparing a heterojunction solar cell, characterized in that, The method for preparing a heterojunction solar cell as described in any one of claims 1-7 comprises: An N-type silicon substrate is provided, and the corresponding areas of the gate line electrodes on the front and back sides of the N-type silicon substrate are grooved. The N-type silicon substrate after grooving is sequentially subjected to double-sided pre-cleaning, damage layer removal, texturing, and post-cleaning to form a clean texturized silicon wafer surface. Intrinsic amorphous silicon layers are deposited on the front and back sides of the texturized N-type silicon substrate; A lightly doped P-type amorphous silicon layer is deposited on the surface of the intrinsic amorphous silicon layer on the front side, and a lightly doped N-type amorphous silicon layer is deposited on the surface of the intrinsic amorphous silicon layer on the back side. Heavy doped P-type amorphous silicon is deposited on the surface of the lightly doped P-type amorphous silicon layer, and then heavy doped N-type amorphous silicon is deposited on the surface of the lightly doped N-type amorphous silicon layer. The heavily doped P-type amorphous silicon in the non-groove region on the surface of the lightly doped P-type amorphous silicon layer is removed, and the heavily doped N-type amorphous silicon in the non-groove region on the surface of the lightly doped N-type amorphous silicon layer is removed, forming a P-type doped amorphous silicon layer and an N-type doped amorphous silicon layer. The thickness of the lightly doped P-type amorphous silicon layer is the same as the thickness of the heavily doped P-type amorphous silicon layer, and the surface of the P-type doped amorphous silicon layer is planar. The thickness of the lightly doped N-type amorphous silicon layer is the same as the thickness of the heavily doped N-type amorphous silicon layer, and the surface of the N-type doped amorphous silicon layer is planar. The surfaces of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer are texturized. Transparent conductive oxide layers are deposited on the texturized P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer, respectively. Gate electrodes are fabricated on the transparent conductive oxide layers on the front and back sides.

9. The method for preparing a heterojunction solar cell according to claim 8, characterized in that, The step of grooving the corresponding areas of the gate electrodes on the front and back sides of the N-type silicon substrate is to perform grooving on the corresponding areas of the gate electrodes on the front and back sides of the N-type silicon substrate based on picosecond laser. The steps of removing the heavily doped P-type amorphous silicon in the non-groove corresponding region on the surface of the lightly doped P-type amorphous silicon layer and removing the heavily doped N-type amorphous silicon in the non-groove corresponding region on the surface of the lightly doped N-type amorphous silicon layer are as follows: removing the heavily doped P-type amorphous silicon in the non-groove corresponding region on the surface of the lightly doped P-type amorphous silicon layer and removing the heavily doped N-type amorphous silicon in the non-groove corresponding region on the surface of the lightly doped N-type amorphous silicon layer respectively by using a reactive ion etching device or a chain etching device; The step of depositing transparent conductive oxide layers on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer after texturing is to deposit transparent conductive oxide layers on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer after texturing by magnetron sputtering or evaporation. The step of fabricating gate electrodes on the transparent conductive oxide layers on the front and back sides is to fabricate gate electrodes on the transparent conductive oxide layers on the front and back sides using a screen printing device.

Images