N-type TopCon battery and preparation method thereof

Abstract

The embodiment of the invention provides an N-type TopCon cell and a preparation method thereof, and belongs to the technical field of crystalline silicon solar cell manufacturing. According to the embodiment of the invention, after a third tunneling oxide layer and a third polycrystalline silicon layer are sequentially formed on the front surface of an N-type silicon wafer, a first region where a positive grid line is formed is oxidized to form an oxide layer, and then double-sided alkali etching treatment is carried out on the silicon wafer, so that the third polycrystalline silicon layer is etched into a first polycrystalline silicon layer; the third tunneling oxide layer is etched into the first tunneling oxide layer, the oxide layer is removed, then boron doping processing is carried out on the front face of the silicon wafer, namely, a passivation contact structure composed of the first tunneling oxide layer and the boron-doped polycrystalline silicon layer can be formed in the first area, the boron-doped layer is formed in the second area, and therefore carriers can be transversely transmitted, and the performance of the silicon wafer is improved. Meanwhile, the contact resistance of the positive electrode grid line is reduced, and the filling factor is improved, so that the photoelectric conversion efficiency of the battery is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of crystalline silicon solar cell manufacturing, and in particular to an N-type TopCon cell and a preparation method thereof. Background Art

[0002] Currently, N-type TOPCon cells in crystalline silicon solar cells are widely used due to their advantages such as low attenuation, obvious advantages in overall cell efficiency and power generation.

[0003] Existing N-type TOPCon cells generally form a selective emitter through the SE laser doping process, that is, high-concentration doping is performed at and near the contact point between the metal gate line and the silicon wafer to reduce the contact resistance between the front metal electrode and the silicon wafer, while low-concentration doping is performed in the area outside the electrode to reduce recombination in the diffusion layer.

[0004] However, the above doping process is too complicated and can easily cause laser damage to the cell. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an N-type TopCon battery and a preparation method thereof, so as to solve the problem that the existing method of forming a selective emitter on the front side of the N-type TOPCon battery by SE laser doping is too cumbersome and easily causes laser damage to the battery cell.

[0006] In order to solve the above problems, the present invention is achieved through the following technical solutions:

[0007] The present invention provides a method for preparing an N-type TopCon battery, which comprises:

[0008] After sequentially forming a third tunneling oxide layer and a third polysilicon layer on the front surface of the N-type silicon wafer, an oxidation treatment is performed on a first area on the front surface of the silicon wafer to form an oxide layer; the first area is the front surface area of ​​the silicon wafer where the positive gate line projection is located;

[0009] After the oxidation treatment, performing double-sided alkaline etching on the silicon wafer, etching the third polysilicon layer into a first polysilicon layer, etching the third tunneling oxide layer into a first tunneling oxide layer, and removing the oxide layer;

[0010] After the double-sided alkaline etching treatment, performing a boron doping treatment on the front side of the silicon wafer to form a boron-doped polysilicon layer on the first polysilicon layer and a boron-doped layer in a second region, where the second region is other regions of the front side of the silicon wafer except the first region;

[0011] removing the borosilicate glass layer on the back side of the boron-doped silicon wafer, and then polishing the back side of the silicon wafer;

[0012] forming a second tunneling oxide layer and a second polysilicon layer in sequence on the back side of the silicon wafer subjected to backside polishing, and doping the second polysilicon layer with phosphorus to form a phosphorus-doped polysilicon layer;

[0013] removing the phosphorus-silicate glass layer, the phosphorus-doped polysilicon layer, the borosilicate glass layer on the front side of the phosphorus-doped silicon wafer, and the phosphorus-silicate glass layer on the back side in sequence;

[0014] After removing the phosphosilicate glass layer on the back side, a passivation film layer is formed on both sides of the silicon wafer, and a positive gate line that is conductive to the boron-doped polysilicon layer is formed on the front side, and a negative gate line that is conductive to the phosphorus-doped polysilicon layer is formed on the back side to produce an N-type TopCon battery.

[0015] Furthermore, in the preparation method, the first area on the front side of the silicon wafer is subjected to oxidation treatment, comprising:

[0016] A laser oxidation process is performed on the first area on the front side of the silicon wafer.

[0017] Furthermore, in the preparation method, the laser oxidation power is 20 to 120 W, and the laser action time is 0.5 to 5 s.

[0018] Furthermore, in the preparation method, the thickness of the oxide layer is 10 to 50 nm.

[0019] Furthermore, in the preparation method, the thickness of the third polysilicon layer is 200 to 400 nm.

[0020] Furthermore, in the preparation method, the first tunneling oxide layer is an ultra-thin silicon dioxide layer.

[0021] Furthermore, in the preparation method, the silicon wafer is subjected to double-sided alkaline etching treatment, comprising:

[0022] Firstly, the silicon wafer is alkali-etched by using an etching additive and an alkaline solution, and then the oxide layer is removed by using hydrofluoric acid.

[0023] Furthermore, in the preparation method, the alkaline solution includes an etching additive and 3% to 10% by mass of NaOH or KOH, the treatment temperature is 60 to 90° C., and the treatment time is 150s to 600s.

[0024] Furthermore, in the preparation method, the mass percentage of hydrofluoric acid is 5% to 30%, the treatment temperature is 20 to 30° C., and the treatment time is 150 to 450 seconds.

[0025] Furthermore, in the preparation method, the boron doping concentration on the surface of the boron-doped polysilicon layer is 5E19-2E20cm -3 and / or

[0026] The boron doping concentration on the surface of the boron doping layer is 1E18-7E18cm -3 .

[0027] The present invention also provides an N-type TopCon battery, which is prepared by the above method.

[0028] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0029] In an embodiment of the present invention, after a third tunneling oxide layer and a third polysilicon layer are sequentially formed on the front side of an N-type silicon wafer, an oxide layer is formed by oxidizing the first region where the positive gate line is formed, and then the silicon wafer is subjected to double-sided alkaline etching, thereby etching the third polysilicon layer into a first polysilicon layer, and etching the third tunneling oxide layer into a first tunneling oxide layer, and then removing the oxide layer, and then boron doping is performed on the front side of the silicon wafer, that is, a passivation contact structure consisting of a first tunneling oxide layer and a boron-doped polysilicon layer can be formed in the first region, and a boron-doped layer is formed in the second region, so that carriers can be transmitted laterally, shortening the transmission distance of the carriers, and at the same time reducing the contact resistance of the positive gate line and improving the fill factor, thereby improving the photoelectric conversion efficiency of the battery.

[0030] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of the structure of an N-type TopCon battery provided by an embodiment of the present invention;

[0032] Figure 2 This is a flow chart of a method for preparing an N-type TopCon battery provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] The applicant of the present invention has found that the current N-type TopCon battery has a high front contact resistance and a low photoelectric conversion efficiency, which hinders its further promotion and application.

[0035] In order to solve the above problems, the embodiment of the present invention provides an N-type TopCon battery, wherein, Figure 1 As shown, it includes an N-type silicon wafer 10, a first tunneling oxide layer 11, a second tunneling oxide layer 12, a boron-doped polysilicon layer 13, a boron-doped layer 21, a phosphorus-doped polysilicon layer 14, a first passivation layer 15, a second passivation layer 16, a positive gate line 17 and a negative gate line 18.

[0036] Among them, the first tunneling oxide layer 11, the boron-doped polysilicon layer 13 and the positive gate line 17 are stacked in sequence in the first area on the front side of the silicon wafer 10, and the boron-doped layer 21 and the first passivation layer 15 are stacked in sequence in the second area on the front side of the silicon wafer 10. The first area is the area where the positive gate line 17 is projected toward the silicon wafer 10, and the second area is the other area on the front side of the silicon wafer 10 except the first area, and the positive gate line 17 is in contact with the boron-doped polysilicon layer 13; that is, the first tunneling oxide layer 11 is only arranged in the area of ​​the positive gate line 17, and the first tunneling oxide layer 11 does not partially cover the front side of the silicon wafer 10. The first passivation layer 15 is arranged in the area on the front side of the entire battery structure except the positive gate line 17.

[0037] The second tunneling oxide layer 12 , the phosphorus-doped polysilicon layer 14 , the second passivation layer 16 and the cathode gate line 18 are sequentially stacked on the back side of the silicon wafer 10 , and the cathode gate line 18 is in contact with the phosphorus-doped polysilicon layer 14 .

[0038] It can be understood that the positive gate line 17 protrudes from the first passivation layer 15 , while the negative gate line 18 passes through the second passivation layer 16 and protrudes from the second passivation layer 16 .

[0039] It can be seen that the embodiment of the present invention prepares a first tunneling oxide layer 11 in the positive gate line 17 area on the front side of the silicon wafer 10 and superimposes a boron-doped polysilicon layer 13, while forming a boron-doped layer 21 in other areas on the front side of the silicon wafer 10. This can produce ultra-strong field passivation and chemical passivation effects on the front side, allowing carriers to be transmitted laterally, shortening the carrier transmission distance, and at the same time reducing the contact resistance of the positive gate line 17 and improving the fill factor, thereby improving the photoelectric conversion efficiency of the battery.

[0040] Optionally, in one embodiment, the first tunneling oxide layer 11 is higher than the boron-doped layer 21 , which can better achieve lateral carrier transport.

[0041] Optionally, in one embodiment, the first tunneling oxide layer 11 and the second tunneling oxide layer 12 are both ultra-thin silicon oxide layers, which can effectively achieve a tunneling effect. The thickness of the first tunneling oxide layer 11 and the second tunneling oxide layer 12 can be 1 to 2 nm, for example, in the range of 1 nm, 1.5 nm, 2 nm, or any two thereof.

[0042] Optionally, in one embodiment, the first passivation layer 15 and the second passivation layer 16 are both aluminum oxide layers, that is, the first passivation layer 15 and the second passivation layer 16 can be formed by depositing aluminum oxide; the thickness of the first passivation layer 15 and the second passivation layer 16 can be 1 to 10 nm.

[0043] Optionally, in one embodiment, the N-type TopCon cell further includes a first anti-reflection layer 19 . The first anti-reflection layer 19 is disposed on the surface of the first passivation layer 15 , which can further enhance the back surface anti-reflection effect.

[0044] Optionally, in a specific embodiment, the first anti-reflection layer 19 includes a silicon nitride layer and / or a silicon oxide layer, that is, the entire front surface can be provided with a silicon nitride film, or a silicon nitride and silicon oxide stack, or a silicon nitride oxide layer as the first anti-reflection layer 19, and the thickness can be 50 to 120 nm, which can effectively improve the anti-reflection effect.

[0045] Optionally, in one embodiment, a second anti-reflection layer 20 is further included. The second anti-reflection layer 20 is disposed on the surface of the second passivation layer 16 , which can further enhance the back side anti-reflection effect.

[0046] Optionally, in a specific embodiment, the second anti-reflection layer 20 is a silicon nitride layer with a thickness of 50 to 120 nm, that is, the entire back non-negative gate line 18 area is coated with a silicon nitride layer as the back anti-reflection film.

[0047] Optionally, in one embodiment, the boron doping concentration on the surface of the boron-doped polysilicon layer 13 is 5E19-2E20 cm -3 , its thickness is 200-400nm, which can meet the p-type doping and passivation contact effect; the thickness of the boron-doped polysilicon layer 13 can specifically be one or any two of 200nm, 250nm, 300nm, 350nm, 400nm.

[0048] Optionally, in a specific embodiment, the boron doping concentration on the surface of the second region of the silicon wafer 10 is 1E18-7E18 cm -3 , which can effectively reduce the recombination in the non-gate line area and increase the battery opening voltage.

[0049] Alternatively, in one embodiment, the phosphorus doping concentration on the surface of the phosphorus-doped polysilicon layer 14 is 1E20-7E20 cm -3 , its thickness is 100 to 300 nm, which can meet the passivation contact effect; the thickness of the boron-doped polysilicon layer 13 can specifically be one or any two of 200 nm, 250 nm, 300 nm, 350 nm, and 400 nm.

[0050] Optionally, the positive electrode grid lines 17 are silver-aluminum electrode grid lines, and the negative electrode grid lines 18 are silver electrode grid lines.

[0051] The present invention also provides a method for preparing an N-type TopCon battery. Figure 2As shown, it includes steps 201 to 207:

[0052] Step 201: After sequentially forming a third tunneling oxide layer and a third polysilicon layer on the front surface of the N-type silicon wafer 10, an oxidation treatment is performed on a first region on the front surface of the silicon wafer 10 to form an oxide layer; the first region is the front surface region of the silicon wafer 10 where the positive gate line 17 is projected;

[0053] Step 202: After the oxidation treatment, perform double-sided alkaline etching on the silicon wafer, and etch the third polysilicon layer into a first polysilicon layer, etch the third tunnel oxide layer into a first tunnel oxide layer 11, and remove the oxide layer;

[0054] Step 203: After the double-sided alkaline etching treatment, the front side of the silicon wafer 10 is subjected to a boron doping treatment to form a boron-doped polysilicon layer 13 on the first polysilicon layer and a boron-doped layer 21 in a second region, where the second region is the other region of the front side of the silicon wafer 10 except the first region.

[0055] Step 204: removing the borosilicate glass layer on the back side of the boron-doped silicon wafer 10, and then polishing the back side of the silicon wafer 10;

[0056] Step 205 , forming a second tunneling oxide layer 12 and a second polysilicon layer in sequence on the back side of the back-polished silicon wafer 10 , and doping the second polysilicon layer with phosphorus to form a phosphorus-doped polysilicon layer 14 ;

[0057] Step 206 , sequentially removing the phosphorus-doped glass layer, phosphorus-doped polysilicon layer 14 , borosilicate glass layer, and phosphorus-doped glass layer on the front side of the silicon wafer 10 ;

[0058] Step 207: After removing the phosphosilicate glass layer on the back side, a passivation film layer is formed on both sides of the silicon wafer, and a positive gate line 17 is formed on the front side to be connected to the boron-doped polysilicon layer 13, and a negative gate line 18 is formed on the back side to be connected to the phosphorus-doped polysilicon layer 14, to obtain an N-type TopCon battery.

[0059] In an embodiment of the present invention, a tunneling oxide layer is provided in the front gate line region of the silicon wafer substrate, and a boron-doped polysilicon layer 13 is superimposed on the tunneling oxide layer, which can produce ultra-strong field passivation and chemical passivation effects on the front side. At the same time, a boron-doped layer 21 is formed in the non-front gate line region, so that carriers can be transmitted laterally, shortening the transmission distance of the carriers, and at the same time reducing the contact resistance of the positive gate line 17 and improving the fill factor, thereby improving the photoelectric conversion efficiency of the battery.

[0060] In the above step 201, the first tunnel oxide layer 11 and the first polysilicon layer are formed only in the first region where the positive gate line 17 is formed, and then the entire front surface is doped with boron to form a boron-doped polysilicon layer 13 in the first polysilicon layer, and a boron-doped layer 21 is formed in the second region. The boron doping concentration on the surface of the boron-doped polysilicon layer 13 is 5E19-2E20cm -3 The boron doping concentration on the surface of the second region of the silicon wafer is 1E18 to 7E18 cm -3 It can not only effectively reduce the recombination in the non-gate line area and increase the battery opening voltage, but also form a high and low boron doping concentration gradation with the boron-doped polysilicon layer 13, which facilitates the lateral transmission of carriers, thereby effectively improving the photoelectric conversion efficiency of the battery.

[0061] Specifically, in the above step 201, an N-type single crystal silicon wafer is first taken, and low pressure chemical vapor deposition (LPCVD) is used to first pass oxygen at a flow rate of 10 to 30 sccm to form an ultra-thin silicon oxide layer, i.e., the above-mentioned third tunneling oxide layer, on the front surface of the silicon wafer 10. As the ultra-thin tunneling oxide layer, the thickness of the third tunneling oxide layer can be specifically 1 to 2 nm, for example, 1.5 nm. Then, a segmented low pressure deposition method is used to passivate the wafer 10 at a temperature of 550 to 600° C., and silane is passed at a flow rate of 100 to 400 sccm to prepare a third polysilicon layer on both sides or on one side to have a thickness that meets the passivation effect. The thickness can specifically be 200 to 400 nm, for example, a range of one or any two values ​​among 200 nm, 250 nm, 300 nm, 350 nm, and 400 nm. Among them, because the double-sided preparation of the polysilicon layer is conducive to the subsequent removal of the front polysilicon layer, it is less likely to occur the two extreme situations of excessive removal or insufficient removal, and the yield is better controlled.

[0062] In step 201, after forming the third polysilicon layer, the first region of the front surface of the silicon wafer 10 is oxidized to form a dense oxide layer. The front surface regions outside the first region are not oxidized, and thus, no oxide layer is formed. The oxide layer formed in the first region can resist subsequent double-sided alkaline etching, thereby preventing etching of the polysilicon layer below the oxide layer.

[0063] Optionally, in a specific embodiment, the thickness of the oxide layer is 10 to 50 nm, which can effectively resist subsequent double-sided alkaline etching treatment and avoid etching the polysilicon layer below the oxide layer.

[0064] Optionally, in one embodiment, performing oxidation treatment on the first area on the front surface of the silicon wafer 10 includes:

[0065] The first area on the front surface of the silicon wafer 10 is subjected to laser oxidation treatment.

[0066] In this embodiment, after the third polysilicon layer is formed, the first area on the front surface of the cabinet is subjected to laser oxidation treatment, so that an oxide layer can be quickly formed.

[0067] Optionally, in a specific embodiment, the laser oxidation power is 20 to 120 W and the laser action time is 0.5 to 5 s, which can effectively oxidize the third polysilicon layer in the first region to form a dense oxide layer with a thickness of 10 to 50 nm.

[0068] In step 202, the oxidized silicon wafer is subjected to double-sided alkaline etching. Specifically, the silicon wafer is first alkaline-etched using an etching additive and an alkaline solution, and then the oxide layer is removed using hydrofluoric acid. During the double-sided alkaline etching, because an oxide layer barrier exists in the first region on the front side of the silicon wafer 10, while no oxide layer barrier exists in the second region on the front side of the silicon wafer 10 and on the back side of the silicon wafer 10, the third polysilicon layer in the second region and the polysilicon layer on the back side are removed by the alkaline solution, thereby etching the third polysilicon layer into a first polysilicon layer. Then, under the action of hydrofluoric acid, the third tunneling oxide layer in the second region and the oxide layer on the first polysilicon layer are removed, thereby etching the third tunneling oxide layer into a first tunneling oxide layer 11, and exposing the first polysilicon layer.

[0069] Optionally, in the double-sided alkaline etching, the alkaline solution includes an etching additive and 3% to 10% by mass of NaOH or KOH, the processing temperature is 60 to 90° C., and the processing time is 150 seconds to 600 seconds.

[0070] Optionally, in double-sided alkaline etching, the mass percentage of hydrofluoric acid is 5% to 30%, the processing temperature is 20 to 30° C., and the processing time is 150 to 450 s, which can effectively etch the third tunneling oxide layer into the first tunneling oxide layer 11 and remove the oxide layer on the first polysilicon layer.

[0071] In the above step 203, the silicon wafer is fed into the furnace tube to dope the first polysilicon layer with boron to form a boron-doped polysilicon layer 13, thereby forming a passivation contact structure consisting of the first tunneling oxide layer 11 and the boron-doped polysilicon layer 13, effectively reducing surface recombination and metal contact recombination.

[0072] The first polysilicon layer is doped with boron by boron diffusion. Optionally, the first polysilicon layer is doped with boron, including:

[0073] First, BCl3 and O2 with a flow ratio of 1:2 to 1:5 are introduced at a temperature of 850 to 900°C for low-temperature deposition, and then high-temperature advancement is carried out at a temperature of 900 to 950°C. After the high-temperature advancement is completed, oxidation is carried out and the boat is removed.

[0074] Specifically, in the boron diffusion process, the silicon wafer is first deposited for 0 to 50 minutes at a temperature of 850 to 900°C, a BCl3 to O2 flow ratio of 1:2 to 1:5, and a BCl3 flow rate of 100 to 300 sccm / min. The silicon wafer is then heated to 900 to 950°C for high-temperature advancement. The advancement can achieve a surface boron doping concentration of 5E19 to 2E20 cm -3 The boron-doped polysilicon layer 13 is formed, and after the high-temperature advancement is completed, oxygen with a flow rate of 8000 to 15000 sccm is introduced for oxidation and then taken out of the boat.

[0075] In the above step 204, the boron-doped silicon wafer is chain-picked to remove the thin borosilicate glass film on the back of the silicon wafer 10; optionally, the boron-doped silicon wafer is chain-picked using hydrofluoric acid with a mass percentage of 5 to 30%, which can effectively remove the thin borosilicate glass film on the back of the silicon wafer 10.

[0076] In the above step 204, the back side of the battery after chain pickling is polished by a tank cleaning device using an alkaline etching method to form a polished surface structure on the back side of the silicon wafer 10, which specifically includes pre-cleaning, alkaline polishing, and acid solution cleaning; wherein, the pre-cleaning is performed using a mixed solution of NaOH or KOH and H2O2 with a mass percentage of 0.3-0.5%; the alkaline polishing is performed using a mixed solution of NaOH or KOH with a mass percentage of 4-12%; the acid solution cleaning is performed using a HF and HCL solution with a mass percentage of 3-10%; the total duration of the above polishing treatment is controlled to be 30-60 minutes.

[0077] In step 205, after backside polishing, a low-pressure chemical vapor deposition (LPCVD) method is used to form an ultrathin silicon oxide layer, i.e., the second tunneling oxide layer 12, on the backside of the silicon wafer 10 by first passing oxygen at a flow rate of 10 to 30 sccm. The thickness of the second tunneling oxide layer 12 can be 1 to 2 nm, for example, 1.5 nm. Then, a stepwise low-pressure deposition method is used to passivate the backside of the silicon wafer 10 by passing silane at a flow rate of 100 to 400 sccm at a temperature of 550 to 600°C to form a second polysilicon layer on either the backside or the backside of the silicon wafer 10. The thickness can be 100 to 300 nm, for example, 100 nm, 150 nm, 200 nm, 250 nm, or 300 nm, or any two thereof. Forming the polysilicon layer on both sides facilitates the subsequent removal of the front polysilicon layer, preventing over-removal or under-removal, and thus improving yield control.

[0078] In the above step 205, after preparing the second polysilicon layer, the silicon wafer is sent into the furnace tube to phosphorus-dope the first polysilicon layer to form a phosphorus-doped polysilicon layer 14, thereby forming a passivation contact structure consisting of the second tunneling oxide layer 12 and the phosphorus-doped polysilicon layer 14, effectively reducing backside recombination and metal contact recombination.

[0079] The second polysilicon layer is doped with phosphorus by phosphorus diffusion. Optionally, the second polysilicon layer is doped with phosphorus, including:

[0080] First, the deposition is carried out at a temperature of 850-900 ° C and a flow ratio of N2 and O2 carrying POCl3 of 1:2-1:7 for 0-50 minutes. Then the silicon wafer is heated to 900-950 ° C for high temperature driving. The surface phosphorus doping concentration of 1E20-7E20cm can be obtained by driving. -3 The phosphorus-doped polysilicon layer 14 is formed, and after the high-temperature advancement is completed, oxygen with a flow rate of 8000-15000 sccm is introduced for oxidation at a temperature of 700-850°C for 0-50 minutes to control the thickness of the phosphorus-silicate glass layer formed on the silicon wafer surface to be 20-60 nm.

[0081] In the above step 206 , the phosphosilicate glass layer on the front surface of the silicon wafer 10 is first removed on one side, so as to facilitate the subsequent etching and removal of the phosphorus-doped polysilicon layer 14 on the front surface and the texturing process.

[0082] Optionally, in one embodiment, the front surface of the silicon wafer 10 is cleaned with hydrofluoric acid having a mass percentage of 5 to 30%, thereby achieving acid washing to remove the phosphosilicate glass layer on the front surface of the silicon wafer 10 .

[0083] In the above step 206, after removing the front phosphosilicate glass layer, a trench wet process is used to remove the phosphorus-doped polysilicon layer 14 on the front surface of the silicon wafer 10 by etching and texturing, which specifically includes:

[0084] The silicon wafer is alkali-etched by using 1% to 5% by mass of NaOH and an etching additive, and then the silicon wafer is groove-textured by using 0.5% to 3% by mass of NaOH and a texturizing additive.

[0085] In the above step 206 , after removing the phosphorus-doped polysilicon layer 14 on the front side, the borosilicate glass layer on the front side and the phosphorus-silicate glass layer on the back side are removed by cleaning with 5-30% by mass of hydrofluoric acid and O 3 .

[0086] In this embodiment, the borosilicate glass layer on the front, the phosphosilicate glass layer on the back and other surface additives are removed by cleaning with hydrofluoric acid and O3, thereby exposing the boron-doped polysilicon layer 13 and the boron-doped layer 21 on the front and the phosphorus-doped polysilicon layer 14 on the back.

[0087] Optionally, in another embodiment, the step 206 includes:

[0088] The silicon wafer is cleaned with a mixed acid, wherein the mixed acid comprises 25% to 35% by mass of HNO3 and 5% to 15% by mass of HF.

[0089] In this embodiment, a mixed acid of nitric acid and hydrofluoric acid is used to perform one-step acid etching to achieve the effect of removing the phosphosilicate glass layer on the front surface of the silicon wafer 10 and performing etching.

[0090] In the above step 207, the atomic layer deposition (ALD) process is used to coat the entire front and back of the product as a passivation layer to form field passivation; after the aluminum oxide film layer is formed, the plasma enhanced chemical vapor deposition (PECVD) process is used to coat the anti-reflection film layer on the back of the battery, and then the anti-reflection film layer is coated on the front to further improve the passivation effect of the battery cell.

[0091] Optionally, the passivation layer is an aluminum oxide film layer, that is, the aluminum oxide film layer is plated on the entire front surface and the entire back surface as the passivation layer; the thickness of the passivation layer can be 1 to 10 nm.

[0092] Optionally, the back anti-reflection film layer may be a silicon nitride layer with a thickness of 50 to 120 nm, that is, the silicon nitride layer is plated on the entire back surface as the back anti-reflection film;

[0093] Optionally, the front anti-reflection film layer may be a silicon nitride film, or a stack of silicon nitride and silicon oxide, or a silicon oxynitride layer, and may have a thickness of 50 to 120 nm, which can further enhance the anti-reflection effect.

[0094] Optionally, in one embodiment, in the above step 207, a positive gate line 17 conductively connected to the boron-doped polysilicon layer 13 is formed on the front side, and a negative gate line 18 conductively connected to the phosphorus-doped polysilicon layer 14 is formed on the back side, to produce an N-type TopCon battery, including:

[0095] The silicon wafer with the anti-reflection film formed thereon is screen-printed to form a positive electrode grid line 17 on the front side that is conductive to the boron-doped polysilicon layer 13, and a negative electrode grid line 18 on the back side that is conductive to the phosphorus-doped polysilicon layer 14. The wafer is then sintered at a high temperature to prepare an N-type TopCon battery.

[0096] Optionally, in another embodiment, in the above step 207, a positive gate line 17 conductively connected to the boron-doped polysilicon layer 13 is formed on the front side, and a negative gate line 18 conductively connected to the phosphorus-doped polysilicon layer 14 is formed on the back side, to produce an N-type TopCon battery, including:

[0097] A metal seed layer thin film is deposited on the back of the silicon wafer 10 using physical vapor deposition. The material of the metal seed layer thin film is copper, and the metal seed layer thickness is 150 to 300 nm. A layer of photosensitive ink is coated on the back seed layer and then dried at a temperature of 100°C for 8 to 15 minutes. The photosensitive ink on the back of the silicon wafer 10 is exposed using laser direct write exposure to form a pattern in which the main and auxiliary gates are perpendicular to each other. After the front and back of the silicon wafer are exposed, the silicon wafer is transferred to a chemical solution for development and drying, and finally a groove pattern to be electroplated is formed on the front and back of the silicon wafer. A silicon wafer with patterned front and back surfaces is placed in an electroplating tank for electroplating. The chemical solution in the electroplating tank includes copper sulfate and various additives. Different current parameters are set for the silicon wafer surface. Copper ions in the solution receive electrons and form copper atoms that adhere to the silicon wafer surface. Since only some of the grooved areas on the silicon wafer surface have exposed seed layers, which are conductive areas, while other areas are covered with photosensitive ink on the back and are non-conductive, copper atoms only gather on the surface of the seed layer in the grooves to form copper grid lines. The electroplating time is controlled so that the height of the electroplated copper grid lines does not exceed the height of the patterned grooves.

[0098] After copper plating on the back side of the silicon wafer, the film was removed by placing it in a KOH solution with a KOH concentration of 5% and a film removal time of 6 minutes, which can remove the residual photosensitive ink on the surface of the silicon wafer.

[0099] The silicon wafer is then placed in an acid solution with a certain degree of oxidizing properties to remove the metal seed layer other than the gate lines on the surface of the silicon wafer, so that a positive gate line 17 that is conductive to the boron-doped polysilicon layer 13 can be formed on the front side, and a negative gate line 18 that is conductive to the phosphorus-doped polysilicon layer 14 can be formed on the back side.

[0100] Optionally, in one embodiment, the preparation method provided in the embodiment of the present invention further includes step 200 before step 201:

[0101] The silicon wafer is subjected to texturing treatment.

[0102] In this embodiment, before forming the first tunneling oxide layer 11 and the first polysilicon layer, the silicon wafer is subjected to a texturing treatment using acid and alkaline solutions to remove the mechanical damage layer and metal ions on the surface of the single-crystal N-type original silicon wafer, while forming a "pyramid" appearance on the surface of the battery to improve the light trapping effect of the battery. Optionally, the texturing treatment specifically includes pre-cleaning, alkaline solution texturing, and acid solution cleaning; wherein the pre-cleaning is performed using a mixed solution of HCl and H2O2 with a mass percentage of 0.2-0.5%; the alkaline solution texturing is performed using NaOH or KOH and a texturing additive with a mass percentage of 0.4-2%; the acid solution cleaning is performed using a HF solution with a mass percentage of 0.1-0.3%; the total duration of the above-mentioned texturing treatment is controlled to be 50-60 minutes.

[0103] The present invention is described in detail below by way of examples.

[0104] Example 1

[0105] (1) Take an 182*182 N-type silicon wafer and perform pre-cleaning, alkaline solution texturing, and acid solution cleaning in sequence; wherein, the pre-cleaning is performed with a mixed solution of HCl and H2O2 with a mass percentage of 0.3% for 4 minutes; the alkaline solution texturing is performed with NaOH and texturing additives with a mass percentage of 0.4-2% for 5 minutes; the acid solution cleaning is performed with a HF solution with a mass percentage of 0.1-0.3% for 4 minutes;

[0106] (2) forming an ultra-thin silicon oxide layer with a thickness of 1.5 nm on the back side of the silicon wafer 10 by oxygen gas at a flow rate of 20 sccm, as a third tunneling oxide layer; then, using a segmented low-pressure deposition method, at a temperature of 580°C, introducing silane at a flow rate of 250 sccm, a third polysilicon layer with a thickness of 200 nm is formed on both sides;

[0107] (3) The front emitter region is oxidized by laser to form a dense surface oxide layer with a thickness of 30 nm and a laser oxidation power of 70 W;

[0108] (4) performing double-sided alkaline etching on the laser-oxidized silicon wafer to remove the front non-emitter region and the polysilicon layer on the back, and etching the third tunneling oxide layer into a first tunneling oxide layer using 15% by mass hydrofluoric acid, and removing the oxide layer on the first polysilicon layer; wherein the alkaline solution of the alkaline etching treatment includes an etching additive and 6% by mass NaOH, the treatment temperature is 70° C., and the treatment time is 350 s;

[0109] (5) Boron doping of the first polysilicon layer was performed by boron diffusion. First, the deposition was performed for 25 min at a temperature of 880°C, a flow ratio of BCl3 to O2 of 1:4, and a flow rate of BCl3 of 200 sccm / min. Then, the silicon wafer was heated to 920°C for high-temperature propulsion. After the high-temperature propulsion was completed, oxygen with a flow rate of 12000 sccm was introduced for oxidation and the wafer was taken out of the boat. The surface boron doping concentration was 5E19~2E20 cm -3 a boron-doped polysilicon layer 13;

[0110] (6) using 15% by mass of hydrofluoric acid to chain pickle the boron-doped silicon wafer to remove the thin borosilicate glass film on the back of the silicon wafer 10;

[0111] (7) Using a trough-type tank, the back side of the silicon wafer 10 is subjected to alkaline polishing treatment using an alkaline solution, specifically including pre-cleaning, alkaline polishing treatment, and acid solution cleaning; wherein the pre-cleaning is performed using a mixed solution of NaOH and H2O2 with a mass percentage of 0.4% for 4 minutes; the alkaline polishing treatment is performed using a NaOH solution with a mass percentage of 8% for 5 minutes; and the acid solution cleaning is performed using a HF and HCl solution with a mass percentage of 6% for 4 minutes;

[0112] (8) An ultrathin silicon oxide layer with a thickness of 1.5 nm is formed on the back side of the silicon wafer 10 by passing oxygen at a flow rate of 20 sccm, serving as a second silicon oxide layer. Then, a second polysilicon layer with a thickness of 200 nm is formed on both sides of the silicon wafer 10 by a segmented low-pressure deposition method at a temperature of 580°C and passing silane at a flow rate of 250 sccm.

[0113] (9) phosphorus-doping the second polysilicon layer by phosphorus diffusion, wherein the phosphorus diffusion treatment is first carried out at a temperature of 880° C., a POCl3 flow rate of 120 sccm / min, an oxygen flow rate of 700 sccm / min, a nitrogen flow rate of 1800 sccm / min, and a pressure of 160 mbar for 10 minutes, and then the silicon wafer is heated to 930° C. and treated at a pressure of 800 mbar and an oxygen flow rate of 12000 sccm / min for 70 minutes to obtain a phosphorus-doped polysilicon layer 14;

[0114] (10) Cleaning the front surface of the silicon wafer 10 with 15% by mass hydrofluoric acid to remove the phosphosilicate glass layer on the front surface of the silicon wafer 10;

[0115] (11) alkaline etching is performed on the silicon wafer using 2% by mass of NaOH and an etching additive, and then the silicon wafer is tank-textured using 1% by mass of NaOH and a texturing additive, and then the silicon wafer is cleaned using 15% by mass of hydrofluoric acid and O3 to remove the borosilicate glass layer on the front side of the silicon wafer 10 and the phosphosilicate glass layer on the back side;

[0116] (12) A 5 nm thick aluminum oxide film is deposited on the entire front and back of the product using an atomic layer deposition process to form field passivation;

[0117] (13) After forming the aluminum oxide film layer by PECVD, a first silicon nitride layer with a thickness of 80 nm is first plated on the front side of the battery as a front anti-reflection film layer, and then a second silicon nitride layer with a thickness of 80 nm is plated on the back side as a back anti-reflection film layer;

[0118] (14) Printing a positive electrode paste on the front side of the silicon wafer 10 that is in contact with the boron-doped polysilicon layer 13, and printing a negative electrode paste on the back side that is in contact with the phosphorus-doped polysilicon layer 14;

[0119] (16) The silicon wafer is subjected to high temperature sintering to obtain an N-type TopCon battery.

[0120] Example 2

[0121] The difference between Example 2 and Example 1 is that in step (3), the laser oxidation power is adjusted to 120W and the oxide layer thickness is 50nm;

[0122] In step (4), the mass percentage of hydrofluoric acid is adjusted to 30%.

[0123] Example 3

[0124] The difference between Example 3 and Example 1 is that in step (3), the laser oxidation power is adjusted to 20 W and the oxide layer thickness is 30 nm;

[0125] In step (4), the mass percentage of hydrofluoric acid is adjusted to 5%.

[0126] The above battery was tested for electrical performance, and the results are shown in Table 1:

[0127] Table 1

[0128] Eta (%) Voc(mV) Isc(A) FF(%) Rsh(Ω) Rs(mΩ) Example 1 26.61 743.5 13.94 85.58 923 0.5 Example 2 26.34 738.5 13.92 85.34 842 0.55 Example 3 26.40 742.1 13.9 85.25 487 0.58

[0129] To summarize, in this embodiment, after the third tunneling oxide layer and the third polysilicon layer are sequentially formed on the front side of the N-type silicon wafer 10, an oxide layer is formed by oxidizing the first region where the positive gate line 17 is formed, and then the silicon wafer is subjected to double-sided alkaline etching, thereby etching the third polysilicon layer into the first polysilicon layer, and etching the third tunneling oxide layer into the first tunneling oxide layer, and then removing the oxide layer. Then, the front side of the silicon wafer 10 is subjected to boron doping treatment, that is, a passivation contact structure consisting of the first tunneling oxide layer and the boron-doped polysilicon layer 13 can be formed in the first region, and a boron-doped layer 21 is formed in the second region, so that carriers can be transmitted laterally, shortening the transmission distance of the carriers, and at the same time reducing the contact resistance of the positive gate line 17 and improving the fill factor, thereby improving the photoelectric conversion efficiency of the battery.

[0130] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0131] The above is a detailed introduction to an N-type TopCon battery and its preparation method provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for preparing an N-type TopCon battery, characterized in that: include: After sequentially forming a third tunneling oxide layer and a third polysilicon layer on the front surface of the N-type silicon wafer, an oxidation treatment is performed on a first area on the front surface of the silicon wafer to form an oxide layer; the first area is the front surface area of ​​the silicon wafer where the positive gate line projection is located; After the oxidation treatment, performing double-sided alkaline etching on the silicon wafer, etching the third polysilicon layer into a first polysilicon layer, etching the third tunneling oxide layer into a first tunneling oxide layer, and removing the oxide layer; After the double-sided alkaline etching treatment, performing a boron doping treatment on the front side of the silicon wafer to form a boron-doped polysilicon layer on the first polysilicon layer and a boron-doped layer in a second region, where the second region is other regions of the front side of the silicon wafer except the first region; removing the borosilicate glass layer on the back side of the boron-doped silicon wafer, and then polishing the back side of the silicon wafer; forming a second tunneling oxide layer and a second polysilicon layer in sequence on the back side of the silicon wafer subjected to backside polishing, and doping the second polysilicon layer with phosphorus to form a phosphorus-doped polysilicon layer; removing the phosphorus-silicate glass layer, the phosphorus-doped polysilicon layer, the borosilicate glass layer on the front side of the phosphorus-doped silicon wafer, and the phosphorus-silicate glass layer on the back side in sequence; After removing the phosphosilicate glass layer on the back side, a passivation film layer is formed on both sides of the silicon wafer, and a positive gate line that is conductive to the boron-doped polysilicon layer is formed on the front side, and a negative gate line that is conductive to the phosphorus-doped polysilicon layer is formed on the back side to produce an N-type TopCon battery.

2. The preparation method according to claim 1, characterized in that Performing an oxidation treatment on the first area on the front side of the silicon wafer, comprising: A laser oxidation process is performed on the first area on the front side of the silicon wafer.

3. The preparation method according to claim 2, characterized in that The laser oxidation power is 20 to 120 W, and the laser action time is 0.5 to 5 seconds.

4. The preparation method according to claim 1, characterized in that The thickness of the oxide layer is 10-50 nm.

5. The preparation method according to claim 1, characterized in that The thickness of the third polysilicon layer is 200-400 nm.

6. The preparation method according to claim 1, characterized in that The first tunneling oxide layer is an ultra-thin silicon dioxide layer.

7. The preparation method according to claim 1, characterized in that The silicon wafer is subjected to double-sided alkaline etching treatment, comprising: Firstly, the silicon wafer is alkali-etched by using an etching additive and an alkaline solution, and then the oxide layer is removed by using hydrofluoric acid.

8. The preparation method according to claim 7, characterized in that The alkaline solution includes an etching additive and 3% to 10% by mass of NaOH or KOH, the treatment temperature is 60 to 90° C., and the treatment time is 150s to 600s.

9. The preparation method according to claim 7, characterized in that The mass percentage of hydrofluoric acid is 5% to 30%, the processing temperature is 20 to 30° C., and the processing time is 150 to 450 seconds.

10. An N-type TopCon battery, characterized in that: The method is prepared by any one of claims 1 to 9.

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