Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a driving transistor, a power write-in transistor, a target transistor and a first connecting line, the first connecting line comprises a first branch and a second branch, a first electrode of the driving transistor is electrically connected with a first electrode of the power write-in transistor through the first branch, and a second electrode of the power write-in transistor is electrically connected with a first power line. The first electrode of the driving transistor is electrically connected with the first electrode of the target transistor through the second branch, and the second electrode of the target transistor is electrically connected with the target signal line; a light emission control signal line electrically connected to the gate of the power supply write transistor; a first scan line extending in a first direction; the second connecting line is connected between the first scanning line and the grid electrode of the target transistor; the first scanning line and the second connecting line are located on different film layers; in the thickness direction of the display panel, the first connecting lines and the light-emitting control signal lines are not overlapped. The embodiment of the invention can improve the color cast problem.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] A display panel includes pixel circuits, light-emitting elements, and signal lines. The pixel circuits are used to drive the light-emitting elements. Pixel circuits are typically composed of transistors, which are connected by interconnecting wires. Signal lines include light-control signal lines that control whether the light-emitting elements emit light.

[0003] In related art, some of the pixel circuit's connecting lines overlap with the light-control signal lines, forming parasitic capacitance. Under high-frequency pulse width modulation (PWM), the light-control signal on the light-control signal line frequently transitions. This parasitic capacitance creates instability in the potential of some of the connecting lines, which can easily lead to low-grayscale color cast issues. Summary of the Invention

[0004] Embodiments of the present application provide a display panel and a display device that can improve the color cast problem.

[0005] In the first aspect, an embodiment of the present application provides a display panel, including a driving transistor, a power write transistor, a target transistor, a light-emitting element, and a first connecting line, the first connecting line including a first branch and a second branch, the first electrode of the driving transistor is electrically connected to the first electrode of the power write transistor through the first branch, the second electrode of the power write transistor is electrically connected to the first power line, the first electrode of the driving transistor is electrically connected to the first electrode of the target transistor through the second branch, the second electrode of the driving transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the target transistor is electrically connected to the target signal line; a light-emitting control signal line is electrically connected to the gate of the power write transistor; a first scan line extends along a first direction; a second connecting line is connected between the first scan line and the gate of the target transistor; the first scan line and the second connecting line are located in different film layers; in the thickness direction of the display panel, the first connecting line and the light-emitting control signal line do not overlap.

[0006] According to the display panel and display device provided in the embodiments of the present application, since the first connecting line and the light-emitting control signal line do not overlap, the parasitic capacitance between the node connected to the first electrode of the driving transistor and the light-emitting control signal line can be reduced. In this way, under high-frequency requirements, the impact of high-frequency signal jumps on the light-emitting control signal line on the node potential can be reduced, thereby improving the low grayscale color cast problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0008] Figure 1 A schematic diagram showing a layout structure of a local area in a display panel of related art;

[0009] Figure 2 A schematic diagram showing another layout structure of a local area in a display panel of the related art;

[0010] Figure 3 A schematic diagram showing a layout structure of a local area in a display panel provided in an embodiment of the present application;

[0011] Figure 4 A schematic diagram showing another layout structure of a local area in a display panel provided in an embodiment of the present application;

[0012] Figure 5 A schematic diagram showing an equivalent circuit of a pixel in a display panel provided by an embodiment of the present application is shown;

[0013] Figure 6 Another equivalent circuit diagram of a pixel in a display panel provided by an embodiment of the present application is shown;

[0014] Figure 7 Another equivalent circuit diagram of a pixel in a display panel provided by an embodiment of the present application is shown;

[0015] Figure 8 A schematic diagram showing another layout structure of a local area in a display panel provided in an embodiment of the present application;

[0016] Figure 9 Show Figure 8 A schematic plan view of a first semiconductor layer;

[0017] Figure 10 Show Figure 8 A schematic plan view of a first metal layer;

[0018] Figure 11 Show Figure 8 A planar schematic diagram of a capacitor metal layer;

[0019] Figure 12 Show Figure 8 A plan view of a second metal layer;

[0020] Figure 13 Show Figure 8 A planar schematic diagram of a third metal layer;

[0021] Figure 14 A schematic diagram showing a film layer stacking structure of a display panel provided by an embodiment of the present application is shown;

[0022] Figure 15 A schematic diagram showing another layout structure of a local area in a display panel provided in an embodiment of the present application;

[0023] Figure 16 Show Figure 15 A schematic plan view of a first semiconductor layer;

[0024] Figure 17 Show Figure 15 A schematic plan view of a first metal layer;

[0025] Figure 18 Show Figure 15 A planar schematic diagram of a capacitor metal layer;

[0026] Figure 19 Show Figure 15 A schematic plan view of a second semiconductor layer;

[0027] Figure 20 Show Figure 15 A planar schematic diagram of a gate metal layer;

[0028] Figure 21 Show Figure 15 A plan view of a second metal layer;

[0029] Figure 22 Show Figure 15 A planar schematic diagram of a third metal layer;

[0030] Figure 23 A schematic diagram showing another film layer stacking structure of a display panel provided in an embodiment of the present application is shown;

[0031] Figure 24 A schematic diagram showing another layout structure of a local area in a display panel provided in an embodiment of the present application;

[0032] Figure 25 Show Figure 24 A schematic plan view of a first semiconductor layer;

[0033] Figure 26 Show Figure 24 A schematic plan view of a first metal layer;

[0034] Figure 27 Show Figure 24 A planar schematic diagram of a capacitor metal layer;

[0035] Figure 28 Show Figure 24 A plan view of a second metal layer;

[0036] Figure 29 Show Figure 24 A planar schematic diagram of a third metal layer;

[0037] Figure 30 A schematic structural diagram of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0038] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0039] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0040] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0041] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0042] In the embodiments of the present application, the term "electrically connected" may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components. The term "drive" may refer to "control" or "operate". The term "portion" may refer to "local". The term "pattern" may refer to "component". The term "end" may refer to "end segment" or "end edge". The display panel may be a display device or a module / portion of a display device.

[0043] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0044] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0045] The pixel circuit in the display panel includes an 8T1C or 7T1C structure, where "8T1C" indicates that the pixel circuit includes 8 transistors and 1 storage capacitor, and "7T1C" indicates that the pixel circuit includes 7 transistors and 1 storage capacitor.

[0046] For example, in the related art, for a pixel circuit of 8T1C structure, Figure 1 As shown, the drive transistor M3, the bias adjustment transistor M8, and the power write transistor M1 are connected to node N2. Node N2 is electrically connected to the bias adjustment transistor M8 via a connection line 1'. The gate of the power write transistor M1 is electrically connected to the emission control signal line emit. Connection line 1' at least partially overlaps with the emission control signal line emit, forming a coupling capacitor C_N2_1 between the connection line 1' and the emission control signal line emit. Under high-frequency PWM requirements, the emission control signal on the emission control signal line emit transitions multiple times. Due to the coupling of C_N2_1, low-grayscale color casts can easily occur. This can also easily cause bulging on the bias signal line DVH, to which the bias adjustment transistor M8 is electrically connected.

[0047] For another example, in the related art, for a pixel circuit with a 7T1C structure, Figure 2As shown, the drive transistor M3, the data write transistor M2, and the power write transistor M1 are connected to node N2. Node N2 is electrically connected to the data write transistor M2 via a connection line 2'. The gate of the power write transistor M1 is electrically connected to the emission control signal line emit. Connection line 2' at least partially overlaps with the emission control signal line emit, forming a coupling capacitor C_N2_2 between connection line 2' and the emission control signal line emit. Under high-frequency PWM requirements, the emission control signal on the emission control signal line emit changes multiple times. Due to the coupling of C_N2_2, it is easy to cause low grayscale color cast issues.

[0048] In response to the above technical problems, embodiments of the present application provide a display panel and a display device. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0049] Please refer to Figures 3 to 7 The display panel 100 provided in the embodiment of the present application includes a pixel circuit and a light-emitting element D, wherein the pixel circuit is used to drive the light-emitting element D to emit light. The pixel circuit includes a driving transistor M3, a power writing transistor M1, and a target transistor MT.

[0050] The display panel includes a first connection line 11 , a second connection line 12 , a light emitting control signal line emit, a first scan line SP, a target signal line 21 , and a first power line PVDD.

[0051] The first connecting line 11 includes a first branch 111 and a second branch 112. The first electrode of the driving transistor M3 is electrically connected to the first electrode of the power writing transistor M1 through the first branch 111, the second electrode of the power writing transistor M2 is electrically connected to the first power line PVDD, the first electrode of the driving transistor M2 is electrically connected to the first electrode of the target transistor MT through the second branch 112, the second electrode of the driving transistor M3 is electrically connected to the light-emitting element D, and the second electrode of the target transistor MT is electrically connected to the target signal line 21.

[0052] The first branch 111 of the first connection line 11 is electrically connected to the first electrode of the power write transistor M1. Here, the first connection line 11 does not include the effective channel region of the power write transistor M1. The effective channel region of the power write transistor M1 is the part where the active layer of the power write transistor M1 overlaps with the emission control signal line emit.

[0053] The first branch 111 and the second branch 112 are connected to a node N2 , and the node N2 is electrically connected to a first electrode of the driving transistor M3 .

[0054] For example, the first branch 111 and the second branch 112 may be integrally formed. For example, the first branch 111 and the second branch 112 are located in the same film layer as the active layer of the first type transistor in the display panel. The first type may include a P type.

[0055] The emission control signal line emit is electrically connected to the gate of the power write transistor M1 , and the signal on the emission control signal line emit is used to control the state of the power write transistor M1 .

[0056] The second connection line 12 is connected between the first scan line SP and the gate of the target transistor MT. The signal on the first scan line SP is transmitted to the gate of the target transistor MT through the second connection line 12. The signal on the first scan line SP is used to control the state of the target transistor MT.

[0057] The emission control signal line emit and the first scan line SP extend along the first direction X. The first scan line SP and the second connection line 12 are located in different film layers and are electrically connected to each other through a via.

[0058] Illustratively, in the thickness direction of the display panel, the second connection line 12 at least partially overlaps with the emission control signal line emit.

[0059] In the thickness direction of the display panel, the first connection line 11 does not overlap with the emission control signal line emit.

[0060] In the embodiment of the present application, since the first connecting line 11 does not overlap with the light-emitting control signal line emit, the parasitic capacitance between the node N2 connected to the first electrode of the driving transistor M3 and the light-emitting control signal line emit can be reduced. In this way, under high-frequency PWM requirements, the impact of high-frequency jumps of the signal on the light-emitting control signal line emit on the potential of the node N2 can be reduced, thereby improving the low grayscale color cast problem.

[0061] As an example, Figure 3 or Figure 5 or Figure 6 As shown, the display panel includes a bias adjustment transistor M8, the target transistor MT includes the bias adjustment transistor M8, and the target signal line 21 includes a bias signal line DVH. The bias signal on the bias signal line DVH is used to adjust the bias state of the driving transistor M3.

[0062] In this embodiment, since the first connection line 11 does not overlap with the emission control signal line emit, the parasitic capacitance between the node N2 connected to the first electrode of the driving transistor M3 and the emission control signal line emit can be reduced, thereby improving the bulging problem of the bias signal line DVH.

[0063] In the case where the target signal line 21 includes the bias signal line DVH, as shown in FIG. Figure 3As shown, the display panel further includes a data writing transistor M2, and the first connection line 11 further includes a third branch 113, which is connected between the data writing transistor M2 and the first electrode of the driving transistor M3. The first branch 111, the second branch 112 and the third branch 113 are connected to the node N2.

[0064] As another example, Figure 4 or Figure 7 As shown, the display panel includes a data writing transistor M2, the target transistor MT includes the data writing transistor M2, and the target signal line 21 includes a data line data. The data signal on the data line data is used to adjust the magnitude of the driving current generated by the driving transistor M3.

[0065] In some embodiments, the emission control signal line emit and the first scan line SP are located in the same film layer.

[0066] Compared with adding an additional metal layer to arrange the first scan line SP, setting the two in the same film layer can achieve the situation where the first connecting line 11 and the light-emitting control signal line emit do not overlap, and the light-emitting control signal line emit and the first scan line SP can be prepared using the same process steps, which can simplify the process and is conducive to the thinning of the display panel.

[0067] Exemplarily, in the same pixel circuit, in the second direction Y, the light emitting control signal line emit is located between the driving transistor M3 and the first scan line SP.

[0068] In some embodiments, as Figures 5 to 7 As shown in any of the accompanying drawings, the display panel also includes a first reset transistor M7 and a first reset signal line Vref2, the first electrode of the first reset transistor M7 is electrically connected to the first reset signal line Vref2, the second electrode of the first reset transistor M7 is electrically connected to the first electrode of the light-emitting element D, and the gate of the first reset transistor M7 is electrically connected to the first scan line SP.

[0069] When the first reset transistor M7 is turned on, the reset signal on the first reset signal line Vref2 is transmitted to the first electrode of the light emitting element D to reset the first electrode of the light emitting element D, thereby improving the afterimage or streaking problem of the display panel.

[0070] The first scan line SP is electrically connected to the gate of the first reset transistor M7 and the gate of the target transistor MT. In this way, the states of the first reset transistor M7 and the target transistor MT are simultaneously controlled by a single first scan line SP, which can save the number of gate wirings required for the transistors and help improve pixel density (Pixels Per Inch, PPI).

[0071] In some embodiments, as Figure 3 or Figure 4 In the thickness direction of the display panel, the active layer of the first reset transistor M7 overlaps with the first scan line SP.

[0072] For example, the first scan line SP extends along the first direction X, the active layer of the first reset transistor M7 extends along the second direction Y, and the overlapping portion of the first scan line SP and the active layer of the first reset transistor M7 serves as the gate of the first reset transistor M7. In this way, there is no need to provide an additional connecting line to connect the first scan line SP and the gate of the first reset transistor M7.

[0073] It is understood that, in the thickness direction of the display panel, the active layer of the target transistor MT overlaps with the first scan line SP. The gate gt of the target transistor MT is electrically connected to the first scan line SP via the second connection line 12. When the gate gt of the target transistor MT and the first scan line SP are located in the same film layer, the gate gt of the target transistor MT is disconnected from the first scan line SP in the film layer.

[0074] Figures 8 to 13 Shown are some schematic diagrams of the layout structure of local areas in the display panel. Figures 8 to 13 The structures with the same filling pattern represent structures located in the same film layer, and the structures with different filling patterns represent structures located in different film layers.

[0075] In some embodiments, please refer to Figure 8 、 Figure 12 and Figure 13 The first reset signal line Vref2 extends along the first direction X, and a plurality of first reset signal lines Vref2 are arranged in the second direction Y.

[0076] The display panel further includes a third connection line 13 electrically connected to adjacent first reset signal lines Vref2 in the second direction Y via the third connection line 13. The first reset signal line Vref2 and the third connection line 13 are located in different film layers and are electrically connected via a via.

[0077] The extension direction of the third connection line 13 intersects with the extension direction of the first reset signal line Vref2. Multiple third connection lines 13 and multiple first reset signal lines Vref2 intersect to form a grid-like routing structure, which can reduce the voltage drop of the first reset signal line Vref2 and improve display uniformity.

[0078] Exemplarily, the display panel includes multiple light-emitting elements emitting different colors. In some examples, the multiple light-emitting elements emitting different colors can be electrically connected to the same first reset signal line Vref2. In other examples, at least two light-emitting elements emitting different colors can be electrically connected to different first reset signal lines Vref2. In this way, different reset signals can be transmitted to the light-emitting elements of different colors via different first reset signal lines Vref2, thereby flexibly meeting the needs of light-emitting elements of different colors.

[0079] In some embodiments, as Figure 8 and Figure 12 As shown, at least a portion of the third connecting line 13 and the second connecting line 12 are located in the same film layer.

[0080] As an example, the third connection line 13 includes a first segment 131 and a second segment 132 electrically connected to each other. The second connection line 12 and the first segment 131 are located in the second metal layer 102 , and the second segment 132 is located in a metal layer outside the second metal layer 102 .

[0081] Illustratively, one end of the first segment 131 is electrically connected to the first reset signal line Vref2 through a via, and the other end of the first segment 131 is electrically connected to the second segment 132 through a via.

[0082] Of course, in other embodiments, the entire third connecting line 13 and the second connecting line 12 may be located in the same film layer, which will be described in the following embodiments.

[0083] In this embodiment, at least part of the third connection line 13 and the second connection line 12 are designed in the same film layer. In this way, multiple lines can be placed in one film layer, making full use of the film layer, which is conducive to achieving a lighter and thinner display panel.

[0084] In some embodiments, as Figure 8 and Figure 12 As shown, the second electrode of the target transistor MT is electrically connected to the target signal line 21 via a fourth connection line 14. The fourth connection line 14 and the target signal line 21 are located in different metal layers. One end of the fourth connection line 14 is electrically connected to the second electrode of the target transistor MT through a via, and the other end of the fourth connection line 14 is electrically connected to the target signal line 21 through a via.

[0085] In this embodiment, by designing the fourth connecting line 14, the target signal line 21 can transmit signals to the target transistor MT. When the fourth connecting line 14 and the target signal line 21 are located in different metal layers, the arrangement of the target signal line 21 can be flexibly designed to flexibly meet different needs.

[0086] In some embodiments, as Figure 8 As shown, in the thickness direction of the display panel, the fourth connection line 14 at least partially overlaps with the emission control signal line emit, and the fourth connection line 14 at least partially overlaps with the first scan line SP.

[0087] An extending direction of at least a portion of the fourth connection line 14 intersects with an extending direction of the emission control signal line emit, and an extending direction of at least a portion of the fourth connection line 14 intersects with an extending direction of the first scan line SP.

[0088] Exemplarily, in the same pixel circuit, the driving transistor M3 and the target transistor MT are located on the same side of the emission control signal line emit in the second direction Y, and the fourth connection line 14 crosses the emission control signal line emit and the first scan line SP in the second direction Y.

[0089] In some embodiments, as Figure 5 As shown, the pixel circuit includes a bias adjustment transistor M8, the target transistor MT includes the bias adjustment transistor M8, and the target signal line 21 includes a bias signal line DVH.

[0090] In the case where the target signal line 21 includes the bias signal line DVH, reference Figure 8 and Figure 9 The display panel includes a first semiconductor layer 1001 , the first semiconductor layer 1001 includes a plurality of first semiconductor patterns 1011 , the first semiconductor patterns 1011 include active layers of first type transistors, and the first semiconductor patterns 1011 are an integrated structure.

[0091] Figures 8 to 13 A dotted box in the figure roughly represents the area where a pixel circuit is located, and a first semiconductor pattern 1011 corresponds to the active layer of the first type transistor in a pixel circuit.

[0092] As an example, please refer to Figure 5 and Figure 9 The transistors M1 to M8 in the pixel circuit are all first-type transistors, and the first semiconductor pattern 1011 includes the active layers of the transistors M1 to M8 in the pixel circuit. In the same pixel circuit, the active layers of the first-type transistors are connected to form an integrated structure on the first semiconductor layer 1001.

[0093] During the preparation process of the display panel, static electricity may occur in the active layer of the transistor. In this embodiment, the active layers of multiple first-type transistors in the first semiconductor pattern 1011 are connected into an integrated structure, and static electricity can be evenly distributed in the active layers of multiple first-type transistors, thereby avoiding excessive performance differences between different first-type transistors in the same pixel circuit.

[0094] Exemplarily, the first type of transistor is a P-type transistor, for example, a low-temperature polysilicon (LTPS) transistor.

[0095] In some embodiments, as Figure 9 As shown, the plurality of first semiconductor patterns 1011 arranged in the first direction X are an integrated structure.

[0096] In the first direction X, any two adjacent first semiconductor patterns 1011 are connected to each other, and their connection portions are located in the first semiconductor layer 1001. In other words, the plurality of first semiconductor patterns 1011 arranged in the first direction X are integrally formed.

[0097] The plurality of first semiconductor patterns 1011 arranged in the first direction X correspond to the plurality of pixel circuits arranged in the first direction X. In this embodiment, the plurality of first semiconductor patterns 1011 arranged in the first direction X are integrated into one structure, so that static electricity can be evenly distributed across the plurality of first semiconductor patterns 1011, thereby preventing significant performance differences between transistors in different pixel circuits.

[0098] In some embodiments, please refer to Figure 5 and Figure 9 The display panel includes a first reset transistor M7, which is electrically connected to the first electrode of the light-emitting element D. The first semiconductor pattern 1011 includes a first portion 1011a; the i-th first reset transistor M7(i) and the i+1-th first reset transistor M7(i+1) arranged in the first direction X are electrically connected via the first portion 1011a. i is an integer greater than or equal to 1.

[0099] The first portion 1011 a is a semiconductor portion, and the active layer of the i-th first reset transistor M7 ( i ) and the active layer of the i+1-th first reset transistor M7 ( i+1 ) arranged in the first direction X are electrically connected through the first portion 1011 a .

[0100] Exemplarily, the first semiconductor pattern 1011 further includes a fourth portion 1011d , one end of the fourth portion 1011d is connected to the first portion 1011a , and the other end of the fourth portion 1011d is electrically connected to the first reset signal line Vref2 through a via hole.

[0101] The signal on the first reset signal line Vref2 is sequentially transmitted to the i-th first reset transistor M7(i) and the (i+1)-th first reset transistor M7(i+1) through the fourth portion 1011d and the first portion 1011a.

[0102] In this embodiment, the i-th first reset transistor M7(i) and the (i+1)-th first reset transistor M7(i+1) are electrically connected via the first portion 1011a, such that the i-th first semiconductor pattern 1011 and the (i+1)-th first semiconductor pattern 1011 arranged in the first direction X form an integrated structure. Furthermore, the two first reset transistors M7 electrically connected to each other via the first portion 1011a can be electrically connected to the first reset signal line Vref2 via the same fourth portion 1011d, thereby simplifying the structure and facilitating an improvement in PPI.

[0103] In some embodiments, please refer to Figure 5 and Figure 9 The display panel includes a second reset transistor M5, which is electrically connected to the gate of the driving transistor M3. The first semiconductor pattern 1011 includes a second portion 1011b, through which the i+1th second reset transistor M5(i+1) and the i+2th second reset transistor M5(i+2) arranged in the first direction X are electrically connected.

[0104] The second portion 1011b is a semiconductor portion, and the active layer of the i+1th second reset transistor M5(i+1) and the active layer of the i+2th second reset transistor M5(i+2) arranged in the first direction X are electrically connected through the second portion 1011b.

[0105] Exemplarily, the display panel further includes a seventh connection line 17 , one end of the seventh connection line 17 is electrically connected to the second portion 1011 b through a via hole, and the other end of the seventh connection line 17 is electrically connected to the second reset signal line Vref1 through a via hole.

[0106] The signal on the second reset signal line Vref1 is sequentially transmitted to the (i+1)th second reset transistor M5 (i+1) and the (i+2)th second reset transistor M5 (i+2) through the seventh connection line 17 and the second portion 1011b.

[0107] In this embodiment, the (i+1)th second reset transistor M5(i+1) and the (i+2)th second reset transistor M5(i+2) are electrically connected via the second portion 1011b, such that the (i+1)th first semiconductor pattern 1011 and the (i+2)th first semiconductor pattern 1011 arranged in the first direction X form an integrated structure. Furthermore, the two second reset transistors M5 electrically connected to each other via the second portion 1011b can be electrically connected to the second reset signal line Vref1 via the same seventh connection line 17, thereby simplifying the structure and facilitating an improvement in PPI.

[0108] In some embodiments, please refer to Figure 5 and Figure 9The first semiconductor pattern 1011 includes a third portion 1011 c, and the i+1th bias adjustment transistor M8(i+1) and the i+2th bias adjustment transistor M8(i+2) arranged in the first direction X are electrically connected through the third portion 1011 c.

[0109] The third portion 1011c is a semiconductor portion, and the active layer of the i+1th bias adjustment transistor M8(i+1) and the active layer of the i+2th bias adjustment transistor M8(i+2) arranged in the first direction X are electrically connected through the third portion 1011c.

[0110] Exemplarily, one end of the fourth connection line 14 is connected to the third portion 1011 c through a via hole, and the other end of the third portion 1011 c is electrically connected to the bias signal line DVH through a via hole.

[0111] The signal on the bias signal line DVH is sequentially transmitted to the (i+1)th bias adjustment transistor M8(i+1) and the (i+2)th bias adjustment transistor M8(i+2) through the fourth connection line 14 and the third portion 1011c.

[0112] In this embodiment, the (i+1)th bias adjustment transistor M8(i+1) and the (i+2)th bias adjustment transistor M8(i+2) are electrically connected via the third portion 1011c, such that the (i+1)th first semiconductor pattern 1011 and the (i+2)th first semiconductor pattern 1011 arranged in the first direction X form an integrated structure. Furthermore, the two bias adjustment transistors M8 electrically connected to each other via the third portion 1011c can be electrically connected to the bias signal line DVH via the same fourth connection line 14, simplifying the structure and facilitating an improvement in PPI.

[0113] For example, Figure 9 As shown, the i+2 th first reset transistor M7 (i+2) and the i+3 th first reset transistor M7 (i+3) arranged in the first direction X are electrically connected through the first portion 1011 a.

[0114] Four first semiconductor patterns 1011 arranged in the first direction X constitute a repeating unit, and the display panel includes a plurality of repeating units arranged in the first direction. The four first semiconductor patterns 1011 in the repeating unit are respectively the i-th to the i+3-th first semiconductor patterns 1011 .

[0115] In some embodiments, please refer to Figures 8 to 13 The display panel includes a plurality of circuit rows, each of which includes a plurality of bias adjustment transistors M8 arranged along a first direction X. For example Figures 8 to 13 In FIG, a dotted frame with 2 rows and 4 columns is shown, which is used to represent 8 pixel circuits with 2 rows and 4 columns.

[0116] Please refer to Figure 8 、 Figure 11 and Figure 12 The bias signal line DVH extends along the first direction X, and one bias signal line DVH is provided for each of two adjacent circuit rows. The display panel further includes a fifth connection line 15 , through which adjacent bias signal lines DVH in the second direction Y are electrically connected.

[0117] Exemplarily, the bias signal line DVH and the fifth connection line 15 are located in different film layers and are electrically connected to each other through a via.

[0118] The extension direction of the fifth connecting lines 15 intersects that of the bias signal lines DVH. Multiple fifth connecting lines 15 and multiple bias signal lines DVH intersect to form a grid-like routing structure, which reduces voltage drop across the bias signal lines DVH and improves display uniformity. Furthermore, a bias signal line DVH is provided for every two circuit rows, leaving space for other routing lines in the film layer where the bias signal lines DVH reside. This facilitates the arrangement of more signal lines while utilizing fewer film layers.

[0119] For example, since a bias signal line DVH is provided corresponding to every two circuit rows, in two adjacent circuit rows, the fourth connection line 14 corresponding to one circuit row can be directly electrically connected to the bias signal line DVH through a via, and the fourth connection line 14 corresponding to the other circuit row can be electrically connected to the bias signal line DVH through a fifth connection line 15.

[0120] In some embodiments, please refer to Figure 5 、 Figure 8 、 Figure 11 and Figure 12 The display panel further includes a first reset transistor M7, which is electrically connected to the first reset signal line Vref2 and the first electrode of the light emitting element D.

[0121] The first reset signal line Vref2 extends along the first direction X, and one first reset signal line Vref2 is correspondingly provided for every two circuit rows.

[0122] The display panel further includes a third connection line 13 , and adjacent first reset signal lines Vref2 in the second direction Y are electrically connected via the third connection line 13 .

[0123] The extension direction of the third connection line 13 intersects with the extension direction of the first reset signal line Vref2. Multiple third connection lines 13 and multiple first reset signal lines Vref2 intersect to form a grid-like routing structure, which can reduce the voltage drop of the third connection lines 13 and improve display uniformity. In addition, a first reset signal line Vref2 is provided for every two circuit rows, leaving space for other routing lines in the film layer where the first reset signal line Vref2 is located, facilitating the layout of more signal lines using fewer film layers.

[0124] For example, Figure 9 As shown, the first reset transistor M7 is connected to the fourth portion 1011d. Since a first reset signal line Vref2 is provided for every two circuit rows, the fourth portion 1011d corresponding to one of the two adjacent circuit rows can be directly electrically connected to the first reset signal line Vref2 through a via, and the fourth portion 1011d corresponding to the other circuit row can be electrically connected to the bias signal line DVH through a fourth connection line 14.

[0125] In some embodiments, as Figure 11 As shown, the bias signal lines DVH and the first reset signal lines Vref2 are located in the same film layer and are arranged alternately in the second direction Y. In this way, the two signal lines can be arranged in the same film layer, and both signal lines can form a grid-like structure. Furthermore, the bias signal lines DVH and the first reset signal lines Vref2 can uniformly provide signals to each circuit row, avoiding large differences in the signals received by different circuit rows on the bias signal lines DVH and the first reset signal lines Vref2, thereby further improving display uniformity.

[0126] In some embodiments, please refer to Figure 11 、 Figure 12 and Figure 13 The third connecting line 13 includes a first segment 131 and a second segment 132 electrically connected to each other. The first segment 131 and the second segment 132 are located in different film layers and are electrically connected via a via. The fifth connecting line 15 includes a third segment 153 and a fourth segment 154 electrically connected to each other. The third segment 153 and the fourth segment 154 are located in different film layers and are electrically connected via a via.

[0127] The second segment 132 and the bias signal line DVH are located in different film layers and at least partially overlap with the bias signal line DVH. A connecting via is provided in the overlapping region of the second segment 132 and the bias signal line DVH to connect the two.

[0128] One end of the second segment 132 is electrically connected to the bias signal line DVH through a via hole, and the other end of the second segment 132 is electrically connected to the first segment 131 through a via hole.

[0129] The third segment 153 and the first reset signal line Vref2 are located in different film layers and at least partially overlap with each other. A connecting via is provided in the overlapping region of the third segment 153 and the first reset signal line Vref2 to connect them.

[0130] One end of the third segment 153 is electrically connected to the first reset signal line Vref2 through a via hole, and the other end of the third segment 153 is electrically connected to the fourth segment 154 through a via hole.

[0131] In this embodiment, the third connecting line 13 is designed to include different line segments, and at least one line segment overlaps with the bias signal line DVH, which facilitates the connection between the third connecting line 13 and the bias signal line DVH, and can flexibly arrange other signal lines in other film layers in the area where the first segment 131 is located; similarly, the fifth connecting line 15 is designed to include different line segments, and at least one line segment overlaps with the first reset signal line Vref2, which facilitates the connection between the fifth connecting line 15 and the first reset signal line Vref2, and can flexibly arrange other signal lines in other film layers in the area where the fourth segment 154 is located.

[0132] For example, Figure 12 and Figure 13 As shown, the first section 131 and the third section 153 are located in the same film layer, and the second section 132 and the fourth section 154 are located in the same film layer.

[0133] As an example, please refer to Figure 11 、 Figure 12 、 Figure 13 and Figure 14 The display panel includes a first semiconductor layer 1001 and a first metal layer 101, a capacitor metal layer 10C, a second metal layer 102 and a third metal layer 103 that are sequentially away from the first semiconductor layer 1001. In addition, Figure 14 In the figure, PI represents the substrate, and GI, IMD, ILD, PLN1, PLN2, PDL, and PS are the respective insulating layers.

[0134] The capacitor metal layer 10C includes bias signal lines DVH and first reset signal lines Vref2 , which are alternately arranged in the second direction Y.

[0135] The second metal layer 102 includes a first segment 131 and a third segment 153 .

[0136] The third metal layer 103 includes a second segment 132 and a fourth segment 154 .

[0137] In this embodiment, the bias signal line DVH and the first reset signal line Vref2 are set in the same film layer, the first section 131 and the third section 153 are set in another film layer, and the second section 132 and the fourth section 154 are set in another film layer. The grid design of the bias signal line DVH and the grid design of the first reset signal line Vref2 are realized while occupying fewer film layers.

[0138] In some embodiments, as Figure 5 and Figure 11 As shown, the capacitor metal layer 10C further includes a second reset signal line Vref1 extending along the first direction, and the pixel circuit includes a second reset transistor M5 , which is electrically connected to the second reset signal line Vref1 and the gate of the driving transistor M3 .

[0139] The second reset signal line Vref1 extends along the first direction X. In the capacitor metal layer 10C and in the second direction Y, a portion of the second reset signal line Vref1 is adjacent to the bias signal line DVH, and a portion of the second reset signal line Vref1 is adjacent to the first reset signal line Vref2. "Adjacent" here means that the upper plate c11 of the storage capacitor is not interposed between the two in the second direction Y.

[0140] It is understandable that each circuit row is correspondingly provided with a second reset signal line Vref1 .

[0141] In some embodiments, please refer to Figure 12 and Figure 13 The first power line PVDD includes a first branch line PVDD1 and a second branch line PVDD2 electrically connected to each other. The first branch line PVDD1 extends along the first direction X, and the second branch line PVDD2 extends along the second direction Y. The second metal layer 102 includes the first branch line PVDD1, and the third metal layer 103 includes the second branch line PVDD2.

[0142] The first branch line PVDD1 and the second branch line PVDD2 are electrically connected through a via.

[0143] The plurality of first branch lines PVDD1 and the plurality of second branch lines PVDD2 intersect with each other to form a grid-like first power line PVDD, which can reduce the voltage drop of the first power line PVDD and improve display uniformity.

[0144] Exemplarily, each circuit row is correspondingly provided with a first branch line PVDD1.

[0145] In the thickness direction of the display panel, the first branch line PVDD1 and the second segment 132 of the third connection line 13 at least partially overlap, and the first branch line PVDD1 and the fourth segment 154 of the fifth connection line 15 at least partially overlap.

[0146] Illustratively, the first power line PVDD also includes a fifth branch line PVDD5, which is integrally formed with the first branch line PVDD1. In the thickness direction of the display panel, the second branch line PVDD2, the fifth branch line PVDD5, and the top plate c11 of the storage capacitor at least partially overlap. The second branch line PVDD2 and the fifth branch line PVDD5 are electrically connected via a via, and the fifth branch line PVDD5 is electrically connected to the top plate c11 of the storage capacitor via a via.

[0147] In the thickness direction of the display panel, a fifth branch line PVDD5 at least partially overlaps with two adjacent second branch lines PVDD2. In the thickness direction of the display panel, a fifth branch line PVDD5 at least partially overlaps with the upper plates c11 of two adjacent storage capacitors. A fifth branch line PVDD5 is provided for every two adjacent pixel circuits.

[0148] Illustratively, in the first direction X, the upper plates c11 of the storage capacitors of adjacent pixel circuits are connected as one.

[0149] like Figure 12 and Figure 13 As shown, the display panel further includes a data line data, which extends along the second direction Y and is located in the third metal layer 103 .

[0150] The display panel further includes a first auxiliary line FIAA1 and a second auxiliary line FIAA2 . The first auxiliary line FIAA1 extends along a first direction X, and the second auxiliary line FIAA2 extends along a second direction Y. The first auxiliary line FIAA1 is located in the second metal layer 102 , and the second auxiliary line FIAA2 is located in the third metal layer 103 .

[0151] Illustratively, at least a portion of the first auxiliary line FIAA1 and the second auxiliary line FIAA2 is used to electrically connect to the data line data.

[0152] The first auxiliary line FIAA1 and the first branch line PVDD1 are disposed adjacent to each other. The first auxiliary line FIAA1 and the fifth branch line PVDD5 are located on both sides of the first branch line PVDD1 respectively.

[0153] In the thickness direction of the display panel, the first subline FIAA1 and the second segment 132 of the third connection line 13 at least partially overlap, and the first subline FIAA1 and the fourth segment 154 of the fifth connection line 15 at least partially overlap.

[0154] Exemplarily, every two adjacent second auxiliary lines FIAA2 constitute a auxiliary line group, and every two adjacent data lines data constitute a data line group. In the first direction X, the auxiliary line groups and the data line groups are alternately arranged.

[0155] In some embodiments, please refer to Figure 8 、 Figure 10and Figure 12 In the first direction X, two adjacent bias adjustment transistors M8 form a transistor group, and the gates of the two bias adjustment transistors M8 in the transistor group are electrically connected to the first scan line SP through the same second connection line 12.

[0156] The gates g8 of the two bias adjustment transistors M8 in the transistor group are an integrated structure.

[0157] In this embodiment, one second connection line 12 can transmit the scan signal to the gates of two bias adjustment transistors M8 , which can reduce the number of second connection lines 12 and simplify the structure.

[0158] For example, please refer to Figure 8 、 Figure 10 and Figure 11 The display panel also includes a first shielding structure 41. The first shielding structure 41 at least partially overlaps the channel of the bias adjustment transistor M8 in the thickness direction of the display panel. The first shielding structure 41 can shield the bias adjustment transistor M8 from the effects of light and / or other signals, thereby improving the performance stability of the bias adjustment transistor M8.

[0159] For example, Figure 9 As shown, the channels of some driving transistors M3 are zigzag (e.g., an inverted "X" shape), while the channels of other driving transistors M3 are straight. The channel shapes of the driving transistors M3 are designed to flexibly match the characteristics of different light-emitting elements to improve the overall display effect.

[0160] For example, please refer to Figure 8 and Figure 12 The display panel further includes an eighth connection line 18, one end of which is electrically connected to the gate of the driving transistor M3, and the other end of the eighth connection line 18 is electrically connected to the transistor M4 and the transistor M5. The eighth connection line 18 is located in the third metal layer 103. The eighth connection line 18 extends along the second direction Y. The line width of the eighth connection line 18 is greater than the line widths of other lines in the third metal layer 103. The voltage on the second branch line PVDD2 is substantially constant. The eighth connection line 18 at least partially overlaps with the second branch line PVDD2. When the line width of the eighth connection line 18 is larger, the capacitance formed by the eighth connection line 18 and the second branch line PVDD2 is larger, thereby making the gate potential of the driving transistor M3 more stable.

[0161] Figures 8 to 14 Some examples in which the display panel includes one first semiconductor layer are shown. In other embodiments, the display panel may include at least two semiconductor layers.

[0162] In some embodiments, as Figure 6As shown, the pixel circuit includes a bias adjustment transistor M8, the target transistor MT includes the bias adjustment transistor M8, and the target signal line 21 includes a bias signal line DVH.

[0163] In the case where the target signal line 21 includes the bias signal line DVH, please refer to Figures 15 to 22 The display panel includes a second semiconductor layer 1002 , the second semiconductor layer 1002 includes a second semiconductor pattern 1012 , the second semiconductor pattern 1012 includes an active layer of a second type transistor, the first type includes a P type, and the second type includes an N type.

[0164] For example, the first type of transistor is a low-temperature polysilicon (LTPS) transistor, and the second type of transistor is an indium gallium zinc oxide (IGZO) transistor.

[0165] Figures 15 to 22 A dotted box roughly represents the area where a pixel circuit is located, a first semiconductor pattern 1011 corresponds to the active layer of a first type transistor in a pixel circuit, and a second semiconductor pattern 1012 corresponds to the active layer of a second type transistor in a pixel circuit.

[0166] As an example, please refer to Figure 6 、 Figure 16 and Figure 19 , transistors M1, M2, M3, M6, M7, and M8 in the pixel circuit are all first-type transistors, and transistors M4 and M5 in the pixel circuit are second-type transistors. The first semiconductor pattern 1011 includes the active layers of the transistors M1, M2, M3, M6, M7, and M8 in the pixel circuit. The second semiconductor pattern 1012 includes the active layers of the transistors M4 and M5 in the pixel circuit. In the same pixel circuit, the active layers of each first-type transistor are connected to form an integrated structure on the first semiconductor layer 1001. In the same pixel circuit, the active layers of each second-type transistor are connected to form an integrated structure on the second semiconductor layer 1002.

[0167] For example, Figure 16 As shown, the first semiconductor patterns 1011 of different pixel circuits are disconnected from each other. Figure 19 As shown, the second semiconductor patterns 1012 of different pixel circuits are disconnected from each other.

[0168] The carrier movement speed of the P-type transistor is fast, and the leakage current of the N-type transistor is small. The combination of the P-type transistor and the N-type transistor can improve the overall performance of the pixel circuit.

[0169] In some embodiments, please refer to Figure 6 、 Figure 15 、 Figure 20 and Figure 21 The display panel includes a plurality of circuit rows, each of which includes a plurality of driving transistors M3 arranged along a first direction X.

[0170] The bias signal line DVH extends along the first direction X, and each circuit row is correspondingly provided with a bias signal line DVH.

[0171] The display panel further includes a sixth connection line 16 , and the bias signal lines DVH adjacent to each other in the second direction Y are electrically connected via the sixth connection line 16 .

[0172] Exemplarily, the bias signal line DVH and the sixth connection line 16 are located in different film layers and are electrically connected to each other through a via.

[0173] The extension direction of the sixth connecting lines 16 intersects with the extension direction of the bias signal lines DVH. Multiple sixth connecting lines 16 and multiple bias signal lines DVH intersect to form a grid-like routing structure, which can reduce the voltage drop of the bias signal lines DVH and improve display uniformity. Furthermore, each circuit row is provided with a corresponding bias signal line DVH, making the grid formed by the sixth connecting lines 16 and the bias signal lines DVH denser, further reducing the voltage drop of the bias signal lines DVH.

[0174] Exemplarily, the fourth connection line 14 is electrically connected to the sixth connection line 16. The fourth connection line 14 and the sixth connection line 16 may be an integral structure.

[0175] In some embodiments, as Figure 23 As shown, the display panel includes a first semiconductor layer 1001 and a first metal layer 101, a capacitor metal layer 10C, a second semiconductor layer 1002, a gate metal layer 10G, a second metal layer 102 and a third metal layer 103 that are sequentially away from the first semiconductor layer 1001. In addition, Figure 23 In the figure, PI represents the substrate, and GI1, IMD, ILD1, GI2, GI3, ILD2, PLN1, PLN2, PDL, and PS are respective insulating layers.

[0176] The gate metal layer 10G includes a bias signal line DVH, the second metal layer 102 includes a sixth connection line 16 , and the third metal layer 103 includes a first power line PVDD.

[0177] Exemplarily, the second metal layer 102 further includes a second connection line 12. The capacitor metal layer 10C further includes a first reset signal line Vref2, a second reset signal line Vref1, a scan line SN1, and a scan line SN2.

[0178] The third metal layer 103 further includes a data line data.

[0179] Exemplarily, in the thickness direction of the display panel, the first power line PVDD covers the channels of the transistor M4 and the transistor M5 .

[0180] Figures 8 to 23 Some examples are illustrated in which the target transistor is the bias adjustment transistor M8 and the target signal line is the bias signal line DVH.

[0181] In other examples, such as Figure 7 As shown, the target transistor MT is the data writing transistor M2, and the target signal line 21 is the data line data.

[0182] In the case where the target signal line 21 is a data line, please refer to Figure 25 The display panel includes a first semiconductor layer 1001, the first semiconductor layer includes a third semiconductor pattern 1013, the third semiconductor pattern 1013 includes an active layer of each first type transistor in the pixel circuit, and the third semiconductor patterns 1013 corresponding to different pixel circuits are disconnected from each other.

[0183] Figures 24 to 29 A dotted line frame is roughly the area where a pixel circuit is located, and a third semiconductor pattern 1013 corresponds to the active layer of the first type transistor in a pixel circuit. The third semiconductor patterns 1013 corresponding to the same pixel circuit are an integrated structure.

[0184] As an example, please refer to Figure 7 and Figure 25 The transistors M1 to M7 in the pixel circuit are all first-type transistors, and the third semiconductor pattern 1013 includes active layers of the transistors M1 to M7 in the pixel circuit.

[0185] In some embodiments, the first power line PVDD includes a third branch line PVDD3 and a fourth branch line PVDD4 that are electrically connected to each other, and the third branch line PVDD3 and the fourth branch line PVDD4 both extend along the second direction Y. The third branch line PVDD3 and the fourth branch line PVDD4 are located in different film layers. The third branch line PVDD3 and the fourth branch line PVDD4 are electrically connected together, which is equivalent to thickening the first power line PVDD, reducing the voltage drop on the first power line PVDD and improving display uniformity.

[0186] The third branch line PVDD3 and the second connection line 12 are located in the same film layer.

[0187] Exemplarily, the third branch line PVDD3 , the second connection line 12 , and the fourth connection line 14 are located in a same film layer as the third branch line PVDD3 and the second connection line 12 .

[0188] In some embodiments, as Figure 7 As shown, the display panel further includes a first reset transistor M7 and a second reset transistor M5. The first reset transistor M7 is electrically connected to the first reset signal line Vref2 and the first electrode of the light emitting element D. The second reset transistor M5 is electrically connected to the second reset signal line Vref1 and the gate of the driving transistor M5.

[0189] Please refer to Figure 24 and Figure 27 The first reset signal line Vref2 and the second reset signal line Vref1 are located in the same film layer and are alternately arranged in the second direction Y.

[0190] For example, please refer to Figure 24 、 Figure 27 and Figure 28 The third connection line 13 is electrically connected to the first reset signal line Vref2. A plurality of third connection lines 13 and a plurality of first reset signal lines Vref2 intersect with each other to form a grid structure, which can reduce the voltage drop of the first reset signal line Vref2.

[0191] The seventh connection line 17 is electrically connected to the second reset signal line Vref1 . A plurality of seventh connection lines 17 and a plurality of second reset signal lines Vref1 intersect with each other to form a grid structure, which can reduce the voltage drop of the second reset signal line Vref1 .

[0192] Figures 24 to 29 The film layer stacking structure of the display panel corresponding to the example shown can be as follows Figure 14 As shown, Figure 27 As shown, the capacitor metal layer 10C includes a first reset signal line Vref2, a second reset signal line Vref1, and an upper plate c11 of the storage capacitor. The capacitor metal layer 10C may also include a second shielding structure 42. The transistor M4 includes two sub-transistors, and the two sub-transistors of the transistor M4 are connected via a semiconductor connector. The second shielding structure 42 overlaps the semiconductor connector of the transistor M4 in the thickness direction of the display panel. The second shielding structure 42 is electrically connected to the first power line PVDD.

[0193] The second metal layer 102 includes a second connection line 12 , a third connection line 13 , a fourth connection line 14 , a seventh connection line 17 , an eighth connection line 18 and a third branch line PVDD3 .

[0194] The third metal layer 103 includes a data line data and a fourth branch line PVDD4 .

[0195] Based on the same technical concept, the present application also provides a display device, including the display panel provided by the present application. Figure 30 , Figure 30It is a structural schematic diagram of a display device provided in an embodiment of the present application. Figure 30 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Figure 30 The embodiment only uses a mobile phone as an example to illustrate the display device 1000. It is understandable that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, an in-vehicle display device, or other display device with a display function, and the present application does not impose specific limitations on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0196] While the embodiments described above are not exhaustive, they do not limit the present application to the specific embodiments described. Clearly, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to better utilize the present application and its modifications. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: include: a driving transistor, a power write transistor, a target transistor, a light-emitting element, and a first connecting line, wherein the first connecting line includes a first branch and a second branch, the first electrode of the driving transistor is electrically connected to the first electrode of the power write transistor via the first branch, the second electrode of the power write transistor is electrically connected to the first power line, the first electrode of the driving transistor is electrically connected to the first electrode of the target transistor via the second branch, the second electrode of the driving transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the target transistor is electrically connected to the target signal line; a light emitting control signal line electrically connected to the gate of the power writing transistor; A first scanning line extending along a first direction; a second connecting line connected between the first scan line and the gate of the target transistor; The first scanning line and the second connecting line are located in different film layers; In the thickness direction of the display panel, the first connection line and the light emitting control signal line do not overlap.

2. The display panel according to claim 1, wherein: The first scanning line and the light emitting control signal line are located in the same film layer.

3. The display panel according to claim 1, wherein: The display panel also includes a first reset transistor and a first reset signal line, the first electrode of the first reset transistor is electrically connected to the first reset signal line, the second electrode of the first reset transistor is electrically connected to the first electrode of the light-emitting element, and the gate of the first reset transistor is electrically connected to the first scan line.

4. The display panel according to claim 3, wherein: In a thickness direction of the display panel, the active layer of the first reset transistor overlaps the first scan line.

5. The display panel according to claim 3, wherein: The first reset signal line extends along the first direction. The display panel further includes a third connection line. Adjacent first reset signal lines are electrically connected via the third connection line. The first reset signal line and the third connection line are located in different film layers.

6. The display panel according to claim 3, wherein: At least a portion of the third connecting line and the second connecting line are located in the same film layer.

7. The display panel according to claim 1, wherein: The second electrode of the target transistor is electrically connected to the target signal line through a fourth connecting line, and the fourth connecting line and the target signal line are located in different metal layers.

8. The display panel according to claim 7, wherein: The fourth connecting line at least partially overlaps with the light emitting control signal line, and the fourth connecting line at least partially overlaps with the first scan line.

9. The display panel according to claim 1, wherein: The target transistor includes a bias adjustment transistor, and the target signal line includes a bias signal line.

10. The display panel according to claim 9, wherein: The display panel includes a first semiconductor layer, the first semiconductor layer includes a plurality of first semiconductor patterns, the first semiconductor patterns include active layers of first-type transistors, and the first semiconductor patterns are an integrated structure.

11. The display panel according to claim 10, wherein: The plurality of first semiconductor patterns arranged in the first direction form an integrated structure.

12. The display panel according to claim 11, wherein: The display panel includes a first reset transistor electrically connected to the light emitting element; the first semiconductor pattern includes a first portion; the i-th first reset transistor and the i+1-th first reset transistor arranged in the first direction are electrically connected through the first portion.

13. The display panel according to claim 11, wherein: The display panel includes a second reset transistor, which is electrically connected to the gate of the driving transistor; the first semiconductor pattern includes a second part, and the i+1th second reset transistor and the i+2th second reset transistor arranged in the first direction are electrically connected through the second part.

14. The display panel according to claim 11, wherein: The first semiconductor pattern includes a third portion, and the (i+1)th bias adjustment transistor and the (i+2)th bias adjustment transistor arranged in the first direction are electrically connected through the third portion.

15. The display panel according to claim 11, wherein: The display panel includes a plurality of circuit rows, each of the circuit rows including a plurality of bias adjustment transistors arranged along the first direction; The bias signal line extends along the first direction, and two adjacent circuit rows are correspondingly provided with one bias signal line; The display panel further includes a fifth connecting line, and adjacent bias signal lines are electrically connected via the fifth connecting line.

16. The display panel according to claim 15, wherein: The display panel further includes a first reset transistor electrically connected to a first reset signal line and a first electrode of the light emitting element; The first reset signal line extends along the first direction, and one first reset signal line is correspondingly provided for every two circuit rows; The display panel further includes a third connecting line, and adjacent first reset signal lines are electrically connected via the third connecting line.

17. The display panel according to claim 16, wherein: The bias signal lines and the first reset signal lines are located in the same film layer and are alternately arranged in the second direction.

18. The display panel according to claim 17, wherein: The third connecting line includes a first section and a second section electrically connected to each other, and the fifth connecting line includes a third section and a fourth section electrically connected to each other; The second section and the bias signal line are located in different film layers, and the second section and the bias signal line at least partially overlap; The third section and the first reset signal line are located in different film layers, and the third section and the first reset signal line at least partially overlap.

19. The display panel according to claim 18, wherein: The display panel includes a first semiconductor layer and a first metal layer, a capacitor metal layer, a second metal layer and a third metal layer that are sequentially away from the first semiconductor layer; The capacitor metal layer includes the bias signal line and the first reset signal line; The second metal layer includes the first segment and the third segment; The third metal layer includes the second segment and the fourth segment.

20. The display panel according to claim 19, wherein The capacitor metal layer further includes a second reset signal line extending along the first direction. The pixel circuit includes a second reset transistor. The second reset transistor is electrically connected to the second reset signal line and the gate of the driving transistor.

21. The display panel according to claim 19, wherein The first power line includes a first branch line and a second branch line electrically connected to each other, the first branch line extends along a first direction, and the second branch line extends along a second direction; The second metal layer includes the first branch line, and the third metal layer includes the second branch line.

22. The display panel according to claim 11, wherein: In the first direction, two adjacent bias adjustment transistors form a transistor group, and gates of the two bias adjustment transistors in the transistor group are electrically connected to the first scan line through the same second connection line.

23. The display panel according to claim 10, wherein: The display panel includes a second semiconductor layer including a second semiconductor pattern. The second semiconductor pattern includes an active layer of a second type transistor, wherein the first type includes a P type and the second type includes an N type.

24. The display panel according to claim 23, wherein: The display panel includes a plurality of circuit rows, each of which includes a plurality of driving transistors arranged along the first direction; The bias signal line extends along the first direction, and each circuit row is correspondingly provided with one bias signal line; The display panel further includes a sixth connecting line, and adjacent bias signal lines are electrically connected via the sixth connecting line.

25. The display panel according to claim 24, wherein: The display panel includes a first semiconductor layer and a first metal layer, a capacitor metal layer, a second semiconductor layer, a gate metal layer, a second metal layer and a third metal layer that are sequentially away from the first semiconductor layer; The gate metal layer includes the bias signal line, the second metal layer includes the sixth connection line, and the third metal layer includes the first power line.

26. The display panel according to claim 1, wherein The target signal line includes a data line.

27. The display panel according to claim 27, wherein: The display panel includes a first semiconductor layer, the first semiconductor layer includes a third semiconductor pattern, the third semiconductor pattern includes an active layer of a first type transistor, and the third semiconductor patterns corresponding to different pixel circuits are disconnected from each other.

28. The display panel according to claim 27, wherein: The first power line includes a third branch line and a fourth branch line electrically connected to each other, and the third branch line and the fourth branch line both extend along the second direction; The third branch line and the second connection line are located in the same film layer; The third branch line and the fourth branch line are located in different film layers.

29. The display panel according to claim 27, wherein: The display panel further includes a first reset transistor and a second reset transistor, the first reset transistor being electrically connected to a first reset signal line and a first electrode of the light-emitting element, and the second reset transistor being electrically connected to a second reset signal line and a gate of the driving transistor; The first reset signal lines and the second reset signal lines are located in the same film layer and are alternately arranged in the second direction.

30. A display device, characterized in that: Comprising the display panel according to any one of claims 1-29.

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