Etching method of semiconductor device and semiconductor device

Abstract

The application relates to an etching method of a semiconductor device and the semiconductor device, and the semiconductor device has a laminated structure, which comprises a lower electrode layer, a resistance change layer, an upper electrode layer, an organic medium layer and a mask layer arranged in sequence from bottom to top; the etching method comprises the following steps: etching the organic medium layer until the upper electrode layer is exposed to form a patterned organic medium layer; etching the upper electrode layer and the resistance change layer in sequence until the lower electrode layer is exposed; wherein, at least part of the thickness of the patterned organic medium layer is not etched in the process of etching the upper electrode layer and the resistance change layer. Taking a resistance change memory as an example, the etching method of the semiconductor device provided by the application realizes the protection of the thickness of the upper electrode layer to improve the performance and reliability of the resistance change memory.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to an etching method for semiconductor devices and a semiconductor device. Background Technology

[0002] With the rapid development of semiconductor technology, conventional memory can no longer meet people's needs. To meet the ever-increasing demands, non-volatile memory has gradually come into view, such as ferroelectric RAM (FeRAM), magnetic RAM (MRAM), phase-change RAM (PRAM), and resistive random access memory (RRAM). Among them, resistive random access memory mainly consists of an upper electrode layer, a resistive switching layer, and a lower electrode layer. It has advantages such as simple structure, high integration density, good fatigue resistance, long data retention time, and compatibility with CMOS.

[0003] In related technologies, during the etching process of resistive random access memory (PRAM), an inorganic hard mask is used. However, the thickness of the inorganic hard mask cannot be protected during the etching process, resulting in insufficient thickness of the inorganic hard mask after etching. The etchant may penetrate the inorganic mask layer and directly attack the underlying top electrode layer, causing damage to the top electrode layer. This damage to the top electrode layer leads to increased contact resistance and uneven current distribution, and may even cause perforation of the top electrode layer, resulting in short-circuit failure, which affects the performance and reliability of the resistive random access memory. Summary of the Invention

[0004] The present invention aims to solve the problems existing in related technologies and proposes an etching method for semiconductor devices that can protect the thickness of the upper electrode layer and avoid the loss of the upper electrode layer thickness, thereby improving the performance and reliability of semiconductor devices.

[0005] The present invention provides an etching method for a semiconductor device, wherein the resistive switching memory has a stacked structure, the stacked structure comprising, from bottom to top, a lower electrode layer, a resistive switching layer, an upper electrode layer, an organic dielectric layer and a mask layer;

[0006] The etching method includes the following steps:

[0007] The organic dielectric layer is etched until the upper electrode layer is exposed, forming a patterned organic dielectric layer.

[0008] The upper electrode layer and the resistive switching layer are etched sequentially until the lower electrode layer is exposed; wherein, during the etching of the upper electrode layer and the resistive switching layer, at least a portion of the patterned organic dielectric layer is not etched.

[0009] Optionally, a bottom anti-reflective layer is provided between the mask layer and the organic dielectric layer;

[0010] Prior to the step of etching the organic dielectric layer, the etching method includes:

[0011] The bottom anti-reflective layer is etched until the organic dielectric layer is exposed, forming a patterned bottom anti-reflective layer.

[0012] The step of etching the organic dielectric layer further includes: completely removing the mask layer to expose the patterned bottom anti-reflective layer.

[0013] Optionally, a dielectric anti-reflective layer is provided between the organic dielectric layer and the upper electrode layer;

[0014] The steps after etching the bottom anti-reflection layer and before sequentially etching the upper electrode layer and the resistive switching layer include:

[0015] The organic dielectric layer is etched until the dielectric anti-reflective layer is exposed, forming the patterned organic dielectric layer;

[0016] The dielectric antireflective layer is etched until the upper electrode layer is exposed to form the patterned dielectric antireflective layer, and the patterned bottom antireflective layer is completely removed.

[0017] Optionally, the step of etching the dielectric antireflective layer includes:

[0018] The dielectric antireflective layer with the thickness of the main etched portion;

[0019] The remaining thickness of the dielectric antireflective layer is etched until the upper electrode layer is exposed;

[0020] During the main etching and the over-etching processes, at least a portion of the patterned organic dielectric layer is not etched.

[0021] Optionally, the main material of the bottom anti-reflective layer is silicon dioxide;

[0022] The process parameters in the step of etching the bottom anti-reflective layer include:

[0023] The first process gas comprises trifluoromethane and tetrafluoromethane, wherein the flow rate of trifluoromethane is 0-200 sccm, the flow rate of tetrafluoromethane is 0-200 sccm, and the ratio of trifluoromethane to tetrafluoromethane is 1.5-2.5:1, wherein trifluoromethane can form a polymer on the sidewall of the patterned bottom anti-reflective layer; or, the first process gas comprises difluoromethane and tetrafluoromethane, wherein the flow rate of difluoromethane is 0-200 sccm, the flow rate of tetrafluoromethane is 0-200 sccm, and the ratio of difluoromethane to tetrafluoromethane is 0.8-1.5:1, wherein difluoromethane can form a polymer on the sidewall of the patterned bottom anti-reflective layer;

[0024] The chamber pressure is 3-10 mtoor; the upper electrode power is 500-1000 W; the lower electrode power is 50-200 W; and the chuck temperature is 30-40℃.

[0025] Optionally, the main material of the organic dielectric layer is organic spin-coated carbon;

[0026] The process parameters in the step of etching the organic dielectric layer include:

[0027] The second process gas includes oxygen, hydrogen bromide, and an inert gas. The flow rate of oxygen is 20-200 sccm, the flow rate of hydrogen bromide is 0-100 sccm, and the flow rate of the inert gas is 0-200 sccm. The ratio of oxygen, hydrogen bromide, and inert gas is 1:0.5-1.0:1. Hydrogen bromide can form a polymer on the sidewall of the patterned organic medium layer.

[0028] The chamber pressure is 3-15 mToor; the upper electrode power is 200-800W; the lower electrode power is 50-200W; and the chuck temperature is 30-40℃.

[0029] Optionally, the main material of the dielectric antireflective layer is silicon dioxide;

[0030] The process parameters in the dielectric anti-reflection layer step, where the thickness of the main etched portion is specified, include:

[0031] The third process gas comprises tetrafluoromethane, trifluoromethane, and an inert gas. The flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of trifluoromethane is 20-200 sccm, the flow rate of the inert gas is 50-200 sccm, and the ratio of trifluoromethane to tetrafluoromethane is 0.2-0.5:1. Trifluoromethane can form a polymer on the sidewall of the patterned dielectric antireflective layer. Alternatively, the third process gas comprises tetrafluoromethane, difluoromethane, and an inert gas. The flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of difluoromethane is 20-200 sccm, and the ratio of difluoromethane to tetrafluoromethane is 0.1-0.2:1. Difluoromethane can form a polymer on the sidewall of the patterned dielectric antireflective layer.

[0032] The chamber pressure is 5-20 mToor; the upper electrode power is 300-1000 W; the lower electrode power is 50-150 W; and the chuck temperature is 30-40℃.

[0033] The process parameters in the step of etching the remaining dielectric antireflective layer include:

[0034] The fourth process gas includes tetrafluoromethane and trifluoromethane, with a flow rate of 20-200 sccm for both tetrafluoromethane and trifluoromethane. The trifluoromethane is capable of forming a polymer on the sidewall of the patterned dielectric antireflective layer, and the ratio of trifluoromethane to tetrafluoromethane is 0.8-1.2:1. Alternatively, the fourth process gas includes tetrafluoromethane and difluoromethane, with a flow rate of 20-200 sccm for both tetrafluoromethane and difluoromethane. The ratio of difluoromethane to tetrafluoromethane is 0.5-0.8:1, and the difluoromethane is capable of forming a polymer on the sidewall of the patterned dielectric antireflective layer.

[0035] Optionally, after the step of sequentially etching the upper electrode layer and the resistive switching layer until the lower electrode layer is exposed, the etching method further includes: removing the remaining thickness of the patterned organic dielectric layer until the patterned dielectric antireflective layer is exposed.

[0036] Optionally, the process parameters for the step of removing the remaining thickness of the patterned organic dielectric layer until the patterned dielectric antireflective layer is exposed include:

[0037] Oxygen, wherein the flow rate of the oxygen is between 300-400 sccm;

[0038] The chamber pressure is 10-20 mToor; the upper electrode power is 1000-1500 W; the lower electrode power is 80-100 W; and the chuck temperature is 30-40℃.

[0039] Optionally, the upper electrode layer includes a first upper electrode layer and a second upper electrode layer disposed sequentially from top to bottom;

[0040] The step of sequentially etching the upper electrode layer and the resistive switching layer until the lower electrode layer is exposed includes:

[0041] The first upper electrode layer, the second upper electrode layer, and the resistive switching layer are etched sequentially until the lower electrode layer is exposed, thereby forming a patterned first upper electrode layer, a patterned second upper electrode layer, and a patterned resistive switching layer.

[0042] Optionally, the process parameters in the step of etching the first upper electrode layer include: a fifth process gas, which comprises chlorine, methane, and an inert gas; the flow rate of chlorine is 50-300 sccm, the flow rate of methane is 0-200 sccm, the flow rate of the inert gas is 0-200 sccm, and the ratio of chlorine to methane is 4-8:1; methane can form a polymer on the sidewall of the patterned first upper electrode layer; the chamber pressure is 3-20 mTorr; the upper electrode power is between 600-1000 W; the lower electrode power is between 50-150 W; and the chuck temperature is 30-40°C.

[0043] And / or, the process parameters for the step of etching the second upper electrode layer and the resistive switching layer include: a sixth process gas, which includes chlorine, boron trichloride and an inert gas, with a chlorine flow rate of 50-150 sccm, a boron trichloride flow rate between 100-300 sccm, and an inert gas flow rate between 0-200 sccm. Boron trichloride and the inert gas can enhance the physical bombardment effect; the ratio of boron trichloride to chlorine is 2-4:1; the chamber pressure is 3-20 mTorr; the upper electrode power is 800-1200 W; and the lower electrode power is 50-200 W.

[0044] Taking resistive random access memory (RRAM) as an example, the etching method for semiconductor devices provided by this invention has at least the following beneficial technical effects:

[0045] By placing an organic dielectric layer between the top electrode layer and the mask layer, the organic dielectric layer is preferentially etched to form a patterned organic dielectric layer. Then, using the patterned organic dielectric layer as a mask, the top electrode layer and the resistive switching layer are etched sequentially. During the etching of the top electrode layer and the resistive switching layer, at least a portion of the patterned organic dielectric layer is not etched, thus protecting the thickness of the top electrode layer and avoiding thickness loss, thereby improving the performance and reliability of the resistive switching memory. The absence of at least a portion of the patterned organic dielectric layer allows for anisotropic etching in the vertical direction, protecting the sidewalls of the patterned top electrode layer and the patterned resistive switching layer. This reduces secondary bombardment of the sidewalls by process gases, preventing sidewall depressions and ensuring the perpendicularity of the sidewalls of the patterned top electrode layer and the patterned resistive switching layer.

[0046] The present invention also provides a semiconductor device, comprising a semiconductor device formed by the etching method described above. Attached Figure Description

[0047] Figure 1(a) is a schematic diagram of the structure of a semiconductor device before etching according to an embodiment of the present invention;

[0048] Figure 1(b) is a schematic diagram of the structure of a semiconductor device after the bottom anti-reflection layer has been etched according to an embodiment of the present invention;

[0049] Figure 1(c) is a schematic diagram of the structure of a semiconductor device after etching of the organic dielectric layer according to an embodiment of the present invention;

[0050] Figure 1(d) is a schematic diagram of the structure of a semiconductor device after the main etching of the dielectric anti-reflection layer is completed, according to an embodiment of the present invention.

[0051] Figure 1(e) is a schematic diagram of the structure of a semiconductor device after over-etching of the dielectric anti-reflection layer according to an embodiment of the present invention;

[0052] Figure 1(f) is a schematic diagram of the structure of a semiconductor device after etching of the first upper electrode layer according to an embodiment of the present invention;

[0053] Figure 1(g) is a schematic diagram of the structure of a semiconductor device after etching of the barrier layer and the second upper electrode layer according to an embodiment of the present invention;

[0054] Figure 2 A flowchart of an etching method for a semiconductor device provided in an embodiment of the present invention;

[0055] Figure 3 A flowchart of an etching method for a semiconductor device provided in an embodiment of the present invention. Figure 2 ;

[0056] Figure 4 A flowchart of an etching method for a semiconductor device provided in an embodiment of the present invention. Figure 3 .

[0057] Explanation of reference numerals in the attached figures:

[0058] 1. Mask layer; 2. Bottom anti-reflection layer; 21. Patterned bottom anti-reflection layer; 3. Organic dielectric layer; 31. Patterned organic dielectric layer; 4. Dielectric anti-reflection layer; 41. Patterned dielectric anti-reflection layer; 5. First upper electrode layer; 51. Patterned first upper electrode layer; 6. Second upper electrode layer; 61. Patterned second upper electrode layer; 7. Barrier layer; 71. Patterned barrier layer; 8. Bottom electrode layer; 9. First dielectric layer; 10. Second dielectric layer. Detailed Implementation

[0059] A method for manufacturing a resistive switching memory (RSM) is provided in the related art, comprising the following steps: forming a stacked structure, the stacked structure including a lower electrode layer, a resistive switching layer, and an upper electrode layer disposed sequentially from bottom to top; forming a mask layer having a predetermined pattern on the stacked structure, the mask layer including a hard mask such as a silicon oxide layer; etching the upper electrode layer using a first plasma etching method; the first process gas used in the first plasma etching method including a main etching gas and a protective gas capable of forming byproducts on the pattern sidewalls (i.e., the etched upper electrode sidewalls); etching the resistive switching layer using a second plasma etching method; etching the lower electrode layer using a third plasma etching method; the third process gas used in the third plasma etching method including a main etching gas and a protective gas. During the etching process of this resistive switching memory, the use of strong bombardment gases (such as Cl2 / BCl3 / Ar) may result in insufficient hard mask thickness. The strong bombardment gases may penetrate the inorganic mask layer and directly attack the underlying upper electrode layer, causing damage to the upper electrode layer. This damage can lead to increased contact resistance and uneven current distribution, and may even cause perforation of the upper electrode layer, resulting in short-circuit failure and affecting the performance and reliability of the resistive switching memory.

[0060] This invention proposes an etching method for semiconductor devices that can protect the thickness of the upper electrode layer and avoid upper electrode layer thickness loss, thereby improving the performance and reliability of resistive switching memory. The specific details are as follows. To make the above-mentioned objects, features, and advantages of this invention more apparent and understandable, the following description refers to Figures 1(a)-1(g) and... Figures 2-4 Specific embodiments of the present invention will be described in detail below.

[0061] This invention provides a semiconductor device. Referring to Figure 1, the semiconductor device has a stacked structure, which includes, from bottom to top, a bottom electrode layer (BEL) 8, a resistive layer (RL) 7, a top electrode layer (TEL), an organic dielectric layer (ODL) 3, and a mask layer (ML) 1; the mask layer 1 is a patterned photoresist (PR).

[0062] Taking a resistive random access memory (RRAM) as an example, this invention provides an etching method for semiconductor devices. For instance, an inductively coupled plasma (ICP) etching apparatus can be used to etch the corresponding film layer. The etching apparatus includes a process chamber, a gas inlet device, an upper electrode device, and a lower electrode device. The process parameters involved include process gas, chamber pressure, upper electrode power, lower electrode power, and chuck temperature. See Figures 1(a)-1(g) and the accompanying drawings. Figure 2 The etching method includes the following steps:

[0063] S110, etch the organic dielectric layer 3 until the upper electrode layer is exposed to form a patterned organic dielectric layer 31;

[0064] S130, the upper electrode layer and resistive switching layer 7 are etched sequentially until the lower electrode layer 8 is exposed; wherein, during the etching of the upper electrode layer and resistive switching layer 7, at least a portion of the patterned organic dielectric layer 31 is not etched. With this configuration, an organic dielectric layer 3 is placed between the upper electrode layer and the mask layer 1, serving as an intermediate buffer layer. On the one hand, by adjusting the process gas ratio, the organic dielectric layer 3 is etched preferentially to form a patterned organic dielectric layer 31. Then, using the patterned organic dielectric layer 31 as a mask, the upper electrode layer and resistive switching layer 7 are etched sequentially. During the etching of the upper electrode layer and resistive switching layer 7, the process gas ratio can be adjusted to preferentially etch the upper electrode layer and resistive switching layer 7, while maintaining a lower etching rate for the patterned organic dielectric layer 31, ensuring that at least a portion of the patterned organic dielectric layer 8 is not etched. The substrate layer 31 is not etched, thereby protecting the upper electrode layer and avoiding thickness loss of the upper electrode layer, thus improving the performance and reliability of the resistive switching memory. On the other hand, at least a portion of the patterned organic dielectric layer 31 is not etched. During the etching process, anisotropic etching in the vertical direction can be achieved, which can protect the sidewalls of the patterned upper electrode layer and the patterned resistive switching layer 71, reduce the secondary bombardment of the sidewalls of the patterned upper electrode layer and the patterned resistive switching layer 71 by the process gas, avoid the sidewalls of the patterned upper electrode layer and the patterned resistive switching layer from being recessed, and ensure the perpendicularity of the etched sidewalls.

[0065] Referring to Figure 1, in this embodiment of the invention, a bottom anti-reflection layer 2 is provided between the mask layer 1 and the organic dielectric layer 3;

[0066] See Figures 1(a)-1(g) and Appendix Figure 2 Before the step of etching the organic dielectric layer 3 until the upper electrode layer is exposed, the etching method includes: S100, etching the bottom anti-reflection layer 2 until the organic dielectric layer 3 is exposed to form a patterned bottom anti-reflection layer 21;

[0067] S110, the step of etching the organic dielectric layer 3 further includes: completely removing the mask layer 1 to expose the patterned bottom anti-reflection layer 21. In this step, using the patterned bottom anti-reflection layer 21 as a mask, the organic dielectric layer 3 is etched until the upper electrode layer is exposed, forming the patterned organic dielectric layer 31. With this configuration, a bottom anti-reflection layer 2 is provided between the mask layer 1 and the organic dielectric layer 3. On the one hand, the bottom anti-reflection layer 2 can make the exposure of the patterned photoresist more uniform, reducing the thickness variation and pattern deformation of the photoresist caused by reflection, thereby improving the performance and reliability of the photoresist. On the other hand, the bottom anti-reflection layer 2 can absorb or reduce reflected light, allowing the incident light to be better focused on the patterned photoresist, further improving the edge sharpness of the pattern after photoresist development, and providing a more accurate mask basis for subsequent etching.

[0068] Referring to Figure 1(a), in this embodiment of the invention, a dielectric anti-reflective coating (DARC) 4 is provided between the organic dielectric layer 3 and the upper electrode layer;

[0069] See Figures 1(a)-1(g) and Appendix Figure 3 The steps after etching the bottom anti-reflection layer 2 in S100 and before etching the top electrode layer and resistive switching layer 7 in S130 include:

[0070] S110', Etch the organic dielectric layer 3 until the dielectric anti-reflection layer 4 is exposed to form a patterned organic dielectric layer 31; In this step, the patterned bottom anti-reflection layer 21 is used as a mask to etch the organic dielectric layer 3 until the dielectric anti-reflection layer 4 is exposed to form a patterned organic dielectric layer 31.

[0071] S120, etch the dielectric anti-reflection layer 4 until the upper electrode layer is exposed, forming a patterned dielectric anti-reflection layer 41, and completely remove the patterned bottom anti-reflection layer 21 to expose the patterned organic dielectric layer 31. This arrangement, with the dielectric anti-reflection layer 4 positioned between the organic dielectric layer 3 and the upper electrode layer, effectively absorbs multiple reflections of incident light between the multilayer interfaces, improving the transfer accuracy of the pattern.

[0072] See Figures 1(d)-1(e) and Appendix Figure 4 In this embodiment of the invention, step S120, etching the anti-reflection layer 4, includes:

[0073] S121, the dielectric anti-reflective layer 4 of the main etching portion thickness is formed into a patterned dielectric anti-reflective layer 41 of a portion thickness, and the patterned bottom anti-reflective layer 21 is completely removed to expose the patterned organic dielectric layer 31.

[0074] S122, the remaining thickness of the dielectric anti-reflection layer 4 is etched until the upper electrode layer is exposed, forming a patterned dielectric anti-reflection layer 41 with remaining thickness.

[0075] During the main etching and over-etching processes, at least a portion of the patterned organic dielectric layer 31 is left unetched. This configuration allows the main etching to rapidly penetrate the dielectric anti-reflective layer 4 vertically; the over-etching reduces the etching rate and increases the selectivity between the dielectric anti-reflective layer 4 and the organic dielectric layer 3, prioritizing the etching of the dielectric anti-reflective layer 4 while maintaining a lower etching rate for the patterned organic dielectric layer 31. This ensures that at least a portion of the patterned organic dielectric layer 31 remains unetched, precisely stopping at the upper electrode layer and preventing the formation of pits or residues on the upper electrode layer.

[0076] Referring to Figure 1(a), in this embodiment of the invention, the main material of the bottom anti-reflective coating (BRAC) 2 is silicon dioxide (SiO2).

[0077] S120, the process parameters in the step of etching the bottom anti-reflection layer 2 include:

[0078] The first process gas is a fluorine-based gas, suitable for etching silicon dioxide; the type of the first process gas is not limited, and the specific details are as follows:

[0079] For example, the first process gas includes tetrafluoromethane (CF4) and trifluoromethane (CHF3). Tetrafluoromethane, as the main etching gas, decomposes in a plasma environment to generate highly reactive substances such as fluorine radicals, which react with silicon dioxide to generate volatile products such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), thereby achieving directional etching of silicon dioxide. Trifluoromethane, as a protective gas, can form polymers on the sidewalls of the patterned bottom antireflective layer 21. Specifically, it decomposes in a plasma environment to generate carbon-containing radicals (such as CF2). During the etching process, the carbon-containing radicals are deposited on the sidewalls of silicon dioxide to form a fluorocarbon polymer film. Since fluorocarbon polymers have high chemical stability and their chemical strength is higher than that of the etching product silicon tetrafluoride, the deposition of fluorocarbon polymers on the sidewalls of silicon dioxide can reduce lateral etching, thereby protecting the sidewalls of the patterned bottom antireflective layer 21 and forcing the etching to proceed mainly in the vertical direction. That is, while achieving anisotropy in etching, it avoids the problem of sidewall depression. The flow rate of tetrafluoromethane is 0-200 sccm, the flow rate of trifluoromethane is 0-200 sccm, and the ratio of trifluoromethane to tetrafluoromethane is 1.5-2.5:1. By adjusting the flow rate and ratio of tetrafluoromethane and trifluoromethane, a balance between etching rate and sidewall protection can be achieved.

[0080] For example, the first process gas includes tetrafluoromethane (CF4) and difluoromethane (CH2F2). Tetrafluoromethane, as the main etching gas, decomposes in the plasma environment to generate highly reactive substances such as fluorine radicals, which react with silicon dioxide to generate volatile products such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), thereby achieving directional etching of silicon dioxide. Difluoromethane, as a protective gas, can form polymers on the sidewalls of the patterned bottom anti-reflective layer 21. Specifically, it decomposes in the plasma environment to generate carbon-containing radicals (such as CF2). During the etching process, the carbon-containing radicals are deposited on the sidewalls of silicon dioxide to form a fluorocarbon polymer film. Since fluorocarbon polymers have high chemical stability and their chemical strength is higher than that of the etching product silicon tetrafluoride, the deposition of fluorocarbon polymers on the sidewalls of silicon dioxide can reduce lateral etching, thereby protecting the sidewalls of the patterned bottom anti-reflective layer 21 and forcing the etching to proceed mainly in the vertical direction. That is, while achieving anisotropy in etching, it avoids the problem of sidewall depression. The flow rate of difluoromethane is 0-200 sccm, the flow rate of tetrafluoromethane is 0-200 sccm, and the ratio of difluoromethane to tetrafluoromethane is 0.8-1.5:1. By adjusting the flow rate and ratio of tetrafluoromethane and difluoromethane, a balance between etching rate and sidewall protection can be achieved.

[0081] In this step, the process parameters also include: chamber pressure of 3-10 mtoor; upper electrode power of 500-1000 W; lower electrode power of 50-200 W; and chuck temperature of 30-40℃. This configuration, by limiting the chamber pressure within a certain range, achieves uniform plasma distribution, thereby ensuring the uniformity of the etching of the bottom anti-reflection layer 2; by limiting the upper electrode power within a certain range, the plasma density can be increased; by limiting the lower electrode power within a certain range, the ion bombardment energy can be adjusted, thereby controlling the etching directionality and reducing damage; and by limiting the chuck temperature within a certain range, excessively high temperatures can prevent structural deformation of the resistive switching memory, or excessively low temperatures can lead to condensation and contamination of the resistive switching memory.

[0082] In this embodiment of the invention, the main material of the organic dielectric layer 3 is organic spin-on carbon (SOC).

[0083] S110, the process parameters in the step of etching the organic dielectric layer 3 include:

[0084] The second process gas includes oxygen (O2), hydrogen bromide (HBr), and an inert gas. Hydrogen bromide can form a polymer on the sidewalls of the patterned organic dielectric layer 31. Oxygen, as the primary etching gas, generates plasma that reacts with the organic spin-coated carbon, producing carbon dioxide and other byproducts which are then removed. Hydrogen bromide, as the gas for hardening the organic spin-coated carbon, reacts with the hydroxyl groups in the organic spin-coated carbon of the organic dielectric layer 3 during etching, generating bromides and water, thus etching the organic dielectric layer 3 and forming the patterned organic dielectric layer 31. Simultaneously, it reacts with the silicon dioxide of the patterned bottom anti-reflective layer 21 to form volatile silicon tetrabromide (SiBr4), forming a protective layer on the sidewalls of the patterned organic dielectric layer 31 to reduce lateral etching. The inert gas can be nitrogen, argon, or helium, used as a dilution gas to slow down the etching rate and prevent over-etching due to excessive reaction. The flow rate of oxygen is 20-200 sccm, the flow rate of hydrogen bromide is 0-100 sccm, and the flow rate of inert gas is 0-200 sccm. The ratio of oxygen, hydrogen bromide and inert gas is 1:0.5-1.0:1. By adjusting the flow rate and ratio of oxygen, hydrogen bromide and inert gas, a balance between etching rate and sidewall protection can be achieved.

[0085] In this step, the process parameters also include: chamber pressure of 3-15 mToor; upper electrode power of 200-800 W; lower electrode power of 50-200 W; and chuck temperature of 30-40°C. This configuration, by limiting the chamber pressure within a certain range, achieves uniform plasma distribution, thereby ensuring the uniformity of etching the organic dielectric layer 3; by limiting the upper electrode power within a certain range, the plasma density can be increased; by limiting the lower electrode power within a certain range, the ion bombardment energy can be adjusted, thereby controlling the etching directionality and reducing semiconductor damage; and by limiting the chuck temperature within a certain range, excessively high temperatures can prevent structural deformation of the resistive switching memory, or excessively low temperatures can lead to condensation and contamination of the resistive switching memory.

[0086] In this embodiment of the invention, the main material of the dielectric antireflective layer 4 is silicon carbide (SiOC).

[0087] The process parameters in step S121, the thickness of the dielectric anti-reflection layer 4 in the main etching portion, include:

[0088] The third process gases include fluorine-based gases and inert gases, among which the types of fluorine-based gases are not limited, as detailed below:

[0089] For example, the third process gas includes tetrafluoromethane (CF4), trifluoromethane (CHF3), and an inert gas. Tetrafluoromethane is used as the main etching gas, and the plasma generated reacts with silicon carbide to form volatile gases, such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), which are then removed. Trifluoromethane is used as a protective gas to form polymers on the sidewalls of the patterned dielectric antireflective layer 41, thereby protecting the sidewalls of the patterned dielectric antireflective layer 41. The inert gas can be nitrogen, argon, or helium, which mainly serves as a dilution gas and assists in ignition. The flow rates of tetrafluoromethane and trifluoromethane are 20-200 sccm, and the flow rates of inert gas are 50-200 sccm. The ratio of trifluoromethane to tetrafluoromethane is 0.2-0.5:1. With this configuration, the proportion of tetrafluoromethane is higher than that of trifluoromethane during the main etching stage, thereby providing a higher concentration of fluorine free radicals. The fluorine free radicals react with silicon carbide to achieve rapid etching. Trifluoromethane provides a small amount of carbon source to generate polymers that are deposited on the sidewalls of the patterned dielectric antireflective layer 41.

[0090] For example, the third process gas includes tetrafluoromethane (CF4), difluoromethane (CH2F2), and an inert gas. Tetrafluoromethane is used as the main etching gas, and the plasma generated reacts with silicon carbide to form volatile gases, such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), which are then removed. Difluoromethane is used as a protective gas, which can form polymers on the sidewalls of the patterned dielectric antireflective layer 41 of a certain thickness, thereby protecting the sidewalls of the patterned dielectric antireflective layer 41. The inert gas can be nitrogen, argon, or helium, which mainly serves as a dilution gas and an auxiliary ignition gas. The flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of difluoromethane is 20-200 sccm, and the ratio of difluoromethane to tetrafluoromethane is 0.1-0.2:1. With this setting, the proportion of tetrafluoromethane is higher than that of difluoromethane in the main etching stage, thereby providing a higher concentration of fluorine radicals. The fluorine radicals react with silicon carbide to achieve rapid etching. Difluoromethane provides a small amount of carbon source to generate polymers that are deposited on the sidewalls of the patterned dielectric antireflective layer 41.

[0091] In this step, the process parameters also include: chamber pressure of 5-20 mToor; upper electrode power of 300-1000 W; lower electrode power of 50-150 W; and chuck temperature of 30-40 °C. This setting, by limiting the chamber pressure within a certain range, achieves uniform plasma distribution, thereby ensuring the uniformity of the anti-reflection layer 4 of the etching medium; by limiting the upper electrode power within a certain range, the plasma density can be increased; by limiting the lower electrode power within a certain range, the ion bombardment energy can be adjusted, thereby controlling the etching directionality and reducing semiconductor damage; and by limiting the chuck temperature within a certain range, excessively high temperatures can prevent structural deformation of the resistive switching memory, or excessively low temperatures can lead to condensation and contamination of the resistive switching memory.

[0092] S122, the process parameters in the step of etching the remaining dielectric anti-reflection layer 4 include:

[0093] The fourth type of process gas includes fluorine-based gases, where the type of fluorine-based gas is not limited, as detailed below:

[0094] For example, the fourth process gas includes tetrafluoromethane (CF4) and trifluoromethane (CHF3). Tetrafluoromethane serves as the primary etching gas; the generated plasma reacts with silicon carbide to form volatile gases such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), which are then removed. Trifluoromethane, as a protective gas, forms polymers on the sidewalls of the patterned dielectric anti-reflective layer 41, thus protecting the sidewalls of the patterned dielectric anti-reflective layer 41. The flow rates of both tetrafluoromethane and trifluoromethane are 20-200 sccm, and the ratio of trifluoromethane to tetrafluoromethane is 0.8-1.2:1. With this setup, compared to the main etching process, the increased proportion of trifluoromethane in the over-etching process increases the carbon source and promotes polymer deposition; the decreased proportion of tetrafluoromethane reduces the concentration of fluorine free radicals, lowers the etching rate, and precisely stops at the upper electrode layer, avoiding the formation of pits or residues on the upper electrode layer.

[0095] For example, the fourth process gas includes tetrafluoromethane (CF4) and difluoromethane (CH2F2). Tetrafluoromethane serves as the primary etching gas; the generated plasma reacts with silicon carbide to form volatile gases such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), which are then removed. Difluoromethane, as a protective gas, forms polymers on the sidewalls of the patterned dielectric anti-reflective layer 41 of a certain thickness, thus protecting the sidewalls of the patterned dielectric anti-reflective layer 41. The flow rates of both tetrafluoromethane and difluoromethane are 20-200 sccm, and the ratio of difluoromethane to tetrafluoromethane is 0.5-0.8:1. Difluoromethane is able to form polymers on the sidewalls of the patterned dielectric anti-reflective layer 41. With this setup, compared to the main etching process, the increased proportion of difluoromethane in the over-etching process increases the carbon source and promotes polymer deposition; the decreased proportion of tetrafluoromethane reduces the concentration of fluorine free radicals, lowers the etching rate, and precisely stops at the upper electrode layer, avoiding the formation of pits or residues on the upper electrode layer.

[0096] See attached figure (g) and appendix. Figure 3 In this embodiment of the invention, after the step of sequentially etching the upper electrode layer and the resistive switching layer 7, the etching method further includes: S140, removing the remaining thickness of the patterned organic dielectric layer 31 until the patterned dielectric antireflective layer 41 is exposed.

[0097] In this embodiment of the invention, the process parameters in step S140, the step of removing the remaining thickness of the patterned organic dielectric layer 31, include: oxygen, which is used as the main etching gas; the generated plasma reacts with the organic spin-coated carbon of the patterned organic dielectric layer 31 to form volatile gases such as carbon dioxide, which are then removed; and the etching selectivity ratio for the patterned dielectric anti-reflective layer 41, the patterned upper electrode layer, and the patterned resistive switching layer 71 is greater than 10:1, thereby ensuring that only the patterned organic dielectric layer 31 is removed, without damaging the patterned dielectric anti-reflective layer 41, the patterned upper electrode layer, and the patterned resistive switching layer 71. The oxygen flow rate is between 300-400 sccm.

[0098] This step also includes process parameters: chamber pressure of 10-20 mToor; upper electrode power of 1000-1500 W; lower electrode power of 80-100 W; and chuck temperature of 30-40℃.

[0099] Referring to Figure 1(a), in this embodiment of the invention, the upper electrode layer includes a first upper electrode layer 5 and a second upper electrode layer 6 arranged sequentially from top to bottom;

[0100] S130, the step of sequentially etching the upper electrode layer and the resistive switching layer 7 includes: sequentially etching the first upper electrode layer 5, the second upper electrode layer 6, and the resistive switching layer 7 until the lower electrode layer 8 is exposed, thereby sequentially forming a patterned first upper electrode layer 51, a patterned second upper electrode layer 61, and a patterned resistive switching layer 71. That is, refer to Figures 1(e)-1(g) and the attached figures. Figure 3 S130, the step of sequentially etching the upper electrode layer and the resistive switching layer 7 includes: S131, etching the first upper electrode layer 5 until the second upper electrode layer 6 is exposed to form a patterned first upper electrode layer 51; S132, etching the second upper electrode layer 6 and the resistive switching layer 7 until the lower electrode layer 9 is exposed, the patterned second upper electrode layer 61 and the patterned resistive switching layer 71.

[0101] In this embodiment of the invention, the main material of the first upper electrode layer 5 is one or a combination of titanium nitride (TiN), aluminum (Al), and tungsten (W). For example, the main material of the first upper electrode layer 5 is titanium nitride, S131. The process parameters in the etching step of the first upper electrode layer 5 include: a fifth process gas, which includes chlorine (Cl2), methane (CH4), and an inert gas. Chlorine is used as the main etching gas. The generated plasma reacts with titanium nitride to generate volatile titanium tetrachloride, and nitrogen is extracted to etch the first upper electrode layer 5, forming a patterned first upper electrode layer 51. Methane is used as a protective gas. Methane can form polymers on the sidewalls of the patterned first upper electrode layer 51. Specifically, methane is cracked in the plasma to generate carbon-containing polymers, which adhere to the sidewalls of the patterned first upper electrode layer 5, protecting the sidewalls from lateral etching and preventing the sidewalls from inward depression. The inert gas can be nitrogen, argon, or helium, mainly serving as a dilution gas and assisting in ignition. The flow rates of chlorine and methane are 50-300 sccm, 0-200 sccm, and 0-200 sccm, respectively, with a chlorine-to-methane ratio of 4-8:1. This configuration, by limiting the chlorine-to-methane ratio, ensures that chlorine provides a certain concentration of chlorine radicals, dominating the etching rate; that methane, under plasma action, generates carbon-based polymers to passivate the sidewalls; that limiting the chlorine flow rate prevents excessive chlorine flow from exacerbating the roughness of the sidewalls of the first upper electrode layer 5; that limiting the methane flow rate prevents excessive methane flow from causing residue buildup at the top; and that limiting the inert gas flow rate assists in plasma ignition and dilutes the concentration of the reactive gases.

[0102] In this step, the process parameters also include: chamber pressure of 3-20 mTorr; upper electrode power of 600-1000 W; lower electrode power of 50-150 W; and chuck temperature of 30-40°C. This configuration, by limiting the chamber pressure within a certain range, achieves uniform plasma distribution, thereby ensuring the uniformity of etching the first upper electrode layer 5; by limiting the upper electrode power within a certain range, the plasma density can be increased; by limiting the lower electrode power within a certain range, the ion bombardment energy can be adjusted, thereby controlling the etching directionality and reducing semiconductor damage; and by limiting the chuck temperature within a certain range, excessively high temperatures can prevent structural deformation of the resistive switching memory, or excessively low temperatures can lead to condensation and contamination of the resistive switching memory.

[0103] In this embodiment of the invention, the main material of the second upper electrode layer 6 is one or a combination of several of tantalum (Ta), titanium (Ti), aluminum (Al) and tungsten (W); the main material of the resistive switching layer 7 is a metal oxide with resistive switching properties, wherein the metal oxide is hafnium dioxide (HfO2), nickel oxide (NiO), zirconium dioxide (ZrO2), titanium oxide (TiO2), or aluminum oxide (Al2O3).

[0104] Taking tantalum as the material of the second upper electrode layer 6 and hafnium dioxide as the material of the resistive switching layer 7 as an example; S312, the process parameters in the step of etching the second upper electrode layer 6 and the resistive switching layer 7 include:

[0105] The sixth process gas includes chlorine (Cl2), boron trichloride (BCl3), and an inert gas. Chlorine is the main etching gas, and the plasma generated first reacts with the tantalum in the second upper electrode layer 6 to generate volatile tantalum tetrachloride, which is then removed. Boron trichloride is used as an auxiliary etching gas, which has stronger bombardment properties. After etching the second upper electrode layer 6 and forming the patterned second upper electrode layer 61, a combination of chlorine, boron chloride, and inert gas is used for etching. Boron trichloride and inert gas can enhance the physical bombardment effect and ensure the opening of the hafnium dioxide film. Simultaneously, during the etching process, the presence of the patterned organic dielectric layer 31 forms a non-volatile adhering substance that adheres to the sidewalls of the patterned second upper electrode layer 61 and the patterned resistive switching layer 71, preventing lateral etching of the second upper electrode layer 6 and the resistive switching layer 7 from causing depressions. Furthermore, the presence of the patterned organic dielectric layer 31 provides some protection for the patterned dielectric anti-reflective layer 41 during heavy bombardment, preventing excessive consumption of the patterned dielectric anti-reflective layer 41 during etching. The inert gas can be nitrogen, argon, or helium, primarily serving as a dilution gas and assisting in ignition. The chlorine flow rate is 50-150 sccm, the boron trichloride flow rate is between 100-300 sccm, the inert gas flow rate is between 0-200 sccm, and the ratio of boron trichloride to chlorine is 2-4:1. With this setup, chlorine gas mainly reacts chemically with the second electrode layer 6 to form a patterned second electrode layer 61; boron trichloride has a stronger bombardment capability, which can enhance the etching capability of the resistive switching layer and increase the etching rate of the resistive switching layer.

[0106] In this step, the process parameters also include: chamber pressure of 3-20 mTorr; upper electrode power of 800-1200 W; lower electrode power of 50-200 W; and chuck temperature of 30-40℃. This configuration, by limiting the chamber pressure within a certain range, achieves uniform plasma distribution, thereby ensuring the uniformity of etching the second upper electrode layer 6 and the resistive switching layer 7; by limiting the upper electrode power within a certain range, the plasma density can be increased; by limiting the lower electrode power within a certain range, the ion bombardment energy can be adjusted, thereby controlling the etching directionality and reducing semiconductor damage; and by limiting the chuck temperature within a certain range, excessively high temperatures can prevent structural deformation of the resistive switching memory, or excessively low temperatures can lead to condensation and contamination of the resistive switching memory.

[0107] This invention also provides a semiconductor device, including a semiconductor device formed by the etching method described above.

[0108] Referring to Figure 1(a), in this embodiment of the invention, the semiconductor device has a stacked structure, which includes, from bottom to top, a bottom electrode layer (BEL) 8, a resistive layer (RL) 7, a top electrode layer (TEL), a dielectric anti-reflective coating (DARC) 4, an organic dielectric layer (ODL) 3, a bottom anti-reflective coating (BRAC) 2, and a mask layer (ML) 1; wherein, the mask layer 1 is a patterned photoresist (PR).

[0109] Referring to Figure 1(a), in this embodiment of the invention, the stacked structure further includes a first dielectric layer 9 and a second dielectric layer 10. The first dielectric layer 9 is located below the resistive switching layer 7, the lower electrode layer 8 is located below the first dielectric layer 9, and the mask layer 1 is positioned opposite to the lower electrode layer 8; the second dielectric layer 10 is located below the first dielectric layer 9.

[0110] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An etching method for a semiconductor device, characterized in that, The semiconductor device has a stacked structure, which includes a lower electrode layer (8), a resistive switching layer (7), an upper electrode layer, an organic dielectric layer (3), and a mask layer (1) arranged sequentially from bottom to top; a bottom anti-reflection layer (2) is provided between the mask layer (1) and the organic dielectric layer (3); and a dielectric anti-reflection layer (4) is provided between the organic dielectric layer (3) and the upper electrode layer. The etching method includes the following steps: The bottom anti-reflective layer (2) is etched until the organic dielectric layer (3) is exposed, forming a patterned bottom anti-reflective layer (21); the main material of the bottom anti-reflective layer (2) is silicon dioxide; the process parameters in the step of etching the bottom anti-reflective layer (2) include: a first process gas, the first process gas including trifluoromethane and tetrafluoromethane, the flow rate of trifluoromethane being 0-200 sccm, the flow rate of tetrafluoromethane being 0-200 sccm, the ratio of trifluoromethane to tetrafluoromethane being 1.5-2.5:1, and the trifluoromethane being able to form a patterned bottom anti-reflective layer (21). A polymer is formed on the sidewall of the patterned bottom antireflective layer (21); or, the first process gas includes difluoromethane and tetrafluoromethane, the difluoromethane flow rate is 0-200 sccm, the tetrafluoromethane flow rate is 0-200 sccm, the ratio of difluoromethane to tetrafluoromethane is 0.8-1.5:1, and the difluoromethane is capable of forming a polymer on the sidewall of the patterned bottom antireflective layer (21); the chamber pressure is 3-10 mtoor; the upper electrode power is 500-1000 W; the lower electrode power is 50-200 W; the chuck temperature is 30-40 °C; The organic dielectric layer (3) is etched until the upper electrode layer is exposed, forming a patterned organic dielectric layer (31); wherein, the main material of the organic dielectric layer (3) is organic spin-coated carbon; the process parameters in the step of etching the organic dielectric layer (3) include: a second process gas, the second process gas including oxygen, hydrogen bromide and inert gas, the oxygen flow rate being 20-200 sccm, the hydrogen bromide flow rate being 0-100 sccm, the inert gas flow rate being 0-200 sccm, the ratio of oxygen, hydrogen bromide and inert gas being 1:0.5-1.0:1, and hydrogen bromide being able to form a polymer on the sidewall of the patterned organic dielectric layer (31); the chamber pressure being 3-15 mToor; the upper electrode power being 200-800 W; the lower electrode power being 50-200 W; and the chuck temperature being 30-40 °C; The upper electrode layer and the resistive switching layer (7) are etched sequentially until the lower electrode layer (8) is exposed; wherein, during the etching of the upper electrode layer and the resistive switching layer (7), at least a portion of the patterned organic dielectric layer (31) is not etched; Remove the remaining thickness of the patterned organic dielectric layer (31) until the patterned dielectric antireflective layer (41) is exposed; wherein the process parameters in the step of removing the remaining thickness of the patterned organic dielectric layer (31) include: oxygen, the oxygen flow rate being between 300-400 sccm; chamber pressure being 10-20 mToor; upper electrode power being 1000-1500 W; lower electrode power being 80-100 W; and chuck temperature being 30-40 °C.

2. The etching method for a semiconductor device according to claim 1, characterized in that, The step of etching the organic dielectric layer (3) further includes: completely removing the mask layer (1) to expose the patterned bottom anti-reflective layer (21).

3. The etching method for a semiconductor device according to claim 2, characterized in that, The steps following the etching of the bottom anti-reflection layer (2) and before the sequential etching of the upper electrode layer and the resistive switching layer (7) include: The organic dielectric layer (3) is etched until the dielectric anti-reflection layer (4) is exposed, forming the patterned organic dielectric layer (31). The dielectric antireflective layer (4) is etched until the upper electrode layer is exposed to form the patterned dielectric antireflective layer (41), and the patterned bottom antireflective layer (21) is completely removed to expose the patterned organic dielectric layer (31).

4. The etching method for a semiconductor device according to claim 3, characterized in that, The step of etching the dielectric antireflective layer (4) includes: The dielectric anti-reflective layer (4) of the main etched portion thickness; The remaining thickness of the dielectric antireflective layer (4) is etched until the upper electrode layer is exposed; During the main etching and the over-etching processes, at least a portion of the patterned organic dielectric layer (31) is not etched.

5. The etching method for a semiconductor device according to claim 4, characterized in that, The main material of the dielectric antireflective layer (4) is silicon dioxide; The process parameters in the step of the dielectric anti-reflection layer (4) with the thickness of the main etched portion include: The third process gas includes tetrafluoromethane, trifluoromethane, and an inert gas. The flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of trifluoromethane is 20-200 sccm, the flow rate of the inert gas is 50-200 sccm, and the ratio of trifluoromethane to tetrafluoromethane is 0.2-0.5:

1. Trifluoromethane can form a polymer on the sidewall of the patterned dielectric antireflective layer (41). Alternatively, the third process gas includes tetrafluoromethane, difluoromethane, and an inert gas. The flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of difluoromethane is 20-200 sccm, and the ratio of difluoromethane to tetrafluoromethane is 0.1-0.2:

1. Difluoromethane can form a polymer on the sidewall of the patterned dielectric antireflective layer (41). The chamber pressure is 5-20 mToor; the upper electrode power is 300-1000 W; the lower electrode power is 50-150 W; and the chuck temperature is 30-40℃. The process parameters in the step of etching the remaining dielectric antireflective layer (4) include: The fourth process gas includes tetrafluoromethane and trifluoromethane, with a flow rate of 20-200 sccm for both tetrafluoromethane and trifluoromethane. The trifluoromethane is capable of forming a polymer on the sidewall of the patterned dielectric antireflective layer (41), and the ratio of trifluoromethane to tetrafluoromethane is 0.8-1.2:

1. Alternatively, the fourth process gas includes tetrafluoromethane and difluoromethane, with a flow rate of 20-200 sccm for both tetrafluoromethane and difluoromethane. The ratio of difluoromethane to tetrafluoromethane is 0.5-0.8:1, and the difluoromethane is capable of forming a polymer on the sidewall of the patterned dielectric antireflective layer (41).

6. The etching method for a semiconductor device according to any one of claims 1-4, characterized in that, The upper electrode layer includes a first upper electrode layer (5) and a second upper electrode layer (6) arranged sequentially from top to bottom. The step of sequentially etching the upper electrode layer and the resistive switching layer (7) includes: The first upper electrode layer (5), the second upper electrode layer (6) and the resistive switching layer (7) are etched sequentially until the lower electrode layer (8) is exposed, thereby forming a patterned first upper electrode layer (51), a patterned second upper electrode layer (61) and a patterned resistive switching layer (71).

7. The etching method for a semiconductor device according to claim 6, characterized in that, The process parameters in the step of etching the first upper electrode layer (5) include: a fifth process gas, which includes chlorine, methane and an inert gas, with a chlorine flow rate of 50-300 sccm, a methane flow rate of 0-200 sccm, and an inert gas flow rate of 0-200 sccm, and a chlorine to methane ratio of 4-8:1; methane can form a polymer on the sidewall of the patterned first upper electrode layer (51); the chamber pressure is 3-20 mTorr; the upper electrode power is between 600-1000 W; the lower electrode power is between 50-150 W; and the chuck temperature is 30-40°C. And / or, the process parameters in the step of etching the second upper electrode layer (6) and the resistive switching layer (7) include: a sixth process gas, which includes chlorine, boron trichloride and an inert gas, with a chlorine flow rate of 50-150 sccm, a boron trichloride flow rate between 100-300 sccm, and an inert gas flow rate between 0-200 sccm, wherein boron trichloride and the inert gas can enhance the physical bombardment effect; the ratio of boron trichloride to chlorine is 2-4:1; the chamber pressure is 3-20 mTorr; the upper electrode power is 800-1200 W; and the lower electrode power is 50-200 W.

8. A semiconductor device, characterized in that, Semiconductor devices formed by the etching method according to any one of claims 1-7.

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