Method for manufacturing semiconductor structure

Abstract

The invention relates to a method for manufacturing a semiconductor structure. The method includes providing a first structure. The first structure includes a first substrate. The method includes providing a second structure. The second structure includes a second substrate and a first device metal layer on and in contact with the second substrate. The second substrate includes a single crystal semiconductor material and an implanted hydrogen layer. The method includes bonding a first structure and a second structure through a bonding layer to form a bonded structure. The method includes removing a portion of the second substrate from the substantially implanted hydrogen layer to form a first semiconductor layer. The method includes patterning a first semiconductor layer. The method includes forming at least one of a second device metal layer and a second conductive metal layer.

Description

Background of the Invention

[0002] Related applications

[0003] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 387,972, filed on December 19, 2022, entitled “Structures of Vertical Diodes and Memory Cells and Manufacturing Processes Thereof,” which is incorporated herein by reference in its entirety. Technical Field

[0004] The present disclosure relates to methods for fabricating semiconductor structures. In particular, some embodiments of the present disclosure relate to methods for fabricating semiconductor structures including vertical Schottky diodes or vertical PN diodes. Background Art

[0005] Due to the continued development of portable devices, the demand for non-volatile memory is increasing. As device size decreases, non-volatile memory with higher efficiency, faster memory access and low power consumption has become a hot topic to meet market demand. However, there are several technical problems that need to be overcome to provide the desired characteristics. First, in conventional non-volatile memory devices, transistors are used as selectors. When the size of transistors decreases and the integration density increases, the space between these devices also decreases. The space between devices is critical to the performance of the device, and when the space is too small, these devices may interfere with each other. Second, transistors have a saturation region, and the current they can provide is limited by their inherent characteristics. When non-volatile memory devices have high current density requirements, such as magnetoresistive random access memory (MRAM) devices, the size of the transistor that can provide the required current density will be significantly larger. Third, there may be current leakage in the channel region of the transistor formed in the semiconductor substrate, which may reduce efficiency and lead to high power consumption.

[0006] When using transistors as selectors for nonvolatile memory devices, trade-offs must be made to balance feature size and spacing between devices, and the performance of each device may need to be optimized. When more devices are packed onto a chip, parasitic capacitance and power consumption can increase due to reduced spacing between devices and current leakage. Improvements in structure and process technology are still needed to achieve higher efficiency, faster memory access, and lower power consumption for memory devices. Summary of the Invention

[0007] According to the present disclosure, a method for manufacturing a semiconductor structure is provided. The method includes providing a first structure. The first structure includes a first substrate. The method includes providing a second structure. The second structure includes a second substrate and a first device metal layer on and in contact with the second substrate. The second substrate includes a single crystalline semiconductor material and an implanted hydrogen layer. The method includes bonding the first structure and the second structure via a bonding layer to form a bonded structure. The method includes removing a portion of the second substrate substantially at the implanted hydrogen layer to form the first semiconductor layer. The method includes patterning the first semiconductor layer. The method includes forming at least one of the second device metal layer and a second conductive metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1H is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0009] Figures 2A to 2E is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0010] Figure 3 is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0011] Figures 4A to 4F is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0012] Figures 5A to 5C is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0013] Figures 6A to 6G is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0014] Figure 7 is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0015] Figures 8A to 8D is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0016] Figures 9A to 9C is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0017] Figure 10 is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0018] Figures 11A to 11Eis a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0019] 12A to 12C is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0020] Figures 13A to 13G is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0021] Figure 14 is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. DETAILED DESCRIPTION

[0022] The terms used in the description presented below are intended to be interpreted in their broadest reasonable manner, even when used in conjunction with the detailed description of certain specific embodiments of the technology. Certain terms may even be emphasized below; however, any term intended to be interpreted in any restricted manner will be specifically defined as such in this detailed description. Components and implementations of semiconductor structures or memory devices according to the present disclosure can be illustrated in the following figures and embodiments. However, the size and shape of the semiconductor structures or memory devices shown in the figures do not limit the features of the present disclosure.

[0023] As used in this application, the phrase "on..." may mean directly "on..." or indirectly "on..." through an intermediate element or layer. For ease of description, spatially relative terms such as "below...", "below...", "below...", "above...", "on...", etc. may be used herein to describe the relationship of an element or feature to one or more other elements or features as illustrated in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of the device when in use or operation. For example, if the device in the figure is flipped, an element described as being "below" or "below" other elements or features will be oriented as being "above" the other elements or features. Thus, the exemplary term "below..." may include both the orientations of "above..." and "below...". The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0024] Figures 1A to 1H is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0025] like Figure 1AAs shown, a second substrate 40 is provided (step (b1)). The second substrate 40 may include a single crystal semiconductor material, including but not limited to silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In some embodiments, the second substrate 40 is of the first conductivity type. For example, the second substrate 40 may be doped with an n-type dopant, such as phosphorus, arsenic, antimony, bismuth, etc., or a combination thereof. In some embodiments, the doping concentration of the second substrate 40 may be approximately 1.0×10 14 atoms / cm 3 to about 5.0×10 17 atoms / cm 3 These values ​​are merely examples and are not intended to be limiting. In some other embodiments, the second substrate may be doped with a p-type dopant, such as boron, aluminum, gallium, indium, etc., or a combination thereof.

[0026] The second substrate 40 may include a first heavily doped layer 44 extending from the top surface of the second substrate 40. The first heavily doped layer 44 may be formed by ion implantation or epitaxial growth. The first heavily doped layer 44 is of the first conductivity type as described above. The doping concentration of the first heavily doped layer 44 may be higher than the doping concentration of the second substrate 40. In some embodiments, the doping concentration of the first heavily doped layer 44 may be approximately 1.0×10 18 atoms / cm 3 to about 3.0×10 20 atoms / cm 3 In one embodiment, the thickness of the first heavily doped layer 44 may be in the range of 2 nm to 100 nm. These values ​​are merely examples and are not intended to be limiting. Figure 1A In the illustrated embodiment, the first heavily doped layer 44 is unpatterned.

[0027] A hydrogen layer 41 may be implanted into the second substrate 40 (step (b2)). In some embodiments, the implanted hydrogen layer 41 may be formed at a depth of approximately 4×10 -5 inches to approximately 8×10 -5 The implant voltage can be selected appropriately so that the peak of the implanted hydrogen appears at the desired depth. For example, with an implant energy of 50KeV to 150KeV, using a 1×10 16 ions / cm 2 to 2×10 17 ions / cm 2The hydrogen ions are implanted into the second substrate 40 at a dose of . These values ​​are merely examples and are not intended to be limiting. The implantation can be performed before or after the first heavily doped layer 44 is formed, as long as the implanted hydrogen layer 41 is not damaged by subsequent processes. In some embodiments, the hydrogen layer 41 is implanted after the first heavily doped layer 44 is formed. Figure 1A and Figure 1B As shown, the implantation may be performed before forming the first device metal layer 30 .

[0028] like Figure 1B As shown, a first device metal layer 30 is formed on the second substrate 40 (step (b3)). The first device metal layer 30 can be formed to contact the second substrate 40; specifically, the first device metal layer 30 can be formed to contact the first heavily doped layer 44. Figure 1B In the embodiment shown, the first device metal layer 30 includes an ohmic material layer 30o. The ohmic material layer 30o may include a suitable metal, alloy, or conductive metal compound, for example, Mo, Ag, TiN, or a combination thereof, so that an ohmic junction may be formed between the ohmic material layer 30o and the first heavily doped layer 44 (or the second substrate 40). The ohmic material layer 30o may be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Figure 1B In the embodiment shown, the ohmic material layer 30o is unpatterned. In some embodiments, the thickness of the ohmic material layer 30o can be in the range of 2 nm to 100 nm. These values ​​are merely examples and are not intended to be limiting.

[0029] like Figure 1B As shown, a first conductive metal layer 50 may be formed on the first device metal layer 30. Figure 1B In the embodiment shown, the first conductive metal layer 50 comprises an unpatterned layer of conductive metal material. However, in some other embodiments (e.g., Figures 2A to 2E In the embodiment shown, the first conductive metal layer may include patterned conductive features. The first conductive metal layer 50 may include copper, aluminum, tungsten, one or more other suitable materials, or a combination thereof, and may be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0030] refer to Figure 1B , providing a second structure 100B (step (b)). The second structure 100B includes a second substrate 40 and a first device metal layer 30 on and in contact with the second substrate 40. The second substrate 40 may include an implanted hydrogen layer 41. Figure 1BIn the illustrated embodiment, the second structure 100B further includes a first conductive metal layer 50, wherein the first device metal layer 30 is disposed between the first conductive metal layer 50 and the second substrate 40. Figure 1B In the illustrated embodiment, the second substrate 40 further includes a first heavily doped layer 44 in contact with the first device metal layer 30 .

[0031] like Figure 1C As shown, a first structure 100A is provided (step (a)). The first structure 100A includes a first substrate 10. The first substrate 10 may include a single crystal semiconductor material or a polycrystalline semiconductor material, including but not limited to silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN), glass, or ceramic. In some embodiments, the first substrate 10 may include one or more active devices (such as transistors) and / or one or more passive devices (such as capacitors, resistors, diodes, etc.).

[0032] exist Figure 1C In the embodiment shown, a first dielectric layer 22 is formed on the first substrate 10, and a second dielectric layer 24 is formed on the first device metal layer 30 (step (c)). Specifically, the second dielectric layer 24 can be formed on the first conductive metal layer 50. The first dielectric layer 22 and / or the second dielectric layer 24 can include silicon oxide and can be formed by thermal oxidation or deposition (such as CVD, PVD or ALD). Figure 1C and Figure 1D As shown, the first dielectric layer 22 and the second dielectric layer 24 are formed before the first structure 100A and the second structure 100B are bonded together. In some other embodiments, only one of the first dielectric layer 22 and the second dielectric layer 24 is formed.

[0033] like Figure 1D As shown, the second structure 100B is flipped over and bonded to the first structure 100A. The first structure 100A and the second structure 100B are bonded to form a bonded structure 100C via the bonding layer 20 (step (c)). For example, the first structure 100A and the second structure 100B can be bonded by a melt bonding process (such as a hydrophilic melt bonding process). In some embodiments, the first dielectric layer 22 and the second dielectric layer 24 are both cleaned by conventional cleaning techniques (such as an RCA wafer cleaning process). The cleaning process removes surface impurities and particles from the surfaces of the dielectric layers 22 and 24. In one embodiment, due to the presence of atomic charges, hydroxyl groups (OH groups) are formed on the surfaces to be bonded. - ). Hydrogen bonds may be formed between the first dielectric layer 22 and the second dielectric layer 24, and then an annealing process may be performed to form chemical bonds (eg, Si—O bonds) between the surfaces of the first dielectric layer 22 and the second dielectric layer 24. Figure 1DAs shown, the first dielectric layer 22 and the second dielectric layer 24 are bonded to form a bonding layer 20. The bonding layer 20 may include silicon oxide. In one embodiment, the thickness of the bonding layer 20 may be in the range of 0.2 nm to 1000 nm. These values ​​are merely examples and are not intended to be limiting.

[0034] like Figure 1E As shown, a portion of the second substrate 40 is removed from the substantially injected hydrogen layer 41 to form a first semiconductor layer 42 (step (d)). The portion of the second substrate 40 can be removed by heating the bonded structure 100C to a first temperature. The first temperature is typically below 400°C to avoid any damage to the semiconductor devices (if any) fabricated in the first substrate 10 and / or the second substrate 40. In some embodiments, the portion of the second substrate 40 can be removed by other methods, as long as the portion of the second substrate 40 has been sufficiently weakened by the aforementioned hydrogen implantation and some subsequent annealing. For example, the bonded structure 100C can be cracked by applying mechanical pressure to the second substrate 40 or by immersing the bonded structure 100C in liquid nitrogen and quenching.

[0035] Based on the injection depth of the injected hydrogen layer 41, the remaining portion of the second substrate 40 on the bonding structure 100C can be less than 3 μm. After removal, the separation surface of the second substrate 40 can be polished by chemical mechanical polishing (CMP) to flatten the separation surface and minimize its unevenness. Other methods such as etching can be used for the same purpose. When etching is used to flatten the separation surface of the flattened second substrate 40 and minimize its unevenness, it may be necessary to deposit an etch stop layer in advance. In this way, a first semiconductor layer 42 is formed. The first semiconductor layer 42 is the first conductivity type as described above. In some embodiments, the thickness of the first semiconductor layer 42 can be in the range of 5 nm to 200 nm. These values ​​are merely examples and are not intended to be restrictive.

[0036] like Figure 1F and Figure 1G As shown, the first semiconductor layer 42 is patterned to form a plurality of semiconductor layers 42a and 42b (step (e)). The first heavily doped layer 44 may also be patterned to form a plurality of heavily doped regions 44a and 44b. The first semiconductor layer 42 may be patterned by any suitable process (e.g., photolithography and etching processes). In some embodiments, one or more etching processes may be performed to form trenches extending through the first semiconductor layer 42 so that the semiconductor layers 42a and 42b are separated from each other. Figure 1F and Figure 1GIn the illustrated embodiment, the ohmic material layer 30o (first device metal layer 30) is patterned by any suitable process (e.g., photolithography and etching processes) to form a plurality of ohmic contacts 30oa and 30ob. In some embodiments, the first conductive metal layer 50 may also be patterned by a suitable process to form a first wiring layer 50'. The first wiring layer 50' may include conductive features, such as a plurality of conductive lines. However, the present disclosure is not limited thereto.

[0037] like Figure 1F and Figure 1G As shown, a first dielectric structure 92 is formed. The first dielectric structure 92 may surround each of the semiconductor layer 42a, the semiconductor layer 42b, the ohmic contact 30oa, and the ohmic contact 30ob. The first dielectric structure 92 may include one or more stacked dielectric layers. The first dielectric structure 92 may include a dielectric material such as silicon oxide, silicon oxynitride, a low dielectric constant (low-k) material, combinations thereof, and / or other suitable materials, and may be formed by deposition (such as CVD, PVD, or ALD), spin coating, or any other suitable method. The first dielectric structure 92 may fill the trenches between the semiconductor layer 42a and the semiconductor layer 42b and between the ohmic contact 30oa and the ohmic contact 30ob, such that the semiconductor layer 42a and the semiconductor layer 42b are laterally isolated by the first dielectric structure 92, and the ohmic contact 30oa and the ohmic contact 30ob are laterally isolated by the first dielectric structure 92.

[0038] like Figure 1F and Figure 1G As shown, a second device metal layer 60 is formed (step (f)). In the present embodiment, the second device metal layer 60 includes a plurality of Schottky contacts 60sa and 60sb. The Schottky contacts 60sa and 60sb (second device metal layer 60) can be formed to contact the corresponding semiconductor layers 42a and 42b. The Schottky contacts 60sa and 60sb may include a suitable metal, alloy or conductive metal compound, for example, Pt, Pd, Ir, Ru, Cu, W, etc., or a combination thereof, so that a Schottky junction can be formed between the Schottky contacts 60sa and 60sb and the corresponding semiconductor layers 42a and 42b. In some embodiments, the thickness of the Schottky contacts 60sa and 60sb can be in the range of 1nm to 100nm. These values ​​are merely examples and are not intended to be limiting.

[0039] In some embodiments, the Schottky material layer 60s (eg, Figure 1F), and then patterning the Schottky material layer to form a plurality of Schottky contacts 60sa and 60sb before patterning the first semiconductor layer 42 by any suitable process (e.g., photolithography and etching). In some embodiments, the Schottky contacts 60sa and 60sb can be formed in the first dielectric structure 92 using a damascene process or a dual damascene process after patterning the first semiconductor layer 42.

[0040] refer to Figure 1G , Schottky diodes 201a and 201b are provided. The Schottky diode 201a includes an ohmic contact 30oa, a semiconductor layer 42a, and a Schottky contact 60sa. Figure 1G As shown, semiconductor layer 42a is disposed on ohmic contact 30oa, and Schottky contact 60sa is disposed on semiconductor layer 42a. In other words, Schottky diode 201a can be a "vertical diode." In some embodiments, semiconductor layer 42a includes a single crystal semiconductor material. Schottky contact 60sa is disposed in contact with semiconductor layer 42a at one end of semiconductor layer 42a, forming a Schottky junction therebetween. Ohmic contact 30oa is disposed in contact with semiconductor layer 42a at an opposite end of semiconductor layer 42a, forming an ohmic junction therebetween. Semiconductor layer 42a may further include a heavily doped region 44a. Both semiconductor layer 42a and heavily doped region 44a are of the first conductivity type as described above. Ohmic contact 30oa may be in contact with heavily doped region 44a, forming an ohmic junction therebetween.

[0041] The Schottky diode 201b includes an ohmic contact 30ob, a semiconductor layer 42b, and a Schottky contact 60sb. Figure 1G As shown, semiconductor layer 42b is disposed on ohmic contact 30ob, and Schottky contact 60sb is disposed on semiconductor layer 42b. In other words, Schottky diode 201b can be a "vertical diode." In some embodiments, semiconductor layer 42b comprises a single-crystalline semiconductor material. Schottky contact 60sb is disposed in contact with semiconductor layer 42b at one end thereof, forming a Schottky junction therebetween. Ohmic contact 30ob is disposed in contact with semiconductor layer 42b at an opposite end thereof, forming an ohmic junction therebetween. Semiconductor layer 42b may further include a heavily doped region 44b. Both semiconductor layer 42b and heavily doped region 44b are of the first conductivity type as described above. Ohmic contact 30ob may be in contact with heavily doped region 44b, forming an ohmic junction therebetween. A first dielectric structure 92 surrounds each of Schottky diodes 201a and 201b.

[0042] By using the method disclosed herein, a vertical Schottky diode can be formed, wherein a Schottky contact and an ohmic contact are respectively provided at opposite ends of a semiconductor layer in contact with the semiconductor layer, and the semiconductor layer is made of a single crystal semiconductor material. In this way, a Schottky diode with a smaller size (characteristic square) and better electrical characteristics can be formed. Moreover, by using the process described herein, a high-temperature annealing process can be completed at an early stage, thereby avoiding the need for high-temperature processes in subsequent stages.

[0043] like Figure 1H As shown, memory cell components 70a and 70b can be formed (step (i)). In this embodiment, memory cell components 70a and 70b are formed after removing the portion of the second substrate 40 and after the first semiconductor layer 42 is formed and patterned. Memory cell components 70a and 70b can each include a magnetic tunnel junction (MTJ) structure, a phase change material, or a resistance variable material. Figure 1H In the illustrated embodiment, memory cell assemblies 70a and 70b can each include a phase change material or a resistance variable material. In some embodiments, a second dielectric structure 94 substantially similar to the first dielectric structure 92 can be formed on the first dielectric structure 92, and memory cell assemblies 70a and 70b can be formed in the second dielectric structure 94.

[0044] like Figure 1H As shown, a second conductive metal layer 80 is formed (step (f)). The second conductive metal layer 80 can be a second wiring layer including conductive features (e.g., conductive lines or vias). In this embodiment, the second wiring layer 80 is formed after the first semiconductor layer 42 is formed and patterned and after the memory cell components 70a and 70b are formed. The second wiring layer 80 can include copper, aluminum, tungsten, one or more other suitable materials, or a combination thereof, and can be formed in the second dielectric structure 94 using a damascene process, a dual damascene process, or any other suitable method.

[0045] refer to Figure 1H , memory cells 301a and 301b are provided. Memory cell 301a includes a Schottky diode 201a and a memory cell component 70a. Memory cell component 70a is electrically coupled from a first end of memory cell component 70a to a Schottky contact 60sa, and from a second end of memory cell component 70a to a second wiring layer 80. Memory cell 301b includes a Schottky diode 201b and a memory cell component 70b. Memory cell component 70b is electrically coupled from a first end of memory cell component 70b to a Schottky contact 60sb, and from a second end of memory cell component 70b to a second wiring layer 80. Figure 1HThe illustrated memory cells 301a and 301b may be PcRAM cells or RRAM cells, and the first wiring layer 50' and the second wiring layer 80 may serve as bit lines and / or word lines for these memory cells. Figures 1A to 1H Only two diodes and two memory cells are illustrated in FIG, but multiple diodes and multiple memory cells or arrays of diodes and memory cells can be manufactured simultaneously using the methods disclosed herein.

[0046] Figures 2A to 2E is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0047] like Figure 2A As shown, a second structure 101B is provided (step (b)). Figure 2A The second structure 101B shown can be substantially similar to the above combination Figure 1B The second structure 100B, wherein like reference numerals denote like elements. In this embodiment, the first device metal layer 30 includes a plurality of ohmic contacts 30oa and 30ob. The ohmic contacts 30oa and 30ob may include the same as those described above. Figure 1B The material of the ohmic material layer 30o discussed above is similar to the material of the ohmic material layer 30o. Figure 2A In the illustrated embodiment, a dielectric structure 91 substantially similar to the first dielectric structure 92 can be formed on the second substrate 40. Ohmic contacts 30oa and 30ob can be formed in the dielectric structure 91 using a damascene process or a dual damascene process before bonding the first and second structures 101B. Ohmic contacts 30oa and 30ob can be formed in contact with the first heavily doped layer 44. In some embodiments, the thickness of ohmic contacts 30oa and 30ob can range from 2 nm to 100 nm. These values ​​are merely examples and are not intended to be limiting.

[0048] like Figure 2A As shown, a first conductive metal layer 50' can be formed on the ohmic contacts 30oa and 30ob. The first conductive metal layer 50' can be a first wiring layer including conductive features (e.g., conductive lines or vias) and can be electrically connected to the ohmic contacts 30oa and 30ob. The first wiring layer 50' can include copper, aluminum, tungsten, one or more other suitable materials, or a combination thereof, and can be formed in the dielectric structure 91 using a damascene process, a dual damascene process, or any other suitable method. In this embodiment, the first wiring layer 50' is formed before the first structure and the second structure 101B are bonded.

[0049] like Figure 2B As shown, a first structure is provided (step (a)), wherein the first structure includes a first substrate 10, which is similar to the first substrate 10 described above. Figure 1Cand flipping the second structure 101B over and bonding it to the first structure via the bonding layer 20 (step (c)). The bonding process and related details described above can be applied here.

[0050] like Figure 2C As shown, a portion of the second substrate 40 is removed from the substantially implanted hydrogen layer 41 to form a first semiconductor layer 42 (step (d)). The removal process and related details described above can be applied here.

[0051] like Figure 2D As shown, the first semiconductor layer 42 is patterned to form a plurality of semiconductor layers 42a and 42b (step (e)), and a second device metal layer 60 is formed (step (f)). In this embodiment, the second device metal layer 60 includes a plurality of Schottky contacts 60sa and 60sb. Figure 2D The semiconductor structure shown can be combined with the above Figure 1F to Figure 1G The Schottky diodes 201a and 201b are formed by a process similar to the process described above. If applicable, the above-mentioned relevant details can be applied here. In this way, Schottky diodes 201a and 201b are provided. Schottky diodes 201a and 201b can be formed similar to the above-mentioned process. Figure 1G The Schottky diode is described, wherein like reference numerals indicate like elements.

[0052] like Figure 2E As shown, memory cell assemblies 70a and 70b can be formed (step (i)). Figure 2E In the embodiment shown, the memory cell components 70a and 70b can each include a phase change material or a resistance variable material. A second conductive metal layer 80 can also be formed (step (f)). The details and formation methods of the memory cell components 70a and 70b and the second conductive metal layer 80 can be similar to those described above in conjunction with Figure 1H The details and formation methods are described, and the related description is omitted for the sake of brevity. Thus, storage units 301a and 301b are provided. Storage units 301a and 301b can be similar to those in the above combination. Figure 1H The memory unit is described, wherein like reference numerals indicate like elements.

[0053] Figure 3 FIG is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. Figure 3 As shown, a memory cell 311 is provided. The memory cell 311 or similar semiconductor structure can be combined with the present invention. Figures 1A to 1H 、 Figures 2A to 2E 、 Figures 4A to 4F ,as well as Figures 5A to 5C The process is similar to the process described above.

[0054] Specifically, in this embodiment, the memory cell 311 includes Schottky diodes 201a and 201b and a memory cell component 70. The Schottky diodes 201a and 201b can be similar to the above combination. Figure 1G and Figure 2D The Schottky diode, wherein like reference numerals indicate like elements. Figure 3 In the embodiment shown, conductive vias 81 and third wiring layer 82 may be formed such that Schottky contact 60sb of Schottky diode 201b is electrically coupled to ohmic contact 30oa of Schottky diode 201a through conductive features of third wiring layer 82, conductive vias 81, and conductive features of first wiring layer 50'. Conductive vias 81 and third wiring layer 82 may be formed in combination with the above. Figure 1H The second wiring layer 80 is formed by a material and a forming method similar to that of the second wiring layer 80. Figure 1H The second wiring layer 80 is shown to be similar to the second wiring layer 84 .

[0055] exist Figure 3 In the illustrated embodiment, the memory cell assembly 70 is electrically coupled from a first end of the memory cell assembly 70 to both the ohmic contact 30oa of the Schottky diode 201a and the Schottky contact 60sb of the Schottky diode 201b, and from a second end of the memory cell assembly 70 to the second wiring layer 84. The memory cell assembly 70 may include a magnetic tunnel junction (MTJ) structure or a phase change material. The MTJ structure may include a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer located between the free magnetic layer and the fixed magnetic layer. The fixed magnetic layer may have a fixed magnetization, and the free magnetic layer may have a magnetization that can be switched by a program current. The orientation of the magnetization in the free magnetic layer relative to the orientation of the magnetization in the fixed magnetic layer may determine whether the MTJ structure is in a high resistance state or a low resistance state (e.g., whether the memory cell assembly stores a "1" or a "0"). For example, if the magnetizations of the free magnetic layer and the fixed magnetic layer are in a parallel orientation, the MTJ structure can be in a low resistance state (e.g., a "0" state); and if the magnetizations of the free magnetic layer and the fixed magnetic layer are in opposite (antiparallel) orientations, the MTJ structure can be in a high resistance state (e.g., a "1" state). Data writing can be performed by switching the orientation of the magnetization of the free magnetic layer. In some embodiments, to enhance the performance of the MTJ structure, the free magnetic layer and / or the fixed magnetic layer may include a multilayer structure. The MTJ structure may be formed by any suitable method and any material suitable for each layer thereof.

[0056] Figure 3The memory cell 311 shown may be a spin-transfer torque MRAM (STT-MRAM) cell, and the first wiring layer 50', the second wiring layer 84, and the third wiring layer 82 may serve as bit lines and / or word lines of the memory cell. Figure 3 Only two diodes and one memory cell are illustrated in FIG, but a plurality of diodes and a plurality of memory cells or an array of diodes and memory cells can be fabricated simultaneously using the method disclosed herein.

[0057] Figures 4A to 4F is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0058] like Figure 4A As shown, a second substrate 40 is provided (step (b1)), and a hydrogen layer 41 may be implanted into the second substrate 40 (step (b2)). The details regarding the second substrate 40 and the implanted hydrogen layer 41 described above may apply here.

[0059] like Figure 4B As shown, a first device metal layer 30 is formed on the second substrate 40 (step (b3)). The first device metal layer 30 may be formed to contact the second substrate 40. Figure 4B In the embodiment shown, the first device metal layer 30 includes a Schottky material layer 30s. The Schottky material layer 30s may include a suitable metal, alloy, or conductive metal compound, such as Pt, Pd, Ir, Ru, Cu, W, or a combination thereof, so that a Schottky junction may be formed between the Schottky material layer 30s and the second substrate 40. The Schottky material layer 30s may be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Figure 4B In the embodiment shown, the Schottky material layer 30s is unpatterned. In some embodiments, the thickness of the Schottky material layer 30s can be in the range of 2 nm to 100 nm. These values ​​are merely examples and are not intended to be limiting. In some other embodiments, the first device metal layer can include a plurality of Schottky contacts formed of a material similar to the Schottky material layer 30s. The Schottky contacts can be formed by combining the above Figure 2A The ohmic contacts 30oa and 30ob are formed in a similar manner.

[0060] like Figure 4B As shown, a metal layer may be formed on the first device metal layer 30 in combination with the above Figure 1B The first conductive metal layer is similar to the first conductive metal layer 50. Figure 4BIn the embodiment shown, the first conductive metal layer 50 comprises an unpatterned layer of conductive metal material. However, in some other embodiments, the first conductive metal layer may comprise patterned conductive features and may be similar to the above-described conductive metal layer. Figure 2A The first wiring layer 50' is thus provided with a second structure 102B (step (b)). Figure 4B The second structure 102B shown may be substantially similar to the above-mentioned Figure 1B In the second structure 100B, like reference numerals denote like elements. In this embodiment, the first device metal layer 30 includes a Schottky material layer 30s.

[0061] like Figure 4C As shown, a first structure is provided (step (a)), wherein the first structure includes a first substrate 10, which is similar to the first substrate 10 described above. Figure 1C and flipping the second structure 102B over and bonding it to the first structure via the bonding layer 20 (step (c)). The bonding process and related details described above can be applied here.

[0062] Then, a portion of the second substrate 40 is removed from the substantially implanted hydrogen layer 41 to form the first semiconductor layer 42 (step (d)). The removal process and related details described above can be applied here.

[0063] like Figure 4D As shown, a second heavily doped layer 45 is formed (step (h)). Figure 4D In the illustrated embodiment, the second heavily doped layer 45 is formed after a portion of the second substrate 40 is removed. In some embodiments, the second heavily doped layer 45 is formed in the first semiconductor layer 42 and extends from the top surface of the first semiconductor layer 42. In some embodiments, the second heavily doped layer 45 is formed on and in contact with the top surface of the first semiconductor layer 42. The second heavily doped layer 45 can be of the first conductivity type as described above. The doping concentration of the second heavily doped layer 45 can be higher than the doping concentration of the first semiconductor layer 42. In some embodiments, the doping concentration of the second heavily doped layer 45 can be approximately 1.0×10 18 atoms / cm 3 to about 3.0×10 20 atoms / cm 3 In some embodiments, the thickness of the second heavily doped layer 45 may be in the range of 2 nm to 100 nm. These values ​​are merely examples and are not intended to be limiting. Figure 4D In the embodiment shown, the second heavily doped layer 45 is not patterned. The second heavily doped layer 45 can be formed by ion implantation or epitaxial growth.

[0064] like Figure 4EAs shown, the first semiconductor layer 42 is patterned to form a plurality of semiconductor layers 42a and 42b (step (e)), and a second device metal layer 60 is formed (step (f)). In this embodiment, the second device metal layer 60 includes a plurality of ohmic contacts 60oa and 60ob. Figure 4E The semiconductor structure shown can be combined with the above Figure 1F to Figure 1G The above-mentioned process is similar to the process of forming the above-mentioned process. If applicable, the above-mentioned relevant details can be applied here.

[0065] Specifically, in Figure 4E In the embodiment shown, the Schottky material layer 30s (first device metal layer 30) can be patterned by any suitable process (e.g., photolithography and etching process) to form a plurality of Schottky contacts 30sa and 30sb. In some embodiments, the first conductive metal layer 50 can also be patterned by a suitable process to form a first wiring layer 50'. The second heavily doped layer 45 can be patterned to form a plurality of heavily doped regions 45a and 45b, and ohmic contacts 60oa and 60ob are formed to contact the corresponding heavily doped regions 45a and 45b. The formation method of the ohmic contacts 60oa and 60ob can be similar to the above combined method. Figure 1F to Figure 1G The method for forming the Schottky contacts 60sa and 60sb.

[0066] refer to Figure 4E , Schottky diodes 202a and 202b are provided. The Schottky diode 202a includes a Schottky contact 30sa, a semiconductor layer 42a, and an ohmic contact 60oa. Figure 4E As shown, semiconductor layer 42a is disposed on Schottky contact 30sa, and ohmic contact 60oa is disposed on semiconductor layer 42a. In other words, Schottky diode 202a can be a "vertical diode." In some embodiments, semiconductor layer 42a includes a single crystal semiconductor material. Schottky contact 30sa is disposed at one end of semiconductor layer 42a in contact with semiconductor layer 42a, forming a Schottky junction therebetween. Ohmic contact 60oa is disposed at an opposite end of semiconductor layer 42a. Ohmic contact 60oa can contact heavily doped region 45a, forming an ohmic junction therebetween. Both semiconductor layer 42a and heavily doped region 45a are of the first conductivity type as described above.

[0067] The Schottky diode 202b includes a Schottky contact 30sb, a semiconductor layer 42b, and an ohmic contact 60ob. Figure 1GAs shown, the semiconductor layer 42b is disposed on the Schottky contact 30sb, and the ohmic contact 60ob is disposed on the semiconductor layer 42b. In other words, the Schottky diode 202b can be a "vertical diode". In some embodiments, the semiconductor layer 42b includes a single crystal semiconductor material. The Schottky contact 30sb is disposed in contact with the semiconductor layer 42b at one end of the semiconductor layer 42b, and a Schottky junction is formed therebetween. The ohmic contact 60ob is disposed at the opposite end of the semiconductor layer 42b. The ohmic contact 60ob can be in contact with the heavily doped region 45b, and an ohmic junction is formed therebetween. The semiconductor layer 42b and the heavily doped region 45b are both of the first conductivity type as described above. In combination with the above Figure 1F and Figure 1G The first dielectric structure 92 similar to the first dielectric structure described above surrounds each of the Schottky diodes 202a and 202b, thereby forming a Schottky diode with a smaller size (square characteristic) and better electrical characteristics.

[0068] like Figure 4F As shown, memory cell assemblies 70a and 70b can be formed (step (i)). Figure 4F In the embodiment shown, the memory cell components 70a and 70b can each include a phase change material or a resistance variable material. A second conductive metal layer 80 can also be formed (step (f)). The details and formation methods of the memory cell components 70a and 70b and the second conductive metal layer 80 can be similar to those described above in conjunction with Figure 1H The details and formation methods are described, and related descriptions are omitted for the sake of brevity.

[0069] refer to Figure 4F Memory cells 302a and 302b are provided. Memory cell 302a includes a Schottky diode 202a and a memory cell component 70a. Memory cell component 70a is electrically coupled from a first end of memory cell component 70a to an ohmic contact 60oa of Schottky diode 202a, and from a second end of memory cell component 70a to a second wiring layer 80. Memory cell 302b includes a Schottky diode 202b and a memory cell component 70b. Memory cell component 70b is electrically coupled from a first end of memory cell component 70b to an ohmic contact 60ob of Schottky diode 202b, and from a second end of memory cell component 70b to a second wiring layer 80. Figure 4F The illustrated memory cells 302a and 302b may be PcRAM cells or RRAM cells, and the first wiring layer 50' and the second wiring layer 80 may serve as bit lines and / or word lines for these memory cells. Figures 4A to 4F Only two diodes and two memory cells are illustrated in FIG, but multiple diodes and multiple memory cells or arrays of diodes and memory cells can be manufactured simultaneously using the methods disclosed herein.

[0070] Figures 5A to 5C is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0071] like Figure 5A As shown, a second substrate 40 is provided (step (b1)), and a hydrogen layer 41 can be implanted into the second substrate 40 (step (b2)). In this embodiment, a second heavily doped layer 45' can be formed at a desired depth from the top surface of the second substrate 40, for example, by ion implantation. The second heavily doped layer 45' is formed before the first structure and the second structure are bonded. The second heavily doped layer 45' can be of the first conductivity type as described above. The doping concentration of the second heavily doped layer 45' can be higher than the doping concentration of the second substrate 40. In some embodiments, the doping concentration of the second heavily doped layer 45' can be about 1.0×10 18 atoms / cm 3 to about 3.0×10 20 atoms / cm 3 These values ​​are merely examples and are not intended to be limiting. The details regarding the second substrate 40 and the implanted hydrogen layer 41 described above may apply here, if applicable. In some embodiments, the second heavily doped layer 45 ′ may be formed before the hydrogen layer 41 is implanted.

[0072] like Figure 5B As shown, a second structure 103B is provided (step (b)). Figure 5B The second structure 103B shown can be substantially similar to the above combination Figure 4B In the second structure 102B, like reference numerals denote like elements. In this embodiment, the second substrate 40 further includes a second heavily doped layer 45'.

[0073] like Figure 5C As shown, a first structure is provided (step (a)), wherein the first structure includes a first substrate 10, which is similar to the first substrate 10 described above. Figure 1C and flipping the second structure 103B over and bonding it to the first structure via the bonding layer 20 (step (c)). The bonding process and related details described above can be applied here.

[0074] Then, a portion of the second substrate 40 is removed from the substantially implanted hydrogen layer 41 to form the first semiconductor layer 42 (step (d)). The removal process and related details described above can be applied here. In this embodiment, after removing a portion of the second substrate 40 and flattening the exposed surface, the second heavily doped layer 45 is exposed. Figure 4E and Figure 4FThe semiconductor structures similar to the Schottky diodes 202a and 202b and the memory cells 302a and 302b can be combined with the above Figures 4E to 4F The process similar to the process described above Figure 5C The structure shown is formed.

[0075] Figures 6A to 6G is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0076] like Figure 6A As shown, a second substrate 40 is provided (step (b1)), and a hydrogen layer 41 can be implanted into the second substrate 40 (step (b2)). In this embodiment, the second substrate 40 includes a patterned first heavily doped layer, and the patterned first heavily doped layer includes a heavily doped region 44a extending from the top surface of the second substrate 40. The heavily doped region 44a can be formed by ion implantation or epitaxial growth. The heavily doped region 44a is of the first conductivity type as described above. The doping concentration of the heavily doped region 44a can be higher than the doping concentration of the second substrate 40. In some embodiments, the doping concentration of the heavily doped region 44a can be about 1.0×10 18 atoms / cm 3 to about 3.0×10 20 atoms / cm 3 In one embodiment, the thickness of the heavily doped region 44a can be in a range of 2 nm to 100 nm. These values ​​are merely examples and are not intended to be limiting. If applicable, the relevant details regarding the second substrate 40 and the implanted hydrogen layer 41 described above can apply here.

[0077] like Figure 6B As shown, a second structure 104B is provided (step (b)). Figure 6B The second structure 104B shown can be substantially similar to the above-mentioned Figure 2A The second structure 101B, wherein similar reference numerals indicate similar elements. In this embodiment, the first device metal layer 30 includes a patterned Schottky material layer 30s and an ohmic contact 30oa. The ohmic contact 30oa can be similar to the above combination Figure 2A The patterned Schottky material layer 30s can be substantially similar to the above combination Figure 4B The Schottky material layer is 30s.

[0078] The patterned Schottky material layer 30s can be formed by deposition (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD)). In some embodiments, an unpatterned Schottky material layer (not shown) can be formed on the second substrate 40 and then patterned by any suitable process (e.g., photolithography and etching process) to form a patterned Schottky material layer 30s. In some embodiments, a groove can be etched through the unpatterned Schottky material layer (not shown), and an ohmic contact 30oa can be formed in the groove. The ohmic contact 30oa can be formed to contact the heavily doped region 44a. In some embodiments, the ohmic contact 30oa can be formed by combining the above Figure 2A In some embodiments, the thickness of the patterned Schottky material layer 30s and the thickness of the ohmic contact 30oa can be in a range of 2 nm to 100 nm. These values ​​are merely examples and are not intended to be limiting.

[0079] In some other embodiments, the first device metal layer may include a patterned ohmic material layer and a Schottky contact, and may be formed by methods similar to those described herein. The patterned ohmic material layer may be similar to the method described above in conjunction with Figure 1B The ohmic material layer 30o. The Schottky contact can be similar to the above combination Figure 4B In some other embodiments, the first device metal layer may include an ohmic contact and a Schottky contact, and the above combination may be used. Figure 2A In yet other embodiments, the first device metal layer may include a patterned ohmic material layer and a patterned Schottky material layer, and may be formed by a similar method as described herein.

[0080] like Figure 6C As shown, a first structure is provided (step (a)), wherein the first structure includes a first substrate 10, which is similar to the first substrate 10 described above. Figure 1C and flipping the second structure 104B over and bonding it to the first structure via the bonding layer 20 (step (c)). The bonding process and related details described above can be applied here.

[0081] like Figure 6D As shown, a portion of the second substrate 40 is removed from the substantially implanted hydrogen layer 41 to form a first semiconductor layer 42 (step (d)). The removal process and related details described above can be applied here.

[0082] like Figure 6EAs shown, a second heavily doped layer is formed (step (h)). In this embodiment, the second heavily doped layer is a patterned layer including heavily doped regions 45b. In some embodiments, the doping concentration of the heavily doped layer 45b may be about 1.0×10 18 atoms / cm 3 to about 3.0×10 20 atoms / cm 3 In some embodiments, the thickness of the heavily doped layer 45b can be in the range of 2 nm to 100 nm. These values ​​are merely examples and are not intended to be limiting. If applicable, the details and formation methods of the second heavily doped layer described above can be applied here.

[0083] like Figure 6F As shown, the first semiconductor layer 42 is patterned to form a plurality of semiconductor layers 42a and 42b (step (e)), and a second device metal layer 60 is formed (step (f)). In this embodiment, the second device metal layer 60 includes: a second device metal layer 60 including both a Schottky contact 60sa and an ohmic contact 60ob. Figure 6F The semiconductor structure shown can be combined with the above Figure 1F to Figure 1G The above-mentioned process is similar to the process of forming the above-mentioned process. If applicable, the above-mentioned relevant details can be applied here.

[0084] Specifically, in Figure 6F In the embodiment shown, the Schottky material layer 30s may be further patterned by any suitable process (eg, photolithography and etching process) to form a Schottky contact 30sb. Figure 6F As shown, an ohmic contact 60ob is formed in contact with the heavily doped region 45b.

[0085] refer to Figure 6F , Schottky diodes 201 and 202 are provided. Figure 6F The Schottky diode 201 shown may be substantially similar to the one described above in conjunction with Figure 1G and Figure 2D The Schottky diodes 201a and 201b are described, wherein like reference numerals indicate like elements. Figure 6F The Schottky diode 202 shown may be substantially similar to the one described above in conjunction with Figure 4E The Schottky diodes 202a and 202b are described, wherein like reference numerals indicate like elements. If applicable, the above-mentioned relevant details may apply here.

[0086] In this embodiment, the vertical Schottky diodes 201 and 202 manufactured under the same set of processes are formed to be arranged in opposite directions. This configuration can simplify wiring and reduce the thickness of the entire semiconductor device.

[0087] like Figure 6G As shown, a storage unit assembly 70 can be formed (step (i)). The storage unit assembly 70 can be similar to the above combined Figure 3 The storage unit component in question.

[0088] exist Figure 6G In the embodiment shown, a third wiring layer 82 may be formed such that the Schottky contact 60sa of the Schottky diode 201 is electrically coupled to the ohmic contact 60ob of the Schottky diode 202 through the conductive features of the third wiring layer 82. The third wiring layer 82 may be formed by combining the above Figure 1H The second wiring layer 80 is formed by a material and a forming method similar to that of the second wiring layer 80. Figure 1H The second wiring layer 80 is shown to be similar to the second wiring layer 84 .

[0089] refer to Figure 6G , a memory cell 312 is provided. The memory cell 312 includes the Schottky diodes 201 and 202 and the memory cell component 70. The memory cell component 70 is electrically coupled from a first end of the memory cell component 70 to both the Schottky contact 60sa of the Schottky diode 201 and the ohmic contact 60ob of the Schottky diode 202, and is electrically coupled from a second end of the memory cell component 70 to the second wiring layer 84. Figure 6G The illustrated memory cell 312 may be a spin-transfer torque MRAM (STT-MRAM) cell, and the first wiring layer 50' and the second wiring layer 84 may serve as bit lines and / or word lines for the memory cell. Figure 6G Only two diodes and one memory cell are illustrated in FIG, but a plurality of diodes and a plurality of memory cells or an array of diodes and memory cells can be fabricated simultaneously using the method disclosed herein.

[0090] Figure 7 is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. Figure 7 , memory cells 321a and 321b are provided. The memory cells 321a and 321b or similar semiconductor structures can be combined with the present invention. Figures 6A to 6G The process is similar to the process described above.

[0091] Specifically, in this embodiment, memory cell 321a includes a first pair of Schottky diodes 201-1a and 202-1a, a second pair of Schottky diodes 201-2a and 202-2a, an electrode 82a, and a memory cell component 70a; memory cell 321b includes a first pair of Schottky diodes 201-1b and 202-1b, a second pair of Schottky diodes 201-2b and 202-2b, an electrode 82b, and a memory cell component 70b. The Schottky diodes 201-1a, 202-1a, 201-2a, and 202-2a of memory cell 321a and the Schottky diodes 201-1b, 202-1b, 201-2b, and 202-2b of memory cell 321b can be disposed on the first wiring layer 50'. Memory cell assembly 70a may be disposed on Schottky diodes 201-1a, 202-1a, 201-2a, and 202-2a; and memory cell assembly 70b may be disposed on Schottky diodes 201-1b, 202-1b, 201-2b, and 202-2b. A second wiring layer 84 may be disposed on memory cell assemblies 70a and 70a.

[0092] The Schottky diodes 201-1a, 201-2a, 201-1b and 201-2b can be substantially similar to the above combination Figure 1G and Figure 2D The Schottky diodes 201a and 201b; the Schottky diodes 202-1a, 202-2a, 202-1b and 202-2b can be substantially similar to the above combination Figure 4E The Schottky diodes 202a and 202b are described, wherein like reference numerals indicate like elements. Figure 7 As shown, the first pair of Schottky diodes 201-1a and 202-1a and the second pair of Schottky diodes 201-2a and 202-2a of the memory cell 321a each include a pair of diodes arranged in opposite directions; and the first pair of Schottky diodes 201-1b and 202-1b and the second pair of Schottky diodes 201-2b and 202-2b of the memory cell 321b each include a pair of diodes arranged in opposite directions.

[0093] like Figure 7 As shown, electrode 82a extends laterally in first direction 102a. In some embodiments, electrode 82a includes a material having a high spin Hall effect, for example, β-tantalum (β-Ta), β-tungsten (β-W), Ta, W, Pt, Cu doped with elements such as Ir and Bi, and any element that can exhibit high spin-orbit coupling. Electrode 82a can be formed using a damascene process or a dual damascene process or any suitable method. Memory cell 321b can be similar to memory cell 321a, with like reference numerals indicating like elements.

[0094] refer to Figure 7 , Schottky diodes 201-1a and 202-1a are both electrically coupled to electrode 82a on a first side of memory cell assembly 70a, and Schottky diodes 201-2a and 202-2a are both electrically coupled to electrode 82a on a second side of memory cell assembly 70a. Similarly, Schottky diodes 201-1b and 202-1b are both electrically coupled to electrode 82b on a first side of memory cell assembly 70b, and Schottky diodes 201-2b and 202-2b are both electrically coupled to electrode 82b on a second side of memory cell assembly 70b.

[0095] The memory cell components 70a and 70b may include a magnetic tunnel junction (MTJ) structure. The details and formation methods of the memory cell components 70a and 70b may be substantially similar to those described above in conjunction with Figure 3 The details and formation methods are described, and the related description is omitted for brevity. Memory cell assembly 70a can be electrically coupled to electrode 82a at a first end of memory cell assembly 70a, and can be electrically coupled to second wiring layer 84 at a second end of memory cell assembly 70a. Memory cell assembly 70b can be electrically coupled to electrode 82b at a first end of memory cell assembly 70b, and can be electrically coupled to second wiring layer 84 at a second end of memory cell assembly 70b.

[0096] Figure 7 Each of the illustrated memory cells 321a and 321b may be a spin-orbit torque MRAM (SOT-MRAM) cell, and the first wiring layer 50' and the second wiring layer 84 may serve as bit lines and / or word lines for these memory cells. Figure 7 As shown, each of the memory cells 321a and 321b may have a cell size of 8F and 2F in the first direction 102a and the second direction 102b, respectively, which provides a 16-characteristic square (F 2 ) unit size. The symbol "F" herein represents the minimum feature size (or half of the minimum feature pitch) typically associated with a particular lithography process. Although Figure 7 Only two memory cells are shown in FIG, but multiple memory cells or cell arrays can be fabricated simultaneously using the methods disclosed herein.

[0097] Figures 8A to 8D is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0098] like Figure 8A As shown, the second structure including the second substrate and the first device metal layer 30 (ohmic material layer 30o) is bonded to the first structure including the first substrate 10 through the bonding layer 20. Then, a portion of the second substrate is removed and the first semiconductor layer 42 is formed. Figure 8AThe details and formation methods of the semiconductor structure shown can be substantially similar to those described above in conjunction with Figures 1A to 1E The details and formation methods are described, and related descriptions are omitted for the sake of brevity.

[0099] like Figure 8B As shown, after removing a portion of the second substrate, a second semiconductor layer 46 is formed on the exposed surface 42S of the first semiconductor layer 42 (step (j1)). Figure 8B In the embodiment shown, the second semiconductor layer 46 is a second conductivity type (e.g., p-type) opposite to the first conductivity type (e.g., n-type). However, the present disclosure is not limited thereto. In some embodiments, the second semiconductor layer 46 is formed on the first semiconductor layer 42 by epitaxial growth. In some embodiments, the second semiconductor layer 46 can be formed on the first semiconductor layer 42 by ion implantation or epitaxial growth. Figure 8A The second semiconductor layer 46 may further include a heavily doped layer 48 , wherein the heavily doped layer 48 is of the second conductivity type and the doping concentration of the heavily doped layer 48 may be higher than the doping concentration of the second semiconductor layer 46 .

[0100] like Figure 8C As shown, the first semiconductor layer 42 is patterned to form a plurality of semiconductor layers 42a and 42b (step (e)). The first heavily doped layer 44 can also be patterned to form a plurality of heavily doped regions 44a and 44b. Figure 8C In the embodiment shown, step (e) further includes patterning the second semiconductor layer 46. The second semiconductor layer 46 is patterned to form a plurality of semiconductor layers 46a and 46b. The heavily doped layer 48 may also be patterned to form a plurality of heavily doped regions 48a and 48b. Figure 8C In the embodiment shown, a plurality of ohmic contacts 30oa and 30ob and a first wiring layer 50' may also be formed. The patterning process and related details described above may apply here.

[0101] like Figure 8C As shown, a second device metal layer 60 is formed (step (f)). In this embodiment, the second device metal layer 60 includes a plurality of ohmic contacts 60oa and 60ob. The ohmic contacts 60oa and 60ob (second device metal layer 60) can be formed to contact the corresponding semiconductor layers 46a and 46b. Figure 8C The semiconductor structure shown can be combined with the above Figure 1F to Figure 1G The above-mentioned process is similar to the process of forming the above-mentioned process. If applicable, the above-mentioned relevant details can be applied here.

[0102] refer to Figure 8C, diodes 211a and 211b are provided. Diode 211a includes an ohmic contact 30oa, a semiconductor layer 42a, a semiconductor layer 46a, and an ohmic contact 60oa. Figure 8C As shown, semiconductor layer 42a is disposed on ohmic contact 30oa, semiconductor layer 46a is disposed on semiconductor layer 42a, and ohmic contact 60oa is disposed on semiconductor layer 46a. In other words, diode 211a can be a "vertical diode." In some embodiments, semiconductor layer 42a comprises a single crystalline semiconductor material. In some embodiments, semiconductor layer 46a comprises a single crystalline semiconductor material. Ohmic contact 60oa can be disposed in contact with semiconductor layer 46a, forming an ohmic junction therebetween. Ohmic contact 30oa can be disposed in contact with semiconductor layer 42a, forming an ohmic junction therebetween. Semiconductor layer 42a has a first conductivity type, and semiconductor layer 46a has a second conductivity type opposite to the first conductivity type. Semiconductor layer 42a can be disposed in contact with semiconductor layer 46a, forming a PN junction therebetween.

[0103] The diode 211b includes an ohmic contact 30ob, a semiconductor layer 42b, a semiconductor layer 46b, and an ohmic contact 60ob. Figure 8C As shown, semiconductor layer 42b is disposed on ohmic contact 30ob, semiconductor layer 46b is disposed on semiconductor layer 42b, and ohmic contact 60ob is disposed on semiconductor layer 46b. In other words, diode 211b can be a "vertical diode." In some embodiments, semiconductor layer 42b includes a single crystal semiconductor material. In some embodiments, semiconductor layer 46b includes a single crystal semiconductor material. Ohmic contact 60ob can be disposed in contact with semiconductor layer 46b, forming an ohmic junction therebetween. Ohmic contact 30ob can be disposed in contact with semiconductor layer 42b, forming an ohmic junction therebetween. Semiconductor layer 42b is of a first conductivity type, and semiconductor layer 46b is of a second conductivity type opposite to the first conductivity type. Semiconductor layer 42b can be disposed in contact with semiconductor layer 46b, forming a PN junction therebetween.

[0104] like Figure 8D As shown, memory cell assemblies 70a and 70b can be formed (step (i)). Figure 8D In the embodiment shown, the memory cell components 70a and 70b can each include a phase change material or a resistance variable material. A second conductive metal layer 80 can also be formed (step (f)). The details and formation methods of the memory cell components 70a and 70b and the second conductive metal layer 80 can be similar to those described above in conjunction with Figure 1H The details and formation methods are described, and related descriptions are omitted for the sake of brevity.

[0105] refer to Figure 8DMemory cells 303a and 303b are provided. Memory cell 303a includes a diode 211a and a memory cell component 70a. Memory cell component 70a is electrically coupled from a first end of memory cell component 70a to an ohmic contact 60oa, and from a second end of memory cell component 70a to a second wiring layer 80. Memory cell 303b includes a diode 211b and a memory cell component 70b. Memory cell component 70b is electrically coupled from a first end of memory cell component 70a to an ohmic contact 60ob, and from a second end of memory cell component 70b to a second wiring layer 80. Figure 8D The illustrated memory cells 303a and 303b may be PcRAM cells or RRAM cells, and the first wiring layer 50' and the second wiring layer 80 may serve as bit lines and / or word lines for these memory cells. Figures 8A to 8D Only two diodes and two memory cells are illustrated in FIG, but multiple diodes and multiple memory cells or arrays of diodes and memory cells can be manufactured simultaneously using the methods disclosed herein.

[0106] Figures 9A to 9C is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0107] like Figure 9A As shown, the second structure including the second substrate and the first device metal layer 30 (ohmic contacts 30oa and 30ob) is bonded to the first structure including the first substrate 10 through the bonding layer 20. Then, a portion of the second substrate is removed and the first semiconductor layer 42 is formed. Figure 9A The details and formation methods of the semiconductor structure shown can be substantially similar to those described above in conjunction with Figures 2A to 2C The details and formation methods are described, and related descriptions are omitted for the sake of brevity.

[0108] like Figure 9B As shown, after a portion of the second substrate is removed, the second semiconductor layer 46 is formed on the exposed surface 42S of the first semiconductor layer 42 (step (j1)). Figure 9B The details and formation method of the second semiconductor layer 46 shown can be substantially similar to those described above in conjunction with Figure 8B The details and formation methods are described, and related descriptions are omitted for the sake of brevity.

[0109] like Figure 9C As shown, the first semiconductor layer 42 is patterned to form a plurality of semiconductor layers 42a and 42b (step (e)). The second semiconductor layer 46 is patterned to form a plurality of semiconductor layers 46a and 46b. A second device metal layer 60 is formed (step (f)). In this embodiment, the second device metal layer 60 includes a plurality of ohmic contacts 60oa and 60ob. Figure 9CThe semiconductor structure shown can be combined with the above Figure 8C The diodes 211a and 211b are formed by a process similar to that described above. If applicable, the above-mentioned relevant details can be applied here. Thus, diodes 211a and 211b are provided. Diodes 211a and 211b can be formed similar to the above-mentioned process. Figure 8C The diode is described, wherein like reference numerals indicate like elements.

[0110] like Figure 9C As shown, memory cell components 70a and 70b can be formed (step (i)). In this embodiment, memory cell components 70a and 70b can each include a phase change material or a resistance variable material. A second conductive metal layer 80 can also be formed (step (f)). The details and formation methods of memory cell components 70a and 70b and second conductive metal layer 80 can be similar to those described above in conjunction with Figure 1H The details and formation methods are described, and the related description is omitted for the sake of brevity. Thus, storage units 303a and 303b are provided. Storage units 303a and 303b can be similar to those in the above combination. Figure 8D The memory unit is described, wherein like reference numerals indicate like elements.

[0111] Figure 10 is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0112] like Figure 10 As shown, a memory cell 313 is provided. The memory cell 313 or similar semiconductor structure can be combined with the present invention. Figures 8A to 8D 、 Figures 9A to 9C 、 Figures 11A to 11E ,as well as 12A to 12C The process is similar to the process described above. Figure 10 The storage unit 313 shown can be substantially similar to the above-mentioned Figure 3 The storage unit 311 is described, wherein like reference numerals indicate like elements.

[0113] exist Figure 10 In the embodiment shown, the memory cell 313 includes diodes 211a and 211b and a memory cell assembly 70. The diodes 211a and 211b may be similar to those described above in conjunction with the memory cell assembly 70. Figure 8C and Figure 9C The diode, wherein like reference numerals indicate like elements. Figure 10 In the embodiment shown, conductive vias 81 and third wiring layer 82 may be formed such that ohmic contact 60ob of diode 211b is electrically coupled to ohmic contact 30oa of diode 211a through conductive features of third wiring layer 82, conductive vias 81, and conductive features of first wiring layer 50'. Figure 10In the illustrated embodiment, the memory cell assembly 70 is electrically coupled to both the ohmic contact 30oa of the diode 211a and the ohmic contact 60ob of the diode 211b from a first end of the memory cell assembly 70 and to the second wiring layer 84 from a second end of the memory cell assembly 70.

[0114] Figure 10 The illustrated memory cell 313 may be an STT-MRAM cell, and the first wiring layer 50', the second wiring layer 84, and the third wiring layer 82 may serve as bit lines and / or word lines for the memory cell. Figure 10 Only two diodes and one memory cell are illustrated in FIG, but a plurality of diodes and a plurality of memory cells or an array of diodes and memory cells can be fabricated simultaneously using the method disclosed herein.

[0115] Figures 11A to 11E is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0116] like Figure 11A As shown, a second substrate 40 is provided (step (b1)), and a hydrogen layer 41 can be implanted into the second substrate 40 (step (b2)). In the present embodiment, a first opposite type doped layer 47 is formed in the second substrate 40. The first opposite type doped layer 47 is a second conductivity type (e.g., p-type) opposite to the first conductivity type. The first opposite type doped layer 47 can be formed by ion implantation or epitaxial growth. In some embodiments, the first opposite type doped layer 47 can further include a heavily doped layer 49, wherein the heavily doped layer 49 is of the second conductivity type. The doping concentration of the heavily doped layer 49 can be higher than the doping concentration of the first opposite type doped layer 47. The relevant details of the second substrate 40 and the implanted hydrogen layer 41 described above can apply here.

[0117] like Figure 11B As shown, a first device metal layer 30 is formed on the second substrate 40 (step (b3)). The first device metal layer 30 may be formed to contact the heavily doped layer 49. Figure 11B In the embodiment shown, the first device metal layer 30 includes an ohmic material layer 30o. A first conductive metal layer 50 may be formed on the first device metal layer 30. Thus, a second structure 105B is provided (step (b)). Figure 11B The second structure 105B shown can be substantially similar to the above combination Figure 1B In the second structure 100B, like reference numerals denote like elements. In this embodiment, the second substrate 40 further includes a first opposite-type doped layer 47 in contact with the first device metal layer 30 .

[0118] like Figure 11CAs shown, a first structure is provided (step (a)), wherein the first structure includes a first substrate 10, which is similar to the first substrate 10 described above. Figure 1C The first substrate is then flipped over and bonded to the first structure via the bonding layer 20 (step (c)). The bonding process and related details described above can be applied here. Then, a portion of the second substrate 40 is removed from the substantially implanted hydrogen layer 41 to form the first semiconductor layer 42 (step (d)). The removal process and related details described above can be applied here.

[0119] like Figure 11D As shown, a second heavily doped layer 45 is formed (step (h)). Figure 11D In the illustrated embodiment, the second heavily doped layer 45 is formed after removing a portion of the second substrate 40. The details related to the second heavily doped layer 45 described above can be applied here.

[0120] like Figure 11E As shown, the first semiconductor layer 42 is patterned to form a plurality of semiconductor layers 42a and 42b and a plurality of semiconductor layers 47a and 47b (step (e)). A second device metal layer 60 is formed (step (f)). In this embodiment, the second device metal layer 60 includes a plurality of ohmic contacts 60oa and 60ob. Figure 11E The semiconductor structure shown can be combined with the above Figure 8C The diodes 212a and 212b are formed by similar processes as described above. If applicable, the relevant details mentioned above can be applied here. In this way, diodes 212a and 212b are provided. Figure 11E The diodes 212a and 212b shown may be substantially similar to those described above in conjunction with Figure 8C The diodes 211a and 211b are described, wherein like reference numerals indicate like elements.

[0121] refer to Figure 11E Diode 212a includes ohmic contact 30oa, semiconductor layer 42a, semiconductor layer 47a, and ohmic contact 60oa. Semiconductor layer 47a is disposed on ohmic contact 30oa, semiconductor layer 42a is disposed on semiconductor layer 47a, and ohmic contact 60oa is disposed on semiconductor layer 42a. In other words, diode 212a can be a "vertical diode."

[0122] Diode 212b includes ohmic contact 30ob, semiconductor layer 42b, semiconductor layer 47b, and ohmic contact 60ob. Semiconductor layer 47b is disposed on ohmic contact 30ob, semiconductor layer 42b is disposed on semiconductor layer 47b, and ohmic contact 60ob is disposed on semiconductor layer 42b. In other words, diode 212b can be a "vertical diode."

[0123] like Figure 11E As shown, memory cell components 70a and 70b can be formed (step (i)). In this embodiment, memory cell components 70a and 70b can each include a phase change material or a resistance variable material. A second conductive metal layer 80 can also be formed (step (f)). The details and formation methods of memory cell components 70a and 70b and second conductive metal layer 80 can be similar to those described above in conjunction with Figure 1H The details and formation methods are described, and the related description is omitted for the sake of brevity. In this way, storage units 304a and 304b are provided. Figure 11E The storage units 304a and 304b shown may be similar to those described above in conjunction with Figure 8D In the memory cells 303a and 303b, like reference numerals denote like elements. In this embodiment, the memory cell 304a includes a diode 212a and a memory cell component 70a, and the memory cell 304b includes a diode 212b and a memory cell component 70b.

[0124] 12A to 12C is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0125] like Figure 12A As shown, a second substrate 40 is provided (step (b1)), and a hydrogen layer 41 may be implanted into the second substrate 40 (step (b2)). Figure 12A The semiconductor structure shown can be similar to Figure 11A The semiconductor structure is shown in FIG. 1 , wherein like reference numerals denote like elements. In this embodiment, a second heavily doped layer 45' may be formed at a desired depth from the top surface of the second substrate 40, for example, by ion implantation. The details of the second heavily doped layer 45' described above may apply here.

[0126] like Figure 12B As shown, a second structure 106B is provided (step (b)). Figure 12B The second structure 106B shown can be substantially similar to the above-mentioned Figure 11B In the second structure 105B, like reference numerals denote like elements. In this embodiment, the second substrate 40 further includes a second heavily doped layer 45'.

[0127] like Figure 12C As shown, a first structure is provided (step (a)), wherein the first structure includes a first substrate 10, which is similar to the first substrate 10 described above. Figure 1C and flipping the second structure 106B over and bonding it to the first structure via the bonding layer 20 (step (c)). The bonding process and related details described above can be applied here.

[0128] Then, a portion of the second substrate 40 is removed from the substantially implanted hydrogen layer 41 to form the first semiconductor layer 42 (step (d)). The removal process and related details described above can be applied here. In this embodiment, after removing a portion of the second substrate 40 and flattening the exposed surface, the second heavily doped layer 45 is exposed. Figure 11E The semiconductor structures similar to the diodes 212a and 212b and the memory cells 304a and 304b can be combined with the above Figure 11E The process similar to the process described above Figure 12C The structure shown is formed.

[0129] Figures 13A to 13G is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0130] like Figure 13A As shown, a second substrate 40 is provided (step (b1)). In this embodiment, the second substrate 40 includes a patterned first opposite-type doped layer, the patterned first opposite-type doped layer including a first opposite-type doped region 47I extending from the top surface of the second substrate 40. The patterned first opposite-type doped layer may include a patterned heavily doped layer, the patterned heavily doped layer including a heavily doped region 49I extending from the top surface of the second substrate 40. If applicable, the relevant details of the second substrate 40, the first opposite-type doped layer 47, and the heavily doped layer 49 described above may apply here.

[0131] In some embodiments, the second substrate 40 may further include a patterned first heavily doped layer including a heavily doped region 44b extending from the top surface of the second substrate 40. Figure 6A The details related to the heavily doped region 44 a described above may apply here.

[0132] like Figure 13B As shown, a hydrogen layer 41 may be implanted into the second substrate 40 (step (b2)). The details previously described regarding the implanted hydrogen layer 41 may apply here.

[0133] like Figure 13C As shown, a first device metal layer 30 is formed on the second substrate 40 (step (b3)). Figure 13CIn the illustrated embodiment, the first device metal layer 30 includes ohmic contacts 30oa and 30ob. Ohmic contact 30oa can be formed to contact the first oppositely doped region 47I and the heavily doped region 49I, and ohmic contact 30ob can be formed to contact the heavily doped region 44b. A first conductive metal layer 50' can be formed on the ohmic contacts 30oa and 30ob. In this way, a second structure 107B is provided (step (b)). The details related to the first device metal layer 30 and the first conductive metal layer 50' described above can be applied here.

[0134] like Figure 13D As shown, a first structure is provided (step (a)), wherein the first structure includes a first substrate 10, which is similar to the first substrate 10 described above. Figure 1C The first substrate is then flipped over and bonded to the first structure via the bonding layer 20 (step (c)). The bonding process and related details described above can be applied here. Then, a portion of the second substrate 40 is removed from the substantially implanted hydrogen layer 41 to form the first semiconductor layer 42 (step (d)). The removal process and related details described above can be applied here.

[0135] like Figure 13E As shown, a second opposite type doped layer is formed (step (j2)). The second opposite type doped layer is a second conductivity type opposite to the first conductivity type. The second opposite type doped layer can be a patterned layer and can include a second opposite type doped region 47II extending from the exposed surface of the first semiconductor layer 42. The second opposite type doped layer can be formed after removing a portion of the second substrate 40. The second opposite type doped layer can be similar to the first opposite type doped layer and can be formed by a similar method as described above. The patterned second opposite type doped layer may include a patterned heavily doped layer, which includes a heavily doped region 49II extending from the exposed surface of the first semiconductor layer 42.

[0136] In some embodiments, a patterned second heavily doped layer may be formed, the patterned second heavily doped layer including heavily doped regions 45a extending from the exposed surface of the first semiconductor layer 42. Figure 6E The details related to the heavily doped region 45b described above may apply here.

[0137] like Figure 13F As shown, the first semiconductor layer 42 is patterned to form a plurality of semiconductor layers 42a and 42b and a plurality of semiconductor layers 47a and 47b (step (e)). A second device metal layer 60 is formed (step (f)). In this embodiment, the second device metal layer 60 includes a plurality of ohmic contacts 60oa and 60ob. Figure 13FThe semiconductor structure shown can be combined with the above Figure 8C The above-mentioned process is similar to the process of forming the above-mentioned process. If applicable, the above-mentioned relevant details can be applied here.

[0138] refer to Figure 13F , diodes 211 and 212 are provided. Figure 13F The diode 211 shown may be substantially similar to the diode 211 described above in conjunction with Figure 8C The diodes 211a and 211b are described, wherein like reference numerals indicate like elements. Figure 13F The diode 212 shown may be substantially similar to the diode 212 described above in conjunction with Figure 11E The diodes 212a and 212b are described, wherein like reference numerals indicate like elements. If applicable, the relevant details described above may apply here.

[0139] In this embodiment, the vertical diodes 211 and 212 manufactured under the same set of processes are formed to be arranged in opposite directions. This configuration can simplify wiring and reduce the thickness of the entire semiconductor device.

[0140] like Figure 13G As shown, a storage unit assembly 70 can be formed (step (i)). The storage unit assembly 70 can be similar to the above combined Figure 3 The storage unit components in question. Figure 13G In the illustrated embodiment, third wiring layer 82 may be formed such that ohmic contact 60oa of diode 212 is electrically coupled to ohmic contact 60ob of diode 211 via conductive features of third wiring layer 82. Second wiring layer 84 may also be formed after memory cell assembly 70 is formed.

[0141] refer to Figure 13G , a storage unit 314 is provided. Figure 13G The storage unit 314 shown can be substantially similar to the above-mentioned Figure 6G Memory cell 312 is described, wherein like reference numerals designate like elements. In this embodiment, memory cell 314 includes diodes 211 and 212 and memory cell assembly 70. Memory cell assembly 70 is electrically coupled from a first end thereof to both ohmic contact 60oa of diode 212 and ohmic contact 60ob of diode 211, and is electrically coupled from a second end thereof to second wiring layer 84. Figure 13G The illustrated memory cell 314 may be a spin-transfer torque MRAM (STT-MRAM) cell, and the first wiring layer 50' and the second wiring layer 84 may serve as bit lines and / or word lines for the memory cell. Figure 13GOnly two diodes and one memory cell are illustrated in FIG, but a plurality of diodes and a plurality of memory cells or an array of diodes and memory cells can be fabricated simultaneously using the method disclosed herein.

[0142] Figure 14 FIG is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. Figure 14 As shown, memory cells 322a and 322b are provided. Memory cells 322a and 322b or similar semiconductor structures can be combined with the present invention. Figures 13A to 13G The process is similar to the process described above. Figure 14 The storage units 322a and 322b shown may be substantially similar to those described above in conjunction with Figure 7 The storage units 321a and 321b are described, wherein like reference numerals indicate like elements. If applicable, the relevant details of the storage units 321a and 321b described above may be applied here.

[0143] Specifically, in this embodiment, the memory cell 322a includes a first pair of diodes 211-1a and 212-1a, a second pair of diodes 211-2a and 212-2a, an electrode 82a, and a memory cell component 70a; the memory cell 322b includes a first pair of diodes 211-1b and 212-1b, a second pair of diodes 211-2b and 212-2b, an electrode 82b, and a memory cell component 70b. The diodes 211-1a, 211-2a, 211-1b, and 211-2b can be substantially similar to the above-mentioned combination. Figure 8C The diodes 211a and 211b; diodes 212-1a, 212-2a, 212-1b and 212-2b can be substantially similar to the above combination Figure 11E Diodes 212a and 212b are described, wherein like reference numerals indicate like elements.

[0144] refer to Figure 14 , diodes 211-1a and 212-1a are both electrically coupled to electrode 82a on a first side of memory cell assembly 70a, and diodes 211-2a and 212-2a are both electrically coupled to electrode 82a on a second side of memory cell assembly 70a. Similarly, diodes 211-1b and 212-1b are both electrically coupled to electrode 82b on a first side of memory cell assembly 70b, and diodes 211-2b and 212-2b are both electrically coupled to electrode 82b on a second side of memory cell assembly 70b.

[0145] Figure 14 Each of the illustrated memory cells 322a and 322b may be a SOT-MRAM cell, and the first wiring layer 50' and the second wiring layer 84 may serve as bit lines and / or word lines for these memory cells. Figure 14 As shown, each of the memory cells 322a and 322b may have a cell size of 8F and 2F in the first direction 102a and the second direction 102b, respectively, which provides a 16-characteristic square (F 2 ) of the unit size. Although Figure 14 Only two memory cells are shown in FIG, but multiple memory cells or cell arrays can be fabricated simultaneously using the methods disclosed herein.

[0146] The foregoing description of the embodiments is provided to enable those skilled in the art to make and use the subject matter. Various modifications to these embodiments will be apparent to those skilled in the art, and the novel principles and subject matter disclosed herein may be applied to other embodiments without inventive effort. The subject matter claimed for protection set forth in the claims is not intended to be limited to the embodiments shown herein, but rather should be given the widest scope consistent with the principles and novel features disclosed herein. Additional embodiments are contemplated to be within the spirit and true scope of the disclosed subject matter. Therefore, it is intended that the present invention covers modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor structure, comprising: (a) providing a first structure, wherein the first structure comprises a first substrate; (b) providing a second structure comprising a second substrate and a first device metal layer on and in contact with the second substrate, wherein the second substrate comprises a single crystalline semiconductor material and an implanted hydrogen layer; (c) bonding the first structure and the second structure via a bonding layer to form a bonded structure; (d) removing a portion of the second substrate substantially from the implanted hydrogen layer to form a first semiconductor layer; (e) patterning the first semiconductor layer; and (f) forming at least one of a second device metal layer and a second conductive metal layer.

2. The method according to claim 1, wherein The second structure further includes a first conductive metal layer, and wherein the first device metal layer is disposed between the first conductive metal layer and the second substrate.

3. The method according to claim 1, wherein The step (b) comprises: (b1) providing the second substrate; (b2) implanting the hydrogen layer into the second substrate; and (b3) Forming the first device metal layer on the second substrate.

4. The method according to claim 1, wherein The step (c) includes forming a first dielectric layer on the first substrate and forming a second dielectric layer on the first device metal layer before bonding.

5. The method according to claim 1, wherein The first substrate includes single crystal semiconductor material, polycrystalline semiconductor material, glass or ceramic.

6. The method of claim 1, wherein: The first device metal layer includes a Schottky material layer.

7. The method of claim 1, wherein: The first device metal layer includes a plurality of Schottky contacts.

8. The method of claim 1, wherein: The first device metal layer includes an ohmic material layer.

9. The method of claim 1, wherein: The first device metal layer includes a plurality of ohmic contacts.

10. The method of claim 1, wherein: The first device metal layer includes any one of a patterned ohmic material layer and an ohmic contact, and a patterned Schottky material layer.

11. The method of claim 1, wherein: The first device metal layer includes any one of a patterned Schottky material layer and a Schottky contact, and a patterned ohmic material layer.

12. The method of claim 1, wherein: The step (f) includes forming the second device metal layer, wherein the second device metal layer includes a plurality of Schottky contacts.

13. The method of claim 1, wherein: The step (f) includes forming the second device metal layer, wherein the second device metal layer includes a plurality of ohmic contacts.

14. The method of claim 1, wherein: The step (f) includes forming the second device metal layer, wherein the second device metal layer includes a plurality of Schottky contacts and a plurality of ohmic contacts.

15. The method of claim 1, wherein: The first semiconductor layer is of a first conductivity type.

16. The method of claim 1, wherein: In the step (b), the second substrate further includes a first heavily doped layer in contact with the first device metal layer.

17. The method of claim 16, wherein: The first heavily doped layer is patterned.

18. The method of claim 16, wherein: The first heavily doped layer is of a first conductivity type.

19. The method of claim 1, further comprising the following step after step (d): (h) forming a second heavily doped layer in or on the first semiconductor layer.

20. The method of claim 19, wherein: The second heavily doped layer is patterned.

21. The method of claim 19, wherein: The second heavily doped layer is of the first conductivity type.

22. The method of claim 1, wherein: In the step (b), the second substrate further includes a second heavily doped layer, and the second heavily doped layer is exposed after the step (d).

23. The method of claim 1, further comprising the following step after step (d): (i) Forming a memory cell assembly.

24. The method of claim 1, further comprising the following step after step (d): (j1) Forming a second semiconductor layer on the exposed surface of the first semiconductor layer.

25. The method of claim 24, wherein: The second semiconductor layer has a second conductivity type opposite to the first conductivity type.

26. The method of claim 24, wherein: The step (e) further includes patterning the second semiconductor layer.

27. The method of claim 1, further comprising the following step after step (d): (j2) forming a second opposite-type doped layer extending from the exposed surface of the first semiconductor layer.

28. The method of claim 27, wherein: The second opposite-type doped layer has a second conductivity type opposite to the first conductivity type.

29. The method of claim 27, wherein: The second opposite-type doped layer is patterned.

30. The method of claim 1, wherein: In the step (b), the second substrate further includes a first opposite type doping layer in contact with the first device metal layer.

31. The method of claim 30, wherein: The first opposite-type doped layer has a second conductivity type opposite to the first conductivity type.

32. The method of claim 30, wherein: The first opposite-type doped layer is patterned.

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