High-gain and low-offset class AB amplifier circuit

Abstract

An amplifier circuit includes: a first folded dual cascode stage configured to receive a differential input signal at a first pair of input transistors and generate a first drive signal; a second folded dual cascode stage configured to receive the differential input signal at a second pair of input transistors and generate a second drive signal; and an output stage. The output stage includes a PMOS common source output transistor configured to receive the first drive signal at a gate thereof, and an NMOS common source output transistor configured to receive the first drive signal at a gate thereof, the PMOS common source output transistor and the NMOS common source output transistor are collectively configured to generate an output signal based on the first drive signal and the second drive signal.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority to U.S. Provisional Application Serial No. 63 / 448,469, filed on February 27, 2023, and U.S. Patent Application Serial No. 18 / 427,535, filed on January 30, 2024, each of which is incorporated herein by reference in its entirety. Background Art

[0003] Amplifiers are commonly used in a range of applications. Class AB amplifiers combine the characteristics of Class A amplifiers, such as low distortion of the input waveform during amplification, with the characteristics of Class B amplifiers, such as high amplification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In the drawings, which are not necessarily drawn to scale, similar reference numerals may describe similar components in different views. To easily identify the discussion of any particular element or action, the most significant digit or digits in a reference numeral refer to the figure in which the element is first introduced. Some non-limiting examples are shown in the figures of the accompanying drawings, in which:

[0005] Figure 1 is a circuit diagram illustrating an example amplifier circuit according to at least one example.

[0006] Figure 2 yes Figure 1 Circuit diagram of the left bias block of the amplifier circuit.

[0007] Figure 3 yes Figure 1 Circuit diagram of the right bias block of the amplifier circuit.

[0008] Figure 4 yes Figure 1 Circuit diagram of the first folded dual-cascode stage of the amplifier circuit.

[0009] Figure 5 yes Figure 1 Circuit diagram of the second folded dual cascode stage of the amplifier circuit.

[0010] Figure 6 yes Figure 1 Circuit diagram of the output stage of the amplifier circuit.

[0011] Figure 7 A method 700 of amplifying a differential input signal is shown according to at least one example. DETAILED DESCRIPTION

[0012] Examples of the present disclosure provide a high voltage gain, low input offset voltage, Class AB amplifier that can be used in a variety of applications, including driving capacitive loads.

[0013] The examples described herein may attempt to solve one or more technical problems. Some examples provide high voltage gain amplifiers, such as amplifiers with a voltage amplification greater than 200,000 (Av>200,000). Some examples provide low input offset voltage amplifiers, such as amplifiers with an input offset voltage less than 100 microvolts (<100μV) or, in some examples, approximately 50μV. Some examples provide amplifiers with class AB output stages, thereby providing output stages with low bias current (e.g., between 15μA and 150μA, such as approximately 50μA) and high peak current capability (e.g., between 30mA and 300mA, such as approximately 100mA) as needed. Some examples provide amplifiers with an equal number of gain stages for positive and negative output signals, thereby providing approximately equal high gain for both positive and negative signal swings. Some examples provide amplifiers with two high impedance nodes in the signal path, thereby facilitating easy and stable compensation and the ability to drive large capacitive loads. Some examples offer amplifiers with near rail-to-rail output voltage swings, such as V DD to ground or from the common-source output stage to V SS (For example, rail-to-rail output voltage swing is within 100 mV for large load currents, or within 10 mV for small load currents, and in some examples within approximately 50 mV).

[0014] As used herein, the term "input offset voltage" refers to the deterministic input offset voltage resulting from low voltage gain and imbalance, rather than the random mismatch that can be inherent to transistors. Random mismatch typically increases the magnitude of an amplifier's total input offset voltage. In some examples described herein, amplifier circuits are provided that avoid significantly increasing the total input offset voltage due to low voltage gain and imbalance.

[0015] Depending on the common-mode input voltage requirements, the example amplifiers described herein can be implemented with either an NMOS input stage or a PMOS input stage. The NMOS input stage common-mode range can be close to the positive supply voltage, while the PMOS input stage common-mode range can be close to the ground potential (e.g., 0V). In some examples, these requirements can be achieved by including two separate, precisely biased, double-folded cascode input stages to enhance or increase the voltage gain before the common-source output stage (driven by an NMOS output transistor and a PMOS output transistor). The DC voltages at the gates of the output transistors may be inherently different or unbalanced, resulting in large input offset voltages and drift when the gain of the first stage is not high enough. For class AB control of the output stage, a translinear harmonic average regulation feedback loop may be employed in some examples.

[0016] The example amplifiers described herein may be suitable for use in the context of integrated circuits (ICs), and in particular in the context of complementary metal oxide semiconductor (CMOS) ICs. However, some of the examples described herein may be implemented outside the context of CMOS ICs, for example in silicon or non-silicon bipolar technologies, gallium arsenide (GaAs) semiconductors, gallium nitride (GaN) semiconductors, indium gallium phosphide (InGaP) semiconductors, or other suitable technologies.

[0017] Figure 1 The example amplifier circuit 100 is shown as a block diagram. The amplifier circuit 100 includes several different functional blocks: a left bias block 200, a first folded dual cascode stage 400, a second folded dual cascode stage 500, a right bias block 300, and an output stage 600. Figures 2 to 6 The circuit diagrams of the example functional blocks shown in FIG. 1 describe each of the functional blocks 200 , 400 , 500 , 300 , 600 shown in greater detail.

[0018] In some examples, the first folded dual cascode stage 400 and the second folded dual cascode stage 500 are identical or nearly identical P-type metal oxide semiconductor (PMOS) input folded dual cascode stages. Each folded dual cascode stage 400, 500 is coupled to a corresponding output transistor of an output stage 600. Thus, each folded dual cascode stage 400, 500 is configured to enhance or increase voltage gain prior to a common source output stage driven by an n-channel metal oxide semiconductor (NMOS) output transistor and a PMOS output transistor. Examples of output stages and output transistors are described below with reference to the example output stage 600. In some examples, the output stage 600 includes an NMOS common source transistor and a PMOS common source transistor coupled to a translinear harmonic average class AB regulation loop.

[0019] Figure 2An example left bias block 200 of the amplifier circuit 100 is shown.

[0020] In some examples, the bias is established using a PTAT (Proportional to Absolute Temperature) current feed consisting of a delta V typically used to implement a bandgap reference voltage. BE The PTAT current is fed and / or copied to the resistors (e.g., lower resistors R12 224, R7 226, R5 228, R4 230 and upper resistors R6 238, R8 236, R35 234, R37 232, R30 242) and is fed back (by setting V GS ) establishes a drain current to produce the desired bias voltage for the current source 216, the current source 218, and the cascode transistors of the first folded dual cascode stage 400 and the second folded dual cascode stage 500. This will bias the common-gate (cascode) transistors (e.g., Figure 4 Transistors N17, N18 and P45, P47 and Figure 5 transistors N30, N31 and P36, P38 in ) and bias (common source / current source) transistors (e.g., Figure 4 Transistors N6, N7 and P50, P51 and Figure 5 V of transistors N28, N29 and P40, P41) DS (drain to source voltage) to establish a PTAT, and accurately set their voltage to approximately between 4 and 5 thermal voltages (e.g., ), thereby ensuring that the transistors are saturated in weak inversion (high gain), and ensuring that V DS Keep above 4 thermovolts to 5 thermovolts.

[0021] The example left bias block 200 shown includes a first voltage source 214. The left bias block 200 shares several nodes with one or more other stages of the amplifier circuit 100, including nodes V4p5 208 (which is separated from ground 240 by the first voltage source 214 and thus corresponds to a positive voltage supply in the example shown), Vp1 212, Vp2 202, Vp3 206, Vn1 608 ( Figure 6 As shown in ), Vn2 222, V SS 204 and Vn3 210. In some examples, V SS 204 is connected to ground 240 .

[0022] Figure 3An example right bias block 300 of the amplifier circuit 100 is shown. The example right bias block 300 shown shares several nodes with one or more other stages of the amplifier circuit 100, including nodes V4p5 208, Vp2x 304, Vp3x 302, Vn1 608, Vn2 222, and V SS 204.

[0023] Figure 4 An example first folded dual cascode stage 400 is shown. The first folded dual cascode stage 400 is configured to receive a differential input signal (Vin+ 404 and Vin- 406) at a first pair of input transistors 408a, 408b (shown as a pair of PMOS transistors in the example shown) and generate a first drive signal Vogp 402 based on the differential input signal. As described below, the first drive signal Vogp 402 is used to drive the output transistors of the output stage 600.

[0024] In some examples, the approximate voltage gain of the dual-cascode folded-input stage shown is about 200,000: In some examples, the approximate voltage gain of the illustrated dual cascode folded input stage is greater than 200,000, such as approximately 400,000 or 500,000. Some examples may achieve a gain less than 200,000, but this may reduce the effectiveness of the design in some cases. In some examples, the first folded dual cascode stage 400 and the second folded dual cascode stage 500 ( Figure 5 The output of the ) has a dual cascode current mirror load, which drives the output stage 600 ( Figure 6 The gates of the two output transistors (shown in FIG) and represent the first high impedance nodes in their respective paths, as described below with reference to Figure 6 Descriptive.

[0025] The illustrated example first folded dual cascode stage 400 shares several nodes with one or more other stages of the amplifier circuit 100, including nodes V4p5 208, Vp1 212, Vp2 202, Vp3 206, Vn3 210, Vn1 608 ( Figure 6 ), Vn2 222, V SS 204 , a differential input signal (Vin+ 404 and Vin− 406 ) and a first drive signal Vogp 402 .

[0026] Figure 5An example second folded dual cascode stage 500 is shown. The example second folded dual cascode stage 500 is substantially similar to the first folded dual cascode stage 400, but is configured to receive a differential input signal (Vin+ 404 and Vin- 406) at a second pair of input transistors 504a, 504b (shown as a pair of PMOS transistors in the example shown) and to generate a second drive signal Vogn 502 based on the differential input signal. As described below, the second drive signal Vogn 502 is used to drive separate, different output transistors of the output stage 600.

[0027] In some examples, the first folded dual cascode stage 400 and the second folded dual cascode stage 500 (when combined with the NMOS common-source output transistor 618 and the PMOS common-source output transistor 620 of the output stage 700 as described below) together implement an equal number of gain stages for positive and negative output signals.

[0028] The illustrated example second folded dual cascode stage 500 shares several nodes with one or more other stages of the amplifier circuit 100 , including nodes V4p5 208 , Vp1 212 , Vp2 202 , Vp3 206 , Vn3 210 , Vn1 608 , Vn2 222 , the differential input signals (Vin+ 404 and Vin− 406 ), and the second drive signal Vogn 502 .

[0029] It should be understood that the various transistors shown as PMOS transistors and NMOS transistors in the dual cascode stage 400, dual cascode stage 500 may be reversed in some examples (i.e., all PMOS transistors are replaced with NMOS transistors, and all NMOS transistors are replaced with PMOS transistors), with different common-mode input voltage ranges. For example, although the illustrated example uses PMOS input transistors for the input transistors 408a, 408b ( Figure 4 ), 504a, 504b, but in some examples, NMOS input transistors may be used with corresponding modifications to the other transistors of the dual cascode stage 400, dual cascode stage 500.

[0030] Figure 6 An example output stage 600 is shown. The output stage 600 shown includes a PMOS common-source output transistor 620 driven by a first drive signal Vogp 402 and an NMOS common-source output transistor 618 driven by a second drive signal Vogn 502. The PMOS common-source output transistor 620 and the NMOS common-source output transistor 618 together form a push-pull output stage configured to generate an output signal at a node Vo 602.

[0031] In some examples, the output stage 600 is compensated with one or more zero-setting resistors (shown as a first zero-setting resistor 604 and a second zero-setting resistor 606) in series with one or more pole-splitting capacitors (shown as a first pole-splitting capacitor 610 and a second pole-splitting capacitor 612) for performing Miller compensation. In some examples, a relatively small output resistor 614 is also included for driving a large capacitive load of a load capacitor (not shown), such as a load capacitor having a capacitance between 100 pF and 100 μF. The output resistor 614 forms a zero together with the load capacitor. In some examples, the output resistor 614 can have a value in the range of 0.1 ohm to 1 ohm for a load capacitance of 0.1 μF to 100 μF, and can have a value in the range of 10 ohms to 1000 ohms for a load capacitance of 100 pF to 10 nF.

[0032] In some examples, the output stage 600 also includes a global feedback loop 616. The global feedback loop 616 sets the closed-loop gain for the amplifier. It should be understood that in different examples, the example global feedback loop 616 shown can be replaced with a different feedback network.

[0033] In some examples, the output stage 600 includes a translinear class AB regulation loop, such as a translinear harmonic averaging regulation loop, which may include: a reference voltage generated by P69 630, N61 628, and bias / drain currents from N59 638 and N66 640; sense transistors P61 (i.e., PMOS common-source output transistor 620) and N54 (i.e., NMOS common-source output transistor 618) / N64 642 / P70 632; transistors N63 634 and N62 636, and control (high gain) amplifiers P75, P74 (cascode formed by P77, P78, P81, P82, collectively forming 644) and control amplifiers P71, P72 (cascode formed by P79, P80, P83, P84, collectively forming 646) in conjunction with the two dual folded cascode stages 400, 500. In some examples, the translinear class AB regulation loop provides a regulation amplifier that makes VCL 648 substantially equal to Vp2x 304.

[0034] A first path through the amplifier circuit 100 is defined as from the differential input signal (Vin+ 404 and Vin- 406), through the first pair of input transistors 408a of the first folded dual cascode stage 400, to the first drive signal Vogp 402, through the PMOS common-source output transistor 620, to the output signal at node Vo 602. A second path through the amplifier circuit 100 is defined as from the differential input signal (Vin+ 404 and Vin- 406), through the second pair of input transistors 504a of the second folded dual cascode stage 500, to the second drive signal Vogn 502, through the NMOS common-source output transistor 618, to the output signal at node Vo 602.

[0035] In some examples, the first high impedance node in each of the two paths is the driving signal: Vogn 502 for the first path and Vogp 402 for the second path. The second high impedance node in each path is the output node Vo 602. In some examples, the two high impedance nodes each have a higher impedance than any other node in their respective paths.

[0036] In some examples, first pole-splitting capacitor 610 and second pole-splitting capacitor 612 each have a capacitance of approximately 1 picofarad (pF), and first zero-setting resistor 604 and second zero-setting resistor 606 each have a resistance of approximately 10 kilo-ohms (kΩ). In some examples, these values ​​can be different, and / or the pole-splitting capacitors and / or zero-setting resistors can be omitted.

[0037] In some examples, as described above, when VCL 648 is set equal to Vp2x 304 , the following set of equations characterizes the voltages and currents present in the output stage 600 .

[0038] The voltage from source to gate of transistor P69 630 (V SG ) plus the gate-to-source voltage of transistor N61 628 (V GS ) is equal to the bias voltage V between nodes V4p5 208 and Vp2x 304 bias .

[0039] At a given temperature and process implementation, current Id61 622 times (x) times current Id58 626 = current Id54 624 times (1-x) times current Id58 626 = C1.

[0040] Given x = 0.5, current Id61 622 = current Id54 624 = 2C1 divided by current Id58 626 = bias current I bias .

[0041] As current Id61 622 increases, x approaches zero, and current Id54 624 approaches C1 divided by current Id58 626 = I bias Divide by 2.

[0042] As current Id54 624 increases, x approaches 1, and current Id61 622 approaches C1 divided by current Id58 626 = I bias Divide by 2.

[0043] Transistor P70 632 V SG + V of transistor N63 634 GS = V of PMOS common-source output transistor P61 620 SG + V of transistor N62 636 GS = V of transistor P69 630 SG + Transistor N61 628 V GS =V bias .

[0044] The use of dual cascode stages 400, 500 may require precise, accurate biasing to be set by left bias block 200 and / or right bias block 300. As described in further detail below, in some examples the biasing is preferably PTAT in order to keep the cascode transistors in saturation while also using a low offset voltage. For example, in some examples, across Figure 4 The voltage across V4p5 208 to Vogp 402 can be as little as 400 mV. Figure 5 The transistors N32+N30+N28 shown in FIG. SS The voltage from 204 to Vogn 502 can be as small as 400mV. Otherwise, the V DS It may become so small (eg, less than 100 mV) that the transistor becomes unsaturated (in the triode region or near the knee voltage), thereby reducing the voltage gain of the amplifier (eg, by reducing the output resistance of the transistor).

[0045] It will be appreciated that in the example shown, V4p5 208 corresponds to the positive voltage supply, Vo 602 corresponds to the output signal, and V SS 204 corresponds to the negative voltage supply. The PMOS common source output transistor 620 and the NMOS common source output transistor 618 are connected to the positive voltage supply V4p5 208 and the negative voltage supply V SS A push-pull output stage is implemented between 204 to generate an output signal Vo 602 .

[0046] Figure 7 Operations of a method 700 for amplifying a differential input signal using an amplifier circuit 100 as described herein are shown. At operation 702, the amplifier circuit 100 receives a differential input signal (Vin+ 404, Vin- 406) at a first pair of input transistors 408a, 408b of a first folded dual cascode stage 400. At operation 704, the amplifier circuit 100 generates a first drive signal (e.g., Vogp 402) at the first folded dual cascode stage 400 based on the differential input signal. At operation 706, the amplifier circuit 100 receives a differential input signal at a second pair of input transistors 504a, 504b of a second folded dual cascode stage 500. At operation 708, the method 700 generates a second drive signal (e.g., Vogn 502) at the second folded dual cascode stage 500 based on the differential input signal. At operation 710, the amplifier circuit 100 receives the first drive signal Vogp 402 at the gate of the NMOS common-source output transistor 618 of the output stage 600. At operation 712, the amplifier circuit 100 receives the second drive signal Vogn 502 at the gate of the PMOS common-source output transistor 620 of the output stage 600. At operation 714, the amplifier circuit 100 generates an output signal Vo 602 at the output stage 600 based on the first drive signal Vogp 402 and the second drive signal Vogn 502.

[0047] The examples described herein can solve one or more technical problems, including but not limited to those identified herein. First, the amplifier circuit 100 can provide a high voltage gain amplifier, such as an amplifier having a voltage amplification greater than 200,000 (Av>200,000). Second, the amplifier circuit 100 can provide a low input offset voltage amplifier, such as an amplifier having an input offset voltage less than 100 microvolts (<100μV). Third, the class AB output stage 600 can provide an output stage with low bias current and large peak current capability as needed. Fourth, the amplifier circuit 100 can provide an equal number of gain stages for positive and negative output signals, thereby providing approximately equal high gain for positive and negative signal swings. Fifth, the amplifier circuit 100 can provide an amplifier with two high impedance nodes in the signal path, thereby facilitating easy, stable compensation and the ability to drive large capacitive loads. Sixth, the amplifier circuit 100 can provide an amplifier with an approximately (e.g., at least 90%) rail-to-rail output voltage swing, such as V DD To ground or V SSto a common-source output stage. In some examples, amplifier circuit 100 can achieve an input offset voltage of approximately 50 μV and a voltage gain of >1,000,000 with a high impedance load. In some such examples, to achieve an input offset voltage of 100 μV over temperature variations (e.g., 0°C to 85°C) and process and power supply variations, the input offset voltage needs to be initially below 100 μV.

[0048] Thus, in a first example, an amplifier circuit is provided that includes a first folded dual cascode stage configured to receive a differential input signal at a first pair of input transistors and generate a first drive signal. The amplifier circuit also includes a second folded dual cascode stage configured to receive a differential input signal at a second pair of input transistors and generate a second drive signal. The amplifier circuit also includes an output stage that includes a PMOS common-source output transistor and an NMOS common-source output transistor, the PMOS common-source output transistor being configured to receive the first drive signal at its gate, the NMOS common-source output transistor being configured to receive the first drive signal at its gate, the PMOS common-source output transistor and the NMOS common-source output transistor being collectively configured to generate an output signal based on the first drive signal and the second drive signal.

[0049] In a second example including features of the first example, the amplifier circuit may further include at least one bias stage configured to apply a bias voltage to one or more transistors of each of the first and second folded dual cascode stages.

[0050] In a third example including features of the first example and may include features of the second example, the amplifier circuit may further include, wherein the output stage further includes a translinear class AB regulation loop.

[0051] In a fourth example, which includes features of the first example and may include features of the second example and / or the third example, the amplifier circuit may further include, wherein the first folded dual cascode stage and the second folded dual cascode stage are operable to apply a voltage gain greater than 180,000 to the differential input signal to generate the first drive signal and the second drive signal.

[0052] In a fifth example including features of the first example and optionally including features of one or more of the second to fourth examples, the first drive signal and the second drive signal include a dual cascode current mirror load.

[0053] In a sixth example including features of the first example and may include features of one or more of the second to fifth examples, the amplifier circuit may further include, wherein the first drive signal and the output signal respectively include a first high impedance node and a second high impedance node of the first path, the first high impedance node and the second high impedance node having a higher impedance than any other node in the first path, and the second drive signal and the output signal respectively include a first high impedance node and a second high impedance node of the second path, the first high impedance node and the second high impedance node having a higher impedance than any other node in the second path.

[0054] In a seventh example that includes features of the first example and may include features of one or more of the second to sixth examples, the amplifier circuit may further include, wherein the output stage also includes one or more pole-splitting capacitors configured to perform Miller compensation, and one or more zero-setting resistors connected in series with the one or more pole-splitting capacitors.

[0055] In an eighth example including features of the first example and may include features of one or more of the second to seventh examples, the amplifier circuit may further include, wherein the amplifier circuit amplifies a voltage greater than 200,000 applied to a differential input signal to generate an output signal.

[0056] In a ninth example including features of the first example and may include features of one or more of the second to seventh examples, the amplifier circuit may further include, wherein the amplifier circuit has a deterministic input offset voltage of less than 100 microvolts.

[0057] In a tenth example including features of the first example and may include features of one or more of the second to seventh examples, the amplifier circuit may further include an output stage having low bias current and large peak current capability.

[0058] In an eleventh example including the features of the first example and including the features of one or more of the second to seventh examples, the amplifier circuit may further include, wherein the output voltage swing of the output signal is within V DD to within 100 mV of the rail-to-rail voltage to ground.

[0059] In a twelfth example including the features of the first example and including the features of one or more of the second to seventh examples, the amplifier circuit may further include, wherein the output voltage swing of the output signal is within V SS To within 100 millivolts of the rail-to-rail voltage of the common source output stage. Other technical features will be readily apparent to those skilled in the art from the accompanying drawings, description and claims.

[0060] In a thirteenth example including features of the first example and may include features of one or more of the second to seventh examples, the amplifier circuit may further include, wherein at least one bias stage is configured to be biased from delta V BE The circuit receives a proportional to absolute temperature (PTAT) current feed.

[0061] In a fourteenth example including features of the first example and may include features of one or more of the second to seventh examples, the amplifier circuit may further include, wherein the bias voltage is operable to establish a V between the 4th thermal voltage and the 5th thermal voltage for the one or more common-gate transistors and the one or more common-source transistors of the first folded dual cascode stage and the one or more common-gate transistors and the one or more common-source transistors of the second folded dual cascode stage. DS .

[0062] In a fifteenth example that includes features of the first example and may include features of one or more of the second to seventh examples, the amplifier circuit may further include, wherein the amplifier circuit includes an equal number of gain stages for positive output signals and negative output signals.

[0063] In a sixteenth example including features of the first example and may include features of one or more of the second to seventh examples, the amplifier circuit may further include, wherein the translinear class AB regulation loop includes a translinear harmonic averaging regulation loop.

[0064] In a seventeenth example that includes the features of the first example and may include the features of one or more of the second to seventh examples, the amplifier circuit may further include, wherein the amplifier circuit drives a capacitive load having a load capacitor with a capacitance between 100pF and 100μF, and the output stage also includes an output resistor that forms a zero point together with the load capacitor.

[0065] In an eighteenth example, a method for amplifying a differential input signal is provided, the method comprising: receiving the differential input signal at a first pair of input transistors of a first folded dual cascode stage, generating a first drive signal at the first folded dual cascode stage based on the differential input signal, receiving the differential input signal at a second pair of input transistors of a second folded dual cascode stage, generating a second drive signal at the second folded dual cascode stage based on the differential input signal, receiving the first drive signal at a gate of an NMOS common-source output transistor of an output stage, receiving the second drive signal at a gate of a PMOS common-source output transistor of the output stage, and generating an output signal at the output stage based on the first drive signal and the second drive signal.

[0066] In a nineteenth example including the features of the eighteenth example, the method may further include applying a bias voltage to one or more transistors of each of the first and second folded dual cascode stages using at least one bias stage.

[0067] In a twentieth example including the features of the eighteenth example and including the features of the nineteenth example, the method may further include: regulating the output stage using a translinear class AB regulation loop. Other technical features will be readily apparent to those skilled in the art from the accompanying drawings, description, and claims.

[0068] In the examples described above, the input and output terminals of the amplifier circuit include one or more transistors. For example, the input terminal may be the gate of one or more CMOS transistors, and the output terminal may be an inverting common terminal implemented as the source of the CMOS transistor. However, in other examples, the input terminal and / or the inverting common terminal may be implemented using other technologies, such as silicon or non-silicon bipolar technology or GaAs semiconductors, as described above.

Claims

1. An amplifier circuit comprising: a first folded dual cascode stage configured to receive a differential input signal at a first pair of input transistors and generate a first drive signal; a second folded dual cascode stage configured to receive the differential input signal at a second pair of input transistors and generate a second drive signal; as well as An output stage, the output stage comprising: a PMOS common-source output transistor configured to receive the first drive signal at a gate thereof; and an NMOS common-source output transistor configured to receive the second drive signal at a gate thereof; The PMOS common-source output transistor and the NMOS common-source output transistor are collectively configured to generate an output signal based on the first drive signal and the second drive signal.

2. The amplifier circuit according to claim 1 , further comprising: At least one bias stage is configured to apply a bias voltage to one or more transistors of each of the first and second folded dual cascode stages.

3. The amplifier circuit according to claim 2, wherein: The at least one bias stage is configured to BE The circuit receives at least one proportional to absolute temperature (PTAT) current feed.

4. The amplifier circuit according to claim 3, wherein: The bias voltage is operable to establish a V between 4 and 5 thermal voltages for the following DS : one or more common-gate transistors and one or more common-source transistors of the first folded dual-cascode stage; and One or more common-gate transistors and one or more common-source transistors of the second folded dual-cascode stage.

5. The amplifier circuit according to claim 2, further comprising: An equal number of gain stages are used for positive and negative output signals.

6. The amplifier circuit according to claim 1 , wherein: The output stage also includes a translinear class AB regulation loop.

7. The amplifier circuit according to claim 6, wherein: The translinear class AB regulation loop includes a translinear harmonic averaging regulation loop.

8. The amplifier circuit according to claim 1, wherein: The first and second folded dual cascode stages are operable to apply a voltage gain greater than 180,000 to the differential input signal to generate the first and second drive signals.

9. The amplifier circuit according to claim 1 , wherein: The first drive signal and the second drive signal include a dual cascode current mirror load.

10. The amplifier circuit according to claim 1, wherein: The first drive signal and the output signal respectively include a first high impedance node and a second high impedance node of a first path, the first high impedance node and the second high impedance node having a higher impedance than any other node in the first path; as well as The second drive signal and the output signal respectively include a first high impedance node and a second high impedance node of a second path, the first high impedance node and the second high impedance node having a higher impedance than any other node in the second path.

11. The amplifier circuit according to claim 1, wherein The output stage further comprises: one or more pole-splitting capacitors configured to perform Miller compensation; and One or more zero-setting resistors in series with the one or more pole-splitting capacitors.

12. The amplifier circuit according to claim 11, wherein: The amplifier circuit drives a capacitive load having a load capacitor having a capacitance between 100 pF and 100 μF; and The output stage also includes an output resistor that forms a zero point together with the load capacitor.

13. The amplifier circuit according to claim 1, wherein: The amplifier circuit applies a voltage amplification greater than 200,000 to the differential input signal to generate the output signal.

14. The amplifier circuit according to claim 1, wherein: The amplifier circuit has a deterministic input offset voltage of less than 100 microvolts.

15. The amplifier circuit according to claim 1, wherein The output stage has: a bias current between 15 microamperes and 150 microamperes; and Peak current capability between 30 mA and 300 mA.

16. The amplifier circuit of claim 1 , wherein: The output voltage swing of the output signal is V DD to within 100 mV of the rail-to-rail voltage to ground.

17. The amplifier circuit of claim 1, wherein: The output voltage swing of the output signal is V SS to within 100 mV of the rail-to-rail voltage of the output signal.

18. A method for amplifying a differential input signal, comprising: receiving the differential input signal at a first pair of input transistors of a first folded dual cascode stage; generating a first drive signal at the first folded dual cascode stage based on the differential input signal; receiving the differential input signal at a second pair of input transistors of a second folded dual cascode stage; generating a second drive signal at the second folded dual cascode stage based on the differential input signal; receiving the first drive signal at a gate of an NMOS common-source output transistor of an output stage; receiving the second drive signal at a gate of a PMOS common-source output transistor of the output stage; as well as An output signal is generated at the output stage based on the first drive signal and the second drive signal.

19. The method according to claim 18, further comprising: A bias voltage is applied to one or more transistors of each of the first and second folded dual cascode stages using at least one bias stage.

20. The method of claim 18, further comprising: The output stage is regulated using a translinear class AB regulation loop.

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