Imaging apparatus and imaging method

Abstract

The purpose of the present invention is to enable signals to be transmitted through a plurality of signal lines while suppressing crosstalk between signals read out from pixels adjacent to each other. An imaging device includes: pixels arranged in a matrix in a row direction and a column direction; and a plurality of signal lines configured to simultaneously transmit signals read out from pixels belonging to the same column and mutually different rows in the column direction. In at least one column, the signal lines and the pixels are connected such that an arrangement order of the signal lines and an arrangement order of the pixels are different from each other. The image pickup apparatus may include shield lines disposed between the plurality of signal lines. The shielded lines may be disposed between signal lines adjacent to each other connected to pixels of different colors.

Description

Technical Field

[0001] The present technology relates to an imaging device and an imaging method, and more particularly to an imaging device and an imaging method in which a plurality of signal lines are arranged in a row. Background Art

[0002] There are known imaging devices in which a plurality of pixels are arranged in a plurality of rows and columns. For example, an imaging device has been proposed in which shield wiring is provided between some of the plurality of signal lines and other of the plurality of signal lines are adjacent to each other (for example, see Patent Document 1). Reference List Patent Literature

[0003] Patent Document 1: JP 2019-102948 A Summary of the Invention Technical problem to be solved by the invention

[0004] However, in the above-described prior art, signals read out from adjacent pixels are simultaneously transmitted through adjacent signal lines, which may result in an increase in crosstalk between the signals read out from adjacent pixels.

[0005] The present technology has been proposed in view of such circumstances, and an object of the present technology is to enable transmission of signals through a plurality of signal lines while suppressing crosstalk between signals read out from pixels adjacent to each other. Technical solutions to technical problems

[0006] The present technology was developed to address the aforementioned issues. A first aspect of the present technology is an imaging device comprising: pixels arranged in a matrix in row and column directions; and a plurality of signal lines configured to simultaneously transmit signals read from pixels belonging to the same column but different rows in the column direction. In at least one column, the signal lines and pixels are connected such that the arrangement order of the signal lines differs from the arrangement order of the pixels. This configuration achieves the effect of simultaneously transmitting signals via the plurality of signal lines while suppressing crosstalk between signals read from adjacent pixels.

[0007] Furthermore, in the first aspect, the image pickup device may include a shield line provided between the signal lines. According to this configuration, an effect of suppressing crosstalk between signals transmitted through adjacent signal lines is achieved.

[0008] Furthermore, in the first aspect, the shield line may be provided between adjacent signal lines connected to pixels of different colors. According to this configuration, an effect of suppressing color mixing of signals transmitted through adjacent signal lines is achieved.

[0009] Furthermore, in the first aspect, at least one of the shielded wires may be connected to a ground potential. According to this configuration, an effect of stabilizing the shielding performance of the shielded wire is achieved.

[0010] Furthermore, in the first aspect, at least one of the shield lines may be connected to a power supply potential. According to this configuration, the shield line is arranged between the signal lines while suppressing restrictions on the layout of the power supply line.

[0011] Furthermore, in the first aspect, at least one of the shielded wires may be divided so that a portion connected to the power supply potential is sandwiched between portions connected to the ground potential. This configuration stabilizes the shielding performance of the shielded wire while suppressing restrictions on the layout of the power supply wire.

[0012] Furthermore, in the first aspect, the pixels may include pixels of different colors arranged alternately in the column direction. This configuration achieves an effect of suppressing color mixing of signals transmitted simultaneously through a plurality of signal lines while arranging pixels of different colors adjacent to each other in the column direction.

[0013] Furthermore, in the first aspect, pixels of the same color configured to be read simultaneously in each column can be connected to adjacent signal lines. This configuration achieves the effect of suppressing crosstalk between signals while simultaneously transmitting signals read from adjacent pixels via multiple signal lines.

[0014] Furthermore, in the first aspect, the plurality of signal lines may include: a first signal line connected to a first pixel; a second signal line connected to a second pixel adjacent to the first pixel in the column direction; and a third signal line connected to a third pixel and located between the first signal line and the second pixel. This configuration achieves an effect in which pixels adjacent to each other in the column direction are connected to signal lines that are not adjacent to each other.

[0015] Furthermore, in the first aspect, the pixels may include a first pixel, a second pixel, and a third pixel sequentially arranged in the column direction, the plurality of signal lines may include a first signal line, a second signal line, and a third signal line sequentially arranged in the row direction, the first pixel may be connected to the first signal line, the second pixel may be connected to the third signal line, and the third pixel may be connected to the second signal line. With this configuration, pixels adjacent to each other in the column direction are connected to signal lines that are not adjacent to each other.

[0016] Furthermore, in the first aspect, the first pixel and the third pixel may be pixels of the same color, and the first pixel and the second pixel may be pixels of different colors. This configuration achieves the effect of suppressing color mixing of signals transmitted simultaneously through a plurality of signal lines while alternately arranging pixels of different colors in the column direction.

[0017] Furthermore, in the first aspect, signals can be read out from the first, second, and third pixels simultaneously. This configuration achieves the effect of simultaneously transmitting signals read out from pixels of different colors through a plurality of signal lines while suppressing color mixing.

[0018] Furthermore, in the first aspect, the pixels adjacent to each other may be connected to the same signal line. According to this configuration, an effect is achieved in which signals read out from adjacent pixels are transmitted through the same signal line.

[0019] Furthermore, in the first aspect, the plurality of signal lines may include a first signal line connected to a first pixel and a second pixel adjacent to each other in the column direction; a second signal line connected to a third pixel and a fourth pixel adjacent to each other in the column direction; and a third signal line connected to a fifth pixel and a sixth pixel adjacent to each other in the column direction and located between the first signal line and the second pixel. This configuration achieves an effect of connecting pixels adjacent to each other in the column direction to the same signal line while connecting pixels adjacent to each other at every other position in the column direction to non-adjacent signal lines.

[0020] Furthermore, in the first aspect, the pixels may include a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel sequentially arranged in the column direction, the plurality of signal lines may include a first signal line, a second signal line, and a third signal line sequentially arranged in the row direction, the first pixel and the second pixel may be connected to the first signal line, the third pixel and the fourth pixel may be connected to the third signal line, and the fifth pixel and the sixth pixel may be connected to the second signal line. With this configuration, an effect is achieved in which pixels adjacent to each other in the column direction are connected to the same signal line while pixels adjacent to each other at every other position in the column direction are connected to non-adjacent signal lines.

[0021] Furthermore, in the first aspect, signals can be read out simultaneously from the first, third, and fifth pixels at a first time, and signals can be read out simultaneously from the second, fourth, and sixth pixels at a second time. This configuration achieves the effect of reading out signals from pixels connected to the same signal line and adjacent to each other in the column direction at different times.

[0022] Furthermore, in the first aspect, the first pixel, the third pixel, and the fifth pixel may be pixels of the same color, the second pixel, the fourth pixel, and the sixth pixel may be pixels of the same color, and the first pixel and the second pixel may be pixels of different colors. This configuration achieves the effect of arranging pixels of different colors alternately in the column direction while transmitting signals read from the pixels of different colors at different times via a plurality of signal lines.

[0023] Furthermore, a second aspect is an imaging method that includes: reading signals from pixels belonging to the same column but different rows among pixels arranged in a matrix in row and column directions; and simultaneously transmitting the signals read from the pixels belonging to the same column but different rows in the column direction via a plurality of signal lines connected to the pixels, the arrangement order of the plurality of signal lines being different from the arrangement order of the pixels. This configuration achieves the effect of simultaneously transmitting signals via the plurality of signal lines while suppressing crosstalk between signals read from adjacent pixels.

[0024] In the second aspect, pixels adjacent to each other in the column direction may be pixels of different colors. This configuration achieves the effect of suppressing color mixing of signals transmitted simultaneously through a plurality of signal lines while arranging pixels of different colors adjacent to each other in the column direction.

[0025] Furthermore, in the second aspect, the readout timing of each pixel can be set so that different color pixels are read out at different times in each column. According to this configuration, the effect of suppressing color mixing of signals read out from different color pixels while connecting them to adjacent signal lines is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a block diagram showing a configuration example of an image pickup apparatus according to the first embodiment. Figure 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment. Figure 3 is a block diagram showing a circuit configuration example of a pixel provided in the solid-state image pickup device according to the first embodiment. Figure 4 is a diagram showing a connection example between pixels and vertical signal lines according to the first embodiment. Figure 5 is a diagram illustrating an example of crosstalk by a defective pixel according to the first embodiment. Figure 6 is a block diagram showing a transmission path of a signal read out from a pixel at a first timing according to the first embodiment. Figure 7is a block diagram showing a transmission path of a signal read out from a pixel at the second timing according to the first embodiment. Figure 8 is a perspective view showing a layout example of pixels and vertical signal lines according to the first embodiment. Figure 9 is a block diagram showing a transmission path of a signal read out from a pixel at a first timing according to the second embodiment. Figure 10 is a block diagram showing a transmission path of a signal read out from a pixel at a second timing according to the second embodiment. Figure 11 is a diagram showing a connection example between pixels and vertical signal lines according to the third embodiment. Figure 12 is a diagram illustrating an example of crosstalk by a defective pixel according to the third embodiment. Figure 13 is a block diagram showing a transmission path of a signal read out from a pixel at a first timing according to the third embodiment. Figure 14 is a block diagram showing a transmission path of a signal read out from a pixel at a second timing according to the third embodiment. Figure 15 is a diagram showing a connection example between pixels and vertical signal lines according to the fourth embodiment. Figure 16 is a diagram showing a connection example between pixels and vertical signal lines according to the fifth embodiment. Figure 17 is a diagram showing a configuration example of a pixel array section according to a sixth embodiment. Figure 18 is a diagram showing a configuration example of a pixel array section according to a seventh embodiment. Figure 19 is a diagram showing a configuration example of a pixel array section according to an eighth embodiment. Figure 20 is a diagram showing a configuration example of a pixel according to a ninth embodiment. Figure 21 is a timing chart showing waveforms of respective portions during readout from pixels according to the ninth embodiment. Figure 22 is a diagram showing a configuration example of a pixel according to a tenth embodiment. Figure 23 is a timing chart showing waveforms of respective portions during readout from pixels according to the tenth embodiment. Figure 24 is a perspective view showing a stacking example of a solid-state imaging device according to an eleventh embodiment. Figure 25 is a block diagram showing a schematic configuration example of a vehicle control system. Figure 26 It is an explanatory diagram showing an example of the installation position of the imaging unit. DETAILED DESCRIPTION

[0027] Hereinafter, modes for implementing the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order. 1. First Embodiment (An example in which vertical signal lines and pixels are connected so that the arrangement order of four vertical signal lines arranged in one column and the arrangement order of pixels are different from each other, and signals read out from pixels of different colors at the same timing are transmitted in opposite directions) 2. Second Embodiment (An example in which vertical signal lines and pixels are connected so that the arrangement order of four vertical signal lines arranged in one column and the arrangement order of pixels are identical to each other, and signals read out from pixels of different colors are transmitted in opposite directions at the same timing) 3. Third Embodiment (Example in which vertical signal lines and pixels are connected so that the arrangement order of four vertical signal lines arranged in one column and the arrangement order of pixels are different from each other, and the readout timing of each pixel is set so that different color pixels are read out at mutually different timings in each column) 4. Fourth Embodiment (Example in which vertical signal lines and pixels are connected so that the arrangement order of six vertical signal lines arranged in one column and the arrangement order of pixels are different from each other) 5. Fifth Embodiment (Example in which vertical signal lines and pixels are connected so that the arrangement order of six vertical signal lines arranged in one column and the arrangement order of pixels are different from each other, and the readout timing of each pixel is set so that different color pixels are read out at mutually different timings in each column) 6. Sixth Embodiment (Example in which a Shield Line Connected to Ground Potential is Provided Between Vertical Signal Lines) 7. Seventh Embodiment (Example in which a Shield Line Connected to a Power Supply Potential is Provided Between Vertical Signal Lines) 8. Eighth Embodiment (Example in which a shield line is divided such that, at a shield line provided between vertical signal lines, a portion connected to a power supply potential is sandwiched between portions connected to a ground potential) 9. Ninth Embodiment (Pixel Example with Switchable Conversion Efficiency) 10. Tenth Embodiment (Example in Which Photodiodes Having Mutually Different Sensitivities Are Provided in Pixels) 11. Eleventh Embodiment (Example in which Semiconductor Chips Forming a Solid-State Image Pickup Device are Stacked) 12. Application Examples of Mobile Objects

[0028] 1. First embodiment Figure 1 : is a block diagram showing a configuration example of an image pickup apparatus to which the image pickup apparatus according to the first embodiment is applied.

[0029] exist Figure 1 , the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to each other via a bus 108. Note that the imaging device 100 can be used as a single body, can be incorporated into a mobile terminal such as a smartphone, or can be incorporated into an authentication device or a monitoring device.

[0030] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms a subject image on a light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may include a plurality of lenses such as a wide-angle lens, a standard lens, and a telephoto lens.

[0031] The solid-state imaging device 102 converts light from a subject into an electrical signal for each pixel, digitizes the electrical signal, and outputs the digitized electrical signal. The solid-state imaging device 102 may be, for example, a complementary metal oxide semiconductor (CMOS) image sensor, a charge coupled device (CCD), or an event-based vision sensor.

[0032] The imaging control unit 103 controls imaging of the solid-state imaging device 102 based on a command from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, and the like of the solid-state imaging device 102.

[0033] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and grayscale conversion processing. The image processing unit 104 may include a processor that performs processing based on software.

[0034] The storage unit 105 stores captured images captured by the solid-state imaging device 102 and stores imaging parameters and the like of the solid-state imaging device 102. In addition, the storage unit 105 can store a program for operating the imaging device 100 based on software. The storage unit 105 can include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0035] The display unit 106 displays captured images and various types of information for supporting image capture operations. The display unit 106 may be a liquid crystal display or an organic electroluminescent (EL) display.

[0036] The operation unit 107 provides a user interface for operating the imaging apparatus 100. The operation unit 107 may include, for example, buttons, dials, and switches provided in the imaging apparatus 100. The operation unit 107 may be configured by a touch panel together with the display unit 106.

[0037] Figure 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment.

[0038] exist Figure 2 In FIG. 1 , the solid-state imaging device 102 includes a pixel array section 111 , a vertical scanning circuit 112 , a column readout circuit 113 , a column signal processing unit 114 , a horizontal scanning circuit 115 , and a control circuit 116 .

[0039] The pixel array unit 111 includes a plurality of pixels PIX. The pixels PIX are arranged in a matrix in the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). During signal readout, each pixel PIX can form a source follower with the column readout circuit 113. Each pixel PIX is connected to a horizontal drive line HSL per row and to a vertical signal line VSL per column. During signal readout from each pixel PIX, the horizontal drive line HSL drives each pixel PIX row by row. The vertical signal line VSL transmits the signal read out from the pixel PIX to the column signal processing unit 114 column by column.

[0040] The pixel array section 111 may include multiple vertical signal lines VSL in each column. Here, the vertical signal lines VSL can simultaneously transmit signals read from pixels PIX in different rows in the column direction. In this case, in at least one column, the vertical signal lines VSL and the pixels PIX are connected so that the arrangement order of the vertical signal lines VSL and the arrangement order of the pixels PIX are different. Note that the vertical signal lines VSL are examples of signal lines described within the scope of the claims.

[0041] The captured image generated by the solid-state imaging device 102 can be in color. In this case, the pixels PIX can include pixels of different colors arranged alternately in the column direction. For example, the pixels PIX can form a Bayer array. At this time, the same color pixels configured to be read out simultaneously in each column can be connected to vertical signal lines VSL that are adjacent to each other. In addition, different color pixels configured to be read out simultaneously in each column can be connected to vertical signal lines VSL that are not adjacent to each other. In addition, in each column, in an arrangement in which the vertical signal lines VSL connected to the different color pixels configured to be read out simultaneously are adjacent to each other, a shield line can be provided between the vertical signal lines VSL.

[0042] The vertical scanning circuit 112 scans the pixels PIX to be read out in the column direction. The vertical scanning circuit 112 can be configured using a vertical register. Here, during the signal readout from each pixel PIX, the vertical scanning circuit 112 can drive the pixels PIX row by row via the horizontal drive line HSL. In this case, the vertical scanning circuit 112 can drive the pixels PIX row by row via the horizontal drive line HSL so that signals are read out simultaneously from pixels PIX in different rows corresponding to the number of vertical signal lines VSL per column.

[0043] The column readout circuit 113 can form a source-follower relationship with each pixel PIX during signal readout. In this case, the column readout circuit 113 can change the potential of the vertical signal line VSL based on the charge held in the pixel PIX. The column readout circuit 113 can support both constant current readout and capacitive load readout.

[0044] The column signal processing unit 114 processes the signal transmitted from each pixel PIX in the column direction. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signal transmitted from each pixel PIX in the column direction. The column signal processing unit 114 can perform analog-to-digital (AD) conversion processing based on the signal transmitted from each pixel PIX in the column direction and output the imaging signal Gout. In this case, the column signal processing unit 114 can perform AD conversion processing in parallel for each vertical signal line VSL.

[0045] The column signal processing unit 114 may perform defect correction. For example, the column signal processing unit 114 may interpolate the signal read out from the white pixel with the signals read out from pixels surrounding the white pixel.

[0046] The horizontal scanning circuit 115 scans the pixels PIX to be read out in the row direction. The horizontal scanning circuit 115 can be configured by using a horizontal register.

[0047] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114.

[0048] Figure 3 is a block diagram showing a circuit configuration example of a pixel provided in the solid-state image pickup device according to the first embodiment.

[0049] exist Figure 3 , the pixel PIX includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplifier transistor 124, a selection transistor 125, and a floating diffusion FD. As the transfer transistor 122, the reset transistor 123, the amplifier transistor 124, and the selection transistor 125, metal oxide semiconductor (MOS) transistors can be used.

[0050] Amplification transistor 124 and selection transistor 125 are connected in series. The cathode of photodiode 121 is connected to floating diffusion FD via transfer transistor 122. Floating diffusion FD is connected to power supply Vdd via reset transistor 123. Furthermore, power supply Vdd is connected to vertical signal line VSL via the series circuit of amplification transistor 124 and selection transistor 125. The gate of amplification transistor 124 is connected to floating diffusion FD.

[0051] The transfer signal ΦTG is applied to the gate of the transfer transistor 122. The pixel reset signal ΦPRT is applied to the gate of the reset transistor 123. The selection signal ΦSEL is applied to the gate of the selection transistor 125. The transfer signal ΦTG, the pixel reset signal ΦPRT and the selection signal ΦSEL can be applied to the gate of the selection transistor 125. Figure 2 The horizontal driving line HSL in the CMOS is transmitted to each pixel PIX.

[0052] When the transfer transistor 122 turns on, the charge accumulated in the photodiode 121 is transferred to the floating diffusion FD. Then, when the select transistor 125 turns on, the source potential of the amplifier transistor 124 changes according to the potential of the floating diffusion FD. The source potential of the amplifier transistor 124 is then applied to the vertical signal line VSL via the select transistor 125 and transmitted via the vertical signal line VSL. Furthermore, when the reset transistor 123 turns on, the charge accumulated in the floating diffusion FD is discharged.

[0053] Figure 4This figure shows an example of the connection between pixels and vertical signal lines according to the first embodiment. Note that "a" in the figure represents the connection relationship between the four rows of pixels accessed at the first moment and the vertical signal lines, and "b" in the figure represents the connection relationship between the four rows of pixels accessed at the second moment and the vertical signal lines.

[0054] In the figure, four vertical signal lines VSL1 to VSL4 are provided in each column COL. At this time, the vertical signal lines VSL1 to VSL4 can simultaneously transmit signals read out from four different rows in the column direction.

[0055] In each column COL, pixels PIX1 to PIX12 are arranged in the column direction. In this case, pixels PIX1 to PIX12 can be located in rows ROW1 to ROW12. In addition, in each column COL, pixels of different colors can be arranged adjacent to each other in the column direction. For example, in a Bayer array, pixels PIX1, PIX3, PIX5, PIX7, PIX9, and PIX11 can be red pixels, and pixels PIX2, PIX4, PIX6, PIX8, PIX10, and PIX12 can be green pixels. Pixels PIX1, PIX3, PIX5, PIX7, PIX9, and PIX11 can be green pixels, and pixels PIX2, PIX4, PIX6, PIX8, PIX10, and PIX12 can be blue pixels.

[0056] Here, vertical signal lines VSL1 to VSL4 are connected to pixels PIX so that the arrangement order of the vertical signal lines VSL in each column COL and the arrangement order of the pixels PIX are different from each other. For example, pixels PIX1, PIX5, and PIX9 can be connected to vertical signal line VSL1, and pixels PIX3, PIX7, and PIX11 can be connected to vertical signal line VSL2. Pixels PIX2, PIX6, and PIX10 can be connected to vertical signal line VSL3, and pixels PIX4, PIX8, and PIX12 can be connected to vertical signal line VSL4. At this time, pixels PIX1, PIX3, PIX5, PIX7, PIX9, and PIX11 of the same color are alternately connected to vertical signal lines VSL1 and VSL2 adjacent to each other. In addition, pixels PIX2, PIX4, PIX6, PIX8, PIX10, and PIX12 of the same color are alternately connected to vertical signal lines VSL3 and VSL4 adjacent to each other.

[0057] During signal readout, as shown in a of the figure, at the first moment, access ACS1 is performed on pixels PIX1 to PIX4 belonging to corresponding rows ROW1 to ROW4. At this time, the signals read out from pixels PIX1 to PIX4 are simultaneously transmitted in the column direction via vertical signal lines VSL1, VSL3, VSL2, and VSL4, respectively. Furthermore, as shown in b of the figure, at the second moment, access ACS2 is performed on pixels PIX5 to PIX8 belonging to corresponding rows ROW5 to ROW8. At this time, the signals read out from pixels PIX5 to PIX8 are simultaneously transmitted in the column direction via vertical signal lines VSL1, VSL3, VSL2, and VSL4, respectively.

[0058] Here, the signals read out from the same color pixels (e.g., red pixels) are transmitted through the vertical signal lines VSL1 and VSL2 adjacent to each other, thereby suppressing color mixing. In addition, the signals read out from the same color pixels (e.g., green pixels) are transmitted through the vertical signal lines VSL3 and VSL4 adjacent to each other, thereby suppressing color mixing. On the other hand, the signals read out from different color pixels (e.g., red pixels and green pixels) are transmitted through the vertical signal lines VSL2 and VSL3 adjacent to each other. At this time, in order to suppress color mixing, a shield line can be provided between the vertical signal lines VSL2 and VSL3.

[0059] Figure 5 : is a diagram illustrating an example of crosstalk caused by a defective pixel according to the first embodiment. Note that (a) in the diagram illustrates an example of crosstalk caused by a defective pixel when there is no shield line between vertical signal lines, and (b) in the diagram illustrates an example of crosstalk caused by a defective pixel when there is a shield line between vertical signal lines.

[0060] For example, in figure a, assume that a defect PW, such as a white dot, exists in pixel PIX3. In this case, vertical signal line VSL2 connected to pixel PIX3 is adjacent to vertical signal line VSL1 connected to pixel PIX1 and vertical signal line VSL3 connected to pixel PIX2. Therefore, when signals are read out simultaneously from pixels PIX1 to PIX4, defect PW in pixel PIX3 also affects the signals read out from pixels PIX1 and PIX2.

[0061] Here, as shown in b in the figure, a shield line SLD is provided between vertical signal lines VSL2 and VSL3 to suppress color mixing. In this case, even if signals are read out simultaneously from pixels PIX1 to PIX4, the defect PW of pixel PIX3 does not affect the signal read out from pixel PIX2.

[0062] Figure 6 1 is a block diagram showing a transmission path of a signal read out from a pixel at a first timing according to the first embodiment. Note that in the figure, an example is shown in which the pixels PIX form a Bayer array.

[0063] In the figure, in the first column, pixels PIX1 to PIX16 are arranged in the column direction. In the second column, pixels PIX1' to PIX16' are arranged in the column direction. Pixels PIX1, PIX3, PIX5, PIX7, PIX9, PIX11, PIX13, and PIX15 can be red pixels. Pixels PIX2, PIX4, PIX6, PIX8, PIX10, PIX12, PIX14, PIX16, PIX1', PIX3', PIX5', PIX7', PIX9', PIX11', PIX13', and PIX15' can be green pixels. Pixels PIX2', PIX4', PIX6', PIX8', PIX10', PIX12', PIX11', and PIX16' can be blue pixels. Furthermore, vertical signal lines VSL1 to VSL4 are arranged in a first column, and vertical signal lines VSL5 to VSL8 are arranged in a second column.

[0064] Pixels PIX1, PIX5, PIX9, and PIX13 are connected to a vertical signal line VSL1, and pixels PIX3, PIX7, PIX11, and PIX15 are connected to a vertical signal line VSL2. Pixels PIX2, PIX6, PIX10, and PIX14 are connected to a vertical signal line VSL3, and pixels PIX4, PIX8, PIX12, and PIX16 are connected to a vertical signal line VSL4.

[0065] Pixels PIX1′, PIX5′, PIX9′, and PIX13′ are connected to a vertical signal line VSL5, and pixels PIX3′, PIX7′, PIX11′, and PIX15′ are connected to a vertical signal line VSL6. Pixels PIX2′, PIX6′, PIX10′, and PIX14′ are connected to a vertical signal line VSL7, and pixels PIX4′, PIX8′, PIX12′, and PIX16′ are connected to a vertical signal line VSL8.

[0066] The column readout circuit 113 is provided with constant current readout sections 202A and 202B. The constant current readout sections 202A and 202B form a source follower with each pixel PIX and can read a signal from each pixel PIX. The constant current readout sections 202A and 202B can be provided on both sides of the vertical signal lines VSL1 to VSL8. In this case, the constant current readout section 202A can be provided at one end of the vertical signal lines VSL1 to VSL8, and the constant current readout section 202B can be provided at the other end of the vertical signal lines VSL1-VSL8.

[0067] The constant current readout section 202A includes current sources 212A, 222A, 232A, and 242A. The current source 212A is connected to the vertical signal line VSL3, the current source 222A is connected to the vertical signal line VSL4, the current source 232A is connected to the vertical signal line VSL5, and the current source 242A is connected to the vertical signal line VSL6.

[0068] The constant current readout section 202B includes current sources 212B, 222B, 232B, and 242B. Current source 212B is connected to vertical signal line VSL1, current source 222B is connected to vertical signal line VSL2, current source 232B is connected to vertical signal line VSL7, and current source 242B is connected to vertical signal line VSL8.

[0069] The column signal processing unit 114 includes column ADC units 203A and 203B. The column ADC units 203A and 203B can perform A / D conversion on the signals read out from the pixels PIX in parallel, column by column. The column ADC units 203A and 203B can be provided on both sides of the vertical signal lines VSL1 to VSL8. In this case, the column ADC unit 203A can be provided at one end of the vertical signal lines VSL1 to VSL8, and the column ADC unit 203B can be provided at the other end of the vertical signal lines VSL1 to VSL8.

[0070] Column ADC section 203A includes comparators 213A, 223A, 233A, and 243A, and capacitors 214A, 224A, 234A, and 244A. Comparator 213A is connected to vertical signal line VSL3 via capacitor 214A, and comparator 223A is connected to vertical signal line VSL4 via capacitor 224A. Comparator 233A is connected to vertical signal line VSL5 via capacitor 234A, and comparator 243A is connected to vertical signal line VSL6 via capacitor 244A.

[0071] The column ADC section 203B includes comparators 213B, 223B, 233B, and 243B, and capacitors 214B, 224B, 234B, and 244B. Comparator 213B is connected to vertical signal line VSL1 via capacitor 214B, and comparator 223B is connected to vertical signal line VSL2 via capacitor 224B. Comparator 233B is connected to vertical signal line VSL7 via capacitor 234B, and comparator 243B is connected to vertical signal line VSL8 via capacitor 244B.

[0072] Comparators 213A, 223A, 233A, 243A, 213B, 223B, 233B, and 243B compare signals transmitted from the vertical signal lines VSL3, VSL4, VSL5, VSL6, VSL1, VSL2, VSL7, and VSL8, respectively, with a reference voltage. Comparators 213A, 223A, 233A, 243A, 213B, 223B, 233B, and 243B perform AD conversion on the signals transmitted from the vertical signal lines VSL3, VSL4, VSL5, VSL6, VSL1, VSL2, VSL7, and VSL8 based on the count value until the signals match the reference voltage.

[0073] Here, during the first horizontal period, signals are read out simultaneously from pixels PIX1 to PIX4 and PIX1' to PIX4'. The signals read out from pixels PIX1 to PIX4 and PIX1' to PIX4' are then transmitted in the column direction via vertical signal lines VSL3, VSL4, VSL5, VSL6, VSL1, VSL2, VSL7, and VSL8, respectively. At this time, the signals read out from pixels PIX2, PIX4, PIX1', and PIX3' are transmitted in the opposite direction to the signals read out from pixels PIX1, PIX3, PIX2', and PIX4'. The signals read out from pixels PIX2, PIX4, PIX1', and PIX3' are then transmitted to column ADC unit 203A, and the signals read out from pixels PIX1, PIX3, PIX2', and PIX4' are then transmitted to column ADC unit 203B.

[0074] Figure 7 is a block diagram showing a transmission path of a signal read out from a pixel at the second timing according to the first embodiment.

[0075] In the figure, during the second horizontal period, signals are read out simultaneously from pixels PIX5 to PIX8 and PIX5' to PIX8'. The signals read out from pixels PIX5 to PIX8 and PIX5' to PIX8' are then transmitted in the column direction via vertical signal lines VSL3, VSL4, VSL5, VSL6, VSL1, VSL2, VSL7, and VSL8, respectively. At this time, the signals read out from pixels PIX6, PIX8, PIX5', and PIX7' are transmitted in the opposite direction to the signals read out from pixels PIX5, PIX7, PIX6', and PIX8'. The signals read out from pixels PIX6, PIX8, PIX5', and PIX7' are then transmitted to column ADC unit 203A, and the signals read out from pixels PIX5, PIX7, PIX6', and PIX8' are then transmitted to column ADC unit 203B.

[0076] Figure 8 : is a perspective view showing an example of the layout of pixels and vertical signal lines according to the first embodiment. Note that this figure shows an example of the layout of pixels and vertical signal lines of a back-illuminated image sensor.

[0077] In this figure, the back-illuminated image sensor includes a semiconductor substrate 151 and a wiring layer 152. The wiring layer 152 is formed on the semiconductor substrate 151. Pixels PIX1 to PIX12 are formed on the back side of the semiconductor substrate 151. At this time, light is incident on each of the pixels PIX1 to PIX12 from the back side of the semiconductor substrate 151. Vertical signal lines VSL1 to VSL4 are formed in the wiring layer 152. Signals read out from the pixels PIX1 to PIX12 are transmitted via the vertical signal lines VSL1 to VSL4. Note that the vertical signal lines VSL1 to VSL4 may be formed in the same wiring layer, or any one of the vertical signal lines VSL1 to VSL4 may be formed in a different wiring layer.

[0078] Therefore, in the first embodiment described above, the vertical signal lines VSL1 to VSL4 and the pixels IX1 to PIX12 are connected so that the arrangement order of the four vertical signal lines VSL1 to VSL4 and the arrangement order of the pixels PIX1 to PIX12 arranged in the column COL are different from each other. Therefore, the adjacent different-color pixels PIX1 and PIX2 can be connected to the vertical signal lines VSL1 and VSL3 that are not adjacent to each other, and the adjacent different-color pixels PIX3 and PIX4 can be connected to the vertical signal lines VSL2 and VSL4 that are not adjacent to each other. This makes it possible to suppress color mixing of the signals read out from the different-color pixels PIX1 and PIX2, and to suppress color mixing of the signals read out from the different-color pixels PIX3 and PIX4.

[0079] However, the adjacent different color pixels PIX2 and PIX3 are connected to the adjacent vertical signal lines VSL3 and VSL2. At this time, in order to suppress the color mixing of the signals read out from the different color pixels PIX2 and PIX3, a shield line SLD may be provided between the vertical signal lines VSL2 and VSL3. Figure 5 As shown in b.

[0080] In addition, in the above embodiment, an example has been described in which the pixels PIX include pixels of different colors, but the pixels PIX may include only pixels of the same color. In this case, the image generated by the camera is not necessarily limited to a color image and may also be a monochrome image, an infrared image, or a range image.

[0081] 2. Second embodiment In the first embodiment described above, the vertical signal lines VSL1 to VSL4 and the pixels IX1 to PIX12 are connected so that the arrangement order of the four vertical signal lines VSL1 to VSL4 provided in the column COL and the arrangement order of the pixels PIX1 to PIX12 are different from each other. In this second embodiment, the vertical signal lines VSL1 to VSL4 and the pixels IX1 to PIX12 are connected so that the arrangement order of the four vertical signal lines VSL1 to VSL4 provided in the column COL and the arrangement order of the pixels PIX1 to PIX12 are consistent with each other.

[0082] Figure 9 1 is a block diagram showing a transmission path of a signal read out from a pixel at a first timing according to the second embodiment. Note that in the figure, an example is shown in which the pixels PIX form a Bayer array.

[0083] In the figure, in this imaging device, the arrangement order of the four vertical signal lines VSL1 to VSL4 arranged in the first column and the arrangement order of the pixels PIX1 to PIX16 are consistent with each other. In addition, the arrangement order of the four vertical signal lines VSL5 to VSL8 arranged in the second column and the arrangement order of the pixels PIX1' to PIX16' are consistent with each other. The rest of the configuration of the imaging device of the second embodiment is similar to that of the imaging device of the first embodiment described above.

[0084] At this time, pixels PIX1, PIX5, PIX9, and PIX13 are connected to vertical signal line VSL1, and pixels PIX2, PIX6, PIX10, and PIX14 are connected to vertical signal line VSL2. Pixels PIX3, PIX7, PIX11, and PIX15 are connected to vertical signal line VSL3, and pixels PIX4, PIX8, PIX12, and PIX16 are connected to vertical signal line VSL4.

[0085] Pixels PIX1′, PIX5′, PIX9′, and PIX13′ are connected to a vertical signal line VSL5, and pixels PIX2′, PIX6′, PIX10′, and PIX14′ are connected to a vertical signal line VSL6. Pixels PIX3′, PIX7′, PIX11′, and PIX15′ are connected to a vertical signal line VSL7, and pixels PIX4′, PIX8′, PIX12′, and PIX16′ are connected to a vertical signal line VSL8.

[0086] The current source 212A is connected to the vertical signal line VSL2 , the current source 222A is connected to the vertical signal line VSL4 , the current source 232A is connected to the vertical signal line VSL5 , and the current source 242A is connected to the vertical signal line VSL7 .

[0087] The current source 212B is connected to the vertical signal line VSL1 , the current source 222B is connected to the vertical signal line VSL3 , the current source 232B is connected to the vertical signal line VSL6 , and the current source 242B is connected to the vertical signal line VSL8 .

[0088] Comparator 213A is connected to vertical signal line VSL2 via capacitor 214A, and comparator 223A is connected to vertical signal line VSL4 via capacitor 224A. Comparator 233A is connected to vertical signal line VSL5 via capacitor 234A, and comparator 243A is connected to vertical signal line VSL7 via capacitor 244A.

[0089] Comparator 213B is connected to vertical signal line VSL1 via capacitor 214B, and comparator 223B is connected to vertical signal line VSL3 via capacitor 224B. Comparator 233B is connected to vertical signal line VSL6 via capacitor 234B, and comparator 243B is connected to vertical signal line VSL8 via capacitor 244B.

[0090] Here, during the first horizontal period, signals are simultaneously read from each of pixels PIX1 to PIX4 and PIX1' to PIX4'. The signals read from pixels PIX1 to PIX4 and PIX1' to PIX4' are then transmitted in the column direction via vertical signal lines VSL2, VSL4, VSL5, VSL7, VSL1, VSL3, VSL6, and VSL8, respectively. At this point, the signals read from pixels PIX2, PIX4, PIX1', and PIX3' are transmitted in the opposite direction to the signals read from pixels PIX1, PIX3, PIX2', and PIX4'. The signals read from pixels PIX2, PIX4, PIX1', and PIX3' are then transmitted to column ADC unit 203A, and the signals read from pixels PIX1, PIX3, PIX2', and PIX4' are then transmitted to column ADC unit 203B.

[0091] Figure 10 is a block diagram showing a transmission path of a signal read out from a pixel at a second timing according to the second embodiment.

[0092] In the figure, during the second horizontal period, signals are read out simultaneously from each of pixels PIX5 to PIX8 and PIX5' to PIX8'. The signals read out from pixels PIX5 to PIX8 and PIX5' to PIX8' are then transmitted in the column direction via vertical signal lines VSL2, VSL4, VSL5, VSL7, VSL1, VSL3, VSL6, and VSL8, respectively. At this point, the signals read out from pixels PIX6, PIX8, PIX5', and PIX7' are transmitted in the opposite direction to the signals read out from pixels PIX5, PIX7, PIX6', and PIX8'. The signals read out from pixels PIX6, PIX8, PIX5', and PIX7' are then transmitted to column ADC unit 203A, and the signals read out from pixels PIX5, PIX7, PIX6', and PIX8' are then transmitted to column ADC unit 203B.

[0093] Therefore, in the second embodiment described above, the vertical signal lines and pixels are connected so that the arrangement order of the multiple vertical signal lines arranged in the columns and the arrangement order of the pixels in the column direction match each other. Furthermore, signals read from pixels belonging to the same column but in different rows are transmitted in opposite directions at the same time. This makes it possible to arrange the column ADC units 203A and 203B on both sides of the vertical signal lines VSL1 to VSL8, thereby increasing the layout flexibility of the column ADC units 203A and 203B.

[0094] 3. Third embodiment In the first embodiment described above, the vertical signal lines VSL1 to VSL4 and the pixels IX1 to PIX12 are connected so that the arrangement order of the four vertical signal lines VSL1 to VSL4 provided in the column COL and the arrangement order of the pixels PIX1 to PIX12 are different from each other. In this third embodiment, the readout timing from each of the pixels PIX1 to PIX12 in the column COL provided with the four vertical signal lines VSL1 to VSL4 is set so that different color pixels are read out at mutually different timings.

[0095] Figure 11 This figure shows an example of the connection between pixels and vertical signal lines according to the third embodiment. Note that "a" in the figure represents the connection relationship between four rows of pixels accessed at the first moment and the vertical signal lines, while "b" in the figure represents the connection relationship between four rows of pixels accessed at the second moment and the vertical signal lines.

[0096] In the figure, in this imaging device, vertical signal lines VSL1 to VSL4 are connected to pixels PIX, so that the arrangement order of the vertical signal lines VSL and the arrangement order of the pixels PIX in each column COL are different. Here, in each column COL, two adjacent pixels of different colors in the column direction are connected to the same vertical signal lines VSL1 to VSL4. Furthermore, signals are read out from the two pixels of different colors connected to the same vertical signal lines VSL1 to VSL4 at different times. The rest of the configuration of the imaging device of the third embodiment is similar to that of the imaging device of the first embodiment described above.

[0097] Here, pixels PIX1, PIX2, PIX9, and PIX10 can be connected to vertical signal line VSL1, and pixels PIX5 and PIX6 can be connected to vertical signal line VSL2. Pixels PIX3, PIX4, PIX11, and PIX12 can be connected to vertical signal line VSL3, and pixels PIX7 and PIX8 can be connected to vertical signal line VSL4. At this time, two pixels PIX1 and PIX2 of different colors are connected to the same vertical signal line VSL1, and two pixels PIX5 and PIX6 of different colors are connected to the same vertical signal line VSL2. Two pixels PIX3 and PIX4 of different colors are connected to the same vertical signal line VSL3, and two pixels PIX7 and PIX8 of different colors are connected to the same vertical signal line VSL4.

[0098] During signal readout, as shown in a of the figure, pixels PIX1, PIX3, PIX5, and PIX7 belonging to rows ROW1, ROW3, ​​ROW5, and ROW7 access ACS1 at the first moment. At this time, the signals read out from pixels PIX1, PIX3, PIX5, and PIX7 are simultaneously transmitted in the column direction via vertical signal lines VSL1, VSL3, VSL2, and VSL4, respectively. Furthermore, as shown in b of the figure, pixels PIX2, PIX4, PIX6, and PIX8 belonging to rows ROW2, ROW4, ROW6, and ROW8 access ACS2 at the second moment. At this time, the signals read out from pixels PIX2, PIX4, PIX6, and PIX8 are simultaneously transmitted in the column direction via vertical signal lines VSL1, VSL3, VSL2, and VSL4, respectively.

[0099] Figure 12 : is a diagram illustrating an example of crosstalk caused by a defective pixel according to the third embodiment. Note that (a) in the diagram illustrates an example of crosstalk caused by a defective pixel when there is no shield line between vertical signal lines, and (b) in the diagram illustrates an example of crosstalk caused by a defective pixel when there is a shield line between vertical signal lines.

[0100] For example, in a of the figure, assume that a defect PW, such as a white dot, exists in pixel PIX3. In this case, the vertical signal line VSL3 connected to pixel PIX3 is adjacent to the vertical signal line VSL2 connected to pixel PIX5 and the vertical signal line VSL4 connected to pixel PIX7. Therefore, when signals are read out simultaneously from pixels PIX1, PIX3, PIX5, and PIX7, the defect PW in pixel PIX3 will also affect the signals read out from pixels PIX5 and PIX7. However, in the third embodiment, even if signals are read out simultaneously from pixels PIX1, PIX3, PIX5, and PIX7, color mixing does not occur because pixels PIX1, PIX3, PIX5, and PIX7 have the same color.

[0101] Here, as shown in b in the figure, shield line SLD is provided between vertical signal lines VSL2 and VSL3. In this case, even when signals are read simultaneously from pixels PIX1, PIX3, PIX5, and PIX7, defect PW in pixel PIX3 does not affect the signal read from pixel PIX5. Therefore, by interpolating the signal of pixel PIX3 based on the signals of pixels PIX1 and PIX5, which are adjacent to pixel PIX3 among the same-colored pixels, the influence of defect PW in pixel PIX3 can be corrected.

[0102] Figure 13 3 is a block diagram showing a transmission path of a signal read out from a pixel at a first timing according to the third embodiment. Note that in the figure, an example is shown in which the pixels PIX form a Bayer array.

[0103] In the figure, this imaging device is obtained by adding switching sections 201A and 201B to the imaging device of the first embodiment described above. Furthermore, one end of each of the vertical signal lines VSL1 to VSL8 is connected to a constant current readout section 202A and a column ADC section 203A via switching section 201A. The other end of each of the vertical signal lines VSL1 to VSL8 is connected to a constant current readout section 202B and a column ADC section 203B via switching section 201B. The rest of the configuration of the imaging device of the third embodiment is similar to that of the imaging device of the first embodiment described above.

[0104] Each switching section 201A and 201B alternately switches the connection destination of each of the vertical signal lines VSL1 to VSL8 for each horizontal period. For example, in the first horizontal period, the switching section 201A connects the vertical signal lines VSL5 to VSL8 to the constant current readout section 202A and the column ADC section 203A. Furthermore, in the second horizontal period, the switching section 201A connects the vertical signal lines VSL1 to VSL4 to the constant current readout section 202A and the column ADC section 203A. In the first horizontal period, the switching section 201B connects the vertical signal lines VSL1 to VSL4 to the constant current readout section 202B and the column ADC section 203B. Furthermore, in the second horizontal period, the switching section 201B connects the vertical signal lines VSL5 to VSL8 to the constant current readout section 202B and the column ADC section 203B.

[0105] The switches 201A and 201B may be provided on both sides of the vertical signal lines VSL1 to VSL8. In this case, the switch 201A may be provided at one end of the vertical signal lines VSL1 to VSL8, and the switch 201B may be provided at the other end of the vertical signal lines VSL1-VSL8.

[0106] Switching section 201A includes multiplexers 211A to 241A and transmission lines SEA1 to SEA8. Transmission lines SEA1 to SEA8 are connected to vertical signal lines VSL1 to VSL8, respectively. The outputs of multiplexers 211A to 241A are connected to current sources 212A, 222A, 232A, and 242A, respectively. Furthermore, the outputs of multiplexers 211A to 241A are connected to comparators 213A, 223A, 233A, and 243A, respectively, via capacitors 214A, 224A, 234A, and 244A, respectively. Multiplexers 211A to 241A select vertical signal lines VSL5 to VSL8, respectively, during the first horizontal period, and select vertical signal lines VSL1 to VSL4, respectively, during the second horizontal period.

[0107] Switching section 201B includes multiplexers 211B to 241B and transmission lines SEB1 to SEB8. Transmission lines SEBA1 to SEBA8 are connected to vertical signal lines VSL1 to VSL8, respectively. The outputs of multiplexers 211B to 241B are connected to current sources 212B, 222B, 232B, and 242B, respectively. The outputs of multiplexers 211B to 241B are connected to comparators 213B, 223B, 233B, and 243B, respectively, via capacitors 214B, 224B, 234B, and 244B, respectively. Multiplexers 211B to 241B select vertical signal lines VSL1 to VSL4, respectively, during the first horizontal period, and select vertical signal lines VSL5 to VSL8, respectively, during the second horizontal period.

[0108] Here, during the first horizontal period, signals are read out simultaneously from pixels PIX1, PIX3, PIX5, PIX7, PIX1', PIX3', PIX5', and PIX7'. Then, the signals read out from pixels PIX1, PIX3, PIX5, PIX7, PIX1', PIX3', PIX5', and PIX7' are transmitted in the column direction via vertical signal lines VSL4, VSL2, VSL3, VSL1, VSL8, VSL6, VSL7, and VSL5, respectively. At this time, the signals read out from pixels PIX1, PIX3, PIX5, and PIX7 are transmitted in the opposite direction to the signals read out from pixels PIX1', PIX3', PIX5', and PIX7'. Then, the signals read out from the pixels PIX1 , PIX3 , PIX5 , and PIX7 are transferred to the column ADC portion 203B, and the signals read out from the pixels PIX1 ′, PIX3 ′, PIX5 ′, and PIX7 ′ are transferred to the column ADC portion 203A.

[0109] Figure 14 is a block diagram showing a transmission path of a signal read out from a pixel at a second timing according to the third embodiment.

[0110] In the figure, during the second horizontal period, signals are read out simultaneously from pixels PIX2, PIX4, PIX6, PIX8, PIX2', PIX4', PIX6', and PIX8'. The signals read out from pixels PIX2, PIX4, PIX6, PIX8, PIX2', PIX4', PIX6', and PIX8' are then transmitted in the column direction via vertical signal lines VSL4, VSL2, VSL3, VSL1, VSL8, VSL6, VSL7, and VSL5, respectively. At this time, the signals read out from pixels PIX2, PIX4, PIX6, and PIX8 are transmitted in the opposite direction to the signals read out from pixels PIX2', PIX4', PIX6', and PIX8'. Then, the signals read out from the pixels PIX2 , PIX4 , PIX6 , and PIX8 are transferred to the column ADC section 203A, and the signals read out from the pixels PIX2 ′, PIX4 ′, PIX6 ′, and PIX8 ′ are transferred to the column ADC section 203B.

[0111] Therefore, in the third embodiment described above, the readout timings of pixels PIX1 to PIX16 and the readout timings of pixels PIX1' to PIX16' are set so that pixels of different colors are read out at different timings in each column. This prevents signals read out from pixels of different colors from being transmitted via vertical signal lines adjacent to each other, and suppresses color mixing of signals read out from pixels of different colors.

[0112] 4. Fourth Example In the first embodiment described above, the vertical signal lines VSL1 to VSL4 and the pixels IX1 to PIX12 are connected so that the arrangement order of the four vertical signal lines VSL1 to VSL4 provided in the column COL and the arrangement order of the pixels PIX1 to PIX12 are different from each other. In this fourth embodiment, the vertical signal lines and the pixels are connected so that the arrangement order of the six vertical signal lines provided in the column COL and the arrangement order of the pixels are different from each other.

[0113] Figure 15 This figure shows an example of the connection between pixels and vertical signal lines according to the fourth embodiment. Note that "a" in the figure represents the connection relationship between the six rows of pixels accessed at the first moment and the vertical signal lines, and "b" in the figure represents the connection relationship between the six rows of pixels accessed at the second moment and the vertical signal lines.

[0114] In the figure, the imaging device includes six vertical signal lines VSL1 to VSL6 in column COL. The arrangement order of the six vertical signal lines VSL1 to VSL6 in column COL and the arrangement order of the pixels PIX1 to PIX12 are different. The rest of the configuration of the imaging device of the fourth embodiment is similar to that of the imaging device of the first embodiment described above.

[0115] Here, pixels PIX1 and PIX7 can be connected to vertical signal line VSL1, and pixels PIX2 and PIX8 can be connected to vertical signal line VSL4. Pixels PIX3 and PIX9 can be connected to vertical signal line VSL2, and pixels PIX4 and PIX10 can be connected to vertical signal line VSL5. Pixels PIX5 and PIX11 can be connected to vertical signal line VSL3, and pixels PIX6 and PX12 can be connected to vertical signal line VSL6. At this time, pixels PIX1, PIX3, and PIX5 of the same color are connected to vertical signal lines VSL1 to VSL3 adjacent to each other. Pixels PIX7, PIX9, and PIX11 of the same color are connected to vertical signal lines VSL1 to VSL3 adjacent to each other. In addition, pixels PIX2, PIX4, and PIX6 of the same color are connected to vertical signal lines VSL4 to VSL6 adjacent to each other. Pixels PIX8, PIX10, and PIX12 of the same color are connected to vertical signal lines VSL4 to VSL6 adjacent to each other.

[0116] During signal readout, as shown in a of the figure, pixels PIX1 to PIX6 in rows ROW1 to ROW6 access ACS1 at the first moment. At this point, the signals read from pixels PIX1 to PIX6 are simultaneously transmitted in the column direction via vertical signal lines VSL1, VSL4, VSL2, VSL5, VSL3, and VSL6, respectively. Furthermore, as shown in b of the figure, pixels PIX7 to PIX12 in rows ROW7 to ROW12 access ACS2 at the second moment. At this point, the signals read from pixels PIX7 to PIX12 are simultaneously transmitted in the column direction via vertical signal lines VSL1, VSL4, VSL2, VSL5, VSL3, and VSL6, respectively.

[0117] Here, the signals read out from the same color pixels (e.g., red pixels) are transmitted through the vertical signal lines VSL1 to VSL3 adjacent to each other, thereby suppressing color mixing. In addition, the signals read out from the same color pixels (e.g., green pixels) are transmitted through the vertical signal lines VSL4 to VSL6 adjacent to each other, thereby suppressing color mixing. On the other hand, the signals read out from different color pixels (e.g., red pixels and green pixels) are transmitted through the vertical signal lines VSL3 and VSL4 adjacent to each other. At this time, in order to suppress color mixing, a shield line can be provided between the vertical signal lines VSL3 and VSL4.

[0118] Therefore, in the fourth embodiment described above, the vertical signal lines VSL1 to VSL6 and the pixels IX1 to PIX12 are connected so that the arrangement order of the six vertical signal lines VSL1 to VSL6 and the arrangement order of the pixels PIX1 to PIX12 arranged in the column COL are different from each other. Therefore, the adjacent pixels PIX1 and PIX2 of different colors can be connected to the vertical signal lines VSL1 and VSL4 that are not adjacent to each other. Furthermore, the adjacent pixels PIX3 and PIX4 of different colors can be connected to the vertical signal lines VSL2 and VSL5 that are not adjacent to each other. Furthermore, the adjacent pixels PIX5 and PIX6 of different colors can be connected to the vertical signal lines VSL3 and VSL6 that are not adjacent to each other. This makes it possible to suppress color mixing of the signals read out from the pixels PIX1 and PIX2 of different colors, suppress color mixing of the signals read out from the pixels PIX3 and PIX4 of different colors, and suppress color mixing of the signals read out from the pixels PIX5 and PIX6 of different colors.

[0119] 5. Fifth embodiment In the fourth embodiment described above, the vertical signal lines VSL1 to VSL6 and the pixels IX1 to PIX12 are connected so that the arrangement order of the six vertical signal lines VSL1 to VSL6 and the arrangement order of the pixels PIX1 to PIX12 provided in the column COL are different from each other. In this fifth embodiment, the readout timing of each of the pixels PIX1 to PIX12 is set so that different color pixels are read out at mutually different timings in the column COL provided with the six vertical signal lines VSL1 to VSL6.

[0120] Figure 16 This figure shows an example of the connection between pixels and vertical signal lines according to the fifth embodiment. Note that "a" in the figure represents the connection relationship between the six rows of pixels accessed at the first moment and the vertical signal lines, while "b" in the figure represents the connection relationship between the six rows of pixels accessed at the second moment and the vertical signal lines.

[0121] In the figure, in this imaging device, vertical signal lines VSL1 to VSL6 are connected to pixels PIX, so that the arrangement order of the vertical signal lines VSL and the arrangement order of the pixels PIX in each column COL are different. Here, in each column COL, two adjacent pixels of different colors in the column direction are connected to the same vertical signal lines VSL1 to VSL6. Furthermore, signals are read out from the two pixels of different colors connected to the same vertical signal lines VSL1 to VSL6 at different times. The rest of the configuration of the imaging device of the sixth embodiment is similar to that of the imaging device of the fifth embodiment described above.

[0122] Here, pixels PIX1 and PIX2 can be connected to vertical signal line VSL1, and pixels PIX5 and PIX6 can be connected to vertical signal line VSL2. Pixels PIX9 and PIX10 can be connected to vertical signal line VSL3, and pixels PIX3 and PIX4 can be connected to vertical signal line VSL4. Pixels PIX7 and PIX8 can be connected to vertical signal line VSL5, and pixels PIX11 and PIX12 can be connected to vertical signal line VSL6. At this time, two pixels PIX1 and PIX2 of different colors are connected to the same vertical signal line VSL1, and two pixels PIX5 and PIX6 of different colors are connected to the same vertical signal line VSL2. Two pixels PIX9 and PIX10 of different colors are connected to the same vertical signal line VSL3, and two pixels PIX3 and PIX4 of different colors are connected to the same vertical signal line VSL4. Two pixels PIX7 and PIX8 of different colors are connected to the same vertical signal line VSL5, and two pixels PIX11 and PIX12 of different colors are connected to the same vertical signal line VSL6.

[0123] During signal readout, as shown in a of the figure, pixels PIX1, PIX3, PIX5, PIX7, PIX9, and PIX11 belonging to rows ROW1, ROW3, ​​ROW5, ROW7, ROW9, and ROW11 access ACS1 at the first time. At this time, the signals read out from pixels PIX1, PIX3, PIX5, PIX7, PIX9, and PIX11 are simultaneously transmitted in the column direction via vertical signal lines VSL1, VSL4, VSL2, VSL5, VSL3, and VSL6, respectively. Furthermore, as shown in b of the figure, pixels PIX2, PIX4, PIX6, PIX8, PIX10, and PIX12 belonging to rows ROW2, ROW4, ROW6, ROW8, ROW10, and ROW12 access ACS2 at the second time. At this time, signals read out from the pixels PIX2 , PIX4 , PIX6 , PIX8 , PIX10 , and PIX12 are simultaneously transmitted in the column direction via the vertical signal lines VSL1 , VSL4 , VSL2 , VSL5 , VSL3 , and VSL6 , respectively.

[0124] 6. Sixth embodiment In the first embodiment described above, pixels PIX2 and PIX3 of different colors are connected to vertical signal lines VSL3 and VSL2 adjacent to each other. In this sixth embodiment, a shield line connected to a ground potential is provided between vertical signal lines VSL3 and VSL2 connected to pixels PIX2 and PIX3 of different colors.

[0125] Figure 17 This figure shows an example configuration of a pixel array section provided in a solid-state imaging device according to the sixth embodiment. Note that "a" in the figure is a plan view showing an example layout of vertical signal lines. "b" in the figure is a cross-sectional view showing an example configuration of the wiring layer of the pixel array section. Furthermore, "b" in the figure shows a section taken along line AA in "a" in the figure. Furthermore, this figure shows an example of a front-illuminated solid-state imaging device for four pixels.

[0126] In Figure a, shield line PS0 is arranged between vertical signal lines VSL3 and VSL2. Shield line PS0 can be arranged parallel to vertical signal lines VSL3 and VSL2. Furthermore, shield line PS1 can be arranged parallel to vertical signal line VSL1, and shield line PS2 can be arranged parallel to vertical signal line VSL4. Shield lines PS1 and PS2 can be used to shield vertical signal lines in different columns. Shield lines PS0 and PS2 can be connected to ground potential.

[0127] At this time, as shown in b of the figure, the solid-state imaging device may be provided with semiconductor chips P31 and P32. The semiconductor chip P31 is stacked on the semiconductor chip P32.

[0128] The semiconductor chip P31 includes a semiconductor substrate 311. A photodiode PD is formed in the semiconductor substrate 311 for each pixel PIX. The photodiode PD may be provided on the back side of the semiconductor substrate 311. In this case, light may be incident on the photodiode PD from the back side of the semiconductor substrate 311. The material of the semiconductor substrate 311 may be Si, InGaAs, or InP.

[0129] The wiring layer 312 is formed on the semiconductor substrate 311. The wiring layer 312 is provided with wiring 313 embedded in the insulating layer and pad electrodes 333. The wiring layer 312 is provided with through holes 323 for interlayer connection. The pad electrodes 333 can be used for direct bonding between the chips P31 and P32.

[0130] Color filters 315 are formed on the back side of semiconductor substrate 311 for each pixel PIX. Microlenses 316 are formed on color filters 315 for each pixel PIX. Transparent resins such as acrylic or polycarbonate can be used as materials for color filters 315 and microlenses 316. Pigments can be added to color filters 315 for coloring. Color filters 315 can form, for example, a Bayer array or a quad-Bayer array. Color filters 315 can include RGB filters, complementary color filters, or white filters.

[0131] Semiconductor chip P32 includes a semiconductor substrate 321. The material of semiconductor substrate 321 can be Si, GaAs, GaN, or SiC. A logic circuit, a memory, a processor, a signal processing circuit, or an interface circuit can be formed on semiconductor chip P32. At this time, a gate electrode 320 and a wiring layer 322 are formed on semiconductor substrate 321. Gate electrode 320 is formed on semiconductor substrate 321 via a gate insulating film. For example, polycrystalline silicon with impurities introduced can be used as the material for gate electrode 320.

[0132] The gate electrode 320 may be used for a pixel transistor. The pixel transistor includes Figure 3 The transfer transistor 122, the reset transistor 123, the amplifying transistor 124 and the selecting transistor 125 are included.

[0133] The wiring layer 322 is formed on the gate electrode 320. The wiring layer 322 is provided with wiring 314 and pad electrodes 334 embedded in the insulating layer. In addition, the wiring layer 322 is provided with through-holes 324 for interlayer connection. The pad electrodes 334 can be used for direct bonding between the chips P31 and P32. Hybrid bonding can be used for direct bonding between the chips P31 and P32. At this time, the pad electrodes 333 and 334 are arranged at positions facing each other. Then, the pad electrodes 333 and 334 can be bonded to each other based on metal bonding such as Cu-Cu bonding. In addition, in the wiring layer 322, the vertical signal lines VSL1 to VSL4 and the shield lines PS0 to PS2 are arranged in parallel. Note that other wiring (for example, wiring for the control lines of the pixel transistors, etc.) can be formed in the same layer as the vertical signal lines VSL1 to VSL4 and the shield lines PS0 to PS2.

[0134] For example, a silicon oxide film can be used for the insulating layer of the wiring layers 312 and 322. As the material of the wirings 313 and 314, the vias 323 and 324, the pad electrodes 333 and 334, the vertical signal lines VSL1 to VSL4, and the shield lines PS0 to PS2, for example, metal such as Cu can be used.

[0135] Therefore, in the sixth embodiment described above, the shield line PS0 connected to the ground potential is provided between the vertical signal lines VSL3 and VSL2 connected to the pixels PIX2 and PIX3 of different colors. This makes it possible to suppress the color mixing of the signals read out from the pixels PIX2 and PIX3 of different colors in the same column. In this case, by connecting the shield lines PS0 to PS2 to the ground potential, the shielding performance of the shield lines PS0 to PS2 can be stabilized.

[0136] 7. Seventh embodiment In the sixth embodiment described above, the shield line PS0 provided between the vertical signal lines VSL3 and VSL2 connected to the pixels PIX2 and PIX3 of different colors is connected to the ground potential. In this seventh embodiment, the shield line PS0 provided between the vertical signal lines VSL3 and VSL2 connected to the pixels PIX2 and PIX3 of different colors is connected to the power supply potential.

[0137] Figure 18 7. FIG. 7 is a diagram showing a configuration example of a pixel array section provided in a solid-state image pickup device according to Embodiment 7. Note that in the diagram, a configuration example of four pixels is shown.

[0138] In the figure, shield line PS0, provided between vertical signal lines VSL3 and VSL2, is connected to the power supply potential. The remaining configuration of the imaging device of the seventh embodiment is similar to that of the imaging device of the sixth embodiment described above. In this case, by connecting shield line PS0 to the power supply potential, the wiring layer including vertical signal lines VSL1 to VSL4 can be connected to the power supply potential.

[0139] Therefore, in the seventh embodiment described above, the shield line PS0 provided between the vertical signal lines VSL3 and VSL2 connected to the pixels PIX2 and PIX3 of different colors is connected to the power supply potential. This makes it possible to ensure the shielding characteristics between the vertical signal lines VSL3 and VSL2 without connecting the shield line PS0 to the ground potential, and to alleviate restrictions on the layout of the power supply potential and the ground potential.

[0140] 8. Eighth embodiment In the seventh embodiment described above, the shield line PS0 provided between the vertical signal lines VSL3 and VSL2 connected to the pixels PIX2 and PIX3 of different colors is connected to the power supply potential. In this eighth embodiment, the shield line is divided between the vertical signal lines VSL3 and VSL2 so that the portion connected to the power supply potential is sandwiched between portions connected to the ground potential.

[0141] Figure 19 1 is a diagram showing a configuration example of a pixel array section provided in a solid-state image pickup device according to an eighth embodiment. Note that in the diagram, a configuration example of four pixels is shown.

[0142] In the figure, shield lines PS3 to PS5 are arranged between vertical signal lines VSL3 and VSL2. Shield line PS3 is connected to the power supply potential, while shield lines PS4 and PS5 are connected to the ground potential. In this case, shield line PS3 is sandwiched between shield lines PS4 and PS5 in the column direction. This allows connection to the power supply potential in the wiring layer including vertical signal lines VSL1 to VSL4, making it difficult for power supply fluctuations to be transmitted to vertical signal lines VSL3 and VSL2, thereby suppressing degradation of the power supply rejection ratio (PSRR).

[0143] Therefore, in the eighth embodiment described above, the shield lines PS3 to PS5 are arranged between the vertical signal lines VSL3 and VSL2 so that the shield line PS3 connected to the power supply potential is sandwiched between the shield lines PS4 and PS5. This makes it possible to stabilize the shielding characteristics between the vertical signal lines VSL3 and VSL2 while alleviating the restrictions on the layout of the ground potential.

[0144] 9. Ninth embodiment In the first embodiment described above, the image pickup device is provided with pixels having a fixed conversion efficiency. In this ninth embodiment, the image pickup device is provided with pixels having a switchable conversion efficiency.

[0145] Figure 20 is a diagram showing a configuration example of a pixel according to a ninth embodiment.

[0146] In the figure, the image pickup device includes pixels PIX2 instead of the pixels PIX of the above-described first embodiment. Other configurations of the image pickup device of the ninth embodiment are similar to those of the above-described first embodiment.

[0147] The pixel PIX2 is obtained by adding the switching transistor 128 to the pixel PIX of the above-described first embodiment. The other configurations of the pixel PIX2 of the ninth embodiment are similar to those of the pixel PIX of the above-described first embodiment.

[0148] The switching transistor 128 switches the conversion efficiency of the amplifying transistor 124. The switching transistor 128 is connected between the floating diffusion FD and the reset transistor 123. A switching signal FDG is applied to the gate of the switching transistor 128.

[0149] Figure 21 This is a timing diagram showing waveforms of various components during pixel readout according to the ninth embodiment. Note that the SH line represents the shutter line, and the RD line represents the read line. The SH line is executed, followed by the RD line. At this point, the SH line can serve as a reference for starting RD line accumulation.

[0150] In the figure, in row SH, the select signal SEL is set to a low level, and the select transistor 125 is turned off. During the non-selection period K1, the transfer signal TGL, the reset signal RST, and the switching signal FDG are maintained at a low level. Then, after the non-selection period K1 has elapsed, the low-efficiency P-phase readout K2 is performed. At this time, the transfer signal TGL, the reset signal RST, and the switching signal FDG rise, discharging the charge of the photodiode 121 and the floating diffusion FD, and reducing the conversion efficiency of the amplifier transistor 124.

[0151] Subsequently, in the low-efficiency P-phase readout K2, the transfer signal TGL falls, followed by the switching signal FDG and the reset signal RST. The switching signal FDG then rises again, and the AD conversion process is then performed. Here, by causing the switching signal FDG to fall once before the reset signal RST falls, the floating diffusion FD can be coupled to the switching transistor 128. This increases the potential of the floating diffusion FD and facilitates charge transfer from the photodiode 121.

[0152] Next, high-efficiency P-phase readout K3 is performed. At this time, AD conversion processing is performed while the transfer signal TGL, reset signal RST, and switching signal FDG are maintained at levels similar to those during low-efficiency P-phase readout K2.

[0153] Next, high-efficiency D-phase readout K4 is performed. At this point, transfer signal TGL rises, discharging the charge in photodiode 121. Then, transfer signal TGL falls, and A / D conversion processing is performed. Here, during high-efficiency D-phase readout K4, reset signal RST is set to a low level. Consequently, floating diffusion FD is placed in a floating state, allowing it to be coupled to transfer transistor 122. This increases the potential of floating diffusion FD, making it easier to extract charge from photodiode 121.

[0154] Next, the low-efficiency D-phase readout K5 is performed. At this time, the AD conversion process is performed while the level of the reset signal RST is maintained, and the subsequent period shifts to the non-selection period K6.

[0155] In the RD row, during the non-selection period K1, the select signal SEL, transfer signal TGL, reset signal RST, and switching signal FDG remain at a low level. Then, after the non-selection period K1 has elapsed, low-efficiency P-phase readout K2 is performed. At this time, the reset signal RST and switching signal FDG rise, discharging the charge in the floating diffusion FD and reducing the conversion efficiency in the amplifier transistor 124.

[0156] Subsequently, in the low-efficiency P-phase readout K2, the switching signal FDG falls, and subsequently the reset signal RST falls. Then, the switching signal FDG rises again, and subsequently the selection signal SEL rises, and AD conversion processing is performed. Here, by causing the switching signal FDG to fall once before the reset signal RST falls, the floating diffusion FD can be coupled to the switching transistor 128. This increases the potential of the floating diffusion FD and facilitates charge transfer from the photodiode 121.

[0157] Next, high-efficiency P-phase readout K3 is performed. At this time, the switching signal FDG falls, the conversion efficiency in the amplifier transistor 124 increases, and then AD conversion processing is performed.

[0158] Next, high-efficiency D-phase readout K4 is performed. At this point, transfer signal TGL rises, and the charge from photodiode 121 is transferred to floating diffusion FD. Transfer signal TGL then falls, and A / D conversion processing is subsequently performed. Here, during high-efficiency D-phase readout K4, reset signal RST is set to a low level. Consequently, floating diffusion FD is in a floating state, allowing it to be coupled to transfer transistor 122. This increases the potential of floating diffusion FD, making it easier to extract charge from photodiode 121.

[0159] Next, low-efficiency D-phase readout (K5) is performed. At this time, switching signal FDG rises, and the conversion efficiency in amplifier transistor 124 decreases. Subsequently, transfer signal TGL rises, and the charge in photodiode 121 is transferred to floating diffusion FD. Transfer signal TGL then falls, A / D conversion processing is performed, and the subsequent period transitions to a non-selection period (K6). By raising transfer signal TGL after switching signal FDG rises, the capacitance observed by amplifier transistor 124 can be increased. This increases the charge that can be received from photodiode 121, making it easier to extract the charge accumulated in photodiode 121.

[0160] Therefore, in the above-described ninth embodiment, the switching transistor 128 is provided to switch the capacitance of the floating diffusion FD viewed from the amplifying transistor 124. This makes it possible to switch the conversion efficiency in the amplifying transistor 124.

[0161] 9. Tenth embodiment In the ninth embodiment described above, the image pickup device is provided with pixels PIX2 that can switch conversion efficiency. In the tenth embodiment, pixels are provided with photodiodes having mutually different sensitivities.

[0162] Figure 22 is a diagram showing a configuration example of a pixel according to a tenth embodiment.

[0163] In the figure, the image pickup device includes a pixel PIX3 instead of the pixel PIX2 of the above-described ninth embodiment. Other configurations of the image pickup device of the tenth embodiment are similar to those of the above-described ninth embodiment.

[0164] The pixel PIX3 is obtained by adding the photodiode 126, the path transistor 127, and the floating diffusion FD2 to the pixel PIX2 of the ninth embodiment described above. The other configurations of the pixel PIX3 of the tenth embodiment are similar to those of the pixel PIX2 of the ninth embodiment described above.

[0165] The path transistor 127 sets a path for transferring the charge accumulated in the floating diffusion FD2 to the floating diffusion FD. The path transistor 127 is connected between the floating diffusion FD2 and a connection point between the reset transistor 123 and the switching transistor 128. A path setting signal FCG is applied to the gate of the path transistor 127.

[0166] The floating diffusion FD2 is connected between the power supply potential VDD2 and a connection point between the path transistor 127 and the photodiode 126. The planar size of the photodiode 126 can be smaller than the planar size of the photodiode 121.

[0167] Figure 23is a timing chart showing waveforms of respective portions during readout from pixels according to the tenth embodiment.

[0168] In the figure, in row SH, the select signal SEL is set to a low level, and the select transistor 125 is turned off. During the non-selection period K11, the transfer signal TGL and the path setting signal FCG remain at a low level, and the reset signal RST and the switching signal FDG remain at a high level. At this time, the sensitivity of the pixel PIX3 is increased, and the conversion efficiency in the amplifier transistor 124 is reduced. Then, after the non-selection period K11 has passed, the low-efficiency, high-sensitivity P-phase readout K12 is performed. At this time, the transfer signal TGL rises, and the charge of the photodiode 121 and the floating diffusion FD is discharged. In addition, the power supply voltage VDD2 rises and is applied to the floating diffusion FD2.

[0169] Subsequently, the transfer signal TGL falls, followed by the switching signal FDG falling, and the reset signal RST falling. The switching signal FDG then rises again, and AD conversion processing is then performed. Here, by causing the switching signal FDG to fall once before the reset signal RST falls, the floating diffusion FD can be coupled to the switching transistor 128. This increases the potential of the floating diffusion FD and facilitates charge transfer from the photodiode 121.

[0170] Next, high-efficiency high-sensitivity P-phase readout K13 is performed. At this time, AD conversion processing is performed while the transmission signal TGL, reset signal RST, switching signal FDG, and path setting signal FCG are maintained at levels similar to those after AD conversion of low-efficiency high-sensitivity P-phase readout K12.

[0171] Next, high-efficiency, high-sensitivity D-phase readout K14 is performed. At this point, transfer signal TGL rises, discharging the charge in photodiode 121. Then, transfer signal TGL falls, and A / D conversion processing is performed. During high-efficiency, high-sensitivity D-phase readout K14, reset signal RST is set to a low level. Consequently, floating diffusion FD is placed in a floating state, allowing it to be coupled to transfer transistor 122. This increases the potential of floating diffusion FD, facilitating charge extraction from photodiode 121.

[0172] Next, low-efficiency, high-sensitivity D-phase readout K15 is performed. At this time, the reset signal RST rises, and the charge of the floating diffusion FD is discharged. Then, the AD conversion process is performed while maintaining the level of the reset signal RST.

[0173] Next, low-sensitivity D-phase readout K16 is performed. At this time, the switching signal FDG falls, and then the power supply voltage VDD2 falls. Then, the switching signal FDG, the path setting signal FCG, and the power supply voltage VDD2 rise, and then AD conversion processing is performed.

[0174] Next, low-sensitivity P-phase readout K17 is executed. At this time, path setting signal FCG drops, followed by a drop in power supply voltage VDD2, and AD conversion processing is performed. In low-sensitivity P-phase readout K17, after AD conversion processing is performed, switching signal FDG drops. After low-sensitivity P-phase readout K17 is executed, the period transitions to a non-selection period K18. At this time, switching signal FDG rises.

[0175] In the RD row, during the non-selection period K11, the selection signal SEL, transfer signal TGL, and path setting signal FCG remain at a low level, and the reset signal RST and switching signal FDG remain at a high level. Then, after the non-selection period K11 has elapsed, low-efficiency, high-sensitivity P-phase readout K12 is performed. At this time, the switching signal FDG falls, followed by the reset signal RST. Then, the switching signal FDG, the selection signal SEL, and the power supply voltage VDD2 rise, and the AD conversion process is performed. Here, by causing the switching signal FDG to fall once before the reset signal RST falls, the floating diffusion FD can be coupled to the switching transistor 128. This makes it possible to increase the potential of the floating diffusion FD and facilitate charge transfer from the photodiode 121.

[0176] Next, high-efficiency and high-sensitivity P-phase readout K13 is performed. At this time, the switching signal FDG falls, the conversion efficiency in the amplifier transistor 124 increases, and then AD conversion processing is performed.

[0177] Next, high-efficiency, high-sensitivity D-phase readout K14 is performed. At this point, the select signal SEL falls, the transfer signal TGL rises, and the charge from the photodiode 121 is transferred to the floating diffusion FD. Then, the select signal SEL rises and the transfer signal TGL falls, and A / D conversion processing is performed. Here, during high-efficiency, high-sensitivity D-phase readout K14, the reset signal RST is set to a low level. Consequently, the floating diffusion FD is in a floating state, allowing it to be coupled to the transfer transistor 122. This increases the potential of the floating diffusion FD, making it easier to extract charge from the photodiode 121.

[0178] Next, low-efficiency, high-sensitivity D-phase readout K15 is performed. At this point, the switching signal FDG rises, and the conversion efficiency in the amplifier transistor 124 decreases. Subsequently, the select signal SEL falls, the transfer signal TGL rises, and the charge in the photodiode 121 is transferred to the floating diffusion FD. Then, the select signal SEL rises and the transfer signal TGL falls, and the A / D conversion process is performed. Here, by raising the transfer signal TGL after the switching signal FDG rises, the capacitance seen by the amplifier transistor 124 can be increased. This increases the charge that can be received from the photodiode 121, making it easier to extract the charge accumulated in the photodiode 121.

[0179] Next, low-sensitivity D-phase readout K16 is performed. At this point, reset signal RST rises, discharging the charge in floating diffusion FD2. Here, reset signal RST rises, followed by select signal SEL falling. Subsequently, reset signal RST falls, followed by select signal SEL rising. Then, path setting signal FCG rises, and A / D conversion processing is performed.

[0180] Next, low-sensitivity P-phase readout K17 is performed. At this time, the reset signal RST rises, and the charge of the floating diffusion FD2 is discharged. Here, when the reset signal RST rises, the selection signal SEL falls. Subsequently, the path setting signal FCG falls, and then the reset signal RST falls. Subsequently, the selection signal SEL rises, and the path setting signal FCG rises. Then, the selection signal SEL rises and the path setting signal FCG rises, and then AD conversion processing is performed. Subsequently, the setting signal RST rises, and then the selection signal SEL falls. Subsequently, the path setting signal FCG falls, and then the power supply voltage VDD2 falls. After the low-sensitivity P-phase readout K17 is performed, the period transitions to a non-selection period K18.

[0181] Therefore, in the above-described tenth embodiment, by providing the two photodiodes 121 and 126 having mutually different sizes in the pixel PIX3, the dynamic range can be improved.

[0182] 11. Eleventh Embodiment In the first embodiment described above, the vertical signal lines VSL1 to VSL4 and the pixels IX1 to PIX12 are connected so that the arrangement order of the four vertical signal lines VSL1 to VSL4 and the arrangement order of the pixels PIX1 to PIX12 provided in the column COL are different from each other. In this eleventh embodiment, semiconductor chips forming a solid-state imaging device provided with a pixel array section in which pixels are arranged in a matrix are stacked.

[0183] Figure 24is a perspective view showing a stacking example of a solid-state imaging device according to an eleventh embodiment.

[0184] In this figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0185] The pixel array section 923 is formed on the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row direction and the column direction. The pixels 931 may be Figure 3 The pixel PIX in can be Figure 20 Pixel PIX2 in, or it can be Figure 22 The connection between each pixel 931 and the vertical signal line can be any of the connections in the first to fourth embodiments described above. A pad electrode 932 and a through-hole electrode 933 are formed around the pixel array portion 923. The through-hole electrode 933 can penetrate the semiconductor chip 922 and electrically connect the semiconductor chips 921 and 922 to each other.

[0186] The peripheral circuit 924 is formed in the semiconductor chip 921. The peripheral circuit 924 includes a column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillation circuit 928. The column readout circuit 925 and the column ADC 926 can be formed to correspond to positions on both sides of the pixel array section 923 in the column direction. In addition, any of the vertical signal lines according to the first to fourth embodiments described above can be formed in the semiconductor chip 921. In addition, any of the shield lines according to the fifth to eighth embodiments described above can be formed in the semiconductor chip 921.

[0187] Therefore, in the above-described eleventh embodiment, the semiconductor chip 922 having the pixel array portion 923 formed therein is stacked on the semiconductor chip 921 having the peripheral circuit 924 formed therein. This makes it possible to improve the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip forming the solid-state imaging device.

[0188] 12. Application Examples of Mobile Objects The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, and a robot.

[0189] Figure 25 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0190] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 25 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional components of the integrated control unit 12050.

[0191] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating drive force for the vehicle; a drive force transmission mechanism for transmitting drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating braking force for the vehicle.

[0192] The body system control unit 12020 controls the operation of various devices attached to the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a portable device serving as a key substitute or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, and lights.

[0193] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle having the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can detect objects such as people, vehicles, obstacles, signs, or symbols on the road surface, or detect the distance to such objects.

[0194] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as information regarding the measured distance. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0195] The in-vehicle information detection unit 12040 detects information about the vehicle interior. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 that detects the driver's condition. For example, the driver status detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0196] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on information about the interior or exterior of the vehicle (this information is obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040), and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, vehicle-to-vehicle distance-based following, vehicle speed maintenance, vehicle collision warning, or vehicle lane departure warning.

[0197] In addition, the microcomputer 12051 can perform collaborative control with the intention of achieving automatic driving (making the vehicle drive automatically without relying on the driver's operation, etc.) by controlling the driving force generating device, steering mechanism or braking device, etc. based on information about the inside or outside of the vehicle (the information is obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040).

[0198] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information about the exterior of the vehicle, which information is obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beam to low beam based on the position of a preceding vehicle or an oncoming vehicle detected by the exterior information detection unit 12030.

[0199] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device that can visually or auditorily notify the vehicle's passengers or the outside of the vehicle of information. Figure 25 In the example of FIG, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0200] Figure 26 12031 is a diagram showing an example of the installation position of the camera unit 12031.

[0201] exist Figure 26 , the camera unit 12031 includes camera units 12101 , 12102 , 12103 , 12104 and 12105 .

[0202] Camera units 12101, 12102, 12103, 12104, and 12105 are located, for example, on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, as well as on the upper portion of the windshield inside the vehicle. Camera unit 12101 located on the front nose and camera unit 12105 located on the upper portion of the windshield inside the vehicle primarily capture images of the front of vehicle 12100. Camera units 12102 and 12103 located on the side mirrors primarily capture images of the sides of vehicle 12100. Camera unit 12104 located on the rear bumper or rear door primarily captures images of the rear of vehicle 12100. Camera unit 12105 located on the upper portion of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0203] By the way, Figure 26 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, which is located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, which are located on the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, which is located on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100, viewed from above, is obtained.

[0204] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0205] For example, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the temporal change in distance (relative speed with respect to vehicle 12100) based on the distance information obtained from imaging units 12101 to 12104, thereby extracting the closest three-dimensional object as the preceding vehicle. Specifically, this three-dimensional object is located on the travel path of vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as vehicle 12100. Furthermore, microcomputer 12051 can set a following distance to be maintained between the vehicle and the preceding vehicle, and execute automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control), etc. Thus, cooperative control such as automatic driving, which is intended to enable the vehicle to travel autonomously without relying on driver operation, can be executed.

[0206] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify 3D object data regarding 3D objects into 3D object data for two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, extract the classified 3D object data, and use the extracted 3D object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those that the driver of the vehicle 12100 can visually identify and those that are difficult for the driver of the vehicle 12100 to visually identify. The microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value, indicating a potential collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or display unit 12062, and the drive system control unit 12010 executes forced deceleration or evasive steering. The microcomputer 12051 can thus assist driving to avoid collisions.

[0207] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether a pedestrian exists in images captured by the imaging units 12101 to 12104. This identification of pedestrians can be performed, for example, by a program that extracts feature points from images captured by the infrared cameras 12101 to 12104 and then performs pattern matching on a series of feature points representing the object's outline to determine whether the pedestrian is present. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasis. The audio / video output unit 12052 can also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0208] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied to the imaging unit 12031 and the like in the above-described configuration. Specifically, for example, the imaging devices of the first to twentieth embodiments described above can be applied to the imaging unit 12031 and the like. By applying the technology of the present disclosure to the vehicle control system 12000, crosstalk between signals read out from the pixels of the pixel array unit can be reduced, and the image quality of the imaging unit 12031 can be improved.

[0209] Note that the above-described embodiments illustrate examples of implementing the present technology, and the matters in the embodiments correspond to the matters specifying the present invention within the scope of the claims. Similarly, the matters specifying the present invention within the scope of the claims correspond to the matters given the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be implemented by applying various modifications to the embodiments without departing from the gist thereof. In addition, the effects described in this specification are merely examples and are not limiting, and other effects can be provided.

[0210] It should be noted that the present technology can also adopt the following configurations. (1) A camera device comprising: pixels arranged in a matrix in row and column directions; and a plurality of signal lines configured to simultaneously transmit signals read out from pixels belonging to the same column and different rows in the column direction, In at least one column, the signal lines and the pixels are connected such that an arrangement order of the signal lines and an arrangement order of the pixels are different from each other. (2) The imaging device according to (1), comprising: A shielding line is provided between the signal lines. (3) The imaging device according to (2), The shielding line is provided between adjacent signal lines connected to pixels of different colors. (4) The imaging device according to (2) or (3), Wherein, at least one of the shielding lines is connected to the ground potential. (5) The imaging device according to (2) or (3), Wherein, at least one of the shielding lines is connected to a power supply potential. (6) The imaging device according to (2) or (3), Here, at least one of the shield lines is divided so that a portion connected to a power supply potential is sandwiched between portions connected to a ground potential. (7) The imaging device according to any one of (1) to (6), The pixels include pixels of different colors alternately arranged in the column direction. (8) The imaging device according to any one of (1) to (7), Here, pixels of the same color configured to be read simultaneously in each column are connected to signal lines adjacent to each other. (9) The imaging device according to any one of (1) to (8), Wherein, the signal line includes: a first signal line connected to a first pixel; a second signal line connected to a second pixel adjacent to the first pixel in the column direction; and A third signal line is connected to a third pixel and is located between the first signal line and the second pixel. (10) The imaging device according to any one of (1) to (9), The pixels include a first pixel, a second pixel, and a third pixel sequentially arranged in the column direction. The signal lines include a first signal line, a second signal line, and a third signal line sequentially arranged in the row direction, the first pixel is connected to the first signal line, The second pixel is connected to the third signal line, and The third pixel is connected to the second signal line. (11) The imaging device according to (10), The first pixel and the third pixel are pixels of the same color, and the first pixel and the second pixel are pixels of different colors. (12) The imaging device according to (10) or (11), Wherein, signals are read out from the first pixel, the second pixel, and the third pixel at the same time. (13) The imaging device according to any one of (1) to (8), The adjacent pixels are connected to the same signal line. (14) The imaging device according to any one of (1) to (8), Wherein, the signal line includes: a first signal line connected to a first pixel and a second pixel adjacent to each other in the column direction; a second signal line connected to a third pixel and a fourth pixel adjacent to each other in the column direction; and a third signal line connected to a fifth pixel and a sixth pixel adjacent to each other in the column direction and located between the first signal line and the second pixel. (15) The imaging device according to any one of (1) to (8), The pixels include a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel sequentially arranged in the column direction. The signal lines include a first signal line, a second signal line, and a third signal line sequentially arranged in the row direction, The first pixel and the second pixel are connected to the first signal line, The third pixel and the fourth pixel are connected to the third signal line, and The fifth pixel and the sixth pixel are connected to the second signal line. (16) The imaging device according to (15), wherein, at a first moment, signals are read out from the first pixel, the third pixel, and the fifth pixel simultaneously, and Signals are read out from the second pixel, the fourth pixel, and the sixth pixel simultaneously at a second time. (17) The imaging device according to (15) or (16), The first pixel, the third pixel and the fifth pixel are pixels of the same color. The second pixel, the fourth pixel and the sixth pixel are pixels of the same color, and The first pixel and the second pixel are pixels of different colors. (18) A camera method comprising: Reading out signals from pixels belonging to the same column but different rows among pixels arranged in a matrix in the row and column directions; and Signals read out from pixels belonging to the same column and different rows are simultaneously transmitted in the column direction by a plurality of signal lines connected to the pixels, and an arrangement order of the plurality of signal lines and an arrangement order of the pixels are different from each other. (19) The imaging method according to (18), The pixels adjacent to each other in the column direction are pixels of different colors. (20) The imaging method according to (18) or (19), The readout timing of each pixel is set so that pixels of different colors are read out at different timings in each column. Reference Signs List

[0211] 100 camera devices 101 Optical System 102 Solid-state imaging device 103 Camera Control Unit 104 image processing unit 105 storage units 106 display units 107 operating unit 108 bus 111 pixel array unit 112 vertical scanning circuit 113 column readout circuit 114 columns of signal processing units 115 horizontal scanning circuit 116 control circuit 121 photodiode 122 pass transistor 123 reset transistor 124 amplifier transistors 125 selection transistor PIX, PIX1 to PIX12 pixels HSL horizontal drive line VSL, VSL1 to VSL4 vertical signal lines Rows ROW1 to ROW12 COL column

Claims

1. A camera device, comprising: Pixels are arranged in a matrix in row and column directions; as well as a plurality of signal lines configured to simultaneously transmit signals read out from pixels belonging to the same column and different rows in the column direction, In at least one column, the signal lines and the pixels are connected such that an arrangement order of the signal lines and an arrangement order of the pixels are different from each other.

2. The camera device according to claim 1, comprising: A shielding line is provided between the signal lines.

3. The imaging device according to claim 1, in, The shield line is provided between mutually adjacent signal lines connected to pixels of different colors.

4. The imaging device according to claim 1, in, At least one of the shielding lines is connected to ground potential.

5. The imaging device according to claim 1, in, At least one of the shielding lines is connected to a power supply potential.

6. The imaging device according to claim 1, in, At least one of the shield lines is divided so that a portion connected to a power supply potential is sandwiched between portions connected to a ground potential.

7. The imaging device according to claim 1, in, The pixels include pixels of different colors alternately arranged in the column direction.

8. The imaging device according to claim 1, in, Pixels of the same color configured to be read simultaneously in each column are connected to signal lines adjacent to each other.

9. The imaging device according to claim 1, in, The signal line includes: a first signal line connected to a first pixel; a second signal line connected to a second pixel adjacent to the first pixel in the column direction; and A third signal line is connected to a third pixel and is located between the first signal line and the second pixel.

10. The imaging device according to claim 1, in, The pixels include a first pixel, a second pixel, and a third pixel sequentially arranged in the column direction. The signal lines include a first signal line, a second signal line, and a third signal line sequentially arranged in the row direction, the first pixel is connected to the first signal line, The second pixel is connected to the third signal line, and The third pixel is connected to the second signal line.

11. The imaging device according to claim 10, in, The first pixel and the third pixel are pixels of the same color, and the first pixel and the second pixel are pixels of different colors.

12. The imaging device according to claim 10, in, Signals are read out from the first pixel, the second pixel, and the third pixel at the same time.

13. The imaging device according to claim 1, in, The pixels adjacent to each other are connected to the same signal line.

14. The imaging device according to claim 1, in, The signal line includes: a first signal line connected to a first pixel and a second pixel adjacent to each other in the column direction; a second signal line connected to a third pixel and a fourth pixel adjacent to each other in the column direction; and a third signal line connected to a fifth pixel and a sixth pixel adjacent to each other in the column direction and located between the first signal line and the second pixel.

15. The imaging device according to claim 1, in, The pixels include a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel sequentially arranged in the column direction. The signal lines include a first signal line, a second signal line, and a third signal line sequentially arranged in the row direction, The first pixel and the second pixel are connected to the first signal line, The third pixel and the fourth pixel are connected to the third signal line, and The fifth pixel and the sixth pixel are connected to the second signal line.

16. The imaging device according to claim 15, in, At a first moment, signals are read out from the first pixel, the third pixel, and the fifth pixel simultaneously, and Signals are read out from the second pixel, the fourth pixel, and the sixth pixel simultaneously at a second time.

17. The imaging device according to claim 15, in, The first pixel, the third pixel, and the fifth pixel are pixels of the same color, The second pixel, the fourth pixel and the sixth pixel are pixels of the same color, and The first pixel and the second pixel are pixels of different colors.

18. A camera method, comprising: Reading signals from pixels belonging to the same column but different rows among pixels arranged in a matrix in the row and column directions; and Signals read out from pixels belonging to the same column and different rows are simultaneously transmitted in the column direction by a plurality of signal lines connected to the pixels, and an arrangement order of the plurality of signal lines and an arrangement order of the pixels are different from each other.

19. The imaging method according to claim 18, in, Pixels adjacent to each other in the column direction are pixels of different colors.

20. The imaging method according to claim 18, in, The readout timing of each pixel is set so that different color pixels are read out at mutually different timings in each column.

Images