Semiconductor device

Abstract

Provided is a semiconductor device provided with: a plurality of trench parts which are arranged in a preset arrangement direction on the front surface side of a semiconductor substrate, and which have a repeating structure in which gate trench parts and dummy trench parts are repeated at a preset cycle in the arrangement direction; a drift region of a first conductivity type provided on the semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; and a trench bottom region of the second conductivity type provided below the gate trench portion and having a lower doping concentration than that of the base region, the trench bottom region being provided below the emitter region, the length of the trench bottom region in the arrangement direction being shorter than the length of the repeating structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Patent Document 1 describes an “IGBT having dV / dt controllability”.

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Publication No. 2019-91892 Patent Document 2: Japanese Patent Application Laid-Open No. 2004-6647 Patent Document 3: Japanese Patent Application Laid-Open No. 2015-195307 Patent Document 4: Japanese Patent Application Publication No. 2019-110288 Patent Document 5: International Publication No. 2022 / 158053 Patent Document 6: Japanese Patent No. 6472714 Summary of the Invention

[0004] In an embodiment of the present invention, a semiconductor device is provided, comprising: a plurality of groove portions arranged along a predetermined arrangement direction on the front side of a semiconductor substrate, and having a repeated structure in which gate groove portions and dummy groove portions are repeated according to a predetermined period in the arrangement direction; a drift region of a first conductive type arranged in the semiconductor substrate; a base region of a second conductive type arranged above the drift region; an emitter region of a first conductive type arranged above the base region and having a higher doping concentration than that of the drift region; a contact region of a second conductive type arranged above the base region and having a higher doping concentration than that of the base region; and a trench bottom region of a second conductive type arranged below the gate trench portion and having a lower doping concentration than that of the base region, the trench bottom region being arranged below the emitter region, and the length of the trench bottom region in the arrangement direction being shorter than the length of the repeated structure.

[0005] In the above semiconductor device, the trench bottom region may be in contact with the gate trench portion.

[0006] In any of the above semiconductor devices, the trench bottom region may be in contact with the dummy trench portion adjacent to the gate trench portion.

[0007] Any of the above semiconductor devices may include a trench bottom formation region in which the trench bottom region is formed when viewed from above. Any of the above semiconductor devices may include a trench bottom non-formation region in which the trench bottom region is not formed when viewed from above.

[0008] In any of the above-mentioned semiconductor devices, the trench bottom formation region may cover the emitter region provided in contact with the gate trench portion in a plan view.

[0009] In any of the above semiconductor devices, in a mesa portion adjacent to the gate trench portion, the emitter region and the contact region may be repeatedly arranged along an extending direction of the plurality of trench portions. The trench bottom formation region may cover the emitter region, and the emitter region may be provided extending along the extending direction in the mesa portion adjacent to the gate trench portion and in contact with the gate trench portion in a plan view.

[0010] In any of the above semiconductor devices, in a plan view, a distance between an end side of the emitter region located outermost in the extending direction and an end side of the trench bottom formation region in the extending direction may be 1.0 μm or more and 10.0 μm or less.

[0011] In any of the above-mentioned semiconductor devices, the emitter region may be provided in a mesa portion adjacent to the gate trench portion, extending along the extending direction of the plurality of trench portions so as to contact the gate trench portion and not contact the dummy trench portion. The trench bottom formation region may cover the emitter region, and the emitter region may be provided in a mesa portion adjacent to the gate trench portion, extending along the extending direction and contacting the gate trench portion in a plan view.

[0012] In any of the above semiconductor devices, in a plan view, a distance between an edge of the emitter region in the extending direction and an edge of the trench bottom forming region covering the emitter region in the extending direction may be 1.0 μm or more and 5.0 μm or less.

[0013] In any of the above semiconductor devices, in a mesa portion adjacent to the gate trench portion, the emitter region and the contact region may be repeatedly arranged along the extending direction of the plurality of trench portions. In a mesa portion adjacent to the gate trench portion, the trench bottom formation region and the trench bottom non-formation region may be repeatedly arranged along the extending direction. The repeatedly arranged trench bottom formation regions may overlap the repeatedly arranged emitter regions in a plan view.

[0014] In any of the above semiconductor devices, in a plan view, a distance between an edge of the emitter region in the extending direction and an edge of the trench bottom forming region covering the emitter region in the extending direction may be 1.0 μm to 2.5 μm.

[0015] In any of the above-mentioned semiconductor devices, the plurality of trench portions may include two adjacent dummy trench portions, and a mesa portion sandwiched between the two dummy trench portions may be the trench bottom non-formation region.

[0016] In any of the above semiconductor devices, the emitter region may be further provided in a mesa portion sandwiched between the two dummy trench portions. The trench bottom non-formation region may cover the emitter region provided in the mesa portion sandwiched between the two dummy trench portions in a plan view.

[0017] In any of the above-mentioned semiconductor devices, the plurality of trench portions may have the repeated structure in which the dummy trench portion, the gate trench portion, and the dummy trench portion are repeated in this order along the arrangement direction.

[0018] In any of the above-mentioned semiconductor devices, the plurality of trench portions may have the repeated structure obtained by repeating the dummy trench portion, the dummy trench portion, the gate trench portion, the gate trench portion, the dummy trench portion, and the dummy trench portion in this order along the arrangement direction.

[0019] In any of the above semiconductor devices, the doping concentration of the trench bottom region may be greater than or equal to 1% and less than or equal to 10% of the doping concentration of the base region.

[0020] It should be noted that the above summary of the invention does not list all the features of the present invention, and subcombinations of these feature groups may also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 An example of the upper surface of the semiconductor device 100 is shown.

[0022] Figure 2A Show Figure 1 An example of region R in .

[0023] Figure 2B Show Figure 2A An example of the a-a' section in .

[0024] Figure 3 A region R in a modified example of the semiconductor device 100 is shown.

[0025] Figure 4A A region R in a modified example of the semiconductor device 100 is shown.

[0026] Figure 4B Show Figure 4A An example of the b-b' section in .

[0027] Figure 5 A region R in a modified example of the semiconductor device 100 is shown.

[0028] Figure 6A A region R in a modified example of the semiconductor device 100 is shown.

[0029] Figure 6B Show Figure 6A An example of the c-c' section in.

[0030] Figure 7 A region R in a modified example of the semiconductor device 100 is shown.

[0031] Figure 8A A region R in a modified example of the semiconductor device 100 is shown.

[0032] Figure 8B Show Figure 8A An example of a d-d' section in .

[0033] Explanation of symbols 10···Semiconductor substrate, 12···Emitter region, 14···Base region, 15···Contact region, 16···Accumulation region, 17···Well region, 18···Drift region, 20···Buffer region, 21···Front surface, 22···Collector region, 23···Back surface, 24···Collector electrode, 25···Connection portion, 30···Dummy trench portion, 31···Extension portion, 32···Dummy insulating film, 33···Connection portion, 34···Dummy conductive portion, 38···Interlayer insulating film, 40···Gate trench portion, 41···Extension portion points, 42···gate insulating film, 43···connecting portion, 44···gate conductive portion, 50···gate wiring portion, 52···emitter electrode, 54···contact hole, 55···contact hole, 56···contact hole, 60···trench bottom region, 62···trench bottom formation region, 64···trench bottom non-formation region, 71···mesa portion, 100···semiconductor device, 102···end side, 112···gate pad, 120···active portion, 140···edge terminal structure portion, 151···back side lifetime control region DETAILED DESCRIPTION

[0034] The present invention will be described below by way of embodiments of the invention, but the following embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the technical aspects of the invention.

[0035] In this specification, one side parallel to the depth direction of a semiconductor substrate is referred to as "upper," and the other side is referred to as "lower." One of the two principal surfaces of a substrate, layer, or other component is referred to as the upper surface, and the other is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the orientation when a semiconductor device is mounted.

[0036] In this specification, the X-axis, Y-axis, and Z-axis are sometimes used to describe technical matters. These axes simply determine the relative positions of components and do not define specific directions. For example, the Z-axis is not limited to indicating the height relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is indicated without specifying a positive or negative sign, it refers to a direction parallel to the +Z and -Z axes.

[0037] In this specification, the axes perpendicular to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, is sometimes referred to as the horizontal direction.

[0038] In this specification, the term "same" or "equal" may include a case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0039] In this specification, the conductivity type of the impurity-doped region is described as P-type or N-type. In this specification, the term "impurity" sometimes specifically refers to either an N-type donor or a P-type acceptor, and is sometimes referred to as a dopant. In this specification, "doping" refers to the introduction of donors or acceptors into a semiconductor substrate to produce an N-type or P-type conductivity semiconductor.

[0040] In this specification, the doping concentration refers to the concentration of donors or acceptors in thermal equilibrium. In this specification, the net doping concentration refers to the actual concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, if the donor concentration is N D And the acceptor concentration is set to N A , then the net doping concentration at any position is N D -N A In this specification, the net doping concentration may be described simply as the doping concentration.

[0041] In this specification, when described as P+ type or N+ type, it means the doping concentration is higher than the doping concentration of P type or N type, and when described as P- type or N- type, it means the doping concentration is lower than the doping concentration of P type or N type. In addition, when described as P++ type or N++ type in this specification, it means the doping concentration is higher than the doping concentration of P+ type or N+ type, and when described as P- type or N- type, it means the doping concentration is lower than the doping concentration of P- type or N- type.

[0042] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value can be used as the concentration of the donor, acceptor, or net doping in that region. When the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region can be used as the concentration of the donor, acceptor, or net doping in that region.

[0043] In each embodiment, an example is shown in which the first conductivity type is set to N type and the second conductivity type is set to P type. However, the first conductivity type may be set to P type and the second conductivity type may be set to N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are opposite in polarity.

[0044] The SI system of units is used in this manual. In this manual, distances and lengths are sometimes expressed in cm (centimeter). In such cases, calculations can be performed in m (meter). Regarding numerical representations of powers of 10, for example, 1E+16 represents 1×10 16 , 1E-16 means 1×10 -16 .

[0045] Figure 1 FIG. 1 shows an example of the upper surface of the semiconductor device 100 . The semiconductor device 100 of this example includes a gate wiring portion 50 , a gate pad 112 , an active portion 120 , and an edge termination structure portion 140 .

[0046] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate or a silicon carbide substrate. In this example, the semiconductor substrate 10 is a silicon substrate. It should be noted that in this specification, when referred to as viewed from above, this refers to viewing from the top surface of the semiconductor substrate 10. The semiconductor substrate 10 has an edge 102. Furthermore, as described later, the semiconductor substrate 10 has a front surface 21 and a back surface 23.

[0047] The active portion 120 is a region where the main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode 52 is provided above the active portion 120, but is omitted in this figure.

[0048] The gate pad 112 is provided above the semiconductor substrate 10. A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate trench portion 40 of the active portion 120. The gate trench portion 40 will be described later.

[0049] In a plan view, the gate wiring portion 50 is provided closer to the edge 102 of the semiconductor substrate 10 than the active portion 120. The gate wiring portion 50 connects the gate pad 112 and the gate trench portion 40.

[0050] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. In a plan view, the edge termination structure 140 is located closer to the edge 102 of the semiconductor substrate 10 than the gate wiring portion 50. The edge termination structure 140 mitigates electric field concentration on the front surface 21 of the semiconductor substrate 10. The edge termination structure 140 can include at least one of a guard ring provided in an annular shape to surround the active portion 120, a field plate, and a surface electric field reduction device.

[0051] Figure 2A Show Figure 1 The semiconductor device 100 can be constructed by repeatedly arranging the structure shown in this figure in the positive and negative directions of the X axis. However, Figure 1 As shown, the gate wiring portion 50 and the edge termination structure portion 140 may be provided at the ends in the positive direction and the negative direction of the X-axis.

[0052] The semiconductor device 100 may include a transistor such as an IGBT. In this example, the semiconductor device 100 is an IGBT. It should be noted that the semiconductor device 100 may be a reverse blocking type or a reverse conducting type IGBT, or may be another transistor such as a MOSFET.

[0053] The semiconductor device 100 of this example includes a dummy trench portion 30, a gate trench portion 40, a gate wiring portion 50, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example includes an emitter electrode 52 disposed above the front surface 21 of the semiconductor substrate 10. Furthermore, the semiconductor device 100 of this example includes a trench bottom region 60 disposed below the gate trench portion 40. The trench bottom region 60 is an area that is not exposed on the front surface 21 of the semiconductor substrate 10. However, in this figure, the area where the trench bottom region 60 is disposed is indicated by oblique lines when viewed from above.

[0054] The emitter electrode 52 and the gate wiring portion 50 are provided above the semiconductor substrate 10 via the interlayer insulating film 38. The interlayer insulating film 38 is formed on the Figure 2A Contact holes 54, 55, and 56 are provided through interlayer insulating film 38. Emitter electrode 52 is provided above gate trench 40, dummy trench 30, emitter region 12, base region 14, contact region 15, and well region 17. Gate wiring section 50 is provided above well region 17.

[0055] The emitter electrode 52 and gate wiring portion 50 are formed from a material containing metal. At least a portion of the emitter electrode 52 can be formed from a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate wiring portion 50 can be formed from a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and gate wiring portion 50 can include a barrier metal layer made of titanium or a titanium compound below the aluminum or other metal layer. The emitter electrode 52 and gate wiring portion 50 are provided separately from each other.

[0056] In active portion 120, contact holes 54 are formed above each of emitter region 12 and contact region 15. Contact holes 54 are not provided above well regions 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in interlayer insulating film 38. One or more contact holes 54 can be provided to extend along the extending direction of the plurality of trench portions.

[0057] The contact hole 55 electrically connects the gate wiring portion 50 to the gate conductive portion in the active portion 120 via the connection portion 25. A plug layer made of tungsten or the like may be formed inside the contact hole 55.

[0058] The contact hole 56 connects the emitter electrode 52 to the dummy conductive portion in the dummy trench portion 30 via the connection portion 25. A plug layer made of tungsten or the like may be formed inside the contact hole 56.

[0059] The connection portion 25 is connected to the emitter electrode 52 or the gate wiring portion 50. In one example, the connection portion 25 is provided between the gate wiring portion 50 and the gate conductive portion. The connection portion 25 in this example can be provided to extend along the X-axis direction and be electrically connected to the gate conductive portion. The connection portion 25 can also be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon doped with N-type impurities (N+). The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0060] The dummy trench portion 30 is provided on the front surface 21 side of the semiconductor substrate 10. The dummy trench portion 30 is arranged along a predetermined alignment direction (in this example, the X-axis direction) on the front surface 21 side of the semiconductor substrate 10. The dummy trench portion 30 is electrically connected to the emitter electrode 52. The dummy trench portion 30 may include two extending portions 31 extending parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the alignment direction (in this example, the Y-axis direction), and a connecting portion 33 connecting the two extending portions 31.

[0061] It is preferable that at least a portion of the connection portion 33 is formed in a curved shape. By connecting the ends of the two extension portions 31 of the dummy groove portion 30 , the electric field concentration at the ends of the extension portion 31 can be alleviated.

[0062] The gate trench portion 40 is provided on the front surface 21 side of the semiconductor substrate 10. The gate trench portion 40 is arranged along a predetermined arrangement direction (in this example, the X-axis direction) on the front surface 21 side of the semiconductor substrate 10. The gate trench portion 40 may include two extending portions 41 extending parallel to the front surface 21 of the semiconductor substrate 10 and along an extension direction perpendicular to the arrangement direction (in this example, the Y-axis direction), and a connecting portion 43 connecting the two extending portions 41.

[0063] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, the electric field concentration at the ends of the extension portions 41 can be alleviated.

[0064] The semiconductor device 100 of this embodiment includes a plurality of trenches arranged along a predetermined arrangement direction (in this embodiment, the X-axis direction) on the front surface 21 of the semiconductor substrate 10. The plurality of trenches have a repetitive structure in which gate trenches 40 and dummy trenches 30 are repeated at a predetermined period in the arrangement direction.

[0065] The plurality of trenches in this example have a repeated structure in which dummy trenches 30, gate trenches 40, and dummy trenches 30 are arranged in this order in the arrangement direction (the X-axis direction in this example). In other words, semiconductor device 100 in this example has gate trenches 40 and dummy trenches 30 in a ratio of 1:2.

[0066] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 may be greater than the ratio of the dummy trench portion 30, or the ratio of the dummy trench portion 30 may be the same as the ratio of the gate trench portion 40. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 1:1, 1:5, or 3:2.

[0067] It should be noted that the period of the repeating structure of the plurality of trench portions can be determined based on the repetition of the extensions 41 of the gate trench portion 40 and the extensions 31 of the dummy trench portion 30. For example, the semiconductor device 100 of this example has a repeating structure consisting of an annular gate trench portion 40, an annular dummy trench portion 30 surrounded by the annular gate trench portion 40, and an annular dummy trench portion 30 not surrounded by the annular gate trench portion 40, with a period consisting of six extensions. On the other hand, if only the extensions are considered, the semiconductor device 100 has a repeating structure in which the dummy trench portion 30, the gate trench portion 40, and the dummy trench portion 30 are repeated in this order, with a period consisting of three extensions.

[0068] Thus, the period of the repetitive structure of the plurality of grooves can be the minimum period of the repetitive structure of the extension portions of the plurality of grooves. That is, the length of the repetitive structure of the plurality of grooves in this example is the length Wp shown in the figure.

[0069] The mesa portion 71 is provided adjacent to the trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion refers to a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions and may be a portion extending from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion.

[0070] In active portion 120, mesa portion 71 is provided adjacent to at least one of dummy trench portion 30 and gate trench portion 40. Mesa portion 71 has emitter region 12, base region 14, contact region 15, and well region 17 on front surface 21 of semiconductor substrate 10.

[0071] The base region 14 is a region of the second conductivity type provided above the drift region 18 described later. As an example, the base region 14 in this example is of P-type.

[0072] The emitter region 12 is a region of the first conductivity type that is arranged above the base region 14 and has a doping concentration higher than that of the drift region 18. As an example, the emitter region 12 in this example is of N+ type. An example of a dopant for the emitter region 12 is arsenic (As). On the front side 21, the emitter region 12 is arranged in contact with the gate trench portion 40. The emitter region 12 can be arranged to extend from one of the two trench portions to the other trench portion in the X-axis direction. The emitter region 12 is also arranged below the contact hole 54. A high-concentration portion having a higher doping concentration than that of other portions can also be provided in the portion of the emitter region 12 exposed below the contact hole 54.

[0073] In addition, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0074] The contact region 15 is a region of the second conductivity type that is arranged above the base region 14 and has a higher doping concentration than the doping concentration of the base region 14. As an example, the contact region 15 of this example is of P+ type. The contact region 15 of this example is arranged on the front side 21. The contact region 15 can be arranged from one of the two groove portions to the other groove portion along the X-axis direction. The contact region 15 may or may not be in contact with the gate groove portion 40 or the dummy groove portion 30. The contact region 15 of this example is in contact with the dummy groove portion 30 and the gate groove portion 40. The contact region 15 is also arranged below the contact hole 54. A high-concentration portion with a higher doping concentration than the doping concentration of other portions may also be provided in the portion of the contact region 15 exposed below the contact hole 54.

[0075] In the mesa portion 71 adjacent to the gate trench 40, the emitter regions 12 and contact regions 15 may be arranged repeatedly along the extending direction of the multiple trenches (in this example, the Y-axis direction). In the mesa portion 71 sandwiched between two adjacent dummy trenches 30, the emitter regions 12 and contact regions 15 may also be arranged repeatedly along the extending direction of the multiple trenches. In this example, in all mesa portions 71 shown, the emitter regions 12 and contact regions 15 are arranged repeatedly along the extending direction of the multiple trenches.

[0076] Well region 17 is a second conductivity type region provided above drift region 18 . As an example, well region 17 in this example is of P+ type. The diffusion depth of well region 17 may be deeper than the depths of gate trench 40 and dummy trench 30 .

[0077] The trench bottom region 60 is a region of the second conductivity type disposed below the gate trench portion 40 and having a doping concentration lower than that of the base region 14. As an example, the trench bottom region 60 in this example is of P-type. The doping concentration of the trench bottom region 60 may be greater than 1% and less than 10% of the doping concentration of the base region 14. Providing the trench bottom region 60 increases the gate-collector capacitance and reduces the dV / dt during switching. Thus, since the gate resistance can be reduced when the dV / dt is designed to maintain a constant value, the dI / dt can be increased, thereby reducing the switching loss of the semiconductor device 100.

[0078] The trench bottom region 60 may be disposed below the dummy trench portion 30 or may not be disposed below the dummy trench portion 30. In this embodiment, the trench bottom region 60 is also partially disposed below the dummy trench portion 30.

[0079] If the collector-emitter voltage of the semiconductor device 100 increases, the electric field at the bottom of the gate trench portion 40 becomes stronger, sometimes causing avalanche breakdown. If avalanche breakdown occurs at the bottom of the gate trench portion 40, the charge generated by the avalanche breakdown is trapped by the gate insulating film, which poses a risk of fluctuation in the threshold voltage Vth of the semiconductor device 100. By providing a trench bottom region 60 below the gate trench portion 40 and locally providing the trench bottom region 60 below the dummy trench portion 30, avalanche breakdown can be preferentially generated in the area at the bottom of the dummy trench portion 30 where the trench bottom region 60 is not formed. As a result, the occurrence of avalanche breakdown at the bottom of the gate trench portion 40 can be suppressed, thereby suppressing fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0080] The trench bottom region 60 is disposed below the emitter region 12. The trench bottom region 60 may or may not be disposed below the contact region 15. In this embodiment, the trench bottom region 60 is also disposed below the contact region 15.

[0081] The semiconductor device 100 of this embodiment includes a trench bottom formation region 62 in which the trench bottom region 60 is formed when viewed from above, and a trench bottom non-formation region 64 in which the trench bottom region 60 is not formed when viewed from above. In other words, the region other than the trench bottom formation region 62 in which the trench bottom region 60 is formed when viewed from above can be the trench bottom non-formation region 64. The boundary between the trench bottom formation region 62 and the trench bottom non-formation region 64 can be the boundary between the trench bottom region 60 and another region (e.g., the drift region 18).

[0082] The trench bottom forming region 62 can cover the emitter region 12 provided in contact with the gate trench portion 40 when viewed from above. The trench bottom forming region 62 in this example covers the emitter region 12, which is provided extending along the extension direction of the mesa portion 71 adjacent to the gate trench portion 40 and is provided in contact with the gate trench portion 40 when viewed from above. In the emitter region 12 provided in contact with the gate trench portion 40, a channel is formed when the semiconductor device 100 operates. Since the trench bottom forming region 62 covers the emitter region 12 provided in contact with the gate trench portion 40 when viewed from above, and the trench bottom region 60 is provided below the emitter region 12 provided in contact with the gate trench portion 40, avalanche breakdown can be suppressed in the region where the channel is formed. As a result, fluctuations in the threshold voltage Vth of the semiconductor device 100 can be suppressed.

[0083] In a plan view, the distance L1 between the edge of the outermost emitter region 12 in the extension direction and the edge of the trench bottom formation region 62 in the extension direction can be 1.0 μm or more and 10.0 μm or less. That is, the trench bottom formation region 62 extending in the extension direction can be provided so as to extend only by the distance L1 from the outermost emitter region 12 in the extension direction. In this manner, by extending the trench bottom formation region 62 from the emitter region 12, the trench bottom formation region 62 can reliably cover the emitter region 12. This can suppress avalanche breakdown in the region where the channel is formed, and suppress fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0084] The plurality of groove portions in this example include two adjacent dummy groove portions 30. The mesa portion 71 sandwiched between the two adjacent dummy groove portions 30 may be the groove bottom non-formation region 64.

[0085] In this example, emitter region 12 is also provided in mesa portion 71 sandwiched between two adjacent dummy trench portions 30. In a plan view, trench bottom non-formation region 64 may cover emitter region 12 provided in mesa portion 71 sandwiched between two adjacent dummy trench portions 30. In other words, trench bottom region 60 may not be formed below emitter region 12 provided in mesa portion 71 sandwiched between two adjacent dummy trench portions 30 and where no channel is formed.

[0086] The length Wt of the trench bottom region 60 in the arrangement direction (in this example, the X-axis direction) is shorter than the length Wp of the repeated structure of the plurality of trench portions. In other words, the trench bottom formation region 62 and the trench bottom non-formation region 64 can be provided within one cycle of the repeated structure of the plurality of trench portions. In this manner, the trench bottom formation region 62 can be provided so as to be surrounded by the trench bottom non-formation region 64.

[0087] If avalanche breakdown occurs at the bottom of the trench, a filament current may be generated due to the positive feedback of the avalanche breakdown. This results in a local temperature rise, which suppresses avalanche breakdown and allows the filament current to flow. If the location where the filament current is generated is surrounded by the trench bottom formation region 62, the flow of the filament current is hindered, causing a further temperature rise and risking damage to the semiconductor device 100. In the semiconductor device 100 of this example, since the trench bottom formation region 62 is surrounded by the trench bottom non-formation region 64, the flow of the filament current is not hindered, and damage to the semiconductor device 100 can be suppressed.

[0088] Figure 2B Show Figure 2AThe aa' cross section is an example of the cross section aa' in FIG. The cross section aa' is an XZ plane passing through the emitter region 12 in the active portion 120. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in the cross section aa'.

[0089] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. As an example, the drift region 18 in this embodiment is N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without forming other doped regions. In other words, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0090] The buffer zone 20 is a region of the first conductivity type provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, the buffer zone 20 is N-type. The doping concentration of the buffer zone 20 can be higher than that of the drift region 18. The buffer zone 20 functions as a field stop layer that prevents the depletion layer extending from the lower surface of the base region 14 from reaching the collector region 22 of the second conductivity type. Note that the buffer zone 20 can also be omitted.

[0091] The collector region 22 is provided below the buffer region 20. The collector region 22 has the second conductivity type. As an example, the collector region 22 in this embodiment is of P+ type.

[0092] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. In this embodiment, the accumulation region 16 is in contact with the dummy trench portion 30. As an example, the accumulation region 16 in this embodiment is N+ type. The doping concentration of the accumulation region 16 may be higher than the doping concentration of the drift region 18. The ion implantation dose of the accumulation region 16 may be 1.0E+12 cm -2 Above and 3.0E+13cm -2 By providing the accumulation region 16 , it is possible to enhance the carrier injection enhancement effect (IE effect) and reduce the on-voltage of the semiconductor device 100 .

[0093] Base region 14 is provided in contact with gate trench portion 40. Base region 14 may be provided in contact with dummy trench portion 30. Emitter region 12 is provided between base region 14 and front surface 21.

[0094] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In the region where at least one of the emitter region 12, the base region 14, the contact region 15, and the reservoir region 16 is provided, each trench portion also penetrates these regions and reaches the drift region 18. The case where the trench portion penetrates each region is not limited to the case where the trench portion is formed after each region is formed. The method of forming each region between the trench portions after the trench portion is formed also includes the method of the trench portion penetrating the doped region.

[0095] The gate trench portion 40 includes a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed so as to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position further inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered by an interlayer insulating film 38 on the front surface 21.

[0096] The gate conductive portion 44 includes a region that faces the base region 14 adjacent to the mesa portion 71 via the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface contacting the gate trench in the base region 14.

[0097] The dummy trench portion 30 can have the same structure as the gate trench portion 40. The dummy trench portion 30 includes a dummy trench formed on the front surface 21 side, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed so as to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 can be covered by an interlayer insulating film 38 on the front surface 21.

[0098] The trench bottom region 60 may be in contact with the gate trench portion 40. By making the trench bottom region 60 in contact with the gate trench portion 40, avalanche breakdown at the bottom of the gate trench portion 40 can be suppressed, and fluctuation in the threshold voltage Vth of the semiconductor device 100 can be suppressed.

[0099] The trench bottom region 60 may be in contact with the dummy trench portion 30 adjacent to the gate trench portion 40. By making the trench bottom region 60 contact the dummy trench portion 30, the potential of the trench bottom region 60 can be fixed to be equal to the emitter potential, thereby improving the switching loss reduction characteristics of the semiconductor device 100. It should be noted that the trench bottom region 60 only needs to be partially in contact with the dummy trench portion 30. By making the trench bottom region 60 partially in contact with the dummy trench portion 30, avalanche breakdown can be preferentially generated in the region of the bottom of the dummy trench portion 30 where the trench bottom region 60 is not formed. This can suppress avalanche breakdown at the bottom of the gate trench portion 40, thereby suppressing fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0100] The trench bottom region 60 can be formed by implanting ions of the second conductivity type into the bottom of the gate trench portion 40 and performing thermal diffusion. Specifically, the concentration of the trench bottom region 60 can be high near the bottom of the gate trench portion 40 and decrease as the distance from the bottom of the gate trench portion 40 increases. However, the method for forming the trench bottom region 60 is not limited to this. The trench bottom region 60 can also be formed by implanting ions of the second conductivity type at high acceleration from the front surface 21 of the semiconductor substrate 10, thereby having a substantially uniform concentration.

[0101] The back-side lifetime control region 151 can be provided in the active portion 120. However, the back-side lifetime control region 151 can be omitted. The back-side lifetime control region 151 is a region where a lifetime control body is intentionally formed by injecting impurities, etc., into the interior of the semiconductor substrate 10. In one example, the back-side lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. The back-side lifetime control region 151 can also be formed by injecting protons. By providing the back-side lifetime control region 151, the turn-off time is shortened, the tail current is suppressed, and thus the loss during switching is reduced.

[0102] The lifetime controlling body is a carrier recombination center. The lifetime controlling body can be a lattice defect. For example, the lifetime controlling body can be a vacancy, a multi-vacancy, a composite defect formed by combining these vacancies with elements constituting the semiconductor substrate 10, or a dislocation. Alternatively, the lifetime controlling body can be a rare gas element such as helium or neon, or a metal element such as platinum. Lattice defects can be formed using electron beams or protons.

[0103] The lifetime controlling body concentration refers to the concentration of carrier recombination centers. The lifetime controlling body concentration can be the concentration of lattice defects. For example, the lifetime controlling body concentration can be the concentration of vacancies, such as vacancies and multi-vacancies, or the concentration of complex defects resulting from the recombination of these vacancies with elements constituting the semiconductor substrate 10, or the concentration of dislocations. Furthermore, the lifetime controlling body concentration can be the chemical concentration of a rare gas element such as helium or neon, or the chemical concentration of a metal element such as platinum.

[0104] The back side lifetime control region 151 is arranged at a position closer to the back side 23 than the center of the drift region 18 in the depth direction of the semiconductor substrate 10. The back side lifetime control region 151 of this example is arranged in the buffer zone 20. The back side lifetime control region 151 of this example is arranged on the entire surface of the semiconductor substrate 10 in the XY plane and can be formed without using a mask. The back side lifetime control region 151 can also be arranged on a part of the semiconductor substrate 10 in the XY plane. The dose of the impurity used to form the back side lifetime control region 151 can be 0.5E+10cm -2 Above and 1.0E+14cm -2 Below, can also be 5.0E+10cm -2 Above and 1.0E+13cm -2 the following.

[0105] The back-side lifetime controlled region 151 can be formed by implantation from the back surface 23 side. This makes it easier to avoid affecting the front surface 21 side of the semiconductor device 100. For example, the back-side lifetime controlled region 151 can be formed by irradiating helium or protons from the back surface 23 side. Here, by obtaining the state of the front surface 21 side using the SR method or leakage current measurement, it can be determined whether the back-side lifetime controlled region 151 is formed by implantation from the front surface 21 side or by implantation from the back surface 23 side.

[0106] An interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited thereto.

[0107] Interlayer insulating film 38 may be a silicon oxide film. Interlayer insulating film 38 may be a BPSG (Boro-phosphosilicic Glass) film, a BSG (borosilicate glass) film, or a PSG (Phosphosilicate glass) film. Interlayer insulating film 38 may include a high-temperature silicon oxide (HTO) film.

[0108] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as a metal. At least a portion of the collector electrode 24 can be formed of a metal such as aluminum (Al) or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). The collector electrode 24 can include a barrier metal such as titanium or a titanium compound at a position closer to the semiconductor substrate 10 than the region formed of aluminum or the like.

[0109] Figure 3 The region R in a modified example of the semiconductor device 100 is shown. Figure 2A The difference of the embodiment is that, in the mesa portion 71 adjacent to the gate trench portion 40, the trench bottom forming region 62 and the trench bottom non-forming region 64 are repeatedly arranged in the extension direction. Figure 2A The differences between the embodiments are specifically described, and the other Figure 2A The same as the embodiment.

[0110] In the mesa portion 71 adjacent to the gate trench portion 40, the emitter region 12 and the contact region 15 can be repeatedly arranged along the extension direction of the plurality of trench portions (in this example, the Y-axis direction). In the mesa portion 71 adjacent to the gate trench portion 40, the trench bottom forming region 62 and the trench bottom non-forming region 64 can be repeatedly arranged along the extension direction. The repeatedly arranged trench bottom forming region 62 can cover the repeatedly arranged emitter region 12 when viewed from above. That is, the end of the trench bottom region 60 in the Y-axis direction can be below the contact region 15. Since the trench bottom forming region 62 covers the emitter region 12 when viewed from above, avalanche breakdown in the region where the channel is formed can be suppressed, and fluctuations in the threshold voltage Vth of the semiconductor device 100 can be suppressed.

[0111] In a plan view, the distance L2 between the edge of the emitter region 12 in the extension direction and the edge of the trench bottom formation region 62 covering the emitter region 12 in the extension direction can be greater than or equal to 1.0 μm and less than or equal to 2.5 μm. That is, the trench bottom formation regions 62 repeatedly arranged along the extension direction can be arranged to extend only a distance L2 from the emitter region 12 covering the trench bottom formation region 62. In this way, by providing the trench bottom formation region 62 extending from the emitter region 12, the trench bottom formation region 62 can reliably cover the emitter region 12. This can suppress avalanche breakdown in the region where the channel is formed, and can suppress fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0112] Figure 4A The region R in a modified example of the semiconductor device 100 is shown. Figure 2A The difference between the embodiments is that the repetitive structure of the plurality of groove portions is different. Figure 2AThe differences between the embodiments are specifically described, and the other Figure 2A The same as the embodiment.

[0113] The plurality of trench portions in this example have a repeating structure in which, along the arrangement direction (the X-axis direction in this example), the order of dummy trench portion 30, dummy trench portion 30, gate trench portion 40, gate trench portion 40, dummy trench portion 30, and dummy trench portion 30 is repeated. In other words, semiconductor device 100 in this example has gate trench portion 40 and dummy trench portion 30 at a ratio of 2:4.

[0114] In this example, the contact hole 54 is also provided in the mesa portion 71 sandwiched between the two gate trench portions 40. The contact hole 54 may not be provided in the mesa portion 71 sandwiched between the two gate trench portions 40. In the case where the contact hole 54 is not provided in the mesa portion 71 sandwiched between the two gate trench portions 40, the mesa portion 71 may be a floating region.

[0115] In this example, the emitter region 12 is further provided in the mesa portion 71 sandwiched between the two gate trench portions 40. The emitter region 12 may not be provided in the mesa portion 71 sandwiched between the two gate trench portions 40.

[0116] Figure 4B Show Figure 4A The bb' cross section is an example of the bb' cross section in the active portion 120. The bb' cross section is the XZ plane passing through the emission region 12 in the active portion 120. In this example, Figure 2B The differences between the embodiments are specifically described, and the other Figure 2B The same as the embodiment.

[0117] The trench bottom region 60 may or may not contact the dummy trench portion 30 adjacent to the gate trench portion 40. That is, the semiconductor device 100 may include a dummy trench portion 30 without a trench bottom region 60 formed at the bottom. This allows avalanche breakdown to preferentially occur in the dummy trench portion 30 without a trench bottom region 60 formed at the bottom, suppressing avalanche breakdown at the bottom of the gate trench portion 40 and reducing fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0118] In this example, the trench bottom region 60 is integrally formed, extending from the dummy trench 30a adjacent to one gate trench 40a of the two adjacent gate trenches 40 to the dummy trench 30b adjacent to the other gate trench 40b. Specifically, the trench bottom region 60 can be integrally formed by overlapping the region where the second conductivity type ions implanted into the bottom of the gate trench 40a undergo thermal diffusion with the region where the second conductivity type ions implanted into the bottom of the gate trench 40b undergo thermal diffusion. However, by providing a separation between the two adjacent gate trenches 40 that exceeds the diffusion length of the second conductivity type ions, the trench bottom region 60 can be formed separately at the bottom of each gate trench 40.

[0119] Figure 5 The region R in a modified example of the semiconductor device 100 is shown. Figure 4A The difference of the embodiment is that, in the mesa portion 71 adjacent to the gate trench portion 40, the trench bottom forming region 62 and the trench bottom non-forming region 64 are repeatedly arranged in the extending direction. Figure 4A In addition, for the repeated arrangement of the groove bottom forming region 62 and the groove bottom non-forming region 64, it is possible to Figure 3 The same as the embodiment.

[0120] Figure 6A The region R in a modified example of the semiconductor device 100 is shown. Figure 4A The difference of the embodiment is that the emitter region 12 and the contact hole 54 are not provided in the mesa portion 71 sandwiched by the two gate trench portions 40. Figure 4A The differences between the embodiments are specifically described, and the other Figure 4A The same as the embodiment.

[0121] In this example, the mesa portion 71 sandwiched between two adjacent gate trench portions 40 is not provided with a contact hole 54. Therefore, in this example, the mesa portion 71 sandwiched between two adjacent gate trench portions 40 is a floating region. However, by providing a contact hole 54 in the mesa portion 71 sandwiched between two adjacent gate trench portions 40, the mesa portion 71 is connected to the emitter electrode 52 via the contact hole 54, and the mesa portion 71 can have a hole extraction function. In addition, it can also be like Figure 4A By providing the emitter region 12 and the contact hole 54 in this manner, the emitter region 12 functions as a region where a channel is formed.

[0122] Figure 6B Show Figure 6A The c-c' cross section is an example of the c-c' cross section in the active portion 120. The c-c' cross section is the XZ plane passing through the emission region 12 in the active portion 120. In this example, Figure 4BThe differences between the embodiments are specifically described, and the other Figure 4B The same as the embodiment.

[0123] In this example, the trench bottom region 60 is also provided below a mesa portion 71 sandwiched between two adjacent gate trench portions 40, where no emitter region 12 is provided. By separating the two adjacent gate trench portions 40 by a distance greater than the diffusion length of ions of the second conductivity type, the trench bottom region 60 need not be provided below the mesa portion 71 sandwiched between the two adjacent gate trench portions 40. That is, since the emitter region 12 is not provided in the mesa portion 71 sandwiched between the two adjacent gate trench portions 40 in this example, no channel is formed during operation of the semiconductor device 100, and therefore the trench bottom region 60 need not be provided below the mesa portion 71.

[0124] Figure 7 The region R in a modified example of the semiconductor device 100 is shown. Figure 6A The difference of the embodiment is that in the mesa portion 71 adjacent to the gate trench portion 40, the trench bottom forming region 62 and the trench bottom non-forming region 64 are repeatedly arranged along the extension direction. Figure 6A In addition, for the repeated arrangement of the groove bottom forming region 62 and the groove bottom non-forming region 64, it is possible to Figure 3 and Figure 5 The same as the embodiment.

[0125] Figure 8A The region R in a modified example of the semiconductor device 100 is shown. Figure 2A The difference of the embodiment is that the emission area 12 is arranged to extend along the extension direction. Figure 2A The differences between the embodiments are specifically described, and the other Figure 2A The same as the embodiment.

[0126] The emitter region 12 can be provided in a mesa portion 71 adjacent to the gate trench portion 40, extending along the direction in which the plurality of trench portions extend (in this example, the Y-axis direction) so as to contact the gate trench portion 40 and not contact the dummy trench portion 30. The trench bottom formation region 62 can cover the emitter region 12, which is provided in a mesa portion 71 adjacent to the gate trench portion 40 and extends along the direction in which the gate trench portion 40 extends and contacts the gate trench portion 40 when viewed from above. Since the trench bottom formation region 62 covers the emitter region 12 when viewed from above, avalanche breakdown can be suppressed in the region where the channel is formed, thereby suppressing fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0127] In a plan view, the distance L3 between the edge of the emitter region 12 in the extension direction and the edge of the trench bottom formation region 62 covering the emitter region 12 in the extension direction can be 1.0 μm or more and 5.0 μm or less. That is, the trench bottom formation region 62 extending in the extension direction can be provided to extend only by the distance L3 from the emitter region 12 extending in the extension direction. In this manner, by extending the trench bottom formation region 62 from the emitter region 12, the trench bottom formation region 62 can reliably cover the emitter region 12. This can suppress avalanche breakdown in the region where the channel is formed, and suppress fluctuations in the threshold voltage Vth of the semiconductor device 100.

[0128] Figure 8B Show Figure 8A The d-d' cross section is an example of the cross section of FIG. The cross section of FIG. d-d' is an XZ plane passing through the emission region 12 in the active portion 120. In this example, Figure 2B The differences between the embodiments are specifically described, and the other Figure 2B The same as the embodiment.

[0129] In the mesa portion 71 adjacent to the gate trench portion 40 , the contact hole 54 may be provided above the emitter region 12 and the contact region 15 . That is, the boundary between the emitter region 12 and the contact region 15 may be located below the contact hole 54 .

[0130] While the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that embodiments with such modifications or improvements are also encompassed within the technical scope of the present invention.

[0131] It should be noted that the order of execution of actions, sequences, steps, stages, and other processes in the apparatus, system, program, or method described in the claims, specifications, and drawings may be implemented in any order, unless otherwise indicated by phrases such as "before," "prior to," and so forth, and unless the output of a previous process is used in a subsequent process. Even if the phrases "first," "next," and so forth are used for convenience in describing the process flow in the claims, specifications, and drawings, this does not necessarily imply that the processes must be performed in that order.

Claims

1. A semiconductor device, characterized in that: have: A plurality of trench portions arranged along a predetermined arrangement direction on the front side of the semiconductor substrate and having a repeated structure in which gate trench portions and dummy trench portions are repeated at a predetermined period in the arrangement direction; A drift region of a first conductivity type, which is disposed on the semiconductor substrate; A base region of a second conductivity type, disposed above the drift region; an emitter region of the first conductivity type, which is disposed above the base region and has a doping concentration higher than that of the drift region; a contact region of the second conductivity type, which is disposed above the base region and has a doping concentration higher than that of the base region; as well as a second conductive type trench bottom region, which is disposed below the gate trench portion and has a doping concentration lower than that of the base region; The groove bottom region is arranged below the emitter region, The length of the groove bottom region in the arrangement direction is shorter than the length of the repeating structure.

2. The semiconductor device according to claim 1, wherein The trench bottom region contacts the gate trench portion.

3. The semiconductor device according to claim 2, wherein The trench bottom region is in contact with the dummy trench portion adjacent to the gate trench portion.

4. The semiconductor device according to claim 1, wherein have: a trench bottom forming region which forms the trench bottom region when viewed from above; and The trench bottom non-formation region does not form the trench bottom region when viewed from above.

5. The semiconductor device according to claim 4, wherein The trench bottom formation region covers the emitter region provided in contact with the gate trench portion in a plan view.

6. The semiconductor device according to claim 4, wherein In a mesa portion adjacent to the gate trench portion, the emitter region and the contact region are repeatedly arranged along the extending direction of the plurality of trench portions. The trench bottom forming region covers the emitter region, and the emitter region is provided so as to extend along the extending direction in a mesa portion adjacent to the gate trench portion and to be in contact with the gate trench portion in a plan view.

7. The semiconductor device according to claim 6, wherein: In a plan view, a distance between an end side of the emitter region located outermost in the extending direction and an end side of the trench bottom formation region in the extending direction is 1.0 μm or more and 10.0 μm or less.

8. The semiconductor device according to claim 4, wherein The emitter region is provided in a mesa portion adjacent to the gate trench portion, extending along the extending direction of the plurality of trench portions so as to be in contact with the gate trench portion and not in contact with the dummy trench portion. The trench bottom forming region covers the emitter region, and the emitter region is provided so as to extend along the extending direction in a mesa portion adjacent to the gate trench portion and to be in contact with the gate trench portion in a plan view.

9. The semiconductor device according to claim 8, wherein In a plan view, a distance between an end side of the emitter region in the extending direction and an end side of the trench bottom forming region covering the emitter region in the extending direction is 1.0 μm or more and 5.0 μm or less.

10. The semiconductor device according to claim 4, wherein In a mesa portion adjacent to the gate trench portion, the emitter region and the contact region are repeatedly arranged along the extending direction of the plurality of trench portions. In the mesa portion adjacent to the gate trench portion, the trench bottom formation region and the trench bottom non-formation region are repeatedly arranged along the extension direction. The repeatedly arranged trench bottom forming regions cover the repeatedly arranged emitter regions in a plan view.

11. The semiconductor device according to claim 10, wherein In a plan view, a distance between an end side of the emitter region in the extending direction and an end side of the trench bottom forming region covering the emitter region in the extending direction is 1.0 μm or more and 2.5 μm or less.

12. The semiconductor device according to claim 4, wherein The plurality of groove portions include two adjacent dummy groove portions, The mesa portion sandwiched between the two dummy groove portions serves as the groove bottom non-formation region.

13. The semiconductor device according to claim 12, wherein: The emission region is further provided on the mesa portion sandwiched by the two dummy groove portions. The trench bottom non-formation region covers the emitter region provided on the mesa portion sandwiched between the two dummy trench portions in a plan view.

14. The semiconductor device according to any one of claims 1 to 13, wherein: The plurality of trench portions have the repeated structure in which the dummy trench portion, the gate trench portion, and the dummy trench portion are repeated in this order along the arrangement direction.

15. The semiconductor device according to any one of claims 1 to 13, wherein: The plurality of trench portions have the repeated structure in which the dummy trench portion, the dummy trench portion, the gate trench portion, the gate trench portion, the dummy trench portion, and the dummy trench portion are repeated in this order along the arrangement direction.

16. The semiconductor device according to any one of claims 1 to 13, wherein: The doping concentration of the trench bottom region is greater than or equal to 1% and less than or equal to 10% of the doping concentration of the base region.

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