Semiconductor device

Abstract

A semiconductor device includes a transistor including: a first gate electrode; a first gate insulating film provided on the first gate electrode; an oxide semiconductor layer that is provided on the first gate insulating film, overlaps the first gate electrode, and has a polycrystalline structure; a second gate insulating film provided on the oxide semiconductor layer; and a second gate electrode provided on the second gate insulating film and overlapping the first gate electrode, the first gate electrode having, in plan view, a first region overlapping the oxide semiconductor layer and protruding in the first direction from the second gate electrode; and a second region that overlaps the second gate electrode and protrudes from the oxide semiconductor layer in a second direction that intersects the first direction.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] In recent years, the development of semiconductor devices that use oxide semiconductors for their channels, replacing amorphous silicon, low-temperature polysilicon, and single-crystal silicon, has been progressing (e.g., Patent Document 1). The field-effect mobility of conventional thin-film transistors including oxide semiconductor layers is not that high even when using crystalline oxide semiconductor layers. Therefore, research has been conducted on semiconductor devices that use crystalline silicon for their channels for transistors requiring high-speed driving, and use oxide semiconductors for transistors requiring low off-state current (e.g., Patent Documents 2 and 3).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2013-008946

[0007] Patent Document 3: Japanese Patent Application Laid-Open No. 2011-142621 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] In top-gate transistors, ion implantation is performed using the top gate as a mask to form source and drain regions in the oxide semiconductor layer. Depending on the transistor's channel length and back-gate width, reliability testing can result in a strong electric field being applied not only to the transistor's channel region but also to the junctions between the channel region and the source region, and also to the junctions between the channel region and the drain region. This can lead to a tendency for transistor characteristics to deteriorate. For example, the transistor's threshold voltage may shift negatively.

[0010] In one embodiment of the present invention, one of the objectives is to suppress threshold fluctuation of a transistor in a semiconductor device and improve reliability.

[0011] Means for solving problems

[0012] A semiconductor device according to one embodiment of the present invention has a transistor, which includes: a first gate electrode; a first gate insulating film, which is arranged on the first gate electrode; an oxide semiconductor layer, which is arranged on the first gate insulating film, overlaps with the first gate electrode, and has a polycrystalline structure; a second gate insulating film, which is arranged on the oxide semiconductor layer; and a second gate electrode, which is arranged on the second gate insulating film and overlaps with the first gate electrode, and when viewed from above, the first gate electrode has: a first region, which overlaps with the oxide semiconductor layer and protrudes from the second gate electrode in a first direction; and a second region, which overlaps with the second gate electrode and protrudes from the oxide semiconductor layer in a second direction intersecting with the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] [ Figure 1 ] is a top view showing an overview of a semiconductor device according to one embodiment of the present invention.

[0014] [ Figure 2 ] is a cross-sectional view showing an overview of a semiconductor device according to one embodiment of the present invention.

[0015] [ Figure 3 ] is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0016] [ Figure 4 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0017] [ Figure 5 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0018] [ Figure 6 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0019] [ Figure 7 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0020] [ Figure 8 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0021] [ Figure 9 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0022] [ Figure 10 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0023] [ Figure 11] is a top view showing an overview of a semiconductor device according to one embodiment of the present invention.

[0024] [ Figure 12 ] is a cross-sectional view showing an overview of a semiconductor device according to one embodiment of the present invention.

[0025] [ Figure 13 ] is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0026] [ Figure 14 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0027] [ Figure 15 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0028] [ Figure 16 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0029] [ Figure 17 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0030] [ Figure 18 ] is a plan view showing an overview of a display device according to one embodiment of the present invention.

[0031] [ Figure 19 ] is a block diagram showing the circuit structure of a display device involved in one embodiment of the present invention.

[0032] [ Figure 20 ] is a circuit diagram showing a pixel circuit of a display device according to one embodiment of the present invention.

[0033] [ Figure 21 ] is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention.

[0034] [ Figure 22 ] is a top view of the pixel electrode and common electrode of the display device involved in one embodiment of the present invention.

[0035] [ Figure 23 ] is a circuit diagram showing a pixel circuit of a display device according to one embodiment of the present invention.

[0036] [ Figure 24 ] is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention.

[0037] [ Figure 25 ] is a graph showing the results of the reliability test.

[0038] [ Figure 26 ] is a graph showing the results of the reliability test. DETAILED DESCRIPTION

[0039] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is merely an example. Of course, any configuration that a person skilled in the art can easily conceive of by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is included within the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, film thickness, shape, etc. of each part are sometimes schematically indicated compared to the actual manner. However, the shape shown in the drawings is merely an example and does not limit the interpretation of the present invention. In this specification and the drawings, the same reference numerals are used for the same elements as those described in the drawings that have already appeared, and detailed descriptions are sometimes appropriately omitted.

[0040] A "semiconductor device" refers to any device that functions by utilizing semiconductor properties. Transistors and semiconductor circuits are one form of semiconductor device. The semiconductor devices described in the following embodiments may also be transistors used in integrated circuits (ICs) such as display devices, microprocessors (MPUs), or memory circuits.

[0041] A “display device” refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure in which other optical components (such as polarizing components, backlight sources, touch panels, etc.) are assembled relative to the display unit. As long as there is no technical contradiction, the “electro-optical layer” may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described later, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified for explanation, but the structure in this embodiment can be applied to display devices including the other electro-optical layers mentioned above.

[0042] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for ease of explanation, the phrases "above" or "below" are used for explanation, but for example, the up-down relationship between the substrate and the oxide semiconductor layer may be configured to be opposite to that shown in the figure. In the following description, for example, the expression "oxide semiconductor layer on substrate" is merely used to illustrate the up-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. "Above" or "below" means the stacking order in a structure having a plurality of layers stacked. In the case of a pixel electrode described as being above a transistor, it may also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of a pixel electrode described as being vertically above a transistor, it means a positional relationship in which the transistor and the pixel electrode overlap when viewed from above. It should be noted that viewing from above refers to viewing from a direction perpendicular to the surface of the substrate.

[0043] In this specification, the term "film" and the term "layer" may be used interchangeably depending on the situation. In addition, in this specification, multiple oxide semiconductor layers formed of an oxide semiconductor film may be described as "-1" or "-2." Multiple conductive layers and electrodes formed of a conductive film may also be described similarly.

[0044] It should be noted that, in this specification, etc., ordinal numbers are used to distinguish parts, components, locations, positions, directions, etc., and do not indicate order or priority.

[0045] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," or "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes multiple combinations of A to C. Furthermore, the above expressions do not exclude the case where α includes other elements.

[0046] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0047] <First embodiment>

[0048] use Figures 1 to 11 A semiconductor device 100 according to an embodiment of the present invention will be described.

[0049] [Configuration of Semiconductor Device 100]

[0050] Figure 1 It is a plan view schematically showing a semiconductor device 100 according to one embodiment of the present invention. Figure 21 is a cross-sectional view schematically showing a semiconductor device 100 according to an embodiment of the present invention.

[0051] like Figure 1 and Figure 2 As shown, the semiconductor device 100 includes a transistor 210 provided on a substrate 10. The transistor 210 includes a first gate electrode 12GE, first insulating films 14 and 16, an oxide semiconductor layer 22, a second insulating film 24, and a second gate electrode 26GE. The oxide semiconductor layer 22 includes a channel region 22CH, a source region 22S, and a drain region 22D.

[0052] The first insulating films 14 and 16 function as first gate insulating films of the transistor 210. The second insulating film 24 functions as a second gate insulating film of the transistor 210. The third insulating films 28 and 32 function as interlayer insulating films of the transistor 210.

[0053] The transistor 210 further includes a source electrode 44S and a drain electrode 44D. The source electrode 44S and the drain electrode 44D are provided on the third insulating film 32. The source electrode 44S and the drain electrode 44D are connected to the oxide semiconductor layer 22 via contact holes 31-1 and 31-2 provided in the second insulating film 24 and the third insulating films 28 and 32.

[0054] The oxide semiconductor layer 22 has a polycrystalline structure consisting of multiple crystal grains. Poly-OS (Poly-crystalline Oxide Semiconductor) technology is used to form the oxide semiconductor layer 22 having a polycrystalline structure. Details will be described later. The following describes the structure of the oxide semiconductor layer 22, and the oxide semiconductor having a polycrystalline structure is sometimes referred to as Poly-OS.

[0055] The oxide semiconductor layer 22 contains two or more metal elements, including indium, with the ratio of indium among the two or more metal elements being 50% or greater. Metal elements other than indium include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanide elements. However, the oxide semiconductor layer 22 only needs to contain Poly-OS and may also contain metal elements other than those listed above.

[0056] The particle size of the crystal grains included in the Poly-OS observed from the upper surface of the oxide semiconductor layer 22 (or in the thickness direction of the oxide semiconductor layer 22) or a cross-section of the oxide semiconductor layer 22 is 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The particle size of the crystal grains can be obtained, for example, using cross-sectional SEM observation, cross-sectional TEM observation, or electron backscattered diffraction (EBSD) analysis.

[0057] The oxide semiconductor layer 22 has a thickness greater than 10 nm and less than 50 nm, preferably greater than 10 nm and less than 30 nm. As described above, since the crystal grains included in the Poly-OS have a diameter greater than 0.1 μm, the oxide semiconductor layer 22 includes a region including only one crystal grain in the thickness direction.

[0058] In Poly-OS, multiple crystal grains may have a single crystal structure or multiple crystal structures. The crystal structure of Poly-OS can be determined using electron beam diffraction or XRD. In other words, the crystal structure of the oxide semiconductor layer 22 can be determined using electron beam diffraction or XRD.

[0059] The crystal structure of the oxide semiconductor layer 22 is preferably cubic. The cubic crystal structure is highly symmetric, and even when oxygen vacancies are generated in the oxide semiconductor layer 22, structural relaxation is unlikely to occur, resulting in a stable crystal structure. By increasing the indium ratio as described above, the crystal structure of each of the multiple crystal grains can be controlled, thereby forming an oxide semiconductor layer 22 having a cubic crystal structure.

[0060] The oxide semiconductor layer 22 includes a first crystal region that overlaps with the second gate electrode 26GE and has a first crystal structure, and a second crystal region that does not overlap with the second gate electrode 26GE and has a second crystal structure. Here, the first crystal region corresponds to the channel region 22CH. The second crystal region corresponds to the source region 22S and the drain region 22D. The electrical conductivity of the second crystal region is greater than that of the first crystal region.

[0061] In addition, the second crystal structure is identical to the first crystal structure. Here, the two crystal structures being identical means having the same crystal system. For example, when the crystal structure of the oxide semiconductor layer 22 is cubic, the first crystal structure of the first crystal region and the second crystal structure of the second crystal region are both cubic and identical. The first crystal structure and the second crystal structure can be determined using, for example, microelectron beam diffraction.

[0062] Furthermore, in a predetermined crystal orientation, the interplanar spacing d value of the first crystal structure is substantially the same as the interplanar spacing d value of the second crystal structure. Here, "two interplanar spacing d values ​​being substantially the same" means that the interplanar spacing d value of one is not less than 0.95 times and not more than 1.05 times the interplanar spacing d value of the other. Alternatively, in the context of microelectron beam diffraction, this refers to the situation where two diffraction patterns are substantially identical.

[0063] There may be no grain boundary between the first crystal region and the second crystal region. Alternatively, the first crystal region and the second crystal region may be included in one crystal grain. In other words, the change from the first crystal region to the second crystal region may be a continuous change in crystal structure.

[0064] The source region 22S and the drain region 22D contain the same impurity element. Furthermore, the addition of the impurity element reduces the resistivity of the source region 22S and the drain region 22D compared to the channel region 22CH. In other words, the source region 22S and the drain region 22D have the physical properties of a conductor.

[0065] The concentration of the impurity elements contained in the source region 22S and the drain region 22D is preferably 1×10 18 cm -3 Above 1×10 21 cm -3 Here, the impurity element refers to argon (Ar), phosphorus (P), or boron (B).

[0066] By adding impurity elements to the source region 22S and the drain region 22D, oxygen vacancies are formed. By trapping hydrogen in the oxygen vacancies, the resistance of the source region 22S and the drain region 22D can be reduced compared to the resistance of the channel region 22CH. It should be noted that even if oxygen vacancies are formed by adding impurity elements to the source region 22S and the drain region 22D, the crystal structure is not destroyed and is maintained. Therefore, it can be said that the crystal structure of the source region 22S and the drain region 22D is the same as that of the channel region 22CH.

[0067] If a large number of oxygen vacancies are present in the channel region of an oxide semiconductor layer, hydrogen is trapped in the oxygen vacancies, adversely affecting transistor characteristics. Therefore, it is desirable to reduce the number of oxygen vacancies in the oxide semiconductor layer.

[0068] Compared with amorphous oxide semiconductors, crystalline oxide semiconductors are less likely to form oxygen defects. In addition, it is known that by relatively increasing the ratio of indium contained in the oxide semiconductor, a crystalline oxide semiconductor can be easily obtained. However, even if the ratio of indium is relatively increased to obtain a crystalline oxide semiconductor, there will be more oxygen defects than necessary. Oxygen defects can be repaired by supplying oxygen. Therefore, as an insulating film surrounding the oxide semiconductor layer, it is necessary to repair the oxygen defects of the oxide semiconductor layer by configuring an insulating film that can release oxygen.

[0069] On the other hand, if more oxygen than necessary is supplied to the oxide semiconductor layer, the excess oxygen in the oxide semiconductor layer may form defect levels different from oxygen vacancies, which may cause characteristic fluctuations during reliability testing, a decrease in field-effect mobility, or variations in characteristics.

[0070] In this embodiment, the oxide semiconductor layer 22 includes Poly-OS. The oxide semiconductor layer 22 including Poly-OS has high crystallinity and has sufficiently reduced oxygen vacancies.

[0071] In this embodiment, ion implantation is performed in the transistor 210 using the second gate electrode 26GE as a mask to form a source region 22S and a drain region 22D in the oxide semiconductor layer 22. Depending on the channel length of the transistor and the width of the first gate electrode 12GE, reliability testing may result in a strong electric field being applied not only to the channel region of the transistor but also to the junctions between the channel region and the source region, and also to the junctions between the channel region and the drain region. This can lead to a tendency for transistor characteristics to deteriorate. For example, the threshold voltage of the transistor may shift negatively.

[0072] Here, the reliability test refers to, for example, the NBTIS (Negative Bias Temperature Illumination Stress) test. It should be noted that BT stress tests such as NBTIS are a type of accelerated test that can evaluate the characteristic changes (year-on-year changes) of transistors caused by long-term use in a short period of time. In particular, the change in the threshold voltage of the transistor before and after the BT stress test becomes an important indicator for studying reliability. It can be said that the smaller the change in threshold voltage before and after the BT stress test, the more reliable the transistor.

[0073] In one embodiment of the present invention, one of the objectives is to suppress threshold fluctuation of a transistor in a semiconductor device and improve reliability.

[0074] In the transistor 210, when viewed from above, the first gate electrode 12GE functioning as a back gate has: a first region overlapping with the oxide semiconductor layer 22 and protruding in the first direction D1 from the second gate electrode 26GE functioning as a top gate; and a second region overlapping with the second gate electrode 26GE and protruding from the oxide semiconductor layer 22 in a second direction D2 intersecting the first direction D1.

[0075] As a result, the channel region 22CH, the junction between the channel region 22CH and the source region 22S, and the junction between the channel region 22CH and the drain region 22D in the oxide semiconductor layer 22 are covered by the first gate electrode 12GE. Consequently, during an NBTIS test, degradation of the junction between the channel region 22CH and the source region 22S, and the junction between the channel region 22CH and the drain region 22D, of the transistor 210 due to the electric field applied to the first gate electrode 12GE can be suppressed. Consequently, a negative shift in the threshold of the transistor 210 can be suppressed. Consequently, a semiconductor device 100 with improved reliability can be provided by suppressing threshold fluctuations in the transistor 210.

[0076] Here, the width of the second gate electrode 26GE (the length in the first direction D1) is referred to as the channel length L1. In addition, the length of the first gate electrode 12GE protruding from the end of the second gate electrode 26GE in the first direction D1 is referred to as the length L2. In addition, the length of the first gate electrode 12GE protruding from the oxide semiconductor layer 22 in the second direction D2 is referred to as the length L3. In addition, the length from the end of the second gate electrode 26GE to the source electrode 44S (or the center of the contact hole) is referred to as the length L4. In addition, as Figure 1 As shown, in the oxide semiconductor layer 22, the length L4 (also referred to as the first length) from the end of the second gate electrode 26GE to the source electrode 44S in the first direction D1 may be greater than the length L2 (also referred to as the second length). That is, the first region overlaps at least a portion of the second crystal region. In the transistor 210, the entire oxide semiconductor layer 22 may not be covered by the first gate electrode 12GE. As a result, the area where the first gate electrode 12GE, which is formed of metal or the like, is arranged can be reduced. When the transistor 210 is applied to a display device or the like, the area shielded from light by the transistor 210 can be reduced. In other words, the aperture ratio of the pixel included in the display device can be increased.

[0077] In addition, if Figure 1As shown, the first direction D1 is the same direction as the channel length L1 of the transistor, and the second direction D2 is the channel width direction of the transistor. The length L2 can also be greater than the channel length L1. In addition, the length L3 (also referred to as the third length) can also be smaller than the channel length L1. For example, when the channel length L1 is 3μm, the length L2 can be greater than 3μm, and the length L3 can also be 2μm. By configuring the first gate electrode 12GE in this way, it is possible to reduce the area occupied by the transistor (especially the reduction of the light-shielding area in the transistor) and reduce the design load based on the efficiency of the layout, while suppressing the fluctuation of the threshold voltage of the transistor.

[0078] Furthermore, the oxide semiconductor layer 22 has a crystalline structure not only in the channel region 22CH but also in the source region 22S and the drain region 22D. This allows the source region 22S and the drain region 22D to have sufficiently low resistance. Consequently, the parasitic resistance of the source region 22S and the drain region 22D can be reduced, suppressing variations in the on-state current of the electrical characteristics of the transistor 210. Since the transistor 210 has high mobility, when the semiconductor device 100 is used in a display device or the like, variations are suppressed, leading to improved performance.

[0079] In the semiconductor device 100 according to one embodiment of the present invention, a mobility of 30 cm2 can be obtained within a range where the channel length L1 of the channel region CH of the transistor 210 is 2 μm to 4 μm and the channel width W of the channel region CH is 2 μm to 25 μm. 2 / Vs or above, 35cm 2 / Vs or above or 40cm 2 / Vs or above electrical characteristics. The mobility in this specification, etc. refers to the field-effect mobility in the saturation region of the transistor, which means the maximum value of the field-effect mobility in the region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the transistor from the voltage (Vg) supplied to the gate electrode.

[0080] In this embodiment, a dual-gate transistor is used as the transistor 210, in which the transistor is driven by the first gate electrode 12GE and the second gate electrode 26GE. However, the present invention is not limited to this configuration. A top-gate transistor in which the transistor is driven by the second gate electrode 26GE may also be used as the transistor 210. For example, a bottom-gate transistor in which the transistor is driven by the first gate electrode 12GE may also be used as the transistor 210. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0081] The first gate electrode 12GE functions as the bottom gate of the transistor 210 and as a light shielding film for the oxide semiconductor layer 22. The first insulating films 14, 16, and the second insulating film 24 function to release oxygen through heat treatment during the manufacturing process. The second insulating film 24 and the third insulating films 28, 32 function to insulate the first gate electrode 12GE from the source electrode 44S and the drain electrode 44D to reduce the parasitic capacitance therebetween. The operation of the transistor 210 is mainly controlled by the voltage supplied to the second gate electrode 26GE. An auxiliary voltage is supplied to the first gate electrode 12GE. Alternatively, the first gate electrode 12GE may be used solely as a light shielding film. In this case, the first gate electrode 12GE may be left floating instead of being supplied with a specific voltage.

[0082] [Method of Manufacturing Semiconductor Device 100]

[0083] use Figures 3 to 10 A method for manufacturing the semiconductor device 100 according to an embodiment of the present invention will be described. Figure 3 It is a flowchart showing a method for manufacturing the semiconductor device 100 according to one embodiment of the present invention.

[0084] like Figure 3 and Figure 4 As shown, a first gate electrode 12GE ( Figure 3 "First GE formation" in step S1001 shown).

[0085] As the substrate 10, a glass substrate, a quartz substrate, a sapphire substrate, or other light-transmitting rigid substrate can be used. When the substrate 10 needs to be flexible, a substrate containing resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, can be used as the substrate 10. When a substrate containing resin is used as the substrate 10, impurity elements can be introduced into the resin to improve the heat resistance of the substrate 10. In particular, when the semiconductor device 100 is a top-emission display, since the substrate 10 does not need to be transparent, impurities that reduce the transparency of the substrate 10 can be used. When the semiconductor device 100 is used in an integrated circuit that is not a display device, a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, which is not light-transmitting, can be used as the substrate 10.

[0086] The first gate electrode 12GE is formed by processing a conductive film formed by sputtering. A common metal material can be used for the first gate electrode 12GE. Examples of the first gate electrode 12GE include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. The above materials can be used as a single layer or as a stacked layer.

[0087] like Figure 3 and Figure 4 As shown, first insulating films 14 and 16 are formed on the substrate 10 and the first gate electrode 12GE ( Figure 3 The first insulating films 14 and 16 are formed by CVD (Chemical Vapor Deposition) or sputtering. As the first insulating films 14 and 16, a common insulating material can be used. As the first insulating films 14 and 16, for example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ) and other inorganic insulating materials. The above-mentioned SiO x N y It is a silicon compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). SiN x O y A silicon compound containing oxygen at a ratio less than nitrogen (x>y). In this embodiment, the first insulating films 14 and 16 are stacked with a silicon nitride film and a silicon oxide film on the silicon nitride film. The combined thickness of the first insulating films 14 and 16 is, for example, 100 nm to 600 nm, preferably 150 nm to 300 nm.

[0088] As the first insulating films 14 and 16, it is preferred to form an insulating material containing nitrogen and an insulating material containing oxygen in sequence starting from the substrate 10. For example, by using an insulating material containing nitrogen as the first insulating film 14, impurities diffusing from the substrate 10 side toward the oxide semiconductor layer 22 can be blocked. In addition, by using an insulating material containing oxygen as the first insulating film 16, oxygen can be released by heat treatment. The temperature of the heat treatment for releasing oxygen from the insulating material containing oxygen is, for example, below 500°C, below 450°C, or below 400°C. That is, the insulating material containing oxygen releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 100 when a glass substrate is used as the substrate 10, for example. In this embodiment, an example of using a stacked structure of silicon nitride and silicon oxide as the first insulating films 14 and 16 is described, but a single-layer structure of the above materials can also be used as the first insulating film.

[0089] like Figure 3 and Figure 4 As shown, an oxide semiconductor film 17 is formed on the first insulating film 16 ( Figure 3 (See step S1003 "First OS Film Formation" in the figure). In this process, an oxide semiconductor film 17 is sometimes formed on the substrate 10. The oxide semiconductor film 17 is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor film 17 is, for example, greater than 10 nm and less than 30 nm.

[0090] A metal oxide having semiconductor properties can be used as the oxide semiconductor film 17. The oxide semiconductor film 17 uses an oxide semiconductor containing two or more metal elements including indium. Furthermore, the ratio of indium in the two or more metal elements is 50% or greater. As the metal element other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or a lanthanide element can be used as the oxide semiconductor film 17.

[0091] When the oxide semiconductor film 17 is crystallized by the OS annealing described later, it is preferable that the oxide semiconductor film 17 be amorphous (having a low crystalline oxide semiconductor component) after film formation and before the OS annealing. That is, the oxide semiconductor film 17 is preferably formed under conditions that minimize crystallization of the oxide semiconductor film 17 immediately after film formation. For example, when the oxide semiconductor film 17 is formed by sputtering, the oxide semiconductor film 17 is formed while controlling the temperature of the object to be formed (the substrate 10 and the structures formed thereon).

[0092] When a film is formed on an object to be formed by sputtering, the ions generated in the plasma and the atoms ejected by the sputtering target collide with the object to be formed, so the temperature of the object to be formed rises as the film forming process progresses. If the temperature of the object to be formed rises during the film forming process, the oxide semiconductor film 17 will contain microcrystals in the state just after the film is formed. If microcrystals are contained in the oxide semiconductor film 17, the grain size cannot be increased by the subsequent OS annealing. In order to control the temperature of the object to be formed as described above, for example, the film can be formed while the object to be formed is cooled. For example, the object to be formed can be cooled from the surface opposite to the film forming surface in such a manner that the temperature of the film forming surface of the object to be formed (hereinafter referred to as the “film forming temperature”) is below 100°C, below 70°C, below 50°C or below 30°C. In particular, the film forming temperature of the oxide semiconductor film 17 of this embodiment is preferably below 50°C. By forming the oxide semiconductor film 17 while cooling the substrate, it is possible to obtain an oxide semiconductor film 17 with a low crystalline content immediately after film formation. In this embodiment, the oxide semiconductor film 17 is formed at a film formation temperature of 50°C or less, and the OS annealing described later is performed at a heating temperature of 400°C or higher. Thus, in this embodiment, the difference between the temperature when forming the oxide semiconductor film 17 and the temperature when performing the OS annealing on the oxide semiconductor film 17 is preferably 350°C or higher.

[0093] In the sputtering process, the amorphous oxide semiconductor film 17 is formed under an oxygen partial pressure of 10% or less. If the oxygen partial pressure is high, the oxide semiconductor film 17 immediately after formation may contain microcrystals due to the excess oxygen contained in the oxide semiconductor film 17. Therefore, it is preferable to form the oxide semiconductor film 17 under a low oxygen partial pressure. The oxygen partial pressure is, for example, 3% to 5%, preferably 3% to 4%. It should be noted that when the oxide semiconductor film 17 is formed under an oxygen partial pressure of 2%, even after the OS annealing treatment is performed, the oxide semiconductor film may not crystallize.

[0094] like Figure 3 and Figure 5 As shown, the pattern of the oxide semiconductor layer 18 is formed ( Figure 3 (See "OS pattern formation" in step S1004 shown in the figure). A resist mask 19 is formed on the oxide semiconductor film 17, and the oxide semiconductor film 17 is etched using the resist mask 19. The oxide semiconductor film 17 can be etched by wet etching or dry etching. Wet etching can be performed using an acidic etchant. For example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid can be used as the etchant. In this way, a patterned oxide semiconductor layer 18 can be formed. Thereafter, the resist mask 19 is removed.

[0095] The oxide semiconductor film 17 is preferably patterned before OS annealing. Crystallizing the oxide semiconductor film 17 through OS annealing tends to make etching difficult. Furthermore, even if the patterned oxide semiconductor layer 18 is damaged by etching, OS annealing can repair the damage, making this a preferred method.

[0096] like Figure 3 and Figure 6 As shown, after the patterning of the oxide semiconductor layer 18, the oxide semiconductor layer 18 is subjected to heat treatment (OS annealing) ( Figure 3 (See step S1005 "OS annealing" shown in the figure.) During the OS annealing, the oxide semiconductor layer 18 is held at a predetermined target temperature for a predetermined time. The predetermined target temperature is between 300°C and 500°C, preferably between 350°C and 450°C. The holding time at the target temperature is between 15 minutes and 120 minutes, preferably between 30 minutes and 60 minutes. The OS annealing crystallizes the oxide semiconductor layer 18, forming an oxide semiconductor layer 22 having a polycrystalline structure.

[0097] In a thin film transistor, by reducing the thickness of the oxide semiconductor layer, the carriers near the interface with the gate insulating film are increased, and the field effect mobility tends to increase. That is, the thin film transistor has the following tendency: the smaller the thickness of the region that functions as the channel of the oxide semiconductor layer, the higher the field effect mobility. Therefore, the smaller the thickness of the oxide semiconductor layer, the better. However, after the oxide semiconductor layer is formed to a thickness of less than 10nm, even if heat treatment is performed, the oxide semiconductor layer sometimes does not fully crystallize.

[0098] Furthermore, in thin-film transistors, the crystallinity of the oxide semiconductor layer 22 contributes to improved field-effect mobility. Therefore, the oxide semiconductor layer 22 preferably has a polycrystalline structure. However, if the oxide semiconductor film 17 contains microcrystals during film formation, subsequent heat treatment will not increase the size of the polycrystalline grains. This makes it difficult to achieve both thin film thickness and good crystallization of the oxide semiconductor layer.

[0099] Therefore, when the oxide semiconductor film 17 is formed by sputtering, the film is formed at a low oxygen partial pressure of 3% to 5%. By forming the oxide semiconductor film 17 under conditions of a low oxygen partial pressure, it is possible to suppress excessive oxygen inclusion in the oxide semiconductor film 17 and to suppress the inclusion of microcrystals in the oxide semiconductor film 17 immediately after formation. This can suppress the growth of microcrystals into crystals during the heat treatment of the oxide semiconductor layer 18. Therefore, even when the oxide semiconductor film 17 is formed with a thin film thickness of greater than 10 nm and less than 30 nm, the grain size of the polycrystalline structure of the oxide semiconductor layer 22 can be increased.

[0100] like Figure 3 and Figure 7 As shown, a second insulating film 24 is formed on the oxide semiconductor layer 22 ( Figure 3 (See "Second IF Film Formation" in step S1006 shown in the figure). The film formation method and insulating material of the second insulating film 24 can refer to the description of the first insulating films 14 and 16. The film thickness of the second insulating film 24 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm.

[0101] As the second insulating film 24, an insulating material containing oxygen is preferably used. In addition, as the second insulating film 24, an insulating film with few defects is preferably used. For example, when the oxygen composition ratio in the second insulating film 24 is compared with the oxygen composition ratio in an insulating film having the same composition as the second insulating film 24 (hereinafter referred to as "other insulating film"), the oxygen composition ratio in the second insulating film 24 is closer to the stoichiometric ratio for the insulating film than the oxygen composition ratio in the other insulating film. For example, silicon oxide (SiO x ), the oxygen composition ratio of the silicon oxide used as the second insulating film 24 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio of the silicon oxide used as the third insulating film 32. For example, a film in which no defects are observed when evaluated by electron spin resonance (ESR) may be used as the second insulating film 24.

[0102] To form an insulating film with few defects as the second insulating film 24, the second insulating film 24 may be formed at a film formation temperature of 350°C or higher. After the second insulating film 24 is formed, a process of implanting oxygen into a portion of the second insulating film 24 is performed. In this embodiment, silicon oxide is formed at a film formation temperature of 350°C or higher to form an insulating film with few defects as the second insulating film 24.

[0103] like Figure 3 and Figure 7As shown, a metal oxide film 25 is formed on the second insulating film 24 ( Figure 3 (See "MO film formation" in step S1007 shown in FIG. 1 ) The metal oxide film 25 is formed by sputtering. By forming the metal oxide film 25 by sputtering, oxygen is implanted into the second insulating film 24 .

[0104] As the metal oxide film 25, a metal oxide containing aluminum as a main component is used. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) or other inorganic insulating layers. A metal oxide film containing aluminum as a main component means that the ratio of aluminum contained in the metal oxide film is 1% or more of the total metal oxide film 25. The ratio of aluminum contained in the metal oxide film 25 may be 5% or more but less than 70%, 10% or more but less than 60%, or 30% or more but less than 50% of the total metal oxide film 25. The above ratios may be mass ratios or weight ratios.

[0105] The thickness of the metal oxide film 25 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide film 25. Aluminum oxide has a high barrier property against gases such as oxygen or hydrogen. In this embodiment, the aluminum oxide used as the metal oxide film 25 inhibits the outward diffusion of oxygen injected into the second insulating film 24 when the metal oxide film 25 is formed. In other words, the barrier property refers to the function of inhibiting gases such as oxygen or hydrogen from passing through the aluminum oxide. That is, it means that even if there is oxygen or other gases from a layer provided below the aluminum oxide film, they will not move to the layer provided above the aluminum oxide film. Alternatively, it means that even if there is oxygen or other gases from a layer provided above the aluminum oxide film, they will not move to the layer provided below the aluminum oxide film.

[0106] For example, when the metal oxide film 25 is formed by sputtering, the process gas used in sputtering may remain in the metal oxide film 25. For example, when Ar is used as the process gas for sputtering, Ar may remain in the second insulating film 24. The residual Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the second insulating film 24.

[0107] With the second insulating film 24 and the metal oxide film 25 formed on the oxide semiconductor layer 22, a heat treatment (oxidation annealing) is performed to supply oxygen from the second insulating film 24 to the oxide semiconductor layer 22. Figure 3 (See "Oxidation Annealing" in step S1008 shown in the figure.) During the process from forming the oxide semiconductor film 17 to forming the second insulating film 24 on the oxide semiconductor layer 22, a large number of oxygen vacancies are generated on the upper surface and side surfaces of the oxide semiconductor layer 22. Oxygen released from the first insulating film 16 and the second insulating film 24 by the oxidation annealing is supplied to the oxide semiconductor layer 22, thereby repairing the oxygen vacancies.

[0108] During the oxidation annealing, oxygen injected into the second insulating film 24 is blocked by the metal oxide film 25, thereby suppressing the release of the oxygen into the atmosphere. Therefore, the oxidation annealing efficiently supplies the oxygen to the oxide semiconductor layer 22, thereby repairing oxygen vacancies.

[0109] like Figure 3 As shown, the metal oxide film 25 ( Figure 3 (See "MO removal" in step S1009 shown in FIG. 4 .) Metal oxide film 25 may be etched by wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) is used for wet etching.

[0110] like Figure 3 and Figure 8 As shown, a second gate electrode 26GE ( Figure 3 (See "Second GE Formation" in step S1010 shown in the figure.) The second gate electrode 26GE is formed by processing a conductive film formed by sputtering. Materials that can be used for the second gate electrode 26GE can refer to the description of the materials for the first gate electrode 12GE. The materials listed in the description of the first gate electrode 12GE can be used as the second gate electrode 26GE in a single layer or in a stacked layer. Alternatively, the material of the second gate electrode 26GE can be the same as that of the first gate electrode 12GE.

[0111] The width of the second gate electrode 26GE (in Figure 2 The channel length L1 corresponds to the channel length L2. When viewed from above, the first gate electrode 12GE is formed such that the second gate electrode 26GE has a first region protruding from the second gate electrode 26GE in the first direction D1 and a second region overlapping the second gate electrode 26GE and protruding from the oxide semiconductor layer 22 in a second direction D2 intersecting the first direction D1. Furthermore, the length L2 of the first region in the first direction D1 is preferably longer than the length L3 of the second region in the second direction D2.

[0112] like Figure 3 and Figure 9 As shown, the second gate electrode 26GE is used as a mask to add an impurity element ( Figure 3 (See "SD region formation" in step S1011 shown in the figure.) In this embodiment, the case where the impurity element is added by ion implantation is described, but it may also be added by an ion doping method.

[0113] Specifically, the impurity elements are added to the source region 22S and the drain region 22D by ion implantation through the second insulating film 24. In the oxide semiconductor layer 22, the region overlapping with the second gate electrode 26GE is not doped with impurity elements, and functions as the channel region 22CH. As the impurity element, argon (Ar), phosphorus (P), or boron (B) can be used, for example. In addition, when boron (B) is added by ion implantation, the acceleration energy can be set to 20 keV or more and 40 keV or less, and the implantation amount of boron (B) can be set to 1×10 14 cm -2 Above 1×10 16 cm -2 the following.

[0114] By ion implantation, impurity elements can be implanted at a rate of 1×10 18 cm -3 Above 1×10 21 cm -3 The following concentrations are added to the source region 22S and the drain region 22D. At this time, the oxide semiconductor in the source region 22S and the drain region 22D forms oxygen vacancies by adding impurity elements. Hydrogen is easily captured in these oxygen vacancies. As a result, the resistivity of the source region 22S and the drain region 22D can be reduced, and they can function as conductors. Even if impurity elements are added to the oxide semiconductor layer 22 to form oxygen vacancies, the crystal structure is not destroyed and is maintained. Therefore, it can be said that the crystal structure of the source region 22S and the drain region 22D is the same as the crystal structure of the channel region 22CH.

[0115] For example, when using an IGZO-based oxide semiconductor layer, the resistance of the oxide semiconductor layer is high, so the resistance of the source and drain regions cannot be sufficiently reduced without increasing the film thickness. In contrast, in the oxide semiconductor layer 22 having a polycrystalline structure, by adding impurity elements to the source and drain regions 22S and 22D, the sheet resistance of the source and drain regions 22S and 22D can be reduced to 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less.

[0116] like Figure 3 and Figure 10As shown, the third insulating films 28 and 32 are formed on the second insulating film 24 and the second gate electrode 26GE ( Figure 3 (See "Third IF Film Formation" in step S1012 shown in the figure.) The film formation method and insulating materials of the third insulating films 28 and 32 can refer to the description of the materials of the first insulating films 14 and 16. In this embodiment, for example, silicon nitride is formed as the third insulating film 28, and silicon oxide is formed as the third insulating film 32. The third insulating films 28 and 32 function as interlayer insulating films for the transistor 210.

[0117] like Figure 3 and Figure 10 As shown, contact holes 31-1 and 31-2 are formed in the second insulating film 24 and the third insulating films 28 and 32 ( Figure 3 (See step S1013 “contact opening” in the figure). As a result, the source region 22S and the drain region 22D of the oxide semiconductor layer 22 are exposed.

[0118] Finally, if Figure 3 As shown, a source electrode 44S and a drain electrode 44D are formed on the third insulating films 28 and 32 ( Figure 3 (See step S1014 "SD formation" in the figure.) The source electrode 44S and the drain electrode 44D are formed by processing a conductive film deposited by sputtering. This connects the source region 22S to the source electrode 44S, and the drain region 22D to the drain electrode 44D. For materials that can be used for the source electrode 44S and the drain electrode 44D, refer to the description of the material for the first gate electrode 12GE.

[0119] Through the above process, it is possible to produce Figure 1 and Figure 2 The semiconductor device 100 is shown.

[0120] <Variation 1>

[0121] Figure 11 FIG is a top view showing a semiconductor device 100A having a structure that is partially different from that of the semiconductor device 100. Figure 11 As shown, in the transistor 210A included in the semiconductor device 100A, the shape of the first gate electrode 12GE is different from that of the transistor 210. It should be noted that in the transistor 210A, the cross-sectional view taken along the line A1-A2 is different from that of the transistor 210A. Figure 2 The cross-sectional views shown are the same, so detailed description is omitted.

[0122] In a plan view, the first gate electrode 12GE has a first region protruding from the second gate electrode 26GE in the first direction D1 and a second region overlapping with the second gate electrode 26GE and protruding from the oxide semiconductor layer 22 in the second direction D2, similar to the transistor 210. The transistor 210A differs from the transistor 210 in that the length L2 of the first region in the first direction D1 is shorter than the length L3 of the second region in the second direction D2. In this case, the length L2 is preferably greater than the channel length L1 of the transistor, but the first gate electrode 12GE only needs to protrude from the oxide semiconductor layer 22 in the second direction D2. Even when the length L2 is shorter than the length L3, as long as the first gate electrode 12GE protrudes from the oxide semiconductor layer 22 in the second direction D2, the threshold of the transistor 210A can be suppressed from shifting in the negative direction. Consequently, the semiconductor device 100 can be provided with suppressed threshold fluctuations of the transistor 210A and improved reliability.

[0123] <Second embodiment>

[0124] In this embodiment, a semiconductor device 100B having a partially different configuration from the semiconductor device 100 described in the first embodiment will be described.

[0125] [Configuration of Semiconductor Device 100B]

[0126] Figure 12 It is a cross-sectional view schematically showing a semiconductor device 100B according to one embodiment of the present invention.

[0127] like Figure 12 As shown in FIG. 1 , the semiconductor device 100B includes a transistor 210B provided on a substrate 10. The configuration of the transistor 210B is substantially the same as that of the transistor 210, but differs in that a metal oxide layer 46 is provided between the oxide semiconductor layer 22 and the first insulating film 16. Figure 2 Likewise, illustration is therefore omitted.

[0128] A metal oxide containing aluminum as a main component is used as the metal oxide layer 46. The metal oxide layer 46 can be made of the same material as the metal oxide film 25. The thickness of the metal oxide layer 46 is, for example, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 46. Aluminum oxide has high barrier properties against gases. In this embodiment, the aluminum oxide used as the metal oxide layer 46 blocks hydrogen and oxygen released from the first insulating film 16 and the third insulating film 32, and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 22.

[0129] When the oxide semiconductor layer 22 is excessively supplied with oxygen, defect levels different from oxygen vacancies are formed due to the excess oxygen, which may cause characteristic fluctuations during reliability testing, a decrease in field-effect mobility, or variations in characteristics.

[0130] Providing the metal oxide layer 46 below the oxide semiconductor layer 22 can suppress excessive oxygen supply to the lower surface of the oxide semiconductor layer 22. This can suppress the formation of defect levels on the lower surface of the oxide semiconductor layer 22. Consequently, it is possible to suppress characteristic fluctuations, reductions in field-effect mobility, or variations in characteristics during reliability testing of the transistor 210B.

[0131] [Method of Manufacturing Semiconductor Device 100B]

[0132] use Figure 13 A method for manufacturing the semiconductor device 100B according to one embodiment of the present invention will be described. Figure 13 It is a sequence diagram showing a method for manufacturing the semiconductor device 100B according to one embodiment of the present invention. Figures 14 to 17 1 is a cross-sectional view showing a method for manufacturing a semiconductor device 100B according to an embodiment of the present invention. Detailed descriptions of the same steps as those in the first embodiment will be omitted.

[0133] like Figure 13 As shown, the process of step S1101 to step S1102 is the same as Figure 2 The processes of step S1001 to step S1002 shown are the same.

[0134] In this embodiment, if Figure 13 and Figure 14 As shown, after the process of step S1102, a metal oxide film 45 mainly composed of aluminum and an oxide semiconductor film 17 ( Figure 13 Step S1103 “first MO and OS film formation” is shown).

[0135] The metal oxide film 45 is formed by sputtering or atomic layer deposition. The thickness of the metal oxide film 45 is, for example, 1 nm to 50 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide film 45. Aluminum oxide has high barrier properties against gases such as oxygen and hydrogen. In this embodiment, the aluminum oxide used as the metal oxide film 45 blocks hydrogen and oxygen released from the first insulating film 16 and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 22 formed later.

[0136] For the film forming method and materials of the oxide semiconductor film 17 in this embodiment, refer to the description of the film forming method and materials of the oxide semiconductor film 17 ( Figure 2 The step S1003 "OS film formation" shown in the figure is sufficient.

[0137] like Figure 13 and Figure 15 As shown, the pattern of the oxide semiconductor layer 18 is formed ( Figure 13 A resist mask 19 is formed over the oxide semiconductor film 17, and the oxide semiconductor film 17 is etched using the resist mask 19. For the etching method of the oxide semiconductor film 17 in this embodiment, refer to the description of the etching method of the oxide semiconductor film 17 ( Figure 2 The step S1004 "OS pattern formation" shown in the figure is sufficient.

[0138] like Figure 13 and Figure 16 As shown, after the patterning of the oxide semiconductor layer 18, the oxide semiconductor layer 18 is subjected to heat treatment (OS annealing) ( Figure 13 Regarding the conditions of the OS annealing, refer to the description of the conditions of the OS annealing of the oxide semiconductor layer 18 ( Figure 3 By performing the OS annealing, the oxide semiconductor layer 18 is crystallized to form the oxide semiconductor layer 22 having a polycrystalline structure.

[0139] like Figure 13 and Figure 17 As shown, the metal oxide film 45 is patterned to form a metal oxide layer 46 ( Figure 13 The oxide semiconductor layer 22 that has been fully crystallized by the heat treatment has etching resistance. Therefore, it is possible to prevent the oxide semiconductor layer 22 from disappearing when the metal oxide film 45 is patterned using the crystallized oxide semiconductor layer 22 as a mask. The metal oxide film 45 is etched using the oxide semiconductor layer 22 patterned in the above-mentioned process as a mask. As the etching of the metal oxide film 45, wet etching or dry etching can be used. As wet etching, for example, diluted hydrofluoric acid (DHF) is used. By etching the metal oxide film 45 using the oxide semiconductor layer 22 as a mask, the photolithography process can be omitted.

[0140] after, Figure 13 The steps S1107 to S1108 shown in FIG. Figure 3The steps S1006 to S1007 shown in the figure are the same, and therefore detailed descriptions thereof are omitted.

[0141] like Figure 13 As shown, in a state where the second insulating film 24 and the metal oxide film 25 are formed on the oxide semiconductor layer 22, a heat treatment (oxidation annealing) for supplying oxygen from the second insulating film 24 to the oxide semiconductor layer 22 is performed ( Figure 13 "Oxidation annealing" in step S1109 shown).

[0142] In this embodiment, a metal oxide layer 46 is provided below the oxide semiconductor layer 22. If oxidation annealing is performed in this state, oxygen released from the first insulating film 16 is blocked by the metal oxide layer 46, making it difficult for oxygen to be supplied to the lower surface of the oxide semiconductor layer 22. Oxygen released from the first insulating film 16 diffuses from the region where the metal oxide layer 46 is not formed toward the second insulating film 24 provided above the first insulating film 16, and then reaches the oxide semiconductor layer 22 via the second insulating film 24. As a result, oxygen released from the first insulating film 16 is not easily supplied to the lower surface of the oxide semiconductor layer 22, but is mainly supplied to the side and upper surfaces of the oxide semiconductor layer 22. In addition, oxygen released from the second insulating film 24 by the oxidation annealing is supplied to the upper and side surfaces of the oxide semiconductor layer 22. Although hydrogen may be released from the first insulating films 14 and 16 due to the oxidation annealing described above, this hydrogen is blocked by the metal oxide layer 46.

[0143] As described above, the oxidation annealing step can suppress the supply of oxygen to the lower surface of the oxide semiconductor layer 22 having a small amount of oxygen vacancies while simultaneously supplying oxygen to the upper surface and side surfaces of the oxide semiconductor layer 22 having a large amount of oxygen vacancies.

[0144] after, Figure 13 The steps 1110 to 1115 shown in FIG. Figure 3 The steps S1009 to S1014 shown in the figure are the same.

[0145] Through the above process, it is possible to produce Figure 12 The semiconductor device 100B is shown.

[0146] In the semiconductor device 100B manufactured by the above-described manufacturing method, the oxygen vacancies included in the oxide semiconductor layer 22 can be further reduced compared to the manufacturing method of the semiconductor device 100 described in the first embodiment. Therefore, in the semiconductor device 100B described in this embodiment, a mobility of 50 cm2 can be obtained within the range of 2 μm to 4 μm for the channel length L1 of the channel region CH of the transistor 210B and 2 μm to 25 μm for the channel width W of the channel region CH.2 / Vs or above, 55cm 2 / Vs or above or 60cm 2 / Vs or above such electrical characteristics.

[0147] Furthermore, it is possible to suppress excessive oxygen supply to the lower surface of the oxide semiconductor layer 22. In particular, by sufficiently reducing the number of oxygen vacancies in the channel region CH, it is possible to suppress hydrogen capture in the oxygen vacancies. Consequently, it is possible to further reduce characteristic variations in the transistor 210B during reliability testing, thereby improving the reliability of the semiconductor device 100B.

[0148] <Third embodiment>

[0149] use Figures 18 to 24 A display device 200 using the semiconductor device 100 according to one embodiment of the present invention will be described. In the following embodiment, a circuit configuration in which the semiconductor device 100 described in the first embodiment is applied to a liquid crystal display device will be described.

[0150] [Overview of Display Device 200]

[0151] Figure 18 FIG. 2 is a plan view showing an overview of a display device 200 according to an embodiment of the present invention. Figure 18 As shown, the display device 200 includes an array substrate 300, a sealing portion 310, an opposing substrate 320, a flexible printed circuit substrate (also referred to as FPC 330 in the following description), and an IC chip 340. The array substrate 300 and the opposing substrate 320 are bonded together by the sealing portion 310. A plurality of pixel circuits 301 are arranged in a matrix in the liquid crystal region 220 surrounded by the sealing portion 310. The liquid crystal region 220 is a region that overlaps with a liquid crystal element 311, described later, when viewed from above.

[0152] The sealed region 240, where the seal portion 310 is located, is the area surrounding the liquid crystal region 220. The FPC 330 is located in the terminal region 260. The terminal region 260 is the area of ​​the array substrate 300 that is exposed from the counter substrate 320 and is located outside the sealed region 240. The outside of the sealed region 240 refers to the area where the seal portion 310 is located and the area surrounded by the seal portion 310. An IC chip 340 is located on the FPC 330. The IC chip 340 supplies signals for driving each pixel circuit 301.

[0153] [Circuit Configuration of Display Device 200]

[0154] Figure 19 FIG. 1 is a block diagram showing a circuit configuration of a display device 200 according to an embodiment of the present invention. Figure 19As shown, a source driver circuit 302 is provided at a position adjacent to the liquid crystal region 220 where the pixel circuit 301 is arranged in the second direction D2 (column direction), and a gate driver circuit 303 is provided at a position adjacent to the liquid crystal region 220 in the first direction D1 (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the aforementioned sealed region 240. However, the region where the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the sealed region 240, and may be any region as long as it is outside the region where the pixel circuit 301 is provided.

[0155] The source wiring 304 extends from the source driver circuit 302 along the second direction D2 and is connected to the plurality of pixel circuits 301 arranged in the second direction D2. The second gate electrode 26GE extends from the gate driver circuit 303 along the first direction D1 and is connected to the plurality of pixel circuits 301 arranged in the first direction D1.

[0156] A terminal portion 306 is provided in the terminal region 260. The terminal portion 306 is connected to the source driver circuit 302 via a connection wiring 307. Similarly, the terminal portion 306 is connected to the gate driver circuit 303 via a connection wiring 307. The FPC 330 is connected to the terminal portion 306, thereby connecting an external device connected to the FPC 330 to the display device 200, and each pixel circuit 301 provided in the display device 200 is driven by a signal from the external device.

[0157] The transistors 210 , 210A, and 210B described in the first and second embodiments are used as transistors included in the pixel circuit 301 , the source driver circuit 302 , and the gate driver circuit 303 .

[0158] [Pixel Circuit 301 of Display Device 200]

[0159] Figure 20 FIG. 1 is a circuit diagram showing a pixel circuit of a display device 200 according to an embodiment of the present invention. Figure 20 As shown, the pixel circuit 301 includes components such as the semiconductor device 100, the storage capacitor 350, and the liquid crystal element 311. The semiconductor device 100 has a second gate electrode 26GE, a source electrode 44S, and a drain electrode 44D. The second gate electrode 26GE is connected to the second gate electrode 26GE. The source electrode 44S is connected to the source wiring 304. The drain electrode 44D is connected to the storage capacitor 350 and the liquid crystal element 311. In this embodiment, for convenience of description, the electrode represented by the reference numeral "44S" is referred to as the source electrode, and the electrode represented by the reference numeral "44D" is referred to as the drain electrode. However, the electrode represented by the reference numeral "44S" can also function as a drain electrode, and the electrode represented by the reference numeral "44D" can also function as a source electrode.

[0160] [Configuration of Display Device 200]

[0161] Figure 20 FIG is a cross-sectional view of a display device 200 according to an embodiment of the present invention. Figure 20 As shown, the display device 200 is a display device to which the semiconductor device 100 is applied.

[0162] like Figure 20 and Figure 22 As shown, a first gate electrode 12GE is provided on the substrate 10. Furthermore, an oxide semiconductor layer 22 is provided on the first gate electrode 12GE. A second gate electrode 26GE is provided on the oxide semiconductor layer 22. A source wiring and a drain electrode 44D are provided on the second gate electrode 26GE. The source wiring is connected to the source region 22S via a contact hole 31-1. The region of the source wiring connected to the oxide semiconductor layer 22 functions as the source electrode 44S. Furthermore, the drain electrode 44D is connected to the drain region 22D via a contact hole 31-2.

[0163] An insulating film 360 is provided over the source electrode 44S and the drain electrode 44D. A common electrode 370 is provided over the insulating film 360, and is provided commonly for multiple pixels. An insulating film 380 is provided over the common electrode 370. Openings 381 are provided in the insulating films 360 and 380. A pixel electrode 390 is provided over the insulating film 380 and within the opening 381. The pixel electrode 390 is connected to the drain electrode 44D.

[0164] Figure 22 FIG is a top view of the pixel electrode 390 and the common electrode 370 of the display device 200 according to one embodiment of the present invention. Figure 22 As shown, the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in a plan view, and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a transverse electric field is generated from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. This transverse electric field causes the liquid crystal molecules included in the liquid crystal element 311 to move, thereby determining the grayscale of the pixel.

[0165] In this embodiment, a configuration in which the semiconductor device 100 is used in the pixel circuit 301 is exemplified. However, the semiconductor device 100 may be used in peripheral circuits including the source driver circuit 302 and the gate driver circuit 303 .

[0166] <Fourth embodiment>

[0167] use Figure 23 and Figure 24A display device 200 using the semiconductor device 100 according to one embodiment of the present invention will be described. In this embodiment, the semiconductor device 100 described in the first embodiment is applied to the circuit structure of an organic EL display device. The overview and circuit structure of the display device 200 are related to the following. Figure 23 and Figure 24 The contents shown are the same, so the description is omitted.

[0168] [Pixel Circuit 301 of Display Device 200]

[0169] Figure 23 FIG. 1 is a circuit diagram showing a pixel circuit of a display device 200 according to an embodiment of the present invention. Figure 23 As shown, the pixel circuit 301 includes components such as a driving transistor 110, a selection transistor 1200, a holding capacitor 215, and a light-emitting element DO. The driving transistor 110 and the selection transistor 120 have the same structure as the transistor 210 of the semiconductor device 100. The source electrode of the selection transistor 120 is connected to the signal line 211, and the gate electrode of the selection transistor 120 is connected to the gate line 212. The source electrode of the driving transistor 110 is connected to the anode power line 213, and the drain electrode of the driving transistor 110 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to the cathode power line 214. The gate electrode of the driving transistor 110 is connected to the drain electrode of the selection transistor 120. The holding capacitor 215 is connected to the gate electrode and drain electrode of the driving transistor 110. A grayscale signal that determines the light-emitting intensity of the light-emitting element DO is supplied to the signal line 211. A signal for selecting a pixel row to which the above-mentioned grayscale signal is to be written is supplied to the gate line 212.

[0170] [Cross-sectional Structure of Display Device 200]

[0171] Figure 24 2 is a cross-sectional view of a display device 200 according to an embodiment of the present invention. Figure 24 The display device 200 shown is constructed in the same manner as Figure 20 The display device 200 shown is similar, but Figure 24 The structure above the insulating film 360 in the display device 200 is Figure 20 The structure above the insulating film 360 in the display device 200 is different. Figure 24 The display device 200 shown in FIG. Figure 20 Description of the same configurations as the display device 200 will be omitted, and differences between the two will be described.

[0172] like Figure 24As shown, the display device 200 has a pixel electrode 390, a light-emitting layer 392 and a common electrode 394 (light-emitting element DO) above the insulating film 360. The pixel electrode 390 is arranged on the insulating film 360 and inside the opening 381. An insulating film 362 is provided on the pixel electrode 390. An opening 363 is provided in the insulating film 362. The opening 363 corresponds to the light-emitting area. In other words, the insulating film 362 is used to demarcate the pixels. The light-emitting layer 392 and the common electrode 394 are provided on the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light-emitting layer 392 are provided separately for each pixel. On the other hand, the common electrode 394 is provided in common for multiple pixels. Different materials are used for the light-emitting layer 392 according to the display color of the pixel.

[0173] In the third and fourth embodiments, the semiconductor device 100 described in the first embodiment is applied to a liquid crystal display device and an organic EL display device. However, the semiconductor device can also be applied to display devices other than these (for example, self-luminous display devices other than organic EL display devices or electronic paper display devices). In addition, the semiconductor device 100 can be applied to display devices ranging from small and medium-sized to large display devices without particular limitation.

[0174] Example

[0175] In this embodiment, in the NBTIS test, whether the degradation of the transistor is caused by the difference in the shape of the top gate and the bottom gate is studied. Figures 25 and 26 In this embodiment, as measurement condition 1, the case where the width of the top gate is fixed and the length L2 of the bottom gate in the first region protruding from the top gate in the first direction D1 is changed is described. As measurement condition 2, the case where the width of the top gate is fixed and the length L3 of the bottom gate in the second region protruding from the oxide semiconductor layer in the second direction D2 is changed is described.

[0176] (Transistor Configuration under Measurement Condition 1)

[0177] The transistor used in measurement condition 1 has a configuration equivalent to Figure 1 and Figure 2 The transistor 210 shown in FIG. 1 is constructed as the oxide semiconductor layer 22. An oxide semiconductor having a polycrystalline structure is used. In the following description, the bottom gate corresponds to the first gate electrode, and the top gate corresponds to the second gate electrode. Figure 2In the embodiment, the channel length L1 of the channel region 22CH is set to 3 μm, and the channel width W is set to 4.5 μm. Furthermore, under measurement condition 1, it was confirmed whether the characteristics of the transistor 210 vary depending on the film thicknesses of the first insulating films 14, 16, and the second insulating film 24. Two film thickness conditions were applied: film thickness condition 1 used a stack of a 200 nm silicon nitride film and a 100 nm silicon oxide film as the first insulating films 14, 16, and a 100 nm silicon oxide film as the second insulating film 24; and film thickness condition 2 used a stack of a 100 nm silicon nitride film and a 50 nm silicon oxide film as the first insulating films 14, 16, and a 75 nm silicon oxide film as the second insulating film 24. Under the two film thickness conditions, the length L2 of the first gate electrode 12GE protruding from the second gate electrode 26GE in the first direction D1 was changed to ±0 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, and 10 μm. Here, the length L2 is a design value.

[0178] (NBTIS reliability test conditions)

[0179] The conditions of the NBTIS reliability test are as follows.

[0180] Light irradiation conditions: With irradiation (7000lx)

[0181] Voltage applied to the first gate electrode: -60V

[0182] Voltage applied to the second gate electrode: -20V

[0183] Voltage applied to source and drain electrodes: 0V

[0184] ·Workbench temperature when stress is applied: 85°C, darkroom

[0185] Irradiation time: 1000 sec

[0186] The measurement conditions for the electrical characteristics of the transistor before and after stress application are as follows.

[0187] Source-drain voltage: 0.1V, 10V

[0188] Voltage applied to the second gate electrode: -15V to +15V

[0189] Measurement environment: 85°C, darkroom

[0190] Table 1 shows the relationship between the length L2 of the first gate electrode 12GE protruding from the second gate electrode 26GE in the first direction D1 and the variation ΔVth of the threshold voltage under condition 1 of the film thickness.

[0191] [Table 1]

[0192] L2[μm] 0 1 2 3 4 5 6 7 8 10 ΔVth[V] -3.8 -3.2 -2.9 -2.8 -2.6 -2.7 -2.9 -2.4 -2.2 -1.9

[0193] Table 2 shows the relationship between the length L2 of the first gate electrode 12GE protruding from the second gate electrode 26GE in the first direction D1 and the variation ΔVth of the threshold voltage under condition 2 of the film thickness.

[0194] [Table 2]

[0195] L2[um] 0 1 2 3 4 5 6 7 8 10 ΔVth[V] -2.2 -1.7 -1.2 -1 -0.6 -0.6 -0.6 -0.5 -0.1 -0.4

[0196] exist Figure 25 The table 1 and the table 2 show the results of the reliability tests. Figure 25 In FIG, the X-axis represents the length L2, and the Y-axis represents the variation of the threshold voltage. Figure 25 In the figure, the hollow squares represent the case of film thickness condition 1, and the black squares represent the case of film thickness condition 2. When the channel length L1 is 3 μm, as shown in FIG. Figure 25 As shown in the figure, when the length L2 is within the design value of 0 μm to 4 μm (measured value 3 μm), a dependency is observed in which the threshold voltage fluctuation ΔVth decreases as the length L2 increases. Furthermore, when the length L2 is within the design value of 5 μm to 10 μm, the threshold voltage fluctuation ΔVth does not change significantly even when the length L2 increases.

[0197] Furthermore, under film thickness condition 1, the threshold voltage fluctuation |ΔVth| is preferably 3V or less. Therefore, it is believed that under film thickness condition 1, if the length L2 is at least 2μm, the fluctuation of the transistor threshold voltage can be suppressed. Furthermore, under film thickness condition 2, the threshold voltage fluctuation |ΔVth| is preferably 1V or less. Therefore, it is believed that under film thickness condition 2, if the length L2 is 3μm or more, the fluctuation of the transistor threshold voltage can be suppressed. Furthermore, it was confirmed that film thickness condition 2 is more effective in suppressing the fluctuation of the threshold voltage than film thickness condition 1.

[0198] (Transistor Configuration under Measurement Condition 2)

[0199] The transistor used in measurement condition 2 has a configuration equivalent to Figure 1 and Figure 2 The structure of the transistor 210 shown in FIG. As the oxide semiconductor layer 22, an oxide semiconductor layer having a polycrystalline structure is used. In the following description, the bottom gate corresponds to the first gate electrode 12GE, and the top gate corresponds to the second gate electrode 26GE. Figure 2In the measurement condition 1, the channel length L1 of the channel region 22CH was set to 3 μm, and the channel width W was set to 4.5 μm. Similar to measurement condition 1, under measurement condition 2, it was also confirmed whether the characteristics of the transistor 210 changed depending on the film thicknesses of the first insulating films 14, 16, and the second insulating film 24. Two film thickness conditions were applied: Film thickness condition 1 used a stack of a 200 nm silicon nitride film and a 100 nm silicon oxide film as the first insulating films 14, 16, and a 100 nm silicon oxide film as the second insulating film 24; and film thickness condition 2 used a stack of a 100 nm silicon nitride film and a 50 nm silicon oxide film as the first insulating films 14, 16, and a 75 nm silicon oxide film as the second insulating film 24. Under the two film thickness conditions, the length L3 of the first gate electrode 12GE protruding from the oxide semiconductor layer 22 in the second direction D2 was changed to ±0 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, and 7 μm. Here, the length L3 is a design value.

[0200] (NBTIS reliability test conditions)

[0201] The conditions of the NBTIS reliability test are as follows.

[0202] Light irradiation conditions: With irradiation (7000lx)

[0203] Voltage applied to the first gate electrode: -60V

[0204] Voltage applied to the second gate electrode: -20V

[0205] Voltage applied to source and drain electrodes: 0V

[0206] ·Workbench temperature when stress is applied: 85°C, darkroom

[0207] Irradiation time: 1000 sec

[0208] The measurement conditions for the electrical characteristics of the transistor before and after stress application are as follows.

[0209] Source-drain voltage: 0.1V, 10V

[0210] Voltage applied to the second gate electrode: -15V to +15V

[0211] Measurement environment: 85°C, darkroom

[0212] Table 3 shows the relationship between the length L3 of the first gate electrode 12GE protruding from the oxide semiconductor layer 22 in the second direction D2 and the variation ΔVth of the threshold voltage under condition 1 of the film thickness.

[0213] [Table 3]

[0214] L3[μm] 0 1 2 3 4 5 6 7 ΔVth[V] -3.5 -3.4 -3 -2.6 -2.5 -2.5 -2.3 -2

[0215] Table 4 shows the relationship between the length L3 of the first gate electrode 12GE protruding from the oxide semiconductor layer 22 in the second direction D2 and the variation ΔVth of the threshold voltage under condition 2 of the film thickness.

[0216] [Table 4]

[0217] L3[μm] 0 1 2 3 4 5 6 7 ΔVth[V] -8.6 -4.2 -0.8 -0.6 -0.5 -0.4 -0.4 -0.5

[0218] The graphs showing the reliability test results in Tables 3 and 4 are Figure 26 As shown in Figure 26 In FIG, the X axis represents the length L3, and the Y axis represents the variation of the threshold voltage. Figure 26 In the figure, the hollow squares represent the case of film thickness condition 1, and the black squares represent the case of film thickness condition 2. When the channel length L1 is 3 μm, as shown in FIG. Figure 26 As shown in FIG1 , when the length L3 is within the design value of 0 μm to 1 μm, a positional offset occurs between the end of the oxide semiconductor layer and the end of the first gate electrode, causing the threshold voltage fluctuation |ΔVth| to exceed 3.0 V. When the length L3 is greater than the design value of 2 μm (measured value 1 μm), the threshold voltage fluctuation ΔVth does not change significantly even when the length L3 is increased.

[0219] Furthermore, under film thickness condition 1, the threshold voltage fluctuation |ΔVth| is preferably 3V or less. Therefore, under film thickness condition 1, if the length L3 is at least greater than 0 based on the positional offset between the end portion of the oxide semiconductor layer and the end portion of the first gate electrode, it is believed that the fluctuation in the threshold voltage of the transistor can be suppressed. Furthermore, under film thickness condition 2, the threshold voltage fluctuation |ΔVth| is preferably 1V or less. Therefore, under film thickness condition 2, if the length L3 is 2μm or more based on the positional offset between the end portion of the oxide semiconductor layer and the end portion of the first gate electrode, it is believed that the fluctuation in the threshold voltage of the transistor can be suppressed.

[0220] The various embodiments and modifications described above as embodiments of the present invention may be implemented in appropriate combinations as long as they do not contradict each other. Furthermore, solutions obtained by those skilled in the art by appropriately adding, deleting, or modifying the design of components, or by adding, omitting, or modifying conditions of processes based on the semiconductor devices and display devices of the various embodiments and modifications are also within the scope of the present invention as long as they conform to the spirit of the present invention.

[0221] Even if there are other effects that are different from the effects brought about by the schemes of the above-mentioned embodiments, if they are effects that are clearly known based on the description of this specification or effects that can be easily predicted by those skilled in the art, they are of course understood to be effects brought about by the present invention.

[0222] Description of Reference Numerals

[0223] 10: Substrate, 12GE: First gate electrode, 14: First insulating film, 16: First insulating film, 17: Oxide semiconductor film, 18: Oxide semiconductor layer, 19: Resist mask, 22: Oxide semiconductor layer, 22CH: Channel region, 22D: Drain region, 22S: Source region, 24: Second insulating film, 25: Metal oxide film, 26GE: Second gate electrode, 28: Third insulating film, 31-1, 31-2: Contact hole, 32: Third insulating film, 44D: Drain electrode, 44S: Source electrode, 45: Metal oxide film, 46: Metal oxide layer, 100, 100A, 100B: Semiconductor device, 110: Driving transistor, 120: Selecting transistor, 200: Display device, 203: Drain electrode, 210: Transistor, 210A: Transistor , 210B: transistor, 211: signal line, 212: gate line, 213: anode power line, 214: cathode power line, 215: holding capacitor, 220: liquid crystal area, 240: sealing area, 260: terminal area, 300: array substrate, 301: pixel circuit, 302: source driver circuit, 303: gate driver circuit, 304: source wiring, 306: terminal part, 307: connecting wiring, 310: sealing part, 311: liquid crystal element, 320: opposing substrate, 330: flexible printed circuit substrate, 340: chip, 350: holding capacitor, 360: insulating film, 362: insulating film, 363: opening, 370: common electrode, 380: insulating film, 381: opening, 390: pixel electrode, 392: light-emitting layer, 394: common electrode.

Claims

1. A semiconductor device comprising a transistor, The transistor includes: a first gate electrode; a first gate insulating film provided on the first gate electrode; an oxide semiconductor layer, which is provided on the first gate insulating film, overlaps with the first gate electrode, and has a polycrystalline structure; a second gate insulating film provided over the oxide semiconductor layer; and a second gate electrode provided on the second gate insulating film and overlapping with the first gate electrode; When viewed from above, the first gate electrode has: a first region overlapping the oxide semiconductor layer and protruding from the second gate electrode in a first direction; and a second region overlapping with the second gate electrode and protruding from the oxide semiconductor layer in a second direction intersecting the first direction.

2. The semiconductor device according to claim 1, wherein The transistor further includes a source electrode and a drain electrode provided on the second gate electrode and connected to the oxide semiconductor layer. In the oxide semiconductor layer, a first length from the second gate electrode to the source electrode in the first direction is equal to or greater than a second length in the first direction in the first region.

3. The semiconductor device according to claim 1, wherein The first direction is the same as the channel length of the transistor, and the second direction is the same as the channel width of the transistor.

4. The semiconductor device according to claim 3, wherein The second length is greater than 2 μm.

5. The semiconductor device according to claim 3, wherein In the second region, the third length in the second direction is greater than 0. The semiconductor device according to claim 5 , wherein: The oxide semiconductor layer includes: a first crystal region overlapping with the second gate electrode and having a first crystal structure; and a second crystal region that does not overlap with the second gate electrode and has a second crystal structure, The electrical conductivity of the second crystal region is greater than the electrical conductivity of the first crystal region.

7. The semiconductor device according to claim 6, wherein The first region overlaps with at least a portion of the second crystal region.

8. The semiconductor device according to claim 1, wherein The first gate insulating film is formed by laminating a silicon nitride film and a silicon oxide film. The first gate insulating film has a thickness of not less than 150 nm and not more than 300 nm. 9 . The semiconductor device according to claim 1 , further comprising a first metal oxide layer provided between the first gate insulating film and the oxide semiconductor layer.

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