Nor memory cell with floating gate

Abstract

An electrically erasable programmable non-volatile memory cell (1200) includes a semiconductor substrate (102) having a bit line region (104), a surface region (106) separated from the bit line region in a lateral direction, and a trench region including a bottom portion (108a) and a sidewall portion (108b) adjacent to a trench in the semiconductor substrate; a conductive control gate (120) offset from sidewalls of the trench by a first distance (A) in the lateral direction; a conductive word line (130) offset in the lateral direction relative to a second portion of the control gate by a second distance (B), the second distance being greater than the first distance; and a floating gate (150) insulated from the substrate and the word line and having a first end portion (152) closest to the control gate, separated from the control gate in the lateral direction by a third distance (C) greater than the first distance and less than the second distance.

Description

[0001] Related applications

[0002] This application is a continuation of U.S. patent application No. 18 / 429,938 filed on February 1, 2024, and claims priority to U.S. Provisional Patent Application No. 63 / 626,450 filed on January 29, 2024 and U.S. Provisional Patent Application No. 63 / 443,343 filed on February 3, 2023. Technical Field

[0003] The present invention generally relates to semiconductor memory devices, including but not limited to electrically programmable and erasable nonvolatile memory cells with floating gates, sometimes referred to as NOR memory cells. Background Art

[0004] When programming a non-volatile semiconductor memory cell array (e.g., a conventional stacked-gate memory cell in which each memory cell has a floating gate and a control gate), in order to "inject" electrons onto the floating gate, accelerated electrons in the depletion region and traveling at least partially away from the floating gate must collide with impurities or lattice defects in the substrate to generate momentum toward the floating gate. Furthermore, only electrons with sufficient energy in the direction of the floating gate to overcome the energy barrier at the silicon-oxide interface (i.e., the substrate-gate oxide interface) plus the potential change across the floating gate oxide are injected onto the floating gate. Therefore, the efficiency of the programming operation is highly dependent on the direction and energy of the programming electrons.

[0005] Electric fields within a memory cell can interfere with the direction of electron travel during programming operations. These fields can pull electrons in directions that are not optimal for injection onto the floating gate. The memory cell structure can be adjusted to overcome competing electric fields and maintain optimal electron travel during programming operations. However, such adjustments can affect the threshold voltage of specific gates, negatively impacting other operations of the memory cell. For example, read current is sensitive to the control gate voltage threshold. Therefore, optimizing a memory cell's programming efficiency may make the memory cell less efficient during other operations, resulting in a design tradeoff. Summary of the Invention

[0006] Therefore, there is a need to improve the programming efficiency of nonvolatile memory cells in a manner that minimizes the impact on other operations. This disclosure describes devices and methods configured to improve programming efficiency while maintaining sufficiently high read current when erasing a cell. The memory cell structure described herein includes multiple indium implants strategically placed throughout the substrate of the memory cell. These implants, combined with the specific architecture of the memory cell, advantageously address the tradeoff between programming efficiency and threshold voltage, which affects read current.

[0007] According to some embodiments, an electrically erasable and programmable nonvolatile memory cell (sometimes referred to as a NOR memory cell) includes a semiconductor substrate having a bit line region, a surface region separated from the bit line region in a lateral direction, and a trench region separated from the surface region in the lateral direction, the trench region including a bottom portion and a sidewall portion adjacent to a trench in the semiconductor substrate; and a conductive control gate including: a first portion disposed within the trench, insulated from the bottom portion and the sidewall portion of the trench region of the substrate, and laterally spaced from the trench region. a first end portion substantially aligned with the sidewall portion of the trench region of the substrate; and a second end portion self-aligned with an edge of the word line farthest from the second portion of the control gate.

[0008] In some embodiments, the electrically erasable programmable non-volatile memory cell includes two or more of: a first indium implant disposed in a region of the substrate below the bottom portion of the trench region; a second indium implant disposed in a region of the substrate adjacent to the sidewall portion and the surface region of the substrate; and a third indium implant disposed in a region of the substrate adjacent to a lower portion of a source or drain node of the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a better understanding of the various described embodiments, reference should be made to the following description of the embodiments in conjunction with the following drawings, wherein like reference numerals refer to corresponding parts throughout the several views.

[0010] Figure 1 is a diagram illustrating a cross-sectional view of a pair of electrically erasable and programmable nonvolatile memory cells according to some embodiments.

[0011] Figure 2 is a diagram illustrating the effect of competing electric fields on electron flow during a programming operation, according to some embodiments.

[0012] Figures 3 to 5 is a diagram illustrating an indium implant with post-implant annealing and redistribution in a substrate of a memory cell according to some embodiments.

[0013] Figures 6 and 7is a diagram illustrating a halo implant in a substrate of a memory cell according to some embodiments.

[0014] Figures 8 and 9 is a diagram illustrating an alternative plan view of a memory cell array according to some embodiments.

[0015] 10A to 10F A process for fabricating an electrically erasable programmable nonvolatile memory cell array according to some embodiments is illustrated.

[0016] Figures 11A to 11M A process for fabricating an electrically erasable programmable nonvolatile memory cell array according to some embodiments is illustrated.

[0017] Figures 12A to 12V and Figure 12W Illustrated is a block diagram of a process for fabricating an array of electrically erasable and programmable nonvolatile memory cells, each electrically erasable and programmable nonvolatile memory cell having a polysilicon floating gate, and a resulting pair of memory cells, according to some embodiments.

[0018] Figures 13A to 13V and Figure 13W Illustrated is a block diagram of a process for fabricating an array of electrically erasable and programmable nonvolatile memory cells, each electrically erasable and programmable nonvolatile memory cell having a tantalum nitride floating gate, and a resulting pair of memory cells, according to some embodiments. DETAILED DESCRIPTION

[0019] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the various disclosed embodiments. However, it will be apparent to one of ordinary skill in the art that the various described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail to avoid unnecessarily obscuring aspects of the embodiments.

[0020] It should also be understood that although in some instances, the terms first, second, etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various embodiments described, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact. Both the first contact and the second contact are contacts, but they are not the same contact unless the context clearly indicates otherwise.

[0021] The terms used in the description of the various embodiments described herein are only used to describe the purpose of specific embodiments and are not intended to limit. As used in the description of the various embodiments described and the appended claims, the singular forms "one", "an" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "first", "second" etc. are only used to distinguish an element from another element, and do not limit the element itself. It should also be understood that, as used herein, the term "and / or" refers to and encompasses any and all possible combinations of one or more items in the relevant enumerated items. It should be further understood that, when used in this specification, the term "comprising" specifies the presence of stated features, integers, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or its groups.

[0022] As used herein, the term “if” is alternatively interpreted to mean “when…” or “at…” or “in response to determining…” or “in response to detecting…”, depending on the context. Similarly, the phrases “if it is determined that…” or “if [stated condition or event] is detected” are alternatively interpreted to mean “upon determining…” or “according to determining…” or “in response to determining…” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event]”, depending on the context.

[0023] Unless otherwise stated, all distances, material thicknesses, voltages, and currents included in the following description are examples and are assumed to be specified within a margin of ten percent. For example, unless otherwise stated, the stated distances or thicknesses includes a 10% margin and therefore includes to range.

[0024] Attention is now directed to embodiments of an electrically erasable programmable nonvolatile memory cell, sometimes referred to as a NOR memory cell or a split-gate NOR memory cell, according to some embodiments. Figure 1 1 is a cross-section of a pair of memory cells 100, 101. The memory cells are mirror images of each other, with the memory cells being formed on each side of and including a shared control / erase gate 120. For the sake of brevity, the remainder of this disclosure will refer to only one memory cell, memory cell 100. However, it should be understood that the mirror image memory cell 101 (the adjacent memory cell) has corresponding features and behaves similarly under similar circumstances.

[0025] In some embodiments, memory cell 100 includes a semiconductor substrate 102 having a bitline region 104 (sometimes referred to as a drain region or source region), a surface region 106 laterally separated from the bitline region, and a trench region 108a / 108b laterally separated from the surface region, the trench region including a bottom portion 108a adjacent to the bottom surface of a trench 109 in substrate 102 and a sidewall portion 108b adjacent to the sidewalls of trench 109. In some embodiments, sidewall portion 108b of the trench region is substantially perpendicular to substrate surface 111. In some embodiments, bitline region 104 functions as a drain or source; it should be understood that the drain and source of a transistor can be switched during operation. Furthermore, in some embodiments, bitline region 104 includes substrate region 105, which is a more shallowly doped region than bitline region 104 (e.g., a moderately N-doped region in a P-doped substrate). In some embodiments, region 105 (sometimes referred to as an LDD region) is not moderately N-doped, thereby increasing the threshold voltage required to conduct current through the channel (along the surface of the substrate) between bit line region 104 and the bit line region of another memory cell.

[0026] The substrate 102 also includes a surface region 106. The surface region 106 is disposed between the bit line region 104 and the trench sidewall portion 108b. The substrate 102 also includes a horizontal surface 111 that is disposed above the bit line region 104 and extends in a lateral direction toward the trench sidewall portion 108b. The surface region 106 includes a portion of the surface 111 that is located between the bit line region 104 and the trench sidewall portion 108b. In some embodiments, at least a portion of the surface 111 is a silicon-oxide interface (e.g., between a silicon substrate and an oxide-based insulating region). For purposes of this disclosure, the term "trench" describes a region (109) from which substrate material (109) has been removed and, therefore, is absent, while the terms "trench region" (108a / 108b), "bottom portion" (108a), and "sidewall portion" (108b) describe regions of the substrate 102 that are adjacent to the trench 102.

[0027] In some embodiments, memory cell 100 also includes a conductive control / erase gate 120 (alternatively referred to as a control gate or erase gate). Control / erase gate 120 functions as a control gate or an erase gate depending on the operating mode of memory cell 100. For example, when memory cell 100 (specifically, floating gate 150) is being written to or read from, gate 120 functions as a control gate, and when memory cell 100 (specifically, floating gate 150) is being erased, gate 120 functions as an erase gate.

[0028] The control / erase gate 120 includes a first portion 122 disposed within the trench 109, insulated from the bottom portion 108a and sidewall portions 108b of the trench region of the substrate 102, and laterally separated from the trench sidewall portions 108b by a first distance A. The control / erase gate 120 also includes a second portion 124 disposed above the first portion 122 and extending away from the trench 109. In some embodiments, the first and second control / erase gate portions 122, 124 are heavily doped (e.g., n+) polysilicon, or alternatively are (or include) a metal (e.g., tungsten). In some embodiments, the second control / erase gate portion 124 includes a region 124a that extends laterally at the end of the memory cell 100 furthest from the substrate 102. Because region 124a is substantially orthogonal to the first portion 122 and the lower region of the second portion 124 of the control / erase gate 120 (e.g., forming an angle between 45° and 135°), the control / erase gate 120 can be referred to as a T-shaped gate. In some embodiments, region 124a includes a self-aligned metal silicide (sometimes referred to as a salicide) that increases the conductivity of the control / erase gate. In other words, a metal contact (silicide) is added on top of region 124a to both provide a signal or reference voltage to the control / erase gate 120 and to increase the conductivity of the control / erase line.

[0029] In some embodiments, memory cell 100 further includes a conductive word line 130 (alternatively referred to as a gate) that is insulated from control / erase gate 120 and offset in a laterally direction relative to a second portion of control / erase gate 124 by a second distance B that is greater than first distance A. Word line 130 is further disposed over and insulated from floating gate 150.

[0030] In some embodiments, memory cell 100 further includes a conductive floating gate 150 insulated from substrate 102 and word line 130. Floating gate 150 includes a first end 152 that is substantially aligned with sidewall portion 108b of the trench region of substrate 102 (more specifically, substantially aligned with the sidewall of the trench); and a second end 154 that is self-aligned with edge 132 of word line 130 that is farthest from second portion 124 of control / erase gate. In some embodiments, first end 152 of the floating gate includes a pointed tip, a portion of which has a smaller cross-section than a cross-section of second end 154 of the floating gate. In some embodiments, floating gate 150 is substantially parallel to surface 111 of the substrate. In some embodiments, due to the very thin thickness of the floating gate (e.g., or thinner), so the capacitive coupling between the floating gate 150 and the control / erase gate 120 is very small; therefore, the cross-sectional area of ​​the floating gate end 152 facing the control / erase gate 120 is much smaller than the cross-sectional area of ​​the word line 130 disposed on top of the floating gate 120. This small capacitive coupling, combined with the wider spacing B (between the control / erase gate 120 and the word line 130) relative to the spacing A (between the control / erase gate 120 and the floating gate 150), enables the thin floating gate edge 152 to act as an efficient tunneling injector. Therefore, the erase operation requires a relatively low voltage, as described below with reference to Figure 2 Described in detail.

[0031] In some embodiments, memory cell 100 also includes a dielectric layer 140 located between floating gate 150 and word line 130. Dielectric layer 140 is a "thin" dielectric layer to provide strong capacitive coupling between floating gate 150 and word line 130. In some embodiments, dielectric layer 140 includes an oxide, a nitride, a combination of oxide and nitride, or other high-k dielectric constant material. In some embodiments, dielectric layer 140 has a combined total thickness between 8 nm and 10 nm. In some embodiments, as a result of the manufacturing process, dielectric layer 140 includes: a first portion 142 that is substantially aligned with first end 152 of the floating gate and sidewall portion 108 b of the trench region of the substrate; and a second portion 144 that is substantially aligned with second end 154 of the floating gate and edge 132 of the word line farthest from second portion 124 of the control gate.

[0032] In some embodiments, memory cell 100 further includes insulating material 160 between control / erase gate 120 and word line 130, between control / erase gate 120 and floating gate 150, between control / erase gate 120 and substrate 102, and between control / erase gate 120 and dielectric layer 140. In some embodiments, insulating material 160 includes oxide, nitride, a combination of oxide and nitride, or other dielectric materials. In some embodiments, insulating material 160 provides lower capacitive coupling between control / erase gate 120 and word line 130 than conventional silicon oxide layers.

[0033] In some embodiments, the memory cell 100 further includes an erase gate insulating region 162 disposed between the first end 152 of the floating gate 150 and the second portion 124 of the control / erase gate 120, the erase gate insulating region 162 having a thickness that allows electrons to tunnel from the first end 152 of the floating gate to the second portion 124 of the control / erase gate during an erase operation. In some embodiments, the erase gate insulating region has a thickness greater than And tunneling of electrons is allowed when no more than 7V is applied between the control gate and the floating gate.

[0034] In some embodiments, memory cell 100 further includes a floating gate insulating region 164 (e.g., sometimes referred to herein as a floating gate oxide 164) disposed between surface portion 111 of substrate and floating gate 150. Floating gate insulating region 164 has a thickness that allows head-on injection of electrons traveling in an upward path into the floating gate during a programming operation. In some embodiments, floating gate insulating region 164 has at least This prevents floating gate charge loss even in a high temperature environment, thereby increasing the charge retention of the memory cell, which increases the product life of the memory cell.

[0035] In some embodiments, the conductive elements of the memory cell 100 (e.g., the control / erase gate 120, the floating gate 150, and / or the word line 130) are composed of appropriately doped polysilicon. It should be understood that "polysilicon" refers to any suitable conductive material formed at least in part of silicon or a metallic material that can be used to form the conductive elements of a non-volatile memory cell. In some embodiments, the floating gate 150 is composed of tantalum nitride, which can be very thermally stable, even up to 1000°C. In some embodiments, the floating gate 150 can have a thickness as small as 1000°C. thickness.

[0036] In some implementations, the insulating element of memory cell 100 (eg, insulating material 160) is composed of silicon dioxide, silicon nitride, and / or any suitable insulator that can be used to form an insulating element of a non-volatile memory cell.

[0037] Now turn your attention to the channel portion of the memory cell 100, as shown in FIG. Figure 2104. These channel portions are in operation during a programming operation of memory cell 100 (described in more detail below). In some embodiments, surface portion 106 of mirrored memory cell 101, sidewall portion 108b of the trench region of mirrored memory cell 101, bottom portion 108a of the trench region, and sidewall portion 108b of the trench region of memory cell 100 form a continuous channel 190 that extends from the bit line region 104 of mirrored memory cell 101 to a portion of the substrate positioned closest to the sidewall region 108b of memory cell 100. In some embodiments, adjacent portions of channel 190 are adjacent to or overlap one another, and in some embodiments, surface region 106 of mirrored memory cell 101 overlaps the bit line region 104 of mirrored memory cell 101. In other words, portions 106, 108a, and 108b form a continuous channel 190. In some embodiments, the continuous channel region formed by portion 106 (of cell 101), portion 108b (of cell 101), portions 108a and 108b (of cell 100) is non-coplanar because sidewall portion 108b of channel 190 extends substantially perpendicular to the lateral direction in which surface portion 106 extends, and bottom portion 108a of 190 extends substantially perpendicular to the direction of sidewall portion 108b of channel 190. In some embodiments, "substantially perpendicular" means an angle in the range of 75 degrees to 105 degrees.

[0038] Now refer to Figure 2 The operation of the memory cell 100 according to some embodiments is described. The following discussion discloses the erase, program, and read operations of the memory cell 100. Unless explicitly stated to refer to the mirrored memory cell 101, reference is made to Figure 2 All items described refer to items included in the memory unit 100 .

[0039] To erase the memory cell 100 (in an erase operation), a negative high voltage (e.g., approximately -7V (or alternatively, -7V to -8V)) is applied to the word line 130, and a positive high voltage (e.g., approximately 6V) is applied to the gate 120, thereby keeping the source / drain (bit line region 104) and the substrate 102 at ground. The floating gate 150 is capacitively coupled to the word line 130 and coupled to the negative voltage, which causes Fowler-Nordheim (FN) tunneling of electrons injected from the top of the floating gate (first end 152, the end pointing toward the erase gate 120) due to the enhanced field at the top of the floating gate (first end 152). As electrons are pulled out, the floating gate 150 is positively charged until the voltage drop between the floating gate 150 and the erase gate 120 is no longer strong enough to sustain a meaningful FN tunneling current. As described above, the capacitive coupling between the floating gate 150 and the erase gate 120 is very small compared to the capacitive coupling between the floating gate 150 and the word line 130. Therefore, the erase operation requires a relatively low high voltage, thereby allowing efficient erasure (also called removal or erasure) of the memory cell 100.

[0040] In some embodiments, during an erase operation, the word lines 130 of both adjacent memory cells 100 and 101 are biased at the same voltage, for example, approximately -7 V (or alternatively, -7 V to -8 V). With both word lines set to the same voltage, memory cells 100 and 101 are erased simultaneously because the memory cells along the word line pair are considered a minimum erased sector.

[0041] To program the memory cell 100 (in a programming operation), electrons are injected into the floating gate 150 of the memory cell 100 to neutralize the positive charge from an erase operation on the same memory cell, or to negatively charge the floating gate 150 of the memory cell 100. Example voltage bias values ​​for the programming operation include approximately 4V to 4.5V on the source / drain (bitline region 104) of the memory cell 100, 0V on the source / drain (bitline region 104) of the mirror memory cell 101, a positive high voltage (e.g., approximately 6V to 8V) to the word line 130 of both the memory cell 100 and the mirror memory cell 101, and 1.6V to 1.8V to the control / erase gate 120. These voltage bias values ​​cause a subthreshold current (e.g., less than 100 nA) of electrons to flow along the channel 190 from the bitline region 104 of the mirror memory cell 101 to the bitline region 104 of the memory cell 100. In some embodiments, a fixed potential (i.e., a fixed voltage) is applied to the control / erase gate 120 (e.g., 1.8 V) and the source / drain (bit line region 104) of the memory cell 100 (e.g., 4 V), and the source / drain (bit line region 104 of the mirror cell 101) is controlled with a signal pulse from 1.8 V to ground and then back to 1.8 V to perform a programming operation.

[0042] When electrons flow through the bottom trench portion 108a below the control / erase gate 120 and at the transition from the bottom trench portion 108a to the sidewall trench portion (at Figure 2 As the electrons turn upward (at the corners of the trenches marked with X in FIG), they are subjected to a strong vertical electric field component that accelerates them upward toward the substrate surface 111 below the floating gate 150. If the electrons gain sufficient energy (e.g., 3.2 eV) to overcome the energy barrier at the interface of the substrate and SiO2 at the substrate surface 111 below the floating gate 150, the electrons cross the surface 111 and are pulled toward the floating gate 150 by Coulomb attraction. This programming mechanism provides increased programming speed. As the floating gate gains electrons, the potential of the floating gate 150 decreases. This process continues until the floating gate potential is low enough to reduce the vertical field below the surface portion 106, thereby preventing the electrons in the channel from gaining sufficient energy in the vertical direction to overcome the energy barrier at the interface (the surface 111 below the floating gate 150).

[0043] Thus, during a programming operation, the word line potential (as described above), the control gate potential (as described above), and the bit line potential (as described above) are configured to enable electrons to travel below the bottom portion 108a of the trench region and along the sidewall portion 108b of the trench region (of the memory cell 100) upward toward the floating gate 150. In some embodiments, during such a programming operation, the floating gate 150 can reach a programmed state in 20 ns or less. In other words, in some embodiments, the memory cell 100 is configured during a programming operation so that the floating gate 150 reaches a programmed state in 20 ns or less during the programming operation. Additional details regarding the programming process are discussed below.

[0044] To read the memory cell 100 (in a read operation), 0V is applied to the source / drain (bit line region 104) and word line 130 of the memory cell 100, Vdd (e.g., 1.8V) is applied to the source / drain (bit line region 104) of the mirror memory cell 101, 3V to 4V (or, 2.5V to 5sV) is applied to the control gate 120, and 0V or Vdd (e.g., 1.8V) is applied to the word line 130 of the mirror memory cell 101 (i.e., no charge pump is required). These voltage bias values ​​fully turn on the trench bottom portion 108a and trench sidewall portion 108b of the channel 190, and with the substrate region under the floating gate of the mirror cell 101 fully depleted, electrons can flow freely from any portion of the trench sidewall 108b to the bit line region 104 of the mirror cell 101 without much resistance (e.g., at Figure 2 In other words, during a read operation, due to the 1.8V applied to the source / drain 104 of the mirror cell 101 and the deep halo implant 306 in the region adjacent to the source / drain of the mirror cell 101 (the bit line region 104) (see Figure 3 , and the following Figure 3 (Discussed in the preceding text), the portion of the substrate located on one side of the mirror cell 101 is fully depleted. Regardless of the mirror cell's floating gate voltage, the mirror cell channel region 190 is fully depleted. If the mirror cell floating gate voltage is positive, the mirror cell channel region has an inversion layer, but if the mirror cell floating gate voltage is negative, the mirror cell channel region does not have an inversion layer. In either case, the resistance to electron flow in the mirror cell channel region is nearly identical, and the impact on the read current is less than 3%. In other words, the read current is insensitive to the programmed / erased state of the mirror cell within a 3% tolerance.

[0045] Thus, in some embodiments, during a read operation of the memory cell 100 as discussed above, the only node that requires a charge pump (e.g., to hold the node at a voltage different from the fixed voltage potential provided to the integrated circuit in which the memory cell 100 is located) is the control / erase gate 120, thereby keeping power consumption due to charge pumping to a minimum.

[0046] In an embodiment that includes trench implants and deep halo implants but does not include corner implants (see discussion of implants below), if the floating gate 150 is sufficiently positively charged (e.g., +1.0V, or alternatively, +1.0V to +2.0V in the erased state), the field generated by the floating gate 150 completely turns on the remainder of the channel 190 (the surface portion 106 of the memory cell 100), and a high read current is generated and detected, where the floating gate channel threshold voltage is adjusted to approximately -1.0V to -1.2V. On the other hand, if the floating gate 150 is negatively charged (e.g., in a programmed state, having a potential of approximately -1.0 V to -1.5 V), the field generated by the floating gate 150 is insufficient to turn on the portion of the channel 190 located between the trench sidewall portion 108 b of the channel 190 and the bit line region 104 of the memory cell 100 (e.g., the surface portion 106 of the memory cell 100), and the read current will be at a subthreshold level.

[0047] The following discussion describes embodiments that include features for efficient programming. As described above, to program the floating gate 150 of the memory cell 100, electrons flow from the source node (bit line region 104) along the portion of the channel 190 that is located in the mirror image memory cell 101 (surface portion 106, trench sidewall portion 108b, and trench bottom portion 108a). At the transition from the trench bottom portion 108a (of the memory cell 100) to the trench sidewall portion 108b ( Figure 2 At the trench corners (marked with X in FIG), the electrons are no longer confined in the inversion layer and are released to face a stronger electric field in the fully depleted space charge region, which pulls the electrons leftward and upward (e.g., in the direction of paths 204 and 206).

[0048] To improve programming efficiency, the electrons need to be pulled primarily upward toward the floating gate 150 (in the direction of path 202). These programming electrons gain kinetic energy while accelerating, and if the energy is higher than the energy barrier height at the silicon / oxide interface at the surface 111, the electrons will be injected into the floating gate insulating region 164 ( Figure 1) and are then pulled to the floating gate 150. At the trench corner X, the electrons are affected by a pulling force (e.g., Coulomb attraction or electrostatic force caused by an electric field) from the floating gate 150 located on the top side of the memory cell 100 (in the direction of paths 202 and 204), from the drain node (bit line region 104) of the memory cell 100 (in the direction of path 206), and from the control / erase gate 120 (in the direction of the control / erase gate 120).

[0049] Thus, if the pull from the drain (bit line region 104) is about the same as the pull from the control gate, electrons flow primarily in the direction of path 202. However, if the pull from the drain (bit line region 104) is stronger than the pull from the control gate, electrons flow primarily in the direction of path 204 or 206 (depending on how much stronger the pull from the drain is compared to the pull from the control gate). Figure 2 Three electron paths 202, 204, and 206 are depicted, but for the purposes of illustrating the examples described herein, these paths are shown as three discrete lines. However, in reality, one skilled in the art will appreciate that the paths an electron may take when pulled from position X are more like a spectrum, and that the paths themselves may change based on the magnitude of the pulling force described above, as well as the pulling force from the top due to the floating gate potential. The pulling force from the floating gate decreases as the programming mechanism progresses.

[0050] If the pull from the drain node (bit line region 104) is stronger than the pull from the control / erase gate 230, the electrons will primarily flow toward path 204 or 206 when moving upward, which is undesirable because the horizontal direction of electron movement is less conducive to obtaining the energy required for vertical injection into the floating gate 150. In other words, the electrons must have a sufficient vertical component in the flow direction after passing through corner X in order to obtain sufficient energy to be injected into the floating gate 150. Therefore, in some embodiments, it is desirable to increase the control gate voltage during the programming operation to offset the pull from the drain (bit line region 104), thereby offsetting the horizontal component in the flow direction of the electrons after passing through corner X, and ensuring that the electrons have a sufficient vertical component in the flow direction to obtain sufficient energy to be injected into the floating gate 150.

[0051] However, increasing the control gate voltage during a programming operation while maintaining a low programming current would require the control gate threshold to be high, which has a negative impact on the read current. To address this tradeoff, in some embodiments, memory cells 100 and 101 include (e.g., are configured with) multiple implants to optimize the threshold voltage of different portions of channel 190, thereby achieving high programming efficiency while maintaining a sufficiently high read current for erasing cells.

[0052] For embodiments in which the word lines 130 from both memory cells in the memory cell pair 100 / 101 are biased at the same voltage for read operations (e.g., 0V), program operations (e.g., 7V), and erase operations (e.g., -7V), such a mirrored cell structure may be described above with reference to Figures 1 to 2 100 ); (ii) a drain (e.g., 104 in cells 101 / 100); (iii) a word line (the two word lines 130 are electrically connected together); and (iv) a control / erase gate 120.

[0053] Figure 3 A plurality of implants in the substrate 102 of the memory cell 100 / 101 according to some embodiments are illustrated. In some embodiments, the implants include indium (atomic number 49), which is similar to boron and is a p-type dopant, but indium is much heavier and diffuses much more slowly than boron in a silicon substrate in a high temperature environment. In some embodiments, the dopant of the implants described herein is gallium.

[0054] refer to Figure 3 , the substrate 102 includes: (i) a first indium implant, referred to as a "trench implant" 302, which is disposed in a region of the substrate below the bottom of the trench; (ii) a second indium implant, referred to as a "corner implant" 304, which is disposed in a region of the substrate adjacent to the sidewalls of the trench and in a surface region of the substrate for each memory cell 100 / 101; and (iii) a third indium implant, referred to as a "deep halo implant" 306, which is disposed in a region of the substrate adjacent to a lower portion (e.g., bottom) of the source / drain (bit line region 104) of each memory cell 100 / 101.

[0055] In some embodiments, the trench implant 302 increases the trench bottom channel (the portion of the trench 190 located within the trench bottom portion 108a, Figure 2 ) threshold voltage such that during a programming operation, the channel current is controlled to be approximately 100 nA (where the control gate 120 voltage Vcg is at approximately 1.6 V to 2.0 V) to program the memory cell in 10 ns to 20 ns (or less).

[0056] In some embodiments including corner implants 304, the corner implants 304 of each memory cell 100 / 101 decouple the floating gate channel (the portion of the channel 190 that is located in the surface region 106). Figure 2 ) is controlled at about 0.2V so that for programmed cells, the read current will be less than 1 μA and for erased cells, the read current will be greater than 10 μA. Therefore, the substrate 102 includes a second indium implant (corner implant 304) that causes the channel of the floating gate 150 (region 106, Figure 2 ) has a threshold voltage of approximately 0.2 V, such that the read current is (i) less than 1 μA when the floating gate 150 is programmed (e.g., so as to be negatively or neutrally charged) and (ii) greater than 10 μA when the floating gate 150 is erased (e.g., positively charged to +2.0 V).

[0057] In some embodiments, the deep halo implant 306 is combined with the trench implant 302 to control the punch-through current of the unselected rows (control gate 120 voltage Vcg, word line 130 voltage Vwl) to 10 pA or less. The deep halo implant 306 (which preferably does not include a lateral p-type halo between the deep halo implant and the surface of the substrate) provides the additional advantage that during a read operation of one memory cell 100 or 101, the read current is insensitive to the programmed or erased state of the mirrored memory cell 101 or 100 within a tolerance of 3%. Therefore, the substrate 102 includes a third indium implant (deep halo implant 306) that is combined with the trench implant 302 to provide a punch-through current of the unselected rows of 10 pA or less, and further, the difference in read current between the erased cell 100 and the mirrored cell 101 in the erased state or the programmed state is less than 3%. More generally, in some embodiments, the state of mirrored cell 101 affects the read current by less than 3% when reading memory cell 100, while in some other embodiments, the state of mirrored cell 101 affects the read current by less than 10% or 15% when reading memory cell 100.

[0058] In some embodiments, the substrate 102 for adjacent memory cells 100 / 101 includes only two of the three types of implants discussed above, such as Figures 4 and 5 exemplified.

[0059] For example, Figure 4 As shown, in some embodiments, substrate 102 includes trench implants 302 and halo implants 306, or similar Figure 6 The halo implants of implant 602 are shown, but the corner implants are not included. In some such embodiments, during a read operation on memory cell 100, a voltage of 3V to 4V is applied to the word line of mirror cell 101 to reduce or minimize the read current sensitivity to the programmed / erased state of mirror cell 101.

[0060] In another example, in some embodiments, substrate 102 includes corner implants 304 and deep halo implants 306, but does not include trench implants, e.g. Figure 5 As described.

[0061] Figures 6 and 7 is a diagram illustrating a halo implant in the substrate of the memory cell 100 / 101 according to some embodiments.

[0062] Conventional halo implant 602( Figure 6 ) is disposed around the bit line region 104 (source / drain node), from below the region 104 all the way to the surface 111 of the substrate 102. For this implant, during a read operation, when the source / drain node (region 104) of the mirror cell 101 is at 1.8V, the channel region 106 of the mirror cell 101 is partially depleted due to the source / drain voltage, and the read current when reading the memory cell 100 is greater than that described above with reference to FIG. Figures 1 to 5 The read current in the described memory cell is more sensitive to the programmed / erased state of the mirror cell 101 (eg, the read current when reading cell 100 may vary by as much as 25% or even more depending on the state of the mirror cell 101).

[0063] Deep Halo Implant 306( Figure 7 ) is disposed only around the lower portion of the bit line region 104 (the source / drain node), not between the lower portion and the surface 111 of the substrate 102 (not in the region 702 of the substrate). With this implant, during a read operation, with the source / drain node (region 104 of the mirror memory cell 101) at 1.8V, the channel region 106 of the mirror memory cell 101 is fully depleted, regardless of the floating gate voltage of the floating gate of the mirror memory cell 101. The deep halo implant 306 has no meaningful effect on the doping profile of the channel region 106 (i.e., at the interface between the substrate and the source / drain), where, in this context, “no meaningful effect” is defined as not preventing the depletion region in the mirror cell 101 from reaching the trench sidewall portion 108 b of the channel 190, which allows electrons to flow from the trench sidewall portion 108 b in the mirror cell 101 to the source / drain (bit line region 104) of the mirror cell 101 with little resistance when a read voltage is applied to the source / drain (bit line region 104) of the mirror cell 101.

[0064] Memory array floor plan

[0065] Now turn your attention to Figure 8 and Figure 9 , Figure 8 and Figure 9Alternative plan views of memory cell arrays 800 and 900, respectively, are illustrated according to some embodiments. In some embodiments, bit lines interconnect the drain / source regions of pairs of memory cells.

[0066] Manufacturing Process

[0067] Now turn your attention to 10A to 10F , 10A to 10F A process for fabricating memory cell 100 / 101 according to some embodiments is illustrated.

[0068] The process according to some embodiments begins with Figure 10A , Figure 10A A cross-sectional view of a silicon substrate 1002, a dielectric layer 1004 (e.g., thermal silicon dioxide or low-trap silicon nitride), a tantalum nitride floating gate material 1006, an oxide layer 1008, and a silicon nitride layer 1010 is shown. Multiple N-wells or P-wells are formed, including stripping off all oxides. A floating gate dielectric layer 1004 (e.g., thermal SiO2 or low-trap Si3N4) is formed on the substrate 1002 (e.g., approximately or alternatively, greater than Then, a floating gate material 1006 TaN (tantalum nitride) is deposited (eg, or thinner). Then, an oxide layer 1008 (e.g., approximately or thinner) and a silicon nitride layer 1010 (e.g., Then, an STI (shallow trench isolation) mask is placed for STI formation (including CMP, stopping on the silicon nitride layer).

[0069] like Figure 10B As shown, the nitride layer 1010 is stripped and a high quality Si3N4 film 1012 (approximately ) as the coupling dielectric between the word lines and the TaN floating gates. A cell array protection mask is applied to protect the memory cell array area and remove the nitride / oxide / TaN / oxide stack from other areas (e.g., the non-cell area 1014). Then, a high-voltage gate oxide and a low-voltage thin gate oxide 1016 are grown in the non-cell area, where the masking operation defines the thin oxide region.

[0070] like Figure 10C As shown, polysilicon gate material 1018 is deposited with the correct doping. A gate mask 1020 is then applied in a masking operation to define word lines 1022 and peripheral transistor gates 1024.

[0071] like Figure 10D As shown, a layer 1026 of Si3N4 is deposited (e.g., about to ), and depositing a layer 1028 of SiO2 (e.g., A trench masking operation is performed to form trenches 1030 in the control / erase gate region.

[0072] In some embodiments, a corner implant is performed prior to trench etching to dope the trench corners with p-type dopants.

[0073] like Figure 10E As shown, a stripping operation of the photoresist is performed. Then, a high temperature oxide (HTO) layer 1032 (e.g., to ) or a low-trap Si3N4 layer as the tunnel dielectric. Doped polysilicon 1034 is then deposited to fill the trench areas between the word lines, and the doped polysilicon is then partially etched back. A source / drain TaN removal mask is then placed at location 1036 to protect the trench area and peripheral areas to remove the remaining polysilicon, tunnel dielectric, and TaN in the memory cell array source / drain area. A non-cell area oxide removal mask is then placed to protect the memory cell array area to remove the remaining polysilicon, tunnel dielectric, and oxide in the non-cell area.

[0074] like Figure 10F As shown, source / drain regions 1038 are formed using a typical back-end source / drain formation process.

[0075] Manufacturing Process

[0076] Now turn your attention to Figures 11A to 11M , Figures 11A to 11M A process for fabricating memory cell 100 / 101 according to some embodiments is illustrated.

[0077] The process according to some embodiments begins with Figure 11A , Figure 11A A cross-sectional view of a silicon substrate 1102, a dielectric layer 1104 (e.g., thermal silicon dioxide or low-trap silicon nitride), a floating gate material 1106, an oxide layer 1108, and a silicon nitride layer 1110 is shown. Multiple wells are formed, including an N-well, a deep N-well, and a P-well (for peripheral regions), including stripping all oxides. A floating gate dielectric layer 1104 (e.g., thermal SiO2 or low-trap Si3N4) is formed on the substrate 1102 (e.g., approximately or thicker). Then, a peripheral HV oxide is formed (e.g., to ) and thin oxides (e.g. Then, a polysilicon floating gate material 1106 (approximately N-type doping (Poly 1)), and depositing an oxide layer 1108 (e.g., approximately ) and a sacrificial silicon nitride layer 1110 (e.g., Si3N4, Then, an STI mask is placed for STI formation (including CMP, stopping on the silicon nitride layer).

[0078] like Figure 11B As shown, the portion of the oxide located in the STI (above the substrate) is removed by anisotropic etching.

[0079] like Figure 11C As shown, the remaining silicon nitride is removed and high-quality silicon nitride is re-deposited. A layer 1114 of silicon nitride or a combination of oxide and silicon nitride serves as the coupling dielectric material between the word lines and the floating gates. A cell array protection mask is then placed to protect the memory cell array area and remove the nitride / oxide from other areas (no cell areas). Next, N-type doped polysilicon (Poly 2) 1116 is deposited. This polysilicon will become the word line material in the cell array and the gate material for the peripheral transistors (Poly 2 and Poly 1 are connected together). Oxide 1118 is then deposited.

[0080] like Figure 11D As shown, a gate mask 1120 is placed to define word lines and word line pickup regions in the cell array and gates of peripheral transistors (not shown).

[0081] like Figure 11E As shown, an anisotropic etch is performed to partially remove the oxide / poly 2 / nitride stack and poly 1, with approximately 1% remaining (in region 1122). Then, the photoresist is stripped.

[0082] like Figure 11F As shown, the deposition quality The HTO layer 1124 is then anisotropically etched to remove the remaining On top of Poly 1 HTO.

[0083] like Figure 11G As shown, polysilicon (Poly 1) 1106 is subjected to isotropic etching and appropriate over-etching to produce a sharp Poly 1 edge 1126 (also called a tip, sharp tip or pointed tip) that will serve as a tunneling injector. 10A to 10F The described tantalum floating gate may have to The thickness of the Poly 1 floating gate 1106 may be to The thickness of the top 1126 is less than (usually to ) thickness.

[0084] like Figure 11H As shown, a trench mask 1128 is placed and a corner implant 1130 is applied to define the threshold voltage of the floating gate channel (e.g., an indium implant at a 7 degree angle along the word line direction, where the stray portion of the implanted indium impurities dopes the trench corners). Corner implant 1130 corresponds to Figure 3 Corner implant 304 in.

[0085] like Figure 11I As shown, a portion of the substrate silicon 1102 is subjected to anisotropic etching to produce approximately Then, a trench implant 1134 (e.g., Indium 80 KeV, tilted 7 degrees along the word line direction) is applied. The trench implant 1134 corresponds to Figure 3 The groove implant 302 is formed in the groove.

[0086] like Figure 11J As shown, the photoresist is stripped from region 1136 .

[0087] like Figure 11K As shown, a HTO layer 1138 (e.g., ) as the tunnel dielectric material between the floating gate and the control / erase gate.

[0088] like Figure 11L As shown, a control / erase gate mask is used to define the erase gate, and doped polysilicon (Poly3) 1140 is deposited as the control / erase gate material.

[0089] like Figure 11M As shown, source / drain regions 1142 are formed. In some embodiments, during the formation of source / drain regions 1142, conventional halo implants with lateral haloes are not present in the memory cell array area. Instead, indium punch-through suppression (deep halo) implants 1144 are applied. The deep halo implants 1144 correspond to Figure 3 Deep halo implant 306 in.

[0090] In some embodiments, for applying implant 1130 ( Figure 11H )、1134( Figure 11I ) and 1144( Figure 11M ) is applied in a similar manner to 10A to 10F The process flow in .

[0091] like Figure 11MAs shown, the shape of the floating gate 150 is defined by shallow trench isolation (STI) on one side and the word line 130 on the other side, so no separate mask is involved in forming the floating gate 150 .

[0092] Second manufacturing process

[0093] Now turn your attention to Figures 12A to 12V , Figures 12A to 12V A process for fabricating a pair of electrically erasable and programmable nonvolatile memory cells, including electrically erasable and programmable nonvolatile memory cells 1200 / 1201, is illustrated according to some embodiments. Figures 12A to 12V 1 shows a cross-sectional view of the pair of memory cells 1200, 1201 as the manufacturing process progresses. Note that Figures 12A to 12V as well as Figure 12W 、 Figures 13A to 13V and Figure 13W The structures shown in the drawings are not drawn to scale, and in order to make some features visible in these figures, these features are shown at a disproportionately larger size.

[0094] like Figure 12A As shown, the process of fabricating an electrically erasable programmable non-volatile memory cell begins with a substrate 1202 having an insulator layer 1204 and a floating gate layer 1206 (eg, polysilicon) disposed thereon. Figure 12A A cross-sectional view of a silicon substrate 1202, a dielectric layer 1204 (e.g., thermal silicon dioxide or low-trap silicon nitride), and a floating gate layer 1206 (e.g., polysilicon) are shown. In some embodiments, the polysilicon floating gate layer 1206 has a thickness of 200 angstroms to 400 angstroms ( to ) thickness, for example, The dielectric layer 1204 is sometimes referred to as a floating gate oxide layer because it is positioned between the floating gate layer 1206 and the substrate 1202 .

[0095] Next, if Figure 12B As shown, deposition Figure 12A The structure shown includes a series of additional layers 1208-1216, including a dielectric (e.g., oxide) layer 1208 (sometimes referred to as a coupling oxide / dielectric or a wordline gate oxide / dielectric), a polysilicon layer 1210 (sometimes referred to as a Poly2 layer or a wordline layer), a stacked dielectric (e.g., oxide) layer 1212, a silicon nitride (e.g., Si3N4) layer 1214, and on top another dielectric (e.g., oxide) layer 1216. In some embodiments, dielectric layer 1216 is used to protect memory structure elements beneath dielectric layer 1216 during subsequent processing.

[0096] like Figure 12C As shown, using mask 1220 and a suitable etchant and process (e.g., anisotropic etching), Figure 12B The structure shown has trenches 1222 opened to remove portions of dielectric layer 1216 , silicon nitride layer 1214 , and stacked dielectric layers 1212 that are not protected by mask 1220 . Figure 12C The etching operation depicted in FIG stops at the silicon nitride layer 1210. Note that reference numeral 1222 is used herein to identify the trench, even when the shape (e.g., width and depth) of the trench changes during subsequent processing steps. At this initial stage, the "trench" 1222 is not yet a true trench because it has not yet extended into the substrate 1202.

[0097] Next, if Figure 12D As shown, word line (WL) spacer (eg, dielectric) material is deposited and etched back to form word line (WL) spacers 1224 on the outer vertical edges of the trenches 1222. Thus, the trenches 1222 are substantially narrowed.

[0098] Next, if Figure 12E As shown, using the WL spacer 1224 as a mask, an anisotropic etch 1226 is used to etch the polysilicon word line layer 1210 and the coupling oxide / dielectric layer 1208, and partially etches the polysilicon floating gate layer 1206 so that the trench 1222 is now separated from the substrate 1202 by a portion of the polysilicon floating gate layer 1206 and the floating gate oxide / dielectric 1204.

[0099] Next, if Figure 12F and Figure 12G As shown, offset spacers 1228 (e.g., a dielectric material) are deposited and etched back to create narrower trenches 1222 (for ease of reference, the label 1222 will continue to be applied to "trench" even though the dimensions of the trenches, including width and depth, change as processing continues), wherein the offset spacers 1128 separate the word line layer 1210 from the trenches. The boundary between the WL spacers 1224 and the offset spacers 1228 is indicated by a dashed line. In some embodiments, the WL spacers 1224 and the offset spacers 1228 are formed of the same dielectric (e.g., silicon oxide).

[0100] Next, if Figure 12HAs shown, the etching operation (e.g., isotropic etching) removes the remaining portion of the polysilicon layer 1206 located at the bottom of the trench 1222 and also etches the portion of the polysilicon layer 1206 located below the offset spacer 1228 and adjacent to the bottom of the trench 1222, thereby forming a polysilicon tip 1232 facing the trench 1222 (e.g., the tip 1232 is the narrowest portion of the polysilicon layer and is also the portion of the polysilicon floating gate 150 formed by the polysilicon layer 1206 closest to the trench 1222 (see FIG. 2 ). Figure 12W )).

[0101] Next, if Figure 12I As shown, a first tunnel oxide 1234 (e.g., a dielectric layer) is deposited in the trench 1222. At this point, the polysilicon top 1232 is separated from the trench 1222 only by the first tunnel oxide 1234, while the rest of the polysilicon layer 1206 (floating gate 150) and the word line layer 1210 are separated from the trench 1222 by the offset spacer 1228 and the first tunnel oxide 1234.

[0102] Next, if Figure 12J As shown, an oxide etch (e.g., anisotropic etch) operation is performed to extend the trench 1222 into the substrate while minimizing etching of the first tunnel oxide 1234. In some embodiments, after completing Figure 12J After the etching operation in, the lateral thickness of the first tunnel oxide 1234 is approximately (For example, less than ) (within a margin of 10% to 15%), and in some embodiments has to Thickness. Figure 12J As shown, the floating gate 150 covers the entire portion of the floating gate oxide 164 except for the portion closest to the trench 1222, which portion is sometimes referred to herein as an offset gap 1238. The presence of the offset gap 1238 in the memory cell increases the floating gate threshold voltage (e.g., the voltage of the floating gate 150) relative to the voltage of the substrate 102 required to enable at least a predetermined amount of current (e.g., the amount of current required to determine the state of the memory cell 1200 during a read operation) to flow through the channel 190 below the floating gate oxide 1204 / 164 (see Figure 12W ).

[0103] Next, if Figure 12KAs shown, a trench implant operation is performed during which a trench implant 1240 is introduced into the substrate below the trench 1222 (e.g., in a region of the substrate 102 below the bottom of the trench 1222). In some embodiments, the trench implant 1240 comprises an indium implant. The properties of the trench implant 1240 are discussed above with respect to the trench implant 302 (e.g., to determine or increase the threshold voltage of the trench bottom portion of the channel 190).

[0104] Next, usually after trench implantation, e.g. Figure 12L As shown, a second tunnel oxide 1242 (e.g., a dielectric layer) is deposited in the trench 1222. At this point, the polysilicon top 1232 is separated from the trench by both the first tunnel oxide 1234 and the second tunnel oxide 1242, while the rest of the polysilicon layer 1206 (floating gate 150) and the wordline layer 1210 are separated from the trench 1222 by the offset spacer 1228, the first tunnel oxide 1234, and the second tunnel oxide 1242. Figure 12L The dashed lines in FIG indicate the boundaries between the WL spacers 1224, the offset spacers 1228, the first tunnel oxide 1234, and the second tunnel oxide 1242. In some embodiments, the lateral thickness of the second tunnel oxide 1242 is approximately (within a margin of 10% to 20%), and in some embodiments has to thickness.

[0105] Next, if Figure 12M As shown, one or more conductive materials are deposited in trench 1222 to form a control gate. In some embodiments, the conductive material forming the control gate includes polysilicon, and in some embodiments includes metals such as titanium nitride and / or tungsten. Figure 12M As shown, an etching operation 1244 is performed to remove excess upper portions of the insulator layer and conductive material forming the control gate. Figure 12M Conductors extending in directions not visible in the cross-sectional view of the memory cell form electrical connections to control gates (eg, control gates of other memory cell pairs in the same row or column of the memory cell).

[0106] Next, if Figure 12N As shown, a dielectric material (eg, oxide) is formed on top of the memory cell pair and then planarized, for example, using chemical-mechanical planarization (CMP). Figure 12O As shown, the silicon nitride structure formed by the silicon nitride layer 1214 is removed by etching 1248, thereby producing Figure 12O The structure shown. Figure 12PAs shown, a further etching operation 1250 removes the word line, floating gate, and word line gate layers 1206, 1208, 1210 that are farthest from the control gate to form Figure 12P The structure shown.

[0107] exist Figure 12P In the embodiment, portions of the polysilicon layers 1206, 1210 are exposed and these portions are subsequently covered by a dielectric layer, as shown in FIG. Figure 12Q As shown, a protective dielectric layer is formed over the word lines and outer portions of the floating gates.

[0108] Next, first silicon nitride spacers 1254 are added to the outer portions of the memory pair structure (eg, deposited on these outer portions and then anisotropically etched), as shown. Figure 12R As shown, an oxide etching operation is then performed, as Figure 12S As shown, a silicon oxide layer is then deposited, and then a second silicon nitride spacer is added to the outer portion of the memory pair structure, as shown Figure 12T shown.

[0109] Next, if Figure 12U As shown, a deep halo implant operation 1260 is performed to add dopants such as indium to the region of the substrate below the drain / source regions (bit line regions 104) of both memory cells 1200, 1201. The properties of deep halo implant 1260 are discussed above with respect to deep halo implant 306.

[0110] Finally, bit line (eg, N+) and LDD implant operations are performed to form bit lines and LDD regions for each memory cell 1200, 1201. The LDD implant is optional and depends on the desired threshold level of the floating gate 150 (see Figure 12W ). In addition, if Figure 12W As shown, the floating gate 150 (eg, in Figure 12P The remaining portion of the floating gate region 1206 after the illustrated etching operation does not overlap with the LDD region 105 of each memory cell 1200, 1201 (regardless of whether the "LDD region" 105 is implanted with N+ dopants), thereby forming an offset region in the substrate 102 between the source / drain (bit line) region 104 and the portion of the channel 190 covered by the floating gate 150. The LDD region 105 is sometimes referred to herein as the distal portion of the channel within an electrically erasable and programmable non-volatile memory cell, which is farthest from the trench region and is not overlapped by the floating gate 150.

[0111] Second memory cell structure

[0112] Figure 12WA block diagram of a memory cell pair structure resulting from the fabrication process described above is shown, the memory cell pair structure including electrically erasable programmable nonvolatile memory cells 1200 and 1201 . Figure 9 The following table shows the usage of Figure 12W An example of a plan view of a memory cell array of an embodiment of a memory cell pair structure. In some embodiments, memory cell 1200 includes:

[0113] A semiconductor substrate (102) having a bit line region (104), a Figure 12W a surface region (106) separated from the bit line region in a horizontal direction (in a horizontal direction in a semiconductor substrate), and a trench region separated from the surface region 106 in a lateral direction, the trench region including a bottom portion (108a) and a sidewall portion (108b) adjacent to a trench (109) in the semiconductor substrate;

[0114] A conductive control gate (120), the conductive control gate comprising:

[0115] a first portion (122) disposed within the trench, insulated from a bottom portion and a sidewall portion of the trench region of the substrate, and spaced apart from a sidewall of the sidewall portion of the trench region by a first distance (A) in a lateral direction; and

[0116] a second portion (124) disposed above the groove and extending away from the groove (109);

[0117] a conductive word line (130) insulated from the control gate (120) and offset in a lateral direction relative to the second portion (124) of the control gate by a second distance (B), the second distance being greater than the first distance;

[0118] A floating gate (150) (e.g., a polysilicon floating gate) insulated from the substrate (102) and the word line (130) and comprising:

[0119] a first end portion (152) comprising a portion of the floating gate closest to the control gate, the first end portion being laterally separated from a second portion of the control gate by a third distance (C) that is greater than the first distance (A) and less than the second distance (B); and

[0120] A second end (154) is self-aligned with an edge 132 of the word line farthest from the second portion of the control gate.

[0121] In some embodiments, the second memory cell 1201 in the memory cell pair has the same structural components as the first memory cell 1200 , except that the two memory cells share the same control gate 120 , and the components of the second memory cell 1201 are arranged to mirror the components of the first memory cell 1200 .

[0122] In some embodiments, as Figure 12W As shown (also as Figure 12L ), the conductive word line is insulated from the control gate by a series of insulators and offset relative to the second portion of the control gate, the series of insulators including an offset spacer, a first tunnel oxide, and a second tunnel oxide, the series of insulators separating the word line from the control gate in a lateral direction by a second distance (B), the second distance being greater than the first distance (A). In addition, in such an embodiment, the first end portion (152) of the floating gate is separated from the second portion (124) of the control gate (120) by the first tunnel oxide and the second tunnel oxide rather than the offset spacer.

[0123] In some embodiments, the second tunnel oxide, but not the first tunnel oxide, extends into the trench.

[0124] In some embodiments, memory cell 1200 further comprises a first indium implant (1240) disposed in a region of the substrate below a bottom portion of the trench region and a second indium implant (1260) disposed in a region of the substrate adjacent to a source or drain region of the memory cell. Furthermore, in some embodiments, the first indium implant causes a threshold voltage of the channel in the bottom portion of the trench region to control a programming current of 100 nA during a programming operation, wherein the control gate voltage is between 1.6 V and 2.0 V and the floating gate is configured to reach a programmed state in 20 ns or less upon application of the programming current. In some embodiments, the second indium implant, in combination with the first indium implant, causes: (i) a punch-through current of an unselected row of memory cells to be 10 pA or less; and (ii) a read current to be insensitive to the programmed / erased state of the mirror cell (e.g., memory cell 1201) within a 10% tolerance.

[0125] In some embodiments, the lateral extent of the first tunnel oxide corresponds to a channel (190, Figure 12W ) extending from the bit line region (104) of the substrate (102) to the sidewall portion of the trench region (109), which is not overlapped by the floating gate (150); see Figure 12W In other words, the width (or lateral extent) of the first tunnel oxide corresponds to Figure 12J The offset gap 1238 is shown. See above for Figure 12JDiscussion.

[0126] In some embodiments, the gate insulating region (162, Figure 12W ) is disposed between a first end portion (152) of the floating gate (150) and a second portion (124) of the control gate (120), the erase gate insulating region corresponding to portions of the first tunnel oxide and the second tunnel oxide disposed between the first end portion of the floating gate and the second portion of the control gate, and the erase gate insulating region has a thickness that allows electrons to tunnel from the first end portion of the floating gate to the second portion of the control gate during an erase operation. In some embodiments, the erase gate insulating region has a thickness greater than (For example, within a 10% or 15% error margin), and allows tunneling of electrons when no more than 7V is applied between the control gate and the floating gate.

[0127] In some embodiments, the floating gate includes a thickness between and The polysilicon between the first end and the top end has less than thickness.

[0128] In some embodiments, the control gate is configured to function as an erase gate during an erase operation.

[0129] In some embodiments, the memory cell 1200 includes a floating gate insulating region (164) disposed between a surface region of the substrate and the floating gate, wherein the floating gate insulating region has a thickness that allows front injection of electrons traveling in an upward path into the floating gate during a programming operation.

[0130] In some embodiments, the wordline potential of the wordline, the control gate potential of the control gate, and the bitline potential of the bitline region are configured to enable electrons to travel under a bottom portion of the trench region and then upward toward the floating gate during a programming operation.

[0131] In some embodiments, the floating gate 150 is configured to reach a programmed state in 20 ns or less during a programming operation.

[0132] In some embodiments, the word line (130) is electrically connected to the word line (130) of the mirror memory cell; the electrically erasable and programmable non-volatile memory cell (1200) and the mirror memory cell (1201) form a four-node memory cell pair, the four nodes consisting of a source node, a drain node, a word line node, and a control / erase node; and the word line node includes the electrically connected word line, the control / erase node includes a control gate shared by the electrically erasable and programmable non-volatile memory cell (1200) and the mirror memory cell (1201), and the source node or the drain node includes or is electrically connected to the bit line region (104) of the electrically erasable and programmable non-volatile memory cell (1200). Alternatively, the word line (130) is not electrically connected to the word line (130) of the mirror memory cell; the electrically erasable and programmable non-volatile memory cell (1200) and the mirror memory cell (1201) form a five-node memory cell pair, the five nodes consisting of a source node, a drain node, a first word line node (for the first memory cell 1200) and a second word line node (for the mirror memory cell 1201), and a control / erase node; and the first word line node includes the word line of the first memory cell, the second word line node includes the word line of the mirror memory cell, the control / erase node includes a control gate, which is shared by the electrically erasable and programmable non-volatile memory cell (1200) and the mirror memory cell (1201), the source node includes or is electrically connected to the bit line region (104) of the electrically erasable and programmable non-volatile memory cell (1200), and the drain node includes or is electrically connected to the bit line region (104) of the electrically erasable and programmable non-volatile mirror memory cell (1201).

[0133] 4-node and 5-node configurations of memory cell pairs

[0134] Figure 12W The illustrated memory cell pair (which includes two memory cells 1200 and 1201 sharing a control gate) can be used as a four-node device (where the word lines of the two memory cells are electrically connected to the same node and controlled together), or as a five-node device (where the word lines of the two memory cells are controlled separately). The following table shows examples of control voltages to be applied to the nodes of a four-node device and a five-node device for performing a read operation (a first memory cell and a second memory cell), a program operation (a first memory cell and a second memory cell), and an erase operation. Unless otherwise specified, all voltage examples for operating the pair of memory cells will be considered to vary by up to 10% of the control voltage examples provided in the tables herein.

[0135] Table 1-4 Node Memory Cell Pair, Polysilicon Floating Gate Control Voltage

[0136]

[0137] Table 2-5 Control voltages of the polysilicon floating gate for the memory cell pairs at the node

[0138]

[0139]

[0140] The third manufacturing process

[0141] Figures 13A to 13V Illustrated is a process for fabricating a pair of electrically erasable and programmable nonvolatile memory cells (including electrically erasable and programmable nonvolatile memory cells 1300 / 1301) having a tantalum nitride floating gate, and using Figures 12A to 12V As indicated below in the description of the third manufacturing process, Figures 13A to 13V Many parts of the manufacturing process are related to Figures 12A to 12V The manufacturing process is the same.

[0142] Figures 13A to 13V 1 shows a cross-sectional view of a pair of memory cells 1300, 1301 as the manufacturing process progresses. Note that Figures 13A to 13V as well as Figure 13W The structures shown in the drawings are not drawn to scale, and in order to make some features visible in these figures, these features are shown at a disproportionately larger size.

[0143] like Figure 13A As shown, the process of fabricating an electrically erasable programmable non-volatile memory cell begins with a substrate 1302 on which is disposed an insulator layer 1304 and a floating gate layer 1306 (eg, tantalum nitride (TaN)). Figure 13A A cross-sectional view of a silicon substrate 1302, a dielectric layer 1304 (e.g., thermal silicon dioxide or low-trap silicon nitride), a floating gate layer 1306 (e.g., TaN), and a dielectric (e.g., oxide) layer 1308 (sometimes referred to as a coupling oxide / dielectric or wordline gate oxide / dielectric) is shown. In some embodiments, the TaN floating gate layer 1306 has a thickness of 8 to 20 angstroms ( to ) thickness, for example, The dielectric layer 1304 is sometimes referred to as a floating gate oxide layer because it is positioned between the floating gate layer 1306 and the substrate 1302 .

[0144] Next, if Figure 13B As shown, deposition Figure 13AThe structure shown includes a series of additional layers 1310 through 1316, including a polysilicon layer 1310 (sometimes referred to as a Poly2 layer or wordline layer), a stacked dielectric (e.g., oxide) layer 1312, a silicon nitride (e.g., Si3N4) layer 1314, and on top another dielectric (e.g., oxide) layer 1316. In some embodiments, dielectric layer 1316 is used to protect memory structure elements beneath dielectric layer 1316 during subsequent processing.

[0145] like Figure 13C As shown, using mask 1320 and a suitable etchant and process (e.g., anisotropic etching), Figure 13B The structure shown has trenches 1322 opened to remove portions of dielectric layer 1316 , silicon nitride layer 1314 , and stacked dielectric layers 1312 not protected by mask 1320 . Figure 13C The etching operation depicted in FIG stops at the silicon nitride layer 1314. Note that reference numeral 1322 is used herein to identify the trench, even if the shape (e.g., width and depth) of the trench changes during subsequent processing steps. At this initial stage, the "trench" 1322 is not yet a true trench because it has not yet extended into the substrate 1302.

[0146] Next, if Figure 13D As shown, word line (WL) spacer (eg, dielectric) material is deposited and etched back to form word line (WL) spacers 1324 on the outer vertical edges of the trenches 1322. Thus, the trenches 1322 are substantially narrowed.

[0147] Next, if Figure 13E As shown, the polysilicon wordline layer 1310 is etched using an anisotropic etch 1326 (eg, a polysilicon etch) using the WL spacers 1324 as a mask so that trenches 1322 are now separated from the substrate 1302 by the TaN floating gate layer 1306 and the floating gate oxide / dielectric 1304 .

[0148] Next, if Figure 13F and Figure 13G As shown, offset spacers 1328 (e.g., a dielectric material) are deposited and etched back 1330 to create narrower trenches 1322 (for ease of reference, the label 1322 will continue to be applied to "trench" even though the dimensions of the trenches, including width and depth, change as processing continues), wherein the offset spacers 1328 separate the word line layer 1310 from the trenches. The boundary between the WL spacers 1324 and the offset spacers 1328 is indicated by a dashed line. In some embodiments, the WL spacers 1324 and the offset spacers 1328 are formed of the same dielectric (e.g., silicon oxide).

[0149] Next, if Figure 13H As shown, an etching operation 1332 (eg, isotropic etching) removes the TaN layer 1306 at the bottom of the trench 1322, thereby forming an end portion (TaN top) of the TaN layer 1306 facing the trench 1322 (eg, the TaN top 1333 is the TaN floating gate 150 (see FIG. Figure 13W ) of the portion of the TaN layer 1306 closest to the trench 1322).

[0150] Next, if Figure 13I As shown, a first tunnel oxide 1334 (eg, a dielectric layer) is deposited in the trench 1322. Then, as shown in FIG. Figure 13J As shown, an oxide etch (e.g., anisotropic etch) operation is performed to extend the trench 1322 into the substrate while minimizing etching of the first tunnel oxide 1334. At this point, the TaN top 1333 is separated from the trench 1322 by the first tunnel oxide 1334, while the word line layer 1310 is separated from the trench 1322 by the offset spacer 1328 and the first tunnel oxide 1334.

[0151] In some embodiments, after completing Figure 13J After the etching operation in, the lateral thickness of the first tunnel oxide 1334 is approximately (within a margin of 10% to 15%), and in some embodiments has to Thickness. Figure 13W As shown, the floating gate 150 (corresponding to the TaN layer 1306) covers the entire portion of the floating gate oxide 164, except for the portion closest to the trench 1322, which portion is sometimes referred to herein as an offset gap 1338. The presence of the offset gap 1338 in the memory cell increases the floating gate threshold voltage (e.g., the voltage of the floating gate 150) relative to the voltage of the substrate 102, which is required to enable at least a predefined amount of current (e.g., the amount of current required to determine the state of the memory cell 1300 during a read operation) to flow through the channel 190 below the floating gate oxide 1304 / 164 (see Figure 13W ).

[0152] Next, if Figure 13K As shown, a trench implant operation is performed during which a trench implant 1340 is introduced into the substrate below the trench 1322 (e.g., in a region of the substrate 102 below the bottom of the trench 1322). In some embodiments, the trench implant 1340 comprises an indium implant. The properties of the trench implant 1340 are discussed above with respect to the trench implant 302 (e.g., to determine or increase the threshold voltage of the trench bottom portion of the channel 190).

[0153] Next, usually after trench implantation, e.g. Figure 13L As shown, a second tunnel oxide 1342 (e.g., a dielectric layer) is deposited in the trench 1322. At this point, the TaN top 1333 is separated from the trench by both the first tunnel oxide 1334 and the second tunnel oxide 1342, while the word line layer 1310 is separated from the trench 1322 by the offset spacer 1328, the first tunnel oxide 1334, and the second tunnel oxide 1342. Figure 13L The dashed lines in FIG indicate the boundaries between the WL spacers 1324, the offset spacers 1328, the first tunnel oxide 1334, and the second tunnel oxide 1342. In some embodiments, the lateral thickness of the second tunnel oxide 1342 is approximately (within a margin of 10% to 20%), and in some embodiments has to thickness.

[0154] Next, if Figure 13M As shown, one or more conductive materials are deposited in trench 1322 to form a control gate. In some embodiments, the conductive material forming the control gate includes polysilicon, and in some embodiments includes metals such as titanium nitride and / or tungsten. Figure 13M As shown, an etching operation 1344 is performed to remove excess upper portions of the insulator layer and conductive material forming the control gate. Figure 13M Conductors extending in directions not visible in the cross-sectional view of the memory cell form electrical connections to control gates (eg, control gates of other memory cell pairs in the same row of the memory cell).

[0155] Next, if Figure 13N As shown, a dielectric material (eg, oxide) is formed on top of the memory cell pair and then planarized, for example, using chemical-mechanical planarization (CMP). Figure 13O As shown, the silicon nitride structure formed by the silicon nitride layer 1314 is removed by etching 1348, thereby producing Figure 13O The structure shown. Figure 13P As shown, a further etching operation 1350 removes the word line, floating gate, and word line gate layers 1306, 1308, 1310 that are farthest from the control gate to form Figure 13P The structure shown.

[0156] exist Figure 13P In the embodiment, portions of the TaN layer 1306 and the polysilicon layer 1310 are exposed, and these portions are covered by the dielectric layer 1352 deposited in a subsequent step, as shown in FIG. Figure 13Q As shown, a protective dielectric layer is formed over the word lines and outer portions of the floating gates.

[0157] Next, first spacers 1354 are added to the outer portions of the memory pair structures (eg, deposited on these outer portions and then anisotropically etched), as shown. Figure 13R As shown, an oxide etching operation is then performed, as Figure 13S As shown, second spacers are then added to the outer portions of the memory pair structures (eg, deposited on these outer portions and then anisotropically etched), as shown. Figure 13T shown.

[0158] Next, if Figure 13U As shown, a deep halo implant operation 1360 is performed to add dopants such as indium to the region of the substrate below the drain / source regions (bit line regions 104) of both memory cells 1300, 1301. The properties of deep halo implant 1360 are discussed above with respect to deep halo implant 306.

[0159] Finally, bit line (eg, N+) and LDD implant operations are performed to form bit lines and LDD regions for each memory cell 1300, 1301. The LDD implant is optional and depends on the desired threshold level of the floating gate 150 (see Figure 13W ). In addition, if Figure 13W As shown, the floating gate 150 (eg, in Figure 13P The remaining portion of the floating gate region 1306 after the illustrated etching operation does not overlap with the LDD region 105 of each memory cell 1300, 1301 (regardless of whether the “LDD region” 105 is implanted with N+ dopants), thereby forming an offset region in the substrate 102 between the source / drain (bit line) region 104 and the portion of the channel 190 covered by the floating gate 150. The LDD region 105 is sometimes referred to herein as the distal portion of the channel within an electrically erasable and programmable non-volatile memory cell, which is farthest from the trench region and is not overlapped by the floating gate 150.

[0160] In some embodiments, a method of fabricating an electrically erasable programmable nonvolatile memory cell (such as by a series of Figures 12A to 12V Described method of manufacture, or by Figures 13A to 13V The method includes forming a base structure, forming a series of layers on a substrate, the series of layers including a floating gate layer separated from the substrate by a floating gate insulating layer, a word line layer separated from the floating gate layer by a dielectric layer, and one or more protective layers above the word line layer.

[0161] 1) forming a trench through the series of layers to form electrically isolated portions of the floating gate layer and the word line layer, the electrically isolated portions including a first floating gate region and a first word line region for a first memory cell of a pair of memory cells and a second floating gate region and a second word line region for a second memory cell of the pair of memory cells, and first and second guard regions positioned over the first and second word line regions of the first and second memory cells, respectively;

[0162] 2) forming an offset spacer, a first tunnel oxide, and a second tunnel oxide in the trench in sequence, such that portions of the first floating gate region and the second floating gate region closest to the trench are separated from the control gate formed in the trench by the first tunnel oxide and the second tunnel oxide instead of the offset spacer, and the first word line and the second word line are separated from the trench by the offset spacer, the first tunnel oxide, and the second tunnel oxide; and

[0163] 3) Forming a control gate in the trench.

[0164] In some embodiments, in the aforementioned fabrication method, a portion of the trench extends into the substrate, and the second tunnel oxide, but not the first tunnel oxide, extends into the portion of the trench extending into the substrate.

[0165] In some embodiments, the aforementioned fabrication method includes forming a conductive control gate within the trench, wherein the conductive control gate is a control gate for both a first memory cell and a second memory cell of the pair of memory cells.

[0166] In some embodiments, in the aforementioned manufacturing method, the first tunnel oxide has a thickness less than Similarly, in some embodiments, in the aforementioned manufacturing method, the second tunnel oxide has a lateral thickness of less than lateral thickness.

[0167] In some embodiments, the aforementioned manufacturing method includes: forming a first indium implant in a region of the substrate located below a bottom portion of the trench; and forming a second indium implant in a region of the substrate adjacent to the source / drain region of the first memory cell and the source / drain region of the second memory cell.

[0168] Memory cell structure 3

[0169] Figure 13W A block diagram of a memory cell pair structure resulting from the fabrication process described above is shown, the memory cell pair structure including electrically erasable programmable nonvolatile memory cells 1300 and 1301 . Figure 9 The following table shows the usage of Figure 13WAn example of a plan view of a memory cell array of an embodiment of a memory cell pair structure. In some embodiments, memory cell 1300 includes the same elements as described above for memory cell 1200, except that the floating gate (150) is formed of or includes tantalum nitride (TaN) rather than polysilicon. The TaN floating gate layer typically has a thickness of 8 to 20 angstroms ( to ) thickness, for example, The thickness of the TaN floating gate is within a margin of ten percent (10%). The top 1333 of the TaN floating gate (see Figure 13H ) (including the portion of the TaN floating gate closest to the control gate) typically has the same thickness as the TaN floating gate, e.g. to

[0170] The above discussion of the four-node and five-node implementations (configurations) of memory cell pair 1200 / 1201 also applies to memory cell pair 1300 / 1301, and the control voltages shown in Tables 1 and 2 above also apply to memory cells 1300 and 1301, optionally with adjustments that take into account the floating gate threshold voltage differences between the tantalum nitride and polysilicon floating gates.

[0171] The foregoing description has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit the claims to the precise forms disclosed. In light of the above teachings, many variations are possible, including memory device structures other than floating gates, such as charge trap memory device structures or mask programmable read-only memories (mask ROMs). These implementations were chosen and described in order to best explain the principles of operation and practical applications, thereby enabling others skilled in the art to understand them.

[0172] The various figures illustrate various elements in a particular order. However, elements that are not dependent on order may be reordered, and other elements may be combined or separated. Although some reorderings or other groupings are specifically mentioned, other reorderings or other groupings will be apparent to one of ordinary skill in the art, and thus the orderings and groupings presented herein are not an exhaustive list of alternatives.

Claims

1. An electrically erasable and programmable non-volatile memory cell, comprising: a semiconductor substrate having a bit line region, a surface region spaced apart from the bit line region in a lateral direction, and a trench region spaced apart from the surface region in the lateral direction, the trench region including a bottom portion and a sidewall portion adjacent to a trench in the semiconductor substrate; A conductive control gate, the conductive control gate comprising: a first portion disposed inside the trench, insulated from the bottom portion and sidewall portions of the trench region of the substrate, and separated from sidewalls of the sidewall portions of the trench region by a first distance (A) in the lateral direction; and a second portion disposed above the trench and extending away from the trench; a conductive word line insulated from the control gate and offset in the lateral direction relative to the second portion of the control gate by a second distance (B), the second distance being greater than the first distance; a floating gate insulated from the substrate and the word line, and comprising: a first end portion, the first end portion comprising a portion of the floating gate closest to the control gate, the first end portion being separated from the second portion of the control gate in the lateral direction by a third distance, the third distance being greater than the first distance and less than the second distance; and A second end portion is self-aligned with an edge of the word line farthest from the second portion of the control gate.

2. The electrically erasable and programmable non-volatile memory cell according to claim 1, wherein: the conductive word line being insulated from the control gate by a series of insulators comprising an offset spacer, a first tunnel oxide, and a second tunnel oxide, and offset relative to the second portion of the control gate, the series of insulators separating the word line from the control gate by a second distance in the lateral direction, the second distance being greater than the first distance; and The first end portion of the floating gate is separated from the second portion of the control gate by the first tunnel oxide and the second tunnel oxide instead of the offset spacer.

3. The electrically erasable and programmable non-volatile memory cell of claim 2, wherein the second tunnel oxide, but not the first tunnel oxide, extends into the trench.

4. The electrically erasable and programmable non-volatile memory cell according to any one of claims 1 to 3, further comprising: a first indium implant disposed in a region of the substrate below the bottom portion of the trench region; and A second indium implant is disposed in a region of the substrate adjacent to a source or drain region of the memory cell.

5. The electrically erasable and programmable non-volatile memory cell according to claim 4 , wherein: During a programming operation, the first indium implant causes a threshold voltage of a channel in the bottom portion of the trench region to control a programming current at 100 nA with a control gate voltage between 1.6 V and 2.0 V; The floating gate is configured to reach a programmed state in 20 ns or less when the programming current is applied.

6. The electrically erasable and programmable non-volatile memory cell according to claim 4 or 5, wherein: The first and second indium implants are such that: (i) the punch-through current of an unselected row of memory cells is 10 pA or less; and (ii) the read current is insensitive to the programmed / erased state of the mirrored cells within a 10% tolerance.

7. An electrically erasable and programmable non-volatile memory cell according to any one of claims 2 to 6, wherein the lateral extent of the first tunnel oxide corresponds to a portion of the channel in the substrate extending from the bit line region of the substrate to the sidewall portion of the trench region, the portion not being overlapped by the floating gate.

8. The electrically erasable and programmable non-volatile memory cell according to claim 2 , wherein a distal portion of the channel in the substrate is not overlapped by the floating gate, the distal portion comprising a portion of the channel extending from the bit line region of the substrate to the sidewall portion of the trench region, the portion being within the electrically erasable and programmable non-volatile memory cell and farthest from the trench region.

9. The electrically erasable and programmable non-volatile memory cell according to any one of claims 2 to 6, wherein an erase gate insulating region is arranged between the first end portion of the floating gate and the second portion of the control gate, the erase gate insulating region corresponds to portions of the first tunnel oxide and the second tunnel oxide arranged between the first end portion of the floating gate and the second portion of the control gate, and the erase gate insulating region has a thickness that allows electrons to tunnel from the first end portion of the floating gate to the second portion of the control gate during an erase operation.

10. The electrically erasable and programmable nonvolatile memory cell according to claim 9, wherein the erase gate insulating region has a thickness greater than And tunneling of electrons is allowed when no more than 7V is applied between the control gate and the floating gate.

11. The electrically erasable and programmable non-volatile memory cell according to any one of claims 1 to 10, wherein the floating gate comprises a layer having a thickness between and Tantalum nitride between them.

12. The electrically erasable and programmable non-volatile memory cell according to claim 1 , wherein the floating gate comprises a layer having a thickness between and The polysilicon between the first end and the top end of the first end has less than thickness.

13. The electrically erasable and programmable non-volatile memory cell according to any one of claims 1 to 12, wherein the control gate is configured to function as an erase gate during an erase operation.

14. The electrically erasable and programmable non-volatile memory cell according to any one of claims 1 to 13, further comprising a floating gate insulating region disposed between the surface region of the substrate and the floating gate, wherein the floating gate insulating region has a thickness that allows electrons traveling in an upward path to be positively injected into the floating gate during a programming operation.

15. The electrically erasable and programmable non-volatile memory cell according to any one of claims 1 to 14, wherein a word line potential of the word line, a control gate potential of the control gate, and a bit line potential of the bit line region are configured to enable electrons to travel under the bottom portion of the trench region and then travel upward toward the floating gate during a programming operation.

16. The electrically erasable and programmable non-volatile memory cell of any one of claims 1 to 15, wherein the floating gate is configured to reach a programmed state in 20 ns or less during a programming operation.

17. The electrically erasable and programmable non-volatile memory cell according to any one of claims 1 to 5, wherein: The word line is electrically connected to the word line of the mirror memory cell; The electrically erasable and programmable nonvolatile memory cell and the mirror memory cell form a four-node memory cell pair, the four nodes consisting of a source node, a drain node, a word line node, and a control / erase node; and The word line node includes an electrically connected word line, the control / erase node includes the control gate shared by the electrically erasable and programmable nonvolatile memory cell and the mirror memory cell, and the source node or the drain node includes or is electrically connected to the bit line region of the electrically erasable and programmable nonvolatile memory cell.

18. An electrically erasable and programmable non-volatile memory cell comprising: a semiconductor substrate having a bit line region, a surface region spaced apart from the bit line region in a lateral direction, and a trench region spaced apart from the surface region in the lateral direction, the trench region including a bottom portion and a sidewall portion adjacent to a trench in the semiconductor substrate; A conductive control gate, the conductive control gate comprising: a first portion disposed inside the trench, insulated from the bottom portion and sidewall portions of the trench region of the substrate, and separated from the sidewall portion of the trench region by a first distance (A) in the lateral direction; and a second portion disposed above the trench and extending away from the trench; a conductive word line insulated from the control gate and offset in the lateral direction relative to the second portion of the control gate by a second distance (B), the second distance being greater than the first distance; a conductive floating gate insulated from the substrate and the word line and comprising: a first end portion including a portion of the floating gate closest to the control gate; and a second end portion, the second end portion being self-aligned with an edge 132 of the word line farthest from the second portion of the control gate; a first indium implant disposed in a region of the substrate below the bottom portion of the trench region; and a second indium implant disposed in a region of the substrate adjacent to a bottom of a source or drain region of the memory cell.

19. The electrically erasable and programmable non-volatile memory cell according to claim 18, wherein the first end portion of the conductive floating gate includes a top portion and a bottom portion adjacent to the top portion, and the bottom portion of the floating gate extends closer to the control gate than the top portion of the floating gate in the lateral direction.

20. The electrically erasable programmable non-volatile memory cell according to any one of claims 18 to 19, wherein the second indium implant makes the read current insensitive to the programmed / erased state of the mirrored cell within a tolerance of 10%.

21. The electrically erasable and programmable non-volatile memory cell according to any one of claims 18 to 20, wherein: The word line is electrically connected to the word line of the mirror memory cell; the electrically erasable and programmable nonvolatile memory cell and the mirror memory cell form a four-node memory cell pair, the four nodes consisting of a source node including or electrically connected to the bit line region of the electrically erasable and programmable nonvolatile memory cell, a drain node connected to the bit line region of the mirror memory cell, a word line node, and a control / erase node including or electrically connected to the conductive control gate; and The wordline node includes or is electrically connected to an electrically connected wordline.

22. A memory cell structure comprising: Mirrored pairs of electrically erasable programmable nonvolatile memory cells, wherein each memory cell in the mirrored pair includes a word line, a source / drain region, and a portion of a shared control / erase gate; wherein the word line of each memory cell in the mirrored pair is electrically connected; and Wherein the mirrored pair is a four-node memory cell pair, the four nodes consisting of: a source node comprising a source / drain region of a first memory cell in the mirrored pair; a drain node comprising a source / drain region of a second memory cell in the mirrored pair; a wordline node comprising an electrically connected wordline for each memory cell in the mirrored pair; and A control / erase node includes the shared control / erase gate.

23. The memory cell structure of claim 22, wherein each memory cell of the mirrored pair further comprises one or more of the features of any one of claims 1 to 21.

24. A memory cell structure comprising: Mirrored pairs of programmable nonvolatile memory cells, wherein each memory cell in the mirrored pair includes a word line, a source / drain region, and a portion of a shared control gate; wherein the word line of each memory cell in the mirrored pair is electrically connected; and Wherein the mirrored pair is a four-node memory cell pair, the four nodes consisting of: a source node comprising a source / drain region of a first memory cell in the mirrored pair; a drain node comprising a source / drain region of a second memory cell in the mirrored pair; a wordline node comprising an electrically connected wordline for each memory cell in the mirrored pair; and A control node includes the shared control gate.

25. The memory cell structure of claim 24, wherein each memory cell in the mirrored pair is a charge trap electrically erasable programmable memory cell.

26. The memory cell structure of claim 24, wherein each memory cell in the mirrored pair is a mask programmable read-only memory cell.

27. A method of manufacturing an electrically erasable programmable non-volatile memory cell, the method comprising: After forming a base structure, a series of layers are included on the substrate, the series of layers including a floating gate layer separated from the substrate by a floating gate insulating layer, a word line layer separated from the floating gate layer by a dielectric layer, and one or more protection layers located above the word line layer: forming a trench through the series of layers to form an electrically isolated portion of the floating gate layer and the word line layer, the electrically isolated portion including a first floating gate region and a first word line region for a first memory cell of a pair of memory cells and a second floating gate region and a second word line region for a second memory cell of the pair of memory cells, and first and second guard regions positioned over the first and second word line regions of the first and second memory cells, respectively; forming an offset spacer, a first tunnel oxide, and a second tunnel oxide in the trench in sequence, such that portions of the first floating gate region and the second floating gate region closest to the trench are separated from a control gate formed in the trench by the first tunnel oxide and the second tunnel oxide instead of the offset spacer, and the first word line and the second word line are separated from the control gate by the offset spacer, the first tunnel oxide, and the second tunnel oxide; as well as The control gate is formed in the trench.

28. The method of claim 27, wherein a portion of the trench extends into the substrate, and the second tunnel oxide, but not the first tunnel oxide, extends into the portion of the trench extending into the substrate.

29. The method of claim 27 or 28, comprising forming a conductive control gate within the trench, wherein the conductive control gate is a control gate for both the first and second memory cells of the pair of memory cells.

30. The method of any one of claims 27 to 29, wherein the first tunnel oxide has a thickness less than lateral thickness.

31. The method of any one of claims 27 to 30, wherein the second tunnel oxide has a thickness less than lateral thickness.

32. The method of any one of claims 27 to 30, further comprising forming a first indium implant in a region of the substrate below a bottom portion of the trench; and A second indium implant is formed in a region of the substrate adjacent to the source / drain region of the first memory cell and the source / drain region of the second memory cell.

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