Process control method for thick silicon carbide epitaxial wafer

Abstract

The invention provides a process control method for a thick silicon carbide epitaxial wafer, which belongs to the technical field of semiconductors, and comprises the following steps: before epitaxial growth of a silicon carbide substrate, thinning the C surface of the silicon carbide substrate to enable the Si surface of the silicon carbide substrate to be a concave surface; and quantitatively controlling the warping degree of the Si surface of the silicon carbide substrate so as to reduce the warping degree of the silicon carbide thick epitaxial wafer. According to the process control method of the silicon carbide thick epitaxial wafer, the C surface of the silicon carbide substrate is thinned before epitaxial growth of the silicon carbide substrate, so that the thickness distribution and the stress state of the substrate are changed, the Si surface of the silicon carbide substrate is promoted to present a concave shape, and the warping degree of the Si surface of the silicon carbide substrate is quantitatively controlled; the warping degree of the whole silicon carbide thick epitaxial wafer is reduced, excessive accumulation of internal stress can be effectively avoided, the yield and performance of subsequent devices are improved, and use requirements are met.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and more specifically, relates to a process control method for a silicon carbide thick epitaxial wafer. Background Art

[0002] Due to the limitations of the materials themselves, traditional silicon-based devices are unable to meet the demand for ultra-high voltage power device applications. Silicon carbide (SiC), as a representative of wide bandgap semiconductor materials, will become the first choice for ultra-high voltage thick epitaxial materials due to its excellent material properties. High-quality thick epitaxial materials will also become the focus of competition in future silicon carbide epitaxial processes. At present, thick silicon carbide epitaxial wafers all have the problem of gradually increasing warpage and becoming more convex as the epitaxial thickness increases. Excessive warpage of the epitaxial wafer will cause internal stress accumulation, resulting in a decrease in the yield of subsequent devices, and will also cause a decrease in lithography accuracy and uneven deposition of subsequent dielectric layers, thereby reducing device performance and reliability. At the same time, excessive warpage of the epitaxial wafer may also lead to uneven distribution of carrier mobility, affecting key parameters such as device on-resistance and breakdown voltage, thereby causing deterioration of device performance. Summary of the Invention

[0003] The purpose of the present invention is to provide a process control method for thick silicon carbide epitaxial wafers to solve the technical problem in the prior art that the epitaxial wafer warpage is too large, resulting in subsequent device performance failing to meet requirements.

[0004] To achieve the above-mentioned objectives, the technical solution adopted by the present invention is: to provide a process control method for thick silicon carbide epitaxial wafers, comprising: thinning the C surface of the silicon carbide substrate before epitaxial growth on the silicon carbide substrate to make the Si surface of the silicon carbide substrate concave; and quantitatively controlling the warpage of the Si surface of the silicon carbide substrate to reduce the warpage of the thick silicon carbide epitaxial wafer.

[0005] In a possible implementation, S1: pre-grinding the C-surface of the silicon carbide substrate to reduce the thickness of the C-surface of the silicon carbide substrate, and detecting a warpage of the silicon carbide substrate of -60 to -20 μm;

[0006] S2: In-situ etching of the Si surface of the silicon carbide substrate in the epitaxial equipment;

[0007] S3: growing a buffer layer on the silicon carbide substrate;

[0008] S4: adjusting the growth temperature of the cavity in the epitaxial equipment to 1400-1600° C., interrupting the source flow, and stopping the growth time for 10-120 seconds;

[0009] S5: growing a drift layer on the buffer layer, wherein the drift layer has a thickness of 50 to 200 μm; and detecting a warpage of the silicon carbide thick epitaxial wafer to be ≤30 μm.

[0010] In a possible implementation, in step S1 , the pre-grinding includes coarse grinding and fine grinding performed sequentially.

[0011] In a possible implementation, a coarse grinding wheel is used for rough grinding, and a fine grinding wheel is used for fine grinding; the coarse grinding wheel has a mesh size of 1000 to 3000, and the fine grinding wheel has a mesh size of 5000 to 50000.

[0012] In a possible implementation, in step S1 , after grinding the silicon carbide substrate, the C-surface of the silicon carbide substrate is polished and cleaned.

[0013] In a possible implementation, in step S2, H2 is introduced at a flow rate of 70-150 slm, and etching is performed for 10 minutes at an etching temperature of 1550-1650° C. and a pressure of 50-200 mbar.

[0014] In a possible implementation, in step S3, the carbon-silicon ratio is controlled to be 0.4-0.6, wherein H2 is introduced at a flow rate of 70-150 slm, and the N-type doping concentration is 1×10 18 ~2.5×10 18 cm -3 .

[0015] In a possible implementation, in step S5, the carbon-silicon ratio is controlled at 0.7-0.9, SiHCl3 is introduced at a flow rate of 280-450 sccmH2 carrying SiHCl3 saturated vapor, and C2H4 is introduced at a flow rate of 120-180 sccm; the doping concentration is 3×10 14 ~1×10 17 cm -3 ;The warpage of thick silicon carbide epitaxial wafers is between -5 and 10 μm.

[0016] The beneficial effect of the process control method for a thick silicon carbide epitaxial wafer provided by the present invention is that, compared with the prior art, the process control method for a thick silicon carbide epitaxial wafer of the present invention first performs a thinning operation on the C surface of a silicon carbide substrate before epitaxial growth on the silicon carbide substrate, thereby changing the thickness distribution and stress state of the substrate, causing the Si surface of the silicon carbide substrate to present a concave surface morphology, and quantitatively controlling the warpage of the Si surface of the silicon carbide substrate to achieve a reduction in the warpage of the entire thick silicon carbide epitaxial wafer, thereby effectively avoiding excessive accumulation of internal stress, thereby improving the yield and performance of subsequent devices and meeting usage requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0018] Figure 1 The structural schematic diagram of the silicon carbide thick epitaxial wafer provided by the embodiments of the present application is shown. DETAILED DESCRIPTION

[0019] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects more clearly, the following will further describe the present application in combination with the drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not used to limit the present application.

[0020] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0021] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0022] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0023] Please refer to Figure 1 The process control method of the silicon carbide thick epitaxial wafer provided by the present application will be described. A process control method of a silicon carbide thick epitaxial wafer, comprising: before epitaxial growth of a silicon carbide substrate, performing a thinning operation on the C face of the silicon carbide substrate, so that the Si face of the silicon carbide substrate is a concave surface; quantitatively controlling the warping degree of the Si face of the silicon carbide substrate, so as to reduce the warping degree of the silicon carbide thick epitaxial wafer.

[0024] Compared with the prior art, the process control method for a thick silicon carbide epitaxial wafer provided by the present invention first performs a thinning operation on the C surface of a silicon carbide substrate before epitaxial growth on the silicon carbide substrate, thereby changing the thickness distribution and stress state of the substrate, causing the Si surface of the silicon carbide substrate to present a concave surface morphology, and quantitatively controlling the warpage of the Si surface of the silicon carbide substrate to reduce the warpage of the entire thick silicon carbide epitaxial wafer, thereby effectively avoiding excessive accumulation of internal stress, thereby improving the yield and performance of subsequent devices and meeting usage requirements.

[0025] See also Figure 1 As a specific embodiment of the process control method for a thick silicon carbide epitaxial wafer provided by the present invention, S1: pre-grinding the C surface of the silicon carbide substrate to reduce the thickness of the C surface of the silicon carbide substrate, and detecting the warpage of the silicon carbide substrate to be -60 to -20 μm; S2: in-situ etching the Si surface of the silicon carbide substrate in the epitaxial equipment, with the etching temperature being 1550 to 1650°C and the pressure being 50 to 200 mbar; S3: growing a buffer layer on the silicon carbide substrate; S4: adjusting the growth temperature of the cavity in the epitaxial equipment to 1400 to 1600°C, and interrupting the source flow, and stopping the growth time for 10 to 120 seconds; S5: growing a drift layer on the buffer layer, with the drift layer having a thickness of 50 to 200 μm; detecting the warpage of the thick silicon carbide epitaxial wafer to be ≤30 μm; first, pre-grinding and thinning the C surface of the silicon carbide substrate , the warpage of the silicon carbide substrate is controlled at -60 to -20 μm, providing a substrate with suitable flatness for subsequent epitaxial growth; then the Si surface of the silicon carbide substrate is in-situ etched at 1550-1650°C and 50-200 mbar, the surface is cleaned and the crystal structure is optimized in a high-temperature, low-pressure environment, and the quality of epitaxial layer growth is improved; a buffer layer is grown on the etched silicon carbide substrate to act as a transition buffer to reduce lattice mismatch stress; then the cavity temperature of the processing equipment is adjusted to 1400-1600°C, the source flow is interrupted and the growth is stopped for 10-120 seconds. Through a short growth stagnation and temperature control, the internal stress accumulated during the growth process is released, creating stable conditions for the growth of the drift layer; finally, a drift layer with a thickness of 50-200 μm is grown on the buffer layer, and finally a high-quality silicon carbide thick epitaxial wafer with a warpage of ≤30 μm is produced. This solution effectively reduces the warpage of epitaxial wafers and improves the bonding quality and structural stability of the substrate and epitaxial layer through the coordinated efforts of multiple links such as pre-grinding and pretreatment, in-situ etching surface optimization, buffer layer stress buffering, growth interruption stress release, and precise temperature and pressure control. It provides a substrate material with excellent flatness and high reliability for the preparation of high-voltage power devices, significantly improving the yield and electrical performance of subsequent device manufacturing.

[0026] See also Figure 1As a specific embodiment of the process control method for a thick silicon carbide epitaxial wafer provided by the present invention, in step S1, the pre-grinding includes coarse grinding and fine grinding performed successively; before the epitaxial growth of the silicon carbide substrate is carried out, the C-surface of the silicon carbide substrate is pre-grinded to achieve the purpose of thinning; the pre-grinding adopts a step-by-step processing process combining coarse grinding and fine grinding: first, in the coarse grinding step, the C-surface of the silicon carbide substrate is preliminarily ground using a grinding material with a larger particle size (such as diamond abrasive) to quickly remove the processing damage layer and excess material on the surface of the substrate, significantly thin the substrate thickness, and efficiently achieve preliminary control of the substrate thickness; then, in the fine grinding step, a grinding material with a finer particle size is used to finely polish the substrate surface with lower pressure and finer process parameters, further correcting the surface roughness and geometric deviation that may be generated during the rough grinding process, so that the C-surface of the silicon carbide substrate achieves higher flatness and surface accuracy. Rough grinding ensures material removal efficiency and shortens processing time, while fine grinding accurately controls the substrate warpage within the range of -60 to -20μm through refined processing, providing a substrate with excellent flatness and fewer defects for subsequent epitaxial growth; at the same time, staged grinding can effectively avoid substrate damage or uncontrolled warpage caused by improper pressure or abrasive selection in a single grinding process, improve the stability of substrate pretreatment, and lay a key foundation for the uniform distribution of stress and warpage control during the subsequent epitaxial layer growth process, ultimately ensuring the overall structural performance and reliability of silicon carbide thick epitaxial wafers.

[0027] Preferably, in the pre-grinding process of step S1, differentiated grinding wheel mesh sizes are used to achieve precise division of labor between coarse grinding and fine grinding: a 1000-3000 mesh coarse grinding wheel is selected for the coarse grinding stage, and its abrasive particles are relatively coarse (the lower the mesh number, the larger the particles). The C surface of the silicon carbide substrate is strongly ground by high-speed rotation, which can quickly remove the processing allowance and the deeper mechanical damage layer on the surface of the substrate, efficiently achieve thickness thinning and preliminarily correct the macro warping of the substrate; a 5000-50000 mesh fine grinding wheel is used for the fine grinding stage, and its ultrafine abrasive particles (the higher the mesh number, the finer the particles) are combined with low-pressure, slow-speed fine processing, which can eliminate the surface scratches and micro defects left by the rough grinding layer by layer, and achieve nanometer-level precision polishing of the substrate surface. The core advantages of this process design lie in the following: the wide grit range of the coarse grinding wheel balances material removal efficiency and initial surface quality, avoiding excessive substrate damage caused by overly coarse abrasives. The ultra-high grit of the fine grinding wheel ensures ultra-precision machining of the substrate surface, strictly controlling warpage within the ideal range of -60 to -20 μm. The graded processing of coarse and fine grinding wheels not only shortens the thinning time of thick substrates, but also avoids stress concentration or surface defects caused by a single grinding pass through progressive surface correction. This provides a high-quality substrate with excellent flatness and minimal lattice damage for subsequent epitaxial growth, fundamentally reducing the risk of epitaxial wafer warpage caused by substrate defects and improving overall process stability and finished product yield.

[0028] After the pre-grinding process, polishing and cleaning steps are added to further optimize the surface state of the silicon carbide substrate. First, through the polishing process, a polishing pad containing nano-scale abrasives (such as diamond powder or silica slurry) is used to chemically mechanically polish the ground C-surface of the silicon carbide substrate. The synergistic effect of mechanical grinding and chemical corrosion is used to remove the subsurface damage, microscopic scratches and surface roughness remaining in the grinding process, so that the surface of the silicon carbide substrate reaches atomic level flatness. Subsequently, through a multi-step cleaning process, deionized water, organic solvents (such as acetone, ethanol) and dilute chemical reagents (such as dilute sulfuric acid, hydrogen peroxide mixture) are used for ultrasonic cleaning in sequence, combined with megasonic or spray rinsing to thoroughly remove pollutants such as abrasive particles, polishing waste liquid, oil stains and metal ions remaining on the surface of the silicon carbide substrate. The polishing stage eliminates the microscopic defects that are difficult to avoid during the grinding process through refined processing, further improving the flatness and crystal integrity of the C-surface of the silicon carbide substrate, providing an ideal substrate with low defect density for subsequent epitaxial growth. The cleaning stage ensures that there are no impurities remaining on the substrate surface through multi-stage purification, avoiding abnormal epitaxial layer growth caused by contaminants (such as particle defects and interface mismatch). The combination of the two not only accurately controls the warpage of the silicon carbide substrate within the target range (-60 to -20μm), but also reduces the negative impact of substrate surface defects on the subsequent epitaxial layer stress distribution from the source, laying a key foundation for the preparation of high-quality silicon carbide thick epitaxial wafers with a warpage of ≤30μm, significantly improving the structural stability and electrical performance consistency of the epitaxial wafers.

[0029] See also Figure 1As a specific embodiment of the process control method for silicon carbide thick epitaxial wafers provided by the present invention, in step S2, H2 is introduced at a flow rate of 70-150 slm, and etching is carried out for 10 minutes under the conditions of an etching temperature of 1550-1650°C and a pressure of 50-200 mbar. The etching process is crucial in the preparation of silicon carbide epitaxial structures. First, hydrogen (H2) can serve as a carrier gas during the etching process, which can evenly carry the reaction gas to the surface of the silicon carbide substrate. On the other hand, under high temperature conditions, H2 will decompose into hydrogen atoms, which can react with impurities on the surface of the silicon carbide, thereby cleaning the substrate surface. The H2 flow rate is controlled at 70-150 slm (standard liters per minute). Selecting an appropriate flow rate avoids the situation where the H2 flow rate is too low and the reaction byproducts cannot be taken away in time, thereby affecting the etching effect; and avoids the situation where the gas residence time in the reaction chamber is too short due to excessively high flow rate, resulting in waste of resources. High temperature is a key factor for the smooth progress of the etching process. In such a high-temperature environment, atoms on the silicon carbide surface gain sufficient energy and become active, accelerating their reaction rate with hydrogen atoms. Pressure directly affects the uniformity and rate of etching. In a low-pressure environment, the mean free path of gas molecules is longer, allowing them to reach the substrate surface more evenly, thus ensuring uniform etching.

[0030] See also Figure 1 As a specific embodiment of the process control method for silicon carbide thick epitaxial wafer provided by the present invention, in step S3, the carbon-silicon ratio is controlled at 0.4-0.6, wherein H2 is introduced at a flow rate of 70-150 slm, and the N-type doping concentration is 1×10 18 ~2.5×10 18 cm -3 Specifically, the temperature is 1550-1650°C, the pressure is 70-130 mbar, and H2, SiHCl3, C2H4, and an N-type dopant source are introduced. The carbon-silicon ratio is controlled at 0.4-0.6. H2 is introduced at a flow rate of 70-150 slm, SiHCl3 is introduced at 50-90 sccm of H2 carrying SiHCl3 saturated vapor, and C2H4 is introduced at a flow rate of 10-30 sccm. The conventional buffer layer has a thickness of 0.5-1.5 μm and a doping concentration of 1×10 18 -2.5×10 18 cm -3. In step S3, the temperature and pressure conditions are set as follows: 1550-1650℃ and 70-130mbar. Under high temperature conditions, the migration and crystallization of silicon and carbon atoms on the substrate surface are promoted, and the low pressure environment reduces gas phase reactions, which is beneficial to controlling the thickness uniformity of the epitaxial layer. H2 (70-150slm) is used as a carrier gas and diluent to maintain the atmosphere of the reaction chamber and promote the discharge of by-products. SiHCl3 (50-90sccm) is used as a silicon source and is introduced in the form of saturated steam carried by H2 to provide the silicon atoms required for the epitaxial layer. C2H4 (10-30sccm) is used as a carbon source to provide carbon atoms after decomposition. By precisely controlling the carbon-silicon ratio (C / Si=0.4-0.6), the supply of silicon and carbon atoms can be balanced to avoid defects caused by excessive carbon or silicon. N2 is used as the N-type doping source with a doping concentration of 1×10 18 -2.5×10 18 cm -3 , forming a buffer layer with a medium doping concentration to optimize the electrical performance transition between the substrate and subsequent device layers.

[0031] See also Figure 1 As a specific embodiment of the process control method for a silicon carbide thick epitaxial wafer provided by the present invention, in step S5, the carbon-silicon ratio is controlled at 0.7-0.9, SiHCl3 is introduced at a flow rate of 280-450 sccmH2 carrying SiHCl3 saturated steam, and C2H4 is introduced at a flow rate of 120-180 sccm; the doping concentration is 3×10 14 ~1×10 17 cm -3 The warpage of the thick silicon carbide epitaxial wafer is between -5 and 10 μm. In step S5, the temperature, pressure and H2 introduction conditions are maintained the same as those in step S3, the carbon-silicon ratio is controlled at 0.7-0.9, SiHCl3 is introduced at a flow rate of 280-450 sccmH2 carrying SiHCl3 saturated vapor, and C2H4 is introduced at a flow rate of 120-180 sccm. The drift layer has a thickness of 5-100 μm and a doping concentration of 3×10 14 -1×10 17 cm -3 Controlling the carbon-silicon ratio to 0.7-0.9 helps to form a high-quality silicon carbide crystal structure and avoids crystal defects or impurities introduced by excessive carbon or silicon. Compared with step S3, the flow rates of SiHCl3 and C2H4 are increased, which promotes the growth rate and quality of the drift layer. The thickness of the drift layer is limited to 5-100μm, and the doping concentration is 3×10 14 -1×10 17 cm -3, in order to adjust the electrical properties of the drift layer so that it can play a good role in the device, such as achieving efficient current transmission and electric field control. Maintaining the same temperature, pressure, and H2 injection conditions in steps S4 and S5 is fundamental to providing a stable environment for the entire growth process.

[0032] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A process control method for a thick silicon carbide epitaxial wafer, characterized in that: The method includes thinning the C surface of the silicon carbide substrate before epitaxial growth of the silicon carbide substrate so that the Si surface of the silicon carbide substrate is a concave surface; The warpage of the Si surface of the silicon carbide substrate is quantitatively controlled to reduce the warpage of the silicon carbide thick epitaxial wafer.

2. The process control method for a silicon carbide thick epitaxial wafer according to claim 1, wherein: include: S1: Pre-grinding the C-surface of the silicon carbide substrate to reduce the thickness of the C-surface of the silicon carbide substrate, and detecting the warpage of the silicon carbide substrate to be -60 to -20 μm; S2: In-situ etching of the Si surface of the silicon carbide substrate in the epitaxial equipment; S3: growing a buffer layer on the silicon carbide substrate; S4: adjusting the growth temperature of the cavity in the epitaxial equipment to 1400-1600° C., interrupting the source flow, and stopping the growth time for 10-120 seconds; S5: growing a drift layer on the buffer layer, wherein the drift layer has a thickness of 50 to 200 μm; and detecting a warpage of the silicon carbide thick epitaxial wafer to be ≤30 μm.

3. The process control method for a silicon carbide thick epitaxial wafer according to claim 2, wherein: In step S1 , the pre-grinding includes coarse grinding and fine grinding performed sequentially.

4. The process control method for a silicon carbide thick epitaxial wafer according to claim 3, wherein: The coarse grinding wheel is used for rough grinding, and the fine grinding wheel is used for fine grinding; the mesh size of the coarse grinding wheel is 1000-3000, and the mesh size of the fine grinding wheel is 5000-50000.

5. The process control method for a silicon carbide thick epitaxial wafer according to claim 2, wherein: In step S1 , after grinding the silicon carbide substrate, the C-surface of the silicon carbide substrate is polished and cleaned.

6. The process control method for a silicon carbide thick epitaxial wafer according to claim 2, wherein: In step S2, H2 is introduced at a flow rate of 70-150 slm, and etching is performed for 10 minutes at an etching temperature of 1550-1650° C. and a pressure of 50-200 mbar.

7. The process control method for a silicon carbide thick epitaxial wafer according to claim 2, wherein: In step S3, the carbon-silicon ratio is controlled to be 0.4-0.6, wherein H2 is introduced at a flow rate of 70-150 slm, and the N-type doping concentration is 1×10 18 ~2.5×10 18 cm -3 .

8. The process control method for a silicon carbide thick epitaxial wafer according to claim 2, wherein: In step S5, the carbon-silicon ratio is controlled at 0.7-0.9, SiHCl3 is introduced at a flow rate of 280-450 sccmH2 carrying SiHCl3 saturated vapor, and C2H4 is introduced at a flow rate of 120-180 sccm; the doping concentration is 3×10 14 ~1×10 17 cm -3 ;The warpage of thick silicon carbide epitaxial wafers is between -5 and 10 μm.

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