Test signal verification processing method for PCBA circuit board

Abstract

The invention discloses a test signal verification processing method for a PCBA circuit board, and relates to the technical field of circuit board testing, initial testing is performed on a PBCA circuit board through test data to obtain the test data, the PBCA circuit board is analyzed to construct a signal path model and an element topology layer, and data interaction between the signal path model and the element topology layer is realized. And acquiring a standard signal for testing the PBCA circuit board by using the signal path model, comparing the standard signal with a test signal, positioning a fault element by combining the element topology layer, and obtaining a fault diagnosis report. According to the method, the signal path model and the element topology layer are constructed, and dynamic parameter adjustment of the mapping space is combined, so that accurate verification of the PCBA circuit board test signal is realized, and the signal test efficiency and accuracy are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board testing, and in particular to a test signal verification processing method for a PCBA circuit board. Background Art

[0002] In the PCBA (Printed Circuit Board Assembly) manufacturing process, circuit board testing and quality control are crucial steps. Traditional testing methods mainly include flying probe testing, in-circuit tester (ICT), and functional testing. ICT uses probes to contact test points to detect electrical connectivity and component parameters, but its coverage is limited by physical access points, making it difficult to detect signal integrity or high-frequency performance issues. While functional testing can verify overall performance, it cannot accurately locate faulty components. In addition, existing methods mostly rely on static parameter comparisons and lack the ability to model dynamic signal pathways, resulting in low diagnostic efficiency for hidden faults such as impedance matching anomalies and timing errors. At the same time, existing PCBA circuit board test signal verification methods lack systematic modeling. Most solutions only use discrete test point data to make threshold judgments, which cannot restore the complete propagation characteristics of the signal in the path and easily lead to misjudgment. Secondly, fault location relies on empirical rules or simple correlation analysis, which has difficulty in dealing with the coupling effects between components in multi-layer topologies. For example, power integrity degradation may cause malfunction of remote components, making it difficult to trace the root cause with traditional methods. Therefore, it is of great significance to develop an efficient and intelligent test signal verification processing method for PCBA circuit boards. Summary of the Invention

[0003] The purpose of the present invention is to provide a test signal verification processing method for a PCBA circuit board to solve the shortcomings of the background technology.

[0004] In order to achieve the above object, the present invention provides the following technical solution: a test signal verification processing method for a PCBA circuit board, comprising: Test the PCBA circuit board to obtain the component parameters and test signals of the PCBA circuit board; Build a signal path model and component topology layer, connect the component topology layer to the components in the signal path model one-to-one, and use the signal path model to verify the accuracy of the test signal; Use signal path models and component topology layers to locate faulty components and generate fault diagnosis reports.

[0005] In a preferred embodiment, the steps of testing the PCBA circuit board to obtain component parameters and test signals of the PCBA circuit board are: Extract the standard parameters of each component of the PBCA circuit board; Develop test data for PCBA circuit boards, including input signal type, signal amplitude, and frequency range; The test data is used to perform an initial test on the PCBA circuit board to obtain a test signal.

[0006] The steps of constructing the signal pathway model are: Extract signal path information from the circuit schematic of the PCBA circuit board, including the signal's starting point, end point, components and wires it passes through; Convert the signal path into a circuit network, draw a signal flow graph on the circuit network to obtain a signal path model including components, signal paths and signal flow directions; The initial values ​​of the component parameters are standard parameters and are adjustable; A plurality of detection windows are set on the signal path and at both ends of the component. The plurality of detection windows are connected to a plurality of mapping spaces through mapping channels. The signal path model is stored in the mapping space.

[0007] In a preferred embodiment, the steps of constructing a component topology layer and performing one-to-one connection between the component topology layer and the components in the signal path model are as follows: Place the PBCA circuit board in The components are defined as: , and construct the adjacency matrix between each element: in, represents the adjacency matrix, Display components and adjacency; Defining the association weights between components includes electrical connection weight, physical connection weight and performance connection weight; The electrical connection weight is: in, Display components and The electrical connection weight, Indicates flow through the element and The current between Display components and The equivalent impedance between Physical connection weight: in, Display components and The physical connection weight between express and physical distance, is the distance decay factor; Performance connection weight: in, Display components and The performance connection weight between Indicates the performance benchmark of the circuit board, Respectively represent components and performance benchmarks; The association weights between the components are: in, is an adjustable parameter; The component topology layer is constructed through the adjacency matrix and the association weight. The component topology layer consists of components and directed edges connecting the components. The value of the directed edge is the value of the association weight between the two components. Connect the component topology layer to the components in the signal path model one-to-one through the data transmission channel.

[0008] In a preferred embodiment, the step of verifying the accuracy of the test signal using the signal path model and the component topology layer is: Input the test data into the signal path model to obtain the optimal test signal, and use the optimal test signal passing through the detection point as the standard signal; A preset error threshold is set, and the test signal is compared with the standard signal of the detection point. If the error value between the test signal and the standard signal of a detection point in the signal path model exceeds the preset error threshold, the detection is regarded as an abnormal point; The abnormal point activates the mapping space, and the mapping space expands the stored signal path model as the mapping path. The test signal is transmitted to the mapping space, and the mapping abnormal point is used as the starting point of the mapping path. The test signal is used as input to determine the signal flow direction of the test signal. The abnormal information of the abnormal point is recorded, including the abnormal signal value, the abnormal point location and the signal path to which it belongs. The abnormal information is transmitted to the component topology layer through the component closest to the abnormal point. The component topology layer locates the potential fault component and collects the data of the potential fault component; The component topology layer transmits the data of potential fault components to the mapping space through the data transmission channel and the mapping channel. The mapping space dynamically adjusts the parameters of the potential fault components so that the output of the mapping path is equivalent to the standard data. The mapping path and signal path models are run in parallel until all detection points are compared, the faulty component is identified, and a fault diagnosis report is generated.

[0009] In a preferred embodiment, the steps of locating the potential faulty component and collecting data of the potential faulty component including component ID, component parameters and adjustment range in the component topology layer are as follows: A correlation value threshold is preset, and the component that receives the abnormal information retrieves the components connected to it whose correlation values ​​exceed the correlation value threshold based on the component topology layer as potential fault components.

[0010] In a preferred embodiment, the mapping space dynamically adjusts the parameters of the potential fault component so that the output of the mapping path is equivalent to the standard data by the following steps: The mapping space receives data on potential fault components and defines the priority calculation formula: in, Indicates the The priority of each potentially faulty component, is the output signal error of the mapping path, For the The error between the output signal of a potential fault component and the standard signal, The larger the value of , the higher the priority of the potential fault component to be modified, and the modification sorting table is determined based on the priority; Design objective function: As the optimization target, where F is the objective function, T is the test signal, C is the standard signal, For the The adjusted parameter value of each potential fault component, For the Standard parameters of a potential fault component, is the regularization coefficient; Optimize the objective function using the least squares minimization method; The output error threshold is preset, and the parameters of the potential fault component with the highest priority are adjusted. If the error threshold is not reached, the potential fault component with the next priority is adjusted in turn, and the iterative operation is performed until all potential fault components have been adjusted.

[0011] In a preferred embodiment, the steps of determining the faulty component and generating a fault diagnosis report are: After the iteration operation is completed, define the parameter adjustment value: in, For the Parameter adjustment values ​​of potential faulty components, a preset parameter adjustment threshold, and potential faulty components whose parameters exceed the parameter adjustment threshold are regarded as faulty components; The fault information and abnormal information of the faulty component are summarized into a fault diagnosis report, wherein the fault information includes the component ID and parameter adjustment value.

[0012] In the above technical solution, the technical effects and advantages provided by the present invention are: 1. This invention realizes full-link simulation and dynamic verification of PCBA test signals by constructing a high-precision signal path model and a multi-level mapping space. Traditional methods rely on static parameter comparison of discrete test points and cannot capture the propagation characteristics of signals in complex paths, such as reflection, crosstalk, and timing offset. This solution sets up a multi-level detection window on the signal path and compares the test signal with the standard signal in parallel in the mapping space through the mapping channel, forming a closed-loop mechanism of "signal propagation path-outlier point mapping-dynamic parameter correction". At the same time, the mapping path and signal path model run in parallel, which improves the detection efficiency. 2. The present invention constructs a component topology layer that integrates electrical, physical, and performance weights. This solution realizes the quantitative analysis and precise positioning of the coupling effects between PCBA components. The traditional adjacency matrix only describes the physical connection relationship of the components. This solution introduces a three-dimensional association model based on the electrical connection weight based on the current-impedance relationship, the physical connection weight based on the distance attenuation factor, and the performance connection weight based on the functional dependency. It constructs a topological network that is closer to the actual circuit behavior. The component topology layer interacts with the signal path model in real time, introduces a dynamic parameter adjustment strategy and priority mechanism, and significantly improves the positioning efficiency and repair accuracy of faulty components. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments described in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0014] Figure 1 Flow chart of the method of the present invention. DETAILED DESCRIPTION

[0015] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] Example 1, please refer to Figure 1 As shown, the test signal verification processing method for a PCBA circuit board described in this embodiment includes: S1. Test the PCBA circuit board to obtain component parameters and test signals of the PCBA circuit board; S2. Build a signal path model and a component topology layer, connect the component topology layer to the components in the signal path model one-to-one, and use the signal path model to verify the accuracy of the test signal; S3. Use the signal path model and component topology layer to locate the faulty component and generate a fault diagnosis report.

[0017] As described in steps S1-S3 above, circuit board testing and quality control are crucial links in the PCBA manufacturing process. Traditional testing methods mainly include flying probe testing, in-circuit testing (ICT), and functional testing. In-circuit testing detects electrical connectivity and component parameters by contacting test points with probes, but its coverage is limited by physical access points, making it difficult to detect signal integrity or high-frequency performance issues. Although functional testing can verify overall performance, it cannot accurately locate faulty components. In addition, existing methods mostly rely on static parameter comparison and lack the ability to model dynamic signal paths, resulting in low diagnostic efficiency for hidden faults such as impedance matching anomalies and timing errors.

[0018] At the same time, existing PCBA circuit board test signal verification methods lack systematic modeling. Most solutions only use discrete test point data to make threshold judgments, which cannot restore the complete propagation characteristics of the signal in the path and easily lead to misjudgment. Secondly, fault location relies on empirical rules or simple correlation analysis, which has difficulty in dealing with the coupling effects between components in multi-layer topologies. For example, power integrity degradation may cause malfunction of remote components, making it difficult to trace the root cause with traditional methods. The present invention realizes full-link simulation and dynamic verification of PCBA test signals by constructing a high-precision signal path model and a multi-level mapping space. Traditional methods rely on static parameter comparison of discrete test points and cannot capture the propagation characteristics of signals in complex paths, such as reflection, crosstalk, and timing offset. This solution sets up a multi-level detection window on the signal path and compares the test signal and the standard signal in parallel in the mapping space through the mapping channel, forming a closed-loop mechanism of "signal propagation path-abnormal point mapping-dynamic parameter correction". At the same time, the mapping path and signal path model run in parallel, which improves the detection efficiency. By constructing the element topology layer of fusing electrical, physical and performance weights, the scheme realizes the quantitative analysis and accurate positioning of the coupling effect between PCBA elements. The traditional adjacency matrix only describes the physical connection relationship of the elements, while the scheme introduces a three-dimensional correlation model based on the electrical connection weight of current-impedance relationship, the physical connection weight based on distance attenuation factor, and the performance connection weight based on function dependency, and constructs a topology network closer to the actual circuit behavior. The element topology layer and the signal path model interact in real time, and the dynamic parameter adjustment strategy and priority mechanism are introduced, which significantly improves the positioning efficiency and repair accuracy of the faulty element.

[0019] In one embodiment, the step S1 of testing the PCBA circuit board to obtain the element parameters and test signals of the PCBA circuit board includes: S11, extracting standard parameters of each element of the PBCA circuit board; S12, formulating test data corresponding to the PCBA circuit board, the test data including input signal type, signal amplitude and frequency range; S13, performing initial testing on the PCBA circuit board using the test data to obtain test signals; As described in steps S11-S13 above, use automated test equipment (ATE) or manual detection to identify the elements on the PCBA circuit board. For each identified element, obtain its standard electrical parameters, including voltage level, current level, resistance, capacitance, and frequency response curve, etc. In actual implementation, a database can be constructed to integrate these parameters into a database for subsequent query and use. Define test data to determine the required input signal mode, including analog and digital signals. A signal generator can be designed to generate the required type of signal. According to the rated parameters of the circuit, set different input signal amplitude ranges, including low amplitude test, rated amplitude test and overload amplitude test. According to the circuit function, set the test frequency range, including low frequency test, medium frequency test and high frequency test. Test the PCBA circuit board using the test data to obtain the feedback signals of each detection point and output port on the PCBA circuit board as test signals.

[0020] In one embodiment, the step S2 of constructing a signal path model includes: S21, extracting information of the signal path in the circuit schematic diagram of the PCBA circuit board, including the starting point, ending point, passing elements and wires of the signal; S22, converting the signal path into a circuit network, and drawing a signal flow diagram on the circuit network to obtain a signal path model including elements, signal paths and signal flow direction; S23, wherein the initial value of the parameter of the element is the standard parameter and is adjustable; S24, setting a plurality of detection windows on the signal path and at both ends of the component, the plurality of detection windows being connected to a plurality of mapping spaces via mapping channels, and the signal path model being stored in the mapping space; As described in the above steps S23-S24, use circuit design software such as Altium Designer or Cadence to open the circuit schematic of the PCBA, and use the software's automated tools to extract information about the signal path in the circuit, including the signal starting point: determine the source of the power supply, input terminal or control signal, the signal end point: identify the final output terminal or load or control interface, the components passed through: list all components involved in signal transmission, including resistors, capacitors, diodes, integrated circuits, etc., wire information: identify the propagation path of the signal in the circuit, record the connection relationship, impedance and length of the wire, etc., organize the extracted information in a structured manner to form a basic data model of the signal path, including components and their connection relationships, and convert the extracted signal path information into a circuit network model, in which each component is used as a node in the network and the signal wire is used as an edge connecting these nodes. At the same time, the signal flow direction is determined, and a signal path model is constructed based on the circuit network model and the signal flow using the circuit modeling method, and the initial value of the parameter of each component on the signal path model is set to its Standard parameters, which usually come from the technical data sheet of the component, and a parameter adjustment mechanism is set at the same time. During the test process, the parameters of the component can be adaptively adjusted based on the test environment, and in the signal path model, multiple detection windows are set to specify the key points of the monitoring signal. For example, input point detection is used to monitor the quality of the input signal to ensure that the signal arrives as shown in the design. Intermediate node detection is used to monitor the changes in the signal between key components, such as buffers and amplifiers. Output point detection is used to verify the signal amplitude, current and timing at the output end. In actual situations, the setting of the detection window is dynamically increased or decreased according to the complexity of the PCBA circuit board. The more complex the circuit, the more detection windows should be set. Each detection window is connected to the mapping space through a mapping channel. The mapping space is a data processing center with edge computing capabilities. It stores the mapping of the signal path model. When an activation request is received, the signal path model stored therein will be expanded as a mapping path for signal simulation operations.

[0021] In one embodiment, step S2 of constructing a component topology layer and performing one-to-one connection between the component topology layer and the components in the signal path model includes: S25, put the PBCA circuit board The components are defined as: , and construct the adjacency matrix between each element: S26, among which, represents the adjacency matrix, Display components and adjacency; S27. Define the association weights between components, including electrical connection weights, physical connection weights, and performance connection weights; S28, where electrical connection weight: S29, among which, Display components and The electrical connection weight, Indicates flow through the element and The current between Display components and The equivalent impedance between S210, physical connection weight: S211, among which, Display components and The physical connection weight between express and physical distance, is the distance decay factor; S212, performance connection weight: S213, among which, Display components and The performance connection weight between Indicates the performance benchmark of the circuit board, Respectively represent components and performance benchmarks; S214, then the association weights between the components are: S215, among which, is an adjustable parameter; S216. Construct a component topology layer using the adjacency matrix and the association weights. The component topology layer is composed of components and directed edges connecting the components. The value of the directed edge is the value of the association weight between the two components. S217, connecting the component topology layer and the components in the signal path model one-to-one through the data transmission channel; As described in steps S25-S217 above, each component on the PCBA circuit board is identified as ,in It represents a unique index, determines the function, type and role of each component in the circuit, so as to facilitate subsequent modeling, and constructs an adjacency matrix to represent the connection relationship between components. For those that are not directly connected, it is represented by 0. In actual implementation, the initial connection relationship can be replaced by the electrical connection weight or directly defined as 1. At the same time, the connection weights between components are constructed, including electrical connection weights, physical connection weights and performance connection weights. The electrical connection weight reflects the electrical connection characteristics between two components in the circuit. This weight is mainly measured by the impedance and current flowing between the components. The physical connection weight reflects the physical distance between the two components in the circuit and the impact of this distance on signal transmission. The performance connection weight measures the relationship between the two components in terms of circuit performance benchmarks such as power, stability, etc. In actual implementation, a more comprehensive situation can be considered, and the addition of thermal coupling weights can be considered to reflect the degree of thermal influence between the two components in the circuit, usually through the thermal conductivity and physical distance between the components. and their respective thermal characteristics for evaluation. Further, the impedance matching weight and electromagnetic interference weight can be added to improve the association relationship between circuit board components. Based on the calculated component association weight, various association weights are integrated by designing adjustable parameters. Adjustable parameters allow designers to adjust the importance of weights according to circuit requirements. For example, in high-frequency digital signal circuits, electrical connection weights may be given higher weights as key factors. Designers can increase the weights of electrical connection weights to ensure that signal reflection and distortion are minimized during signal transmission. Based on the constructed adjacency matrix and association weights, a component topology layer is constructed, presenting directed edges between components and connected components, and the values ​​of the directed edges are the values ​​of the association weights. Transmission ports are set on the components, so that the components can realize real-time data interaction with the corresponding components of the signal path model through data transmission channels. The components in the component topology layer and the signal path model are connected one by one through transmission ports and data transmission channels to realize data interaction between the component topology layer and the signal path model.

[0022] In one embodiment, the step S2 of verifying the accuracy of the test signal using the signal path model and the component topology layer includes: S218, inputting the test data into the signal path model to obtain an optimal test signal, and using the optimal test signal passing through the detection point as a standard signal; S219, presetting an error threshold, comparing the test signal with the standard signal of the detection point, and if the error value between the test signal and the standard signal of a detection point in the signal path model exceeds the preset error threshold, then the detection is regarded as an abnormal point; S2110: The abnormal point activates the mapping space, the mapping space expands the stored signal path model as a mapping path, transmits the test signal to the mapping space, uses the abnormal point as the starting point of the mapping path, and uses the test signal as input to determine the signal flow direction of the test signal; S2111. Record abnormal information of the abnormal point, including the abnormal signal value, the abnormal point location, and the signal path to which it belongs. Transmit the abnormal information to the component topology layer via the component closest to the abnormal point. The component topology layer locates the potential fault component and collects data of the potential fault component. S2112. The component topology layer transmits the data of the potential fault component to the mapping space through the data transmission channel and the mapping channel. The mapping space dynamically adjusts the parameters of the potential fault component so that the output of the mapping path is equivalent to the standard data. S2113, the mapping path and signal path models are run in parallel until all detection points are compared, the faulty component is determined, and a fault diagnosis report is generated; As described in the above steps S218-S2113, the test data is transmitted as input to the signal path model, the signal path model is used to obtain the optimal test signal of the PCBA circuit board, and the optimal test data is used as standard data for comparison with the test signal to determine faults in a large range. The specific process includes setting an error threshold, using the detection window on the signal path model to compare the error between the test signal and the standard signal, and taking the detection point with an error exceeding the error threshold as an abnormal point, collecting the abnormal information of the abnormal point including the abnormal signal value, the abnormal point position and the signal path to which it belongs, and at the same time activating the mapping space of the abnormal point, the mapping space expands the signal path model stored therein as a mapping path, and takes the test signal of the detection point as input, and takes the mapping of the detection point on the mapping path as the starting point to determine the signal flow direction so that the test The signal runs in the mapping path. In the signal path model, the test signal and the standard signal are compared at the same time. At the same time, the abnormal point transmits the abnormal information to the corresponding element in the element topology layer through the element closest to it. The element that obtains the abnormal information retrieves the potential fault component through its topological properties, and collects the data of the potential fault component, and transmits it to the mapping space through the data transmission channel and the mapping channel. After obtaining the data of the potential fault component, the mapping space dynamically adjusts the parameters of the potential fault component so that the output of the mapping path is equivalent to the standard data, that is, by changing the components that may have faults, the output of the circuit board becomes accurate. Through the parallel operation of the mapping path and the signal path model and the interaction with the element topology layer, the comparison of all test data and standard data is completed, the faulty component is determined and a fault diagnosis report is generated.

[0023] In one embodiment, the step S2111 of locating a potential faulty component and collecting data of the potential faulty component including component ID, component parameters, and adjustment range at the component topology layer includes: S21111: Preset a correlation value threshold, and the component receiving the abnormal information retrieves, based on the component topology layer, connected components with correlation values ​​exceeding the correlation value threshold as potential fault components; S21112. Record data of potential faulty components including component ID, component parameters, and adjustment range; As described in the above steps S21111-S21112, the component topology layer presents the connection relationship and correlation degree between each component. A correlation threshold is preset. When a component receives abnormal information transmitted from the component closest to the abnormal point, the component is used as the root node, and the components connected to it are retrieved. The components whose edge values ​​exceed the correlation threshold are regarded as potential fault components. For potential fault components, it is necessary to collect their data including component ID, component parameters and adjustment range, and transmit this data to the mapping space as the target component for parameter adjustment.

[0024] In one embodiment, the step S2112 of dynamically adjusting the parameters of the potential faulty components so that the output of the mapping path is equivalent to the standard data includes: S21121. The mapping space receives data on potential fault components and defines a priority calculation formula: S21122, among which, Indicates the The priority of the potentially faulty components, is the output signal error of the mapping path, For the The error between the output signal of a potential fault component and the standard signal, The larger the value of , the higher the priority of the potential fault component to be modified, and the modification sorting table is determined based on the priority; S21123. Design objective function: S21124, as the optimization target, where F is the objective function, T is the test signal, and C is the standard signal. For the The adjusted parameter value of the potential fault component, For the Standard parameters of a potentially faulty component, is the regularization coefficient; S21125. Optimize the objective function using the least squares method; S21121. Preset an output error threshold, adjust the parameters of the highest priority potential fault component, and if the error threshold is not reached, adjust the next priority potential fault component in turn, and iterate until all potential fault components have been adjusted; As described in the above steps S21121-S21121, the mapping space receives the data of the potential fault element sent by the element topology layer, and calculates the ratio of the output signal error of the mapping path and the error between the output signal of the potential fault element and the standard signal. The ratio is used as the priority of the modification of the potential fault element. The larger the ratio, the higher the priority of the modification. The priority is sorted according to the size of the ratio to obtain a modification sorting table, and the objective function is set as the goal of adjusting the potential fault element. The purpose of optimization is to make the output of the mapping path equivalent to the standard signal. The least squares algorithm is used to optimize the objective function. The steps are to set the output error threshold and gradually adjust the parameters of the potential fault element in the objective function based on the priority sorting table. The condition for the end of the iteration is that all potential fault elements have been adjusted and the adjusted values ​​of the parameters of the potential fault elements are recorded.

[0025] In one embodiment, the step S3 of determining the faulty component and generating a fault diagnosis report includes: After the iteration operation is completed, define the parameter adjustment value: in, For the Parameter adjustment values ​​of potential faulty components, a preset parameter adjustment threshold, and potential faulty components whose parameters exceed the parameter adjustment threshold are regarded as faulty components; Summarize the fault information and abnormal information of the faulty component into a fault diagnosis report, wherein the fault information includes the component ID and parameter adjustment value; As described in the above steps S2-S24, after the iterative operation is completed, a function is defined to calculate the adjustment value of the parameter of the potential fault component, and a preset parameter adjustment threshold is used to determine whether the potential fault component is a fault component. The potential fault component whose adjustment value exceeds the adjustment value threshold is defined as a fault component. Its preset parameter adjustment threshold can be set as a dynamic threshold according to the operating status of the circuit board or other relevant factors. For example, when the circuit board load is high, the threshold can be appropriately increased to reduce the false alarm rate; and when the circuit board load is low, the threshold can be appropriately lowered to improve the fault detection sensitivity.

[0026] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A test signal verification processing method for a PCBA circuit board, characterized in that: include: Test the PCBA circuit board to obtain the component parameters and test signals of the PCBA circuit board; Build a signal path model and component topology layer, connect the component topology layer to the components in the signal path model one-to-one, and use the signal path model to verify the accuracy of the test signal; Use signal path models and component topology layers to locate faulty components and generate fault diagnosis reports; The steps of testing the PCBA circuit board to obtain component parameters and test signals of the PCBA circuit board are as follows: Extract the standard parameters of each component of the PBCA circuit board; Develop test data for PCBA circuit boards, including input signal type, signal amplitude, and frequency range; Use the test data to perform initial testing on the PCBA circuit board to obtain the test signal; The steps of constructing the signal pathway model are: Extract signal path information from the circuit schematic of the PCBA circuit board, including the signal's starting point, end point, components and wires it passes through; Convert the signal path into a circuit network, draw a signal flow graph on the circuit network to obtain a signal path model including components, signal paths and signal flow directions; The initial values ​​of the component parameters are standard parameters and are adjustable; A plurality of detection windows are set on the signal path and at both ends of the component. The plurality of detection windows are connected to a plurality of mapping spaces through mapping channels. The signal path model is stored in the mapping space.

2. A test signal verification processing method for a PCBA circuit board according to claim 1, characterized in that: The steps to build the component topology layer and connect the component topology layer to the components in the signal path model one-to-one are as follows: Place the PBCA circuit board in The components are defined as: , and construct the adjacency matrix between each element: ； in, represents the adjacency matrix, Display components and adjacency; Defining the association weights between components includes electrical connection weight, physical connection weight and performance connection weight; The electrical connection weight is: ； in, Display components and The electrical connection weight, Indicates flow through the element and The current between Display components and The equivalent impedance between Physical connection weight: ； in, Display components and The physical connection weight between express and physical distance, is the distance decay factor; Performance connection weight: ； in, Display components and The performance connection weight between Indicates the performance benchmark of the circuit board, Respectively represent components and performance benchmarks; The association weights between the components are: ； in, is an adjustable parameter; The component topology layer is constructed through the adjacency matrix and the association weight. The component topology layer consists of components and directed edges connecting the components. The value of the directed edge is the value of the association weight between the two components. Connect the component topology layer to the components in the signal path model one-to-one through the data transmission channel.

3. A test signal verification processing method for a PCBA circuit board according to claim 2, characterized in that: The steps of locating the faulty component and generating a fault diagnosis report by using the signal path model and the component topology layer are as follows: Input the test data into the signal path model to obtain the optimal test signal, and use the optimal test signal passing through the detection point as the standard signal; A preset error threshold is set, and the test signal is compared with the standard signal of the detection point. If the error value between the test signal and the standard signal of a detection point in the signal path model exceeds the preset error threshold, the detection point is regarded as an abnormal point; The abnormal point activates the mapping space, and the mapping space expands the stored signal path model as the mapping path. The test signal is transmitted to the mapping space, and the mapping abnormal point is used as the starting point of the mapping path. The test signal is used as input to determine the signal flow direction of the test signal. The abnormal information of the abnormal point is recorded, including the abnormal signal value, the abnormal point location and the signal path to which it belongs. The abnormal information is transmitted to the component topology layer through the component closest to the abnormal point. The component topology layer locates the potential fault component and collects the data of the potential fault component; The component topology layer transmits the data of the potential fault component to the mapping space through the data transmission channel and the mapping channel. The mapping space dynamically adjusts the parameters of the potential fault component so that the output of the mapping path is equivalent to the standard data. The mapping path and signal path models are run in parallel until all detection points are compared, the faulty component is identified, and a fault diagnosis report is generated.

4. A test signal verification processing method for a PCBA circuit board according to claim 3, characterized in that: The steps of locating the potential faulty components and collecting data of the potential faulty components including component ID, component parameters and adjustment range in the component topology layer are as follows: A correlation value threshold is preset, and the component receiving the abnormal information retrieves the components connected to it whose correlation values ​​exceed the correlation value threshold based on the component topology layer as potential fault components; The data recorded for the potential fault component includes component ID, component parameters, and adjustment range.

5. A test signal verification processing method for a PCBA circuit board according to claim 4, characterized in that: The mapping space dynamically adjusts the parameters of the potential fault components so that the output of the mapping path is equivalent to the standard data. The steps are: The mapping space receives data on potential fault components and defines the priority calculation formula: ； in, Indicates the The priority of the potentially faulty components, is the output signal error of the mapping path, For the The error between the output signal of a potential fault component and the standard signal, The larger the value of , the higher the priority of the potential fault component to be modified, and the modification sorting table is determined based on the priority; Design objective function: ； As the optimization target, where F is the objective function, T is the test signal, C is the standard signal, For the The adjusted parameter value of each potential fault component, For the Standard parameters of a potential fault component, is the regularization coefficient; Optimize the objective function using the least squares minimization method; The output error threshold is preset, and the parameters of the potential fault component with the highest priority are adjusted. If the error threshold is not reached, the potential fault component with the next priority is adjusted in turn, and the iterative operation is performed until all potential fault components have been adjusted.

6. A test signal verification processing method for a PCBA circuit board according to claim 5, characterized in that: The steps of determining the fault component and generating a fault diagnosis report are: After the iteration operation is completed, define the parameter adjustment value: ； in, For the Parameter adjustment values ​​of potential faulty components, a preset parameter adjustment threshold, and potential faulty components whose parameters exceed the parameter adjustment threshold are regarded as faulty components; The fault information and abnormal information of the faulty component are summarized into a fault diagnosis report, wherein the fault information includes the component ID and parameter adjustment value.

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