Interconnected chip-oriented time delay test method, system and program product

Abstract

The invention provides an interconnected chip-oriented time delay test method and system and a program product. The method comprises the following steps: acquiring a first test signal to obtain an original signal; collecting a second test signal passing through the tested chip to obtain a delay signal; the first test signal and the second test signal are associated periodic binary sequences; the period of the periodic binary sequence is greater than the time delay of the tested chip; intercepting a first intercepted signal in a preset time range from the original signal, and intercepting a second intercepted signal in the preset time range from the delay signal; the time length of the preset time range is not less than the period of the periodic binary sequence; circularly shifting the first intercepted signal or the second intercepted signal towards a set direction, and recording a corresponding target shift digit when the first intercepted signal and the second intercepted signal coincide; and determining the time delay of the tested chip according to the target shift digit. According to the invention, the accuracy of the chip time delay test can be improved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a delay testing method, system and program product for interconnected chips. Background Art

[0002] The emergence and development of new technologies like AI and large models has created a strong demand for high computing power and bandwidth. The increase in computing power per server has also led to higher data exchange rates between servers, making data exchange latency a key indicator of system performance.

[0003] How to evaluate and measure accurate data exchange latency in the early stages of interconnect chip design and optimize it to reduce latency has become a key to improving product competitiveness.

[0004] One existing solution uses a computer to record the time it takes to send and receive a message, then subtracts the send and receive times to determine the module's latency performance. However, testing latency using messages is affected by the computer's inherent latency and message parsing time, resulting in low accuracy.

[0005] One existing solution is to simultaneously send a square wave with a period of f to the link under test and an internal link (which has essentially no latency), and record the period difference n between the two square waves. This yields the latency of the link under test as t = n / f. However, this square wave approach can only be used to test passive links. Currently, the receivers of high-speed interconnect chips all have CDR (Clock and Data Recovery) modules, making shorter-period square waves or pulse signals inappropriate for latency testing. Furthermore, as communication speeds increase, the receivers of high-speed interconnect chips now include equalization capabilities to compensate for transmission link losses. Equalization and connection establishment only begin when the signal at the receiver is present. Testing using this square wave approach would include the time required for equalization and connection establishment, thus not accurately measuring the chip link-to-signal latency.

[0006] An existing solution is that after the module under test inputs the test data, one of the test signals of the module under test is output to the data comparator and compared with the set expected value, that is, the other test signal. When the data comparator outputs the target signal, the counter count bit is obtained, and the delay is calculated by the count bit and each unit delay time. However, this solution requires that the two signals to be calculated are the same digital signals, and in real application scenarios, it is often impossible to ensure that the signals of the two transmitting ends of the chip are exactly the same. Therefore, this solution is only applicable to the digital circuits inside the chip and is not applicable to real analog scenarios. In addition, this solution triggers the calculation of the delay when it is determined that the two signals have changed from alignment to misalignment, resulting in a very short measurable delay, and the total delay of the module under test can only be within one unit time interval. Summary of the Invention

[0007] The first purpose of the present invention is to provide a delay testing method for interconnected chips to solve the problems that existing delay testing methods are not accurate enough and have limited scenarios.

[0008] A second object of the present invention is to provide a system for implementing the above-mentioned delay testing method for interconnected chips.

[0009] A third object of the present invention is to provide a computer program product for implementing the above-mentioned delay testing method for interconnected chips.

[0010] To achieve the above-mentioned first objective, the present invention provides a delay testing method for interconnected chips, which includes the following steps: collecting a first test signal to obtain an original signal; collecting a second test signal passing through the chip under test to obtain a delayed signal; the first test signal and the second test signal are associated periodic binary sequences; the period of the periodic binary sequence is greater than the delay of the chip under test; intercepting a first intercepted signal within a preset time range from the original signal, and intercepting a second intercepted signal within a preset time range from the delayed signal; the time length of the preset time range is not less than the period of the periodic binary sequence; cyclically shifting the first intercepted signal or the second intercepted signal in a set direction, recording the target shift bit number corresponding to the overlap between the first intercepted signal and the second intercepted signal; and determining the delay of the chip under test based on the target shift bit number.

[0011] As can be seen from the above scheme, the present invention can directly quantify the signal delay of the internal link of the chip under test, without being interfered with by message processing delay or computer processing delay, and the measured delay data is close to the actual situation of the chip. The present invention simulates the actual signal flipping situation through a periodic binary sequence, thereby ensuring that the working state of the chip under test during delay measurement is consistent with the actual usage of the interconnected chip, especially high-speed interconnected chips with CDR functions. The present invention has no requirements for whether the signal is analog or digital. Even if the two signals have different swings (for example, one signal is 1V and the other is 3V) and contain non-ideal factors such as clock jitter or inter-symbol interference, the present invention can still normally complete signal alignment and delay analysis, covering a wider range and providing stable results, which is applicable to real simulation scenarios.

[0012] A further solution is that the first test signal and the second test signal are the same or inverted signals; when the first test signal and the second test signal are inverted, the first test signal is collected and the polarity is flipped to obtain the original signal, or the second test signal passing through the chip under test is collected and the polarity is flipped to obtain a delayed signal; the target shift bit number is multiplied by the sampling point interval to obtain the delay of the chip under test.

[0013] It can be seen from this that when the first test signal and the second test signal are the same or in opposite phases, the sampling point interval can be determined according to the sampling rates of the original signal and the delayed signal, and then the delay of the chip under test can be directly determined by multiplying the sampling point interval by the target shift bit number.

[0014] A further solution is that the first test signal and the second test signal are the same signal sent with a set delay, or signals with specific bits that are different in one cycle.

[0015] As can be seen from this, for a first test signal and a second test signal that have a specific relationship, the latency of the chip under test can be determined by combining the specific relationship after determining the target number of shift bits. For example, if a set delay is sent between the first and second test signals, resulting in a set delay during acquisition, the current delay can be calculated based on the target number of shift bits, and the set delay can be added or subtracted to obtain the latency of the chip under test. For example, if a signal has a specific bit that differs within a cycle, when the first and second intercepted signals overlap through cyclic shifting, this specific bit can be ignored when determining the target number of shift bits.

[0016] A further solution is to wait for a preset time before collecting the original signal and the delayed signal so that the chip under test can complete the link establishment.

[0017] This shows that accurate delay test results can be obtained.

[0018] A further solution is to circularly shift the first intercepted signal or the second intercepted signal in a set direction, and record the target shift bit number corresponding to the overlap of the first intercepted signal and the second intercepted signal, including: initializing the count value to 0; repeatedly performing the following steps until the count value is not less than the difference between the number of bits of the first intercepted signal minus 1: circularly shifting the first intercepted signal to the left or right by the same number of bits as the count value to obtain the first shifted signal; calculating the product of the values ​​of the first intercepted signal and the first shifted signal at the same position, and summing the products corresponding to all positions to obtain a correlation coefficient; adding 1 to the count value; and when the count value is not less than the difference between the number of bits of the first intercepted signal minus 1, determining the target shift bit number based on the shift bit number of the first intercepted signal corresponding to the largest correlation coefficient.

[0019] It can be seen that the present invention can calculate the delay based on the corresponding left cyclic shift bit number or right cyclic shift bit number when the first intercepted signal is cyclically shifted left or right until it overlaps with the first intercepted signal.

[0020] A further solution is to circularly shift the first intercepted signal or the second intercepted signal in a set direction, and record the target shift bit number corresponding to the overlap of the first intercepted signal and the second intercepted signal, including: initializing the count value to 0; repeatedly performing the following steps until the count value is not less than the difference between the number of bits of the first intercepted signal minus 1: circularly shifting the second intercepted signal to the left or right by the same number of bits as the count value to obtain a second shifted signal; calculating the product of the values ​​of the first intercepted signal and the second shifted signal at the same position, and summing the products corresponding to all positions to obtain a correlation coefficient; adding 1 to the count value; and when the count value is not less than the difference between the number of bits of the first intercepted signal minus 1, determining the target shift bit number based on the shift bit number of the second intercepted signal corresponding to the largest correlation coefficient.

[0021] It can be seen that the present invention can calculate the delay based on the corresponding left cyclic shift bit number or right cyclic shift bit number when the second intercepted signal is cyclically shifted left or right until it overlaps with the first intercepted signal.

[0022] A further solution is to further include determining the maximum correlation coefficient based on the first intercepted signal; shifting the first intercepted signal or the second intercepted signal in a set direction, and recording the target shift number when the first intercepted signal and the second intercepted signal overlap, including: initializing the count value to 0; repeating the following steps until the current correlation coefficient is the maximum correlation coefficient: circularly shifting the second intercepted signal to the left by the same number of bits as the count value to obtain a second shifted signal; calculating the product of the values ​​of the first intercepted signal and the second shifted signal at the same position, and summing the products corresponding to all positions to obtain the current correlation coefficient; adding 1 to the count value; and when the current correlation coefficient is the maximum correlation coefficient, determining the left circular shift number of the second intercepted signal corresponding to the current correlation coefficient as the target shift number.

[0023] It can be seen that the present invention can determine the target number of shift bits by judging whether the current correlation coefficient is equal to the maximum correlation coefficient, thereby reducing the number of shifts and improving the efficiency of the delay test.

[0024] A further solution is that the code patterns corresponding to the first test signal and the second test signal are PRBS code patterns.

[0025] It can be seen that the present invention can approach the data stream in the actual working scenario of the chip by using the PRBS code type. The delay information obtained by the test is relatively real and will not be interfered by functions such as chip receiving end equalization.

[0026] To achieve the second objective described above, the present invention provides a time delay test system for interconnected chips, comprising: a signal generation module, a signal acquisition module, and a time delay analysis module; the signal generation module is configured to generate a first test signal and a second test signal; the first test signal and the second test signal are associated periodic binary sequences; the period of the periodic binary sequence is greater than the time delay of the chip under test; the signal acquisition module is configured to directly acquire the first test signal to obtain an original signal, and to acquire the second test signal passing through the chip under test to obtain a delayed signal; the time delay analysis module is further configured to determine the time delay of the chip under test, comprising the following steps: intercepting the original signal within a preset time range to obtain a first intercepted signal; intercepting the delayed signal within a preset time range to obtain a second intercepted signal; the time length of the preset time range being no less than the period of the periodic binary sequence; cyclically shifting the first intercepted signal or the second intercepted signal in a set direction, recording a target shift bit number corresponding to when the first intercepted signal and the second intercepted signal coincide; and determining the time delay of the chip under test based on the target shift bit number.

[0027] It can be seen that the present invention can improve the accuracy of the delay test of the chip under test, and can adjust the sampling point interval by setting the sampling rate of the signal sampling module, thereby facilitating the adjustment of different delay test accuracies.

[0028] In order to achieve the third objective mentioned above, the present invention provides a computer program product, comprising computer instructions, wherein: when the computer instructions are executed by a processor, the above-mentioned delay testing method for interconnected chips is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a system framework diagram of the delay test system in the first embodiment of the present invention.

[0030] Figure 2 is a flow chart of the first embodiment of the present invention.

[0031] Figure 3 yes Figure 2Specific flow chart of step S15 in FIG.

[0032] Figure 4 2 is a schematic diagram of calculating the correlation coefficient in the first embodiment of the present invention.

[0033] Figure 5 is a flow chart for determining the target number of shift bits in the second embodiment of the present invention.

[0034] Figure 6 is a flow chart for determining the target number of shift bits in the third embodiment of the present invention.

[0035] Figure 7 FIG. 4 is a flowchart of determining the target shift bit number according to the fourth embodiment of the present invention.

[0036] The present invention will be further described below with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0037] The present invention's latency testing system for high-speed interconnect chips generates two identical test signals through a signal generation module. One signal directly enters the first channel of a signal acquisition module, while the other passes through the device under test and enters the second channel of the signal acquisition module. A latency analysis module intercepts the signals collected by the signal acquisition module within a preset time range to obtain two intercepted signals. By calculating the correlation between the two intercepted signals, the time difference between the two intercepted signals is obtained and the latency of the device under test is determined. The device under test in the present invention is an active chip device such as a high-speed interconnect chip.

[0038] First embodiment: See also Figure 1 The latency test system of this embodiment includes a signal generation module 11, a signal acquisition module 12, and a latency analysis module 13. The signal generation module 11 is connected to the signal acquisition module 12 and the external receiving end of the chip under test 2. The transmitting end of the chip under test 2 is connected to the signal acquisition module 12, which is connected to the latency analysis module 13. This embodiment uses the latency test system to test the latency of the chip under test 2.

[0039] The signal generation module 11 is used to generate a first test signal and a second test signal. The first and second test signals are associated periodic binary sequences. "Associated" means that there is a specific relationship between the first and second test signals, such as being identical, out of phase, having a specific delay in transmission, or having specific bits that differ within a cycle. In this embodiment, the first and second test signals are identical test signals emitted simultaneously by the signal generation module 11. The period of the periodic binary sequence is greater than the delay of the chip under test 2.

[0040] The first test signal directly enters the first channel of the signal acquisition module 12. The second test signal enters the receiving end of the chip under test 2, and then is output from the transmitting end of the chip under test 2 to the second channel of the signal acquisition module.

[0041] A periodic pseudo-random binary sequence is a binary sequence that repeats at a specific period, with the binary sequence being identical in each period. The signal generation module 11 of this embodiment generates two PRBS (Pseudo-Random Binary Sequence) patterns with the same phase as the first test signal and the second test signal, respectively.

[0042] In other embodiments, other binary sequences that repeat periodically may also be used as the first test signal and the second test signal.

[0043] Signal acquisition module 12 includes a first channel and a second channel for signal acquisition. The first channel is used to acquire a first test signal from signal generation module 11, and the second channel is used to acquire a second test signal from the transmitting end of chip under test 2. The first test signal directly acquired by the first channel is called the original signal, and the second test signal acquired by the second channel is transmitted to chip under test 2. The signal transmitted by chip under test 2 is called the delayed signal. Signal acquisition module 12 is also used to send the original signal and the delayed signal to delay analysis module 13.

[0044] The delay analysis module 13 is used to calculate and determine the delay of the chip under test 2. After the delay analysis module 13 obtains the original signal and the delayed signal, it obtains a first intercepted signal by intercepting the original signal within a preset time range, and obtains a second intercepted signal by intercepting the delayed signal within a preset time range. The time length of the preset time range is not less than the period of the periodic binary sequence. Then, the second intercepted signal is circularly shifted to the left, and the target shift bit number corresponding to the overlap of the first intercepted signal and the second intercepted signal is recorded. The target shift bit number is used to calculate the delay of the chip under test 2, which represents the number of bits required to shift between the first intercepted signal and the second intercepted signal to obtain the accurate delay of the chip under test 2 by multiplying by the acquisition point interval.

[0045] In different embodiments, the signal generating module 11 , the signal collecting module 12 and the time delay analyzing module 13 may correspond to specific hardware modules and / or software function modules.

[0046] See also Figure 2 The delay test method of the chip under test implemented based on the delay test system can be implemented by a computer program, and specifically includes the following steps: S11: Control the signal generating module to generate a first test signal and a second test signal.

[0047] Among them, by controlling the output enable signal to the signal generating module, the output code type is configured to be PRBS15, so that the signal generating module can output the same first test signal and second test signal, where "same" not only means that the binary sequences that constitute the signals are the same, but also that the values ​​corresponding to each position in the sequence are the same. For example, the value corresponding to the 0th position of the first test signal is the same as the value corresponding to the 0th position of the first test signal.

[0048] The repetition period of a PRBS pattern is related to the length of the PRBS code and the signal transmission rate. This embodiment uses a PRBS15 pattern (repetition period of 32767 UI) and a 112G PAM4 signal (symbol rate of 56Gsym / s, transmission time of one UI is 1 / 56G≈17.86ps). Therefore, the repetition period of a PRBS15 pattern is 32767*17.86=585218.62ps≈585ns. As long as the latency of the chip under test is no greater than 585ns, the PRBS15 pattern can be used for testing. Otherwise, a PRBS pattern with a longer repetition period, such as PRBS23, must be used. The present invention only requires that the PRBS pattern repetition period be greater than the latency of the chip under test; the specific PRBS pattern used is not limited.

[0049] S12: Wait for a preset time for the chip under test to complete link establishment.

[0050] The chip enters normal operating state by waiting for a preset time. Initialization is required from power-up to normal operating state, and the specific waiting time is determined by the initialization time requirements of the chip under test. Failure to wait and test before the chip enters normal operating state will result in inaccurate delay testing. There are several possible reasons for this: first, the chip's internal data path is not properly established; second, the chip under test may not output a signal to the signal acquisition module; third, the chip under test's output is not yet stable, and the signal acquisition module may be sampling an erroneous signal. By setting a preset time, the chip under test completes receiver equalization and establishes the chip's internal link.

[0051] S13: directly collecting the first test signal through the signal acquisition module to obtain the original signal, and collecting the second test signal passing through the chip under test to obtain the delayed signal.

[0052] The original signal and the delayed signal must have the same length and must be greater than the repetition period of a PRBS pattern. Assuming the sampling rate is Sa, the delay calculation accuracy is 1 / Sa. Therefore, the higher the sampling rate, the higher the delay accuracy. For example, if the sampling rate is 1GSa / s, the delay accuracy is 1ns; if the sampling rate is 100GSa / s, the delay accuracy is 0.01ns.

[0053] S14: intercepting, by the time delay analysis module, a first intercepted signal in a preset time range from the original signal, and intercepting a second intercepted signal in the preset time range from the time-delay signal.

[0054] The time intervals of the original signal and the time-delay signal need to be the same, that is, starting at the same time and ending at the same time. The duration of the preset time range needs to be greater than or equal to the length of a PRBS repetition period.

[0055] S15: circularly shifting, by the time delay analysis module, the second intercepted signal to the left, and recording a target shift bit number corresponding to a time when the first intercepted signal and the second intercepted signal coincide.

[0056] S16: multiplying, by the time delay analysis module, the target shift bit number and a sampling point interval of the signal acquisition module to obtain a time delay of the measured chip.

[0057] In the above step S15, referring to Figure 3 , the method specifically comprises the following steps: S101: initializing a count value k = 0.

[0058] S102: circularly shifting the second intercepted signal to the left by k bits to obtain a shifted second intercepted signal. The shifted second intercepted signal is a second shifted signal.

[0059] S103: calculating the product of the values of the first intercepted signal and the shifted second intercepted signal at the same position, and summing the products of all positions to obtain a correlation coefficient.

[0060] S104: adding 1 to the count value k.

[0061] S105: determining whether the count value is not less than the difference between the bit number of the first intercepted signal and 1. If the result of the determination is yes, step S106 is executed, otherwise, returning to step S102.

[0062] S106: determining that the bit number of the left circular shift corresponding to the maximum correlation coefficient is the target shift bit number.

[0063] Referring to Figure 4 , the bit numbers of the first intercepted signal and the second intercepted signal are both m+1 bits (the value of m+1 is determined by the sampling rate of the signal acquisition module and the preset time range), that is, including m+1 positions, each position corresponding to a binary value collected by a sampling point, that is, each position stores a "0" or a "1".

[0064] When k=0, the first intercepted signal is represented as Wa0, and the corresponding value of the first intercepted signal at its 0th position is A0, the corresponding value at its 1st position is A1, and so on, the corresponding value at its mth position is Am; the second intercepted signal is represented as Wb0, and the corresponding value of the second intercepted signal at its 0th position is B0, the corresponding value at its 1st position is B1, and so on, the corresponding value at its mth position is Bm. At this time, the correlation coefficient [0]=Result0 + Result1 + Result2 + … + Result(m-1)+ Result(m), Result0= A0×B0, Result1= A1×B1, Result2= A2×B2, …, Result(m-1)= A(m-1)×B(m-1), Result(m)=Am×Bm.

[0065] When k=1, the value recorded on the second intercepted signal is cyclically shifted 1 bit to the left relative to when k=0, and is represented as Wb1. The first intercepted signal remains unchanged and is still represented as Wa0. At this time, the value corresponding to the second intercepted signal at its 0th position is B1, the value corresponding to its 1st position is B2, and so on, the value corresponding to its mth position is B0. At this time, the correlation coefficient [1] = Result0 + Result1 + Result2 + … + Result(m-1)+ Result(m), Result0= A0×B1, Result1= A1×B2, Result2= A2×B3, …, Result(m-1)= A(m-1)×Bm, Result(m)= Am×B0.

[0066] When k = m-1, the value recorded in the second intercepted signal is circularly shifted left by (m-1) bits relative to the value when k = 0, represented as Wb(m-1). The first intercepted signal remains unchanged and is represented as Wa0. The value corresponding to the 0th position of the second intercepted signal is now Bm, the value corresponding to the 1st position is B0, and so on, with the value corresponding to the mth position being B(m-1). At this point, the correlation coefficient [m-1] = Result0 + Result1 + Result2 + … + Result(m-1) + Result(m), where Result0 = A0×Bm, Result1 = A1×B0, Result2 = A2×B1, …, Result(m-1) = A(m-1)×B(m-2), and Result(m) = Am×B(m-1).

[0067] Thus, m correlation coefficients can be obtained, and the number of bits of left cyclic shift corresponding to the maximum correlation coefficient is determined as the target number of shift bits.

[0068] In step S106, the target number of shift bits is multiplied by the interval between each sampling point to obtain the latency of the chip under test. The interval between each sampling point is determined by the sampling rate of the signal acquisition module. In this embodiment, the sampling rate is Sa, and the accuracy of the latency calculation is 1 / Sa. Therefore, the interval between each sampling point is 1 / Sa. The target number of shift bits is Pa, and the latency of the chip under test is Pa*1 / Sa.

[0069] The computer instructions for implementing the above method can be stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, so that the computer device performs each step of the above delay testing method for interconnected chips.

[0070] Second embodiment: The difference between this embodiment and the first embodiment is step S15. Figure 5 , step S15 of this embodiment specifically includes the following steps: S201: Initialize the count value j=0.

[0071] S202: Circularly shift the second intercepted signal rightward by a number j, to obtain a shifted second intercepted signal, which is a second shifted signal.

[0072] S203: Calculate the product of the values ​​of the first intercepted signal and the shifted second intercepted signal at the same position, and sum the products corresponding to all positions to obtain a correlation coefficient.

[0073] S204: Add 1 to the count value j.

[0074] S205: Determine whether the count value is not less than the difference of the number of bits of the first intercepted signal minus 1. If the result of the determination is yes, proceed to step S206, otherwise return to step S202.

[0075] S206: Determine the target shift bit value as the difference between the bit number of the first intercepted signal and the bit number of the right cyclic shift corresponding to the maximum correlation coefficient.

[0076] Third embodiment: The difference between this embodiment and the first embodiment is step S15. Figure 6 , step S15 of this embodiment specifically includes the following steps: S301: Initialize the count value i=0.

[0077] S302: Circularly shift the first intercepted signal to the left, the number of bits shifted is i, and obtain a shifted first intercepted signal. The shifted first intercepted signal is the first shifted signal.

[0078] S303: Calculate the product of the values ​​of the shifted first intercepted signal and the second intercepted signal at the same position, and sum the products corresponding to all positions to obtain a correlation coefficient.

[0079] S304: Increment the count value i by 1.

[0080] S305: Determine whether the count value is not less than the difference of the number of bits of the first intercepted signal minus 1. If the result of the determination is yes, proceed to step S306, otherwise return to step S302.

[0081] S306: Determine the target shift bit value as the difference between the bit number of the first intercepted signal and the bit number of the left cyclic shift corresponding to the maximum correlation coefficient.

[0082] Fourth embodiment: The difference between this embodiment and the first embodiment lies in the method of determining the target shift bit number.

[0083] In this embodiment, the delay analysis module is further configured to determine a maximum correlation coefficient based on the first intercepted signal. Since the number of "1" values ​​in the first intercepted signal is fixed, the maximum correlation coefficient value is obtained by counting the number of "1" values. For example, if the number of "1" values ​​in the first intercepted signal is M, then the maximum correlation coefficient value is M.

[0084] The difference from determining the target shift number in step S15 of the first embodiment is that after performing a left cyclic shift, the corresponding correlation coefficient is calculated until the current correlation coefficient is the maximum correlation coefficient. At this time, the current left cyclic shift number is recorded as the target shift number. Figure 7 , specifically including the following steps: S401: Initialize the count value n=0.

[0085] S402: Circularly shift the second intercepted signal to the left by n bits to obtain a shifted second intercepted signal.

[0086] S403: Calculate the product of the values ​​of the first intercepted signal and the shifted second intercepted signal at the same position, and sum the products corresponding to all positions to obtain a correlation coefficient.

[0087] S404: Increment the count value n by 1.

[0088] S405: Determine whether the current correlation coefficient is the maximum correlation coefficient. If so, continue to step S406; otherwise, return to step S402.

[0089] S406: Determine the number of left cyclic shift bits corresponding to the current correlation coefficient as the target shift number.

[0090] Fifth embodiment: The difference between this embodiment and the first embodiment lies in the signal generation module and the delay analysis module.

[0091] The signal generation module is distinguished by its differential output, which outputs a first test signal and a second test signal that are aligned but inverted. The first end of the differential output is connected to the signal acquisition module, allowing the first test signal to enter the signal acquisition module; the second end of the differential output is connected to the receiving terminal of the chip under test, allowing the second test signal to enter the input terminal of the chip under test. The difference of the delay analysis module is that after obtaining the original signal and the delayed signal, the polarity of the original signal or the delayed signal is reversed, and then the first intercepted signal and the second intercepted signal are respectively intercepted.

[0092] Sixth embodiment: This embodiment differs from the first embodiment described above in that the signal generation module sequentially emits the same first and second test signals according to a set delay. The first and second test signals are identical periodic binary sequences, and the set delay is less than the period of the periodic binary sequence. Therefore, when the target number of shift bits is multiplied by the interval between each sampling point, the set delay is subtracted to obtain the delay of the chip under test.

[0093] In summary, the present invention uses PRBS code patterns to ensure the normal operation of the internal circuits of high-speed interconnect chips, ensuring that the delay test results are close to the actual scenarios of the device under test. It also utilizes the characteristic of PRBS codes having a certain repetition period to obtain the delay information between the two signals through the cyclic shift dot product sum method between the two signals, thereby obtaining accurate delay test results.

[0094] Finally, it should be emphasized that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A delay testing method for interconnected chips, characterized in that: The following steps are involved: Acquire a first test signal to obtain an original signal; acquire a second test signal passing through the chip under test to obtain a delayed signal; the first test signal and the second test signal are associated periodic binary sequences; the period of the periodic binary sequence is greater than the delay of the chip under test; intercepting a first intercepted signal within a preset time range from the original signal, and intercepting a second intercepted signal within the preset time range from the delayed signal; the length of the preset time range is not less than the period of the periodic binary sequence; cyclically shifting the first intercepted signal or the second intercepted signal in a set direction, and recording a target shift bit number corresponding to when the first intercepted signal and the second intercepted signal overlap; The delay of the chip under test is determined according to the target number of shift bits.

2. The method for delay testing of interconnected chips according to claim 1, wherein: The first test signal and the second test signal are signals of the same phase or inverted phase; when the first test signal and the second test signal are inverted phase, the first test signal is collected and polarity flipped to obtain the original signal, or the second test signal passing through the chip under test is collected and polarity flipped to obtain the delayed signal; The target shift bit number is multiplied by the sampling point interval to obtain the delay of the chip under test.

3. The method for delay testing of interconnected chips according to claim 1, wherein: The first test signal and the second test signal are the same signal sent with a set delay, or signals with specific bits different in one cycle.

4. The method for delay testing of interconnected chips according to claim 1, wherein: Before collecting the original signal and the delayed signal, wait for a preset time to allow the chip under test to complete the establishment of the link.

5. The delay testing method for interconnected chips according to claim 1, wherein: cyclically shifting the first intercepted signal or the second intercepted signal in a set direction and recording the target shift bit number corresponding to when the first intercepted signal and the second intercepted signal overlap, comprising: Initialize the count value to 0; Repeating the following steps until the count value is not less than the difference between the number of bits of the first intercepted signal and 1: circularly shifting the first intercepted signal leftward or rightward by the same number of bits as the count value to obtain a first shifted signal; calculating the product of the values ​​of the first intercepted signal and the first shifted signal at the same position, and summing the products corresponding to all positions to obtain a correlation coefficient; and incrementing the count value by 1. When the count value is not less than the difference between the number of bits of the first intercepted signal and 1, the target shift number is determined according to the shift number of the first intercepted signal corresponding to the largest correlation coefficient.

6. The delay testing method for interconnected chips according to claim 1, wherein: cyclically shifting the first intercepted signal or the second intercepted signal in a set direction and recording the target shift bit number corresponding to when the first intercepted signal and the second intercepted signal overlap, comprising: Initialize the count value to 0; Repeating the following steps until the count value is not less than the difference between the number of bits of the first intercepted signal and 1: circularly shifting the second intercepted signal leftward or rightward by the same number of bits as the count value to obtain a second shifted signal; calculating the product of the values ​​of the first intercepted signal and the second shifted signal at the same position, and summing the products corresponding to all positions to obtain a correlation coefficient; and incrementing the count value by 1. When the count value is not less than the difference between the number of bits of the first intercepted signal and 1, the target number of shift bits is determined according to the number of shift bits of the second intercepted signal corresponding to the largest correlation coefficient.

7. The delay testing method for interconnected chips according to claim 1, wherein: Also includes: determining a maximum correlation coefficient based on the first intercepted signal; Shifting the first intercepted signal or the second intercepted signal in a set direction and recording the target shift bit number when the first intercepted signal and the second intercepted signal overlap, comprising: Initialize the count value to 0; Repeating the following steps until the current correlation coefficient reaches the maximum correlation coefficient: cyclically shifting the second intercepted signal to the left by the same number of bits as the count value to obtain a second shifted signal; calculating the product of the values ​​of the first intercepted signal and the second shifted signal at the same position, and summing the products corresponding to all positions to obtain the current correlation coefficient; and increasing the count value by 1; When the current correlation coefficient is the maximum correlation coefficient, the number of left cyclic shift bits of the second intercepted signal corresponding to the current correlation coefficient is determined to be the target number of shift bits.

8. The delay testing method for interconnected chips according to claim 1, wherein: The code patterns corresponding to the first test signal and the second test signal are PRBS code patterns.

9. A delay test system for interconnected chips, characterized in that: include: Signal generation module, signal acquisition module, time delay analysis module; The signal generating module is used to generate a first test signal and a second test signal; The first test signal and the second test signal are associated periodic binary sequences; a period of the periodic binary sequence is greater than a delay of the chip under test; The signal acquisition module is used to directly acquire the first test signal to obtain an original signal, and is used to acquire the second test signal passing through the chip under test to obtain a delayed signal; The delay analysis module is further used to determine the delay of the chip under test, including the following steps: intercepting the original signal within a preset time range to obtain a first intercepted signal; intercepting the delayed signal within the preset time range to obtain a second intercepted signal; the time length of the preset time range is not less than the period of the periodic binary sequence; cyclically shifting the first intercepted signal or the second intercepted signal in a set direction, and recording a target shift bit number corresponding to when the first intercepted signal and the second intercepted signal overlap; The delay of the chip under test is determined according to the target number of shift bits.

10. A computer program product comprising computer instructions, characterized in that: When the computer instructions are executed by the processor, the delay testing method for interconnected chips according to any one of claims 1 to 8 is implemented.

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