Low-power-consumption warm start method of multi-core system and multi-core system

Abstract

The invention belongs to the technical field of low power consumption, and discloses a low-power-consumption hot start method of a multi-core system and the multi-core system.The method comprises the steps that when a target function module needs to enter a low-power-consumption state, a first random storage area corresponding to the target function module is controlled to enter a low-power-consumption data retention state, controlling a second random storage area corresponding to the target function module to be powered off, and controlling a target processing core for realizing the target function module to enter a dormant state; when a starting instruction is received, the second-level bootstrap program in the first random storage area is operated, and the second-level bootstrap program calls the communication interface maintenance program to establish communication connection with the host; downloading the service firmware of the target function module to the second random storage area through the second-level bootstrap program; and running the service firmware in the second random storage area. Therefore, the functional module can enter a low-power-consumption standby state when being idle, and quick hot start is realized when the awakening instruction is received, so that low power consumption and high response speed are both considered.

Description

Technical Field

[0001] The present invention belongs to the technical field of low power consumption, and in particular relates to a low power consumption hot start method for a multi-core system and the multi-core system. Background Art

[0002] The rapid development of mobile communications, the Internet of Things (IoT), and portable electronic devices has placed extremely high demands on device battery life. Therefore, effectively reducing power consumption has become a core research topic in this field. Embedded systems, particularly peripheral functional chips (such as wireless connectivity chips (WCNs) and modems), implement a functional module and typically do not operate continuously within the device. Instead, they are activated only when the host computer requires their services. Managing power consumption during idle periods when there is no service demand is key to achieving overall low power consumption.

[0003] In existing technologies, low-power management for these functional modules typically involves completely shutting off their power supply when there's no service demand. This approach reduces the module's static power consumption to zero, offering the most comprehensive approach to achieving the lowest power consumption. However, a significant drawback is that a complete cold boot process must be performed when the host needs to reactivate the module. This process is time-consuming, significantly increasing system response latency and making it unsuitable for applications requiring high real-time performance. Summary of the Invention

[0004] The purpose of the present invention is to provide a low-power control method for a multi-core system, so that the functional modules can enter a low-power standby state when idle and achieve rapid hot start when receiving a wake-up command, thereby taking into account both low power consumption and high response speed.

[0005] In a first aspect, an embodiment of the present invention provides a low-power hot start method for a multi-core system, wherein the multi-core system is connected to a host, the multi-core system includes multiple processing cores, each processing core is configured to implement a functional module, and the method includes: When any target functional module among the multiple functional modules needs to enter a low-power state, controlling a first random access memory area corresponding to the target functional module to enter a low-power data retention state, controlling a second random access memory area corresponding to the target functional module to be powered off, and controlling a target processing core implementing the target functional module to enter a dormant state; wherein the first random access memory area is used to store a secondary boot program and a communication interface maintenance program, and the capacity of the first random access memory area is smaller than the capacity of the second random access memory area; When receiving a startup instruction, running the secondary boot program in the first random access memory area, and having the secondary boot program call the communication interface maintenance program to establish a communication connection with the host; Downloading the service firmware of the target functional module to the second random storage area through the secondary boot program; Run the service firmware in the second random storage area to restore the operation of the target functional module.

[0006] Optionally, the first random storage area and the second random storage area are logical areas divided in the same physical RAM of the target processing core; the second random storage area is used to store the main business firmware and data of the target functional module.

[0007] And for any functional module, the capacity of the first random storage area corresponding to the functional module is independently configured according to the communication interface type and / or wake-up delay requirement of the functional module.

[0008] Optionally, controlling the first random access storage area corresponding to the target functional module to enter a low-power data retention state includes: The first random storage area is controlled by a power management circuit to enter an ultra-low power data retention state, wherein, in the ultra-low power data retention state, the power supply voltage of the first random storage area is reduced to a data retention voltage that can maintain data without loss; and the first random storage area cannot respond to normal read and write access operations.

[0009] Optionally, the startup instruction is: A wake-up command sent by the host through the communication interface; Alternatively, the wake-up signal is triggered by an external interrupt signal, wherein the external interrupt signal includes an interrupt signal triggered by a general-purpose input / output pin level change, a real-time timer timeout, or sensor data reaching a threshold.

[0010] Optionally, the method further includes: Before the step of downloading the service firmware of the target functional module to the second random storage area through the secondary boot program, performing security verification on the service firmware of the target functional module through the secondary boot program to obtain a verification result; If the verification result is that the service firmware security verification passes, the step of downloading the service firmware of the target functional module to the second random storage area through the secondary boot program is executed.

[0011] Optionally, the target functional module is a wireless communication module, and the wireless communication module includes a Wi-Fi module and a Bluetooth module.

[0012] In a second aspect, an embodiment of the present invention provides a multi-core system connected to a host, including: a plurality of processing cores, each processing core being configured to implement a functional module; a power management circuit coupled to the plurality of processing cores; Wherein, the power management circuit is configured as follows: When any target functional module among the multiple functional modules needs to enter a low-power state, controlling a first random access memory area corresponding to the target functional module to enter a low-power data retention state, controlling a second random access memory area corresponding to the target functional module to be powered off, and controlling a target processing core implementing the target functional module to enter a dormant state; wherein the first random access memory area is used to store a secondary boot program and a communication interface maintenance program, and the capacity of the first random access memory area is smaller than the capacity of the second random access memory area; When receiving a startup instruction, running the secondary boot program in the first random access memory area, and having the secondary boot program call the communication interface maintenance program to establish a communication connection with the host; Downloading the service firmware of the target functional module to the second random storage area through the secondary boot program; Run the service firmware in the second random storage area to restore the operation of the target functional module.

[0013] Optionally, the first random storage area and the second random storage area are logical areas divided in the same physical RAM of the target processing core; the second random storage area is used to store the main business firmware and data of the target functional module.

[0014] And for any functional module, the capacity of the first random storage area corresponding to the functional module is independently configured according to the communication interface type and / or wake-up delay requirement of the functional module.

[0015] Optionally, controlling the first random access storage area corresponding to the target functional module to enter a low-power data retention state includes: The first random storage area is controlled by a power management circuit to enter an ultra-low power data retention state, wherein, in the ultra-low power data retention state, the power supply voltage of the first random storage area is reduced to a data retention voltage that can maintain data without loss; and the first random storage area cannot respond to normal read and write access operations.

[0016] Optionally, the startup instruction is: A wake-up command sent by the host through the communication interface; Alternatively, the wake-up signal is triggered by an external interrupt signal, wherein the external interrupt signal includes an interrupt signal triggered by a general-purpose input / output pin level change, a real-time timer timeout, or sensor data reaching a threshold.

[0017] Optionally, the method further includes: Before the step of downloading the service firmware of the target functional module to the second random storage area through the secondary boot program, performing security verification on the service firmware of the target functional module through the secondary boot program to obtain a verification result; If the verification result is that the service firmware security verification passes, the step of downloading the service firmware of the target functional module to the second random storage area through the secondary boot program is executed.

[0018] Optionally, the target functional module is a wireless communication module, and the wireless communication module includes a Wi-Fi module and a Bluetooth module.

[0019] In a third aspect, an embodiment of the present invention provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a multi-core system, enables the multi-core system to execute the method described in the first aspect.

[0020] In a fourth aspect, an embodiment of the present invention provides a computer program product, including a computer program, which implements the method described in the first aspect when executed by a multi-core system.

[0021] The technical solution provided by the embodiments of the present invention achieves both partial system state retention and partial power down through an innovative RAM partitioning design and refined power control. The ultimate technical effect is: standby power consumption approaches the ultra-low level of a "completely powered-off" solution, while startup speed approaches the instantaneous response capability of a "completely powered-on" solution, thus resolving the technical challenge of traditional solutions in achieving both low power consumption and fast startup. Furthermore, by completely powering down the second random access memory area, which occupies the majority of the memory, and placing the processing core into hibernation, the static leakage current and dynamic power consumption of these two major power sources are fundamentally eliminated. Meanwhile, only the extremely small first random access memory area is maintained in a nanoampere-level data retention state, minimizing the overall system standby power consumption. Furthermore, because the first random access memory area remains powered at all times, the secondary bootloader and communication interface maintenance program stored therein are immediately available. Upon system wakeup, the system can directly jump to execution without executing time-consuming processes such as ROM code initialization, communication interface enumeration, and basic driver loading, significantly shortening the recovery time from command reception to full readiness.

[0022] Furthermore, the rapid responsiveness brought by fast hot boot significantly reduces the user-perceived delay in function activation. Furthermore, frequent switching between active and sleep states without incurring significant power consumption overhead provides greater flexibility in system design and contributes to improved overall energy efficiency.

[0023] Furthermore, compared to solutions using two independent physical RAMs, the present invention prioritizes partition management through logical partitioning, eliminating the need for additional physical memory resources, saving chip area and reducing manufacturing costs. Furthermore, the secondary bootloader verifies the downloaded service firmware, ensuring its integrity and reliability. This avoids multi-core system startup failures or security risks caused by firmware errors or tampering, ensuring the reliability and security of the multi-core system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A flowchart of a low-power hot start method for a multi-core system provided by an embodiment of the present invention; Figure 2 A block diagram of a system architecture provided by an embodiment of the present invention; Figure 3 A schematic diagram of the overall technical solution of an embodiment of the present invention; Figure 4 Schematic diagram of the structure of a multi-core system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be described in detail below through examples.

[0026] The rapid development of mobile communications, the Internet of Things (IoT), and portable electronic devices has placed extremely high demands on device battery life. Therefore, effectively reducing power consumption has become a core research topic in this field. Embedded systems, particularly peripheral functional chips (such as wireless connectivity chips (WCNs) and modems), implement a functional module and typically do not operate continuously within the device. Instead, they are activated only when the host computer requires their services. Managing power consumption during idle periods when there is no service demand is key to achieving overall low power consumption.

[0027] In existing technologies, low-power management for these functional modules typically involves completely shutting off their power supply when there's no service demand. This approach reduces the module's static power consumption to zero, offering the most comprehensive approach to achieving the lowest power consumption. However, a significant drawback is that a complete cold boot process must be performed when the host needs to reactivate the module. This process is time-consuming, significantly increasing system response latency and making it unsuitable for applications requiring high real-time performance.

[0028] In order to solve the above technical problems in the prior art, embodiments of the present invention provide a low-power hot start method and device for a multi-core system, and a multi-core system.

[0029] The key of the embodiment of the present invention is that, when there is no business, some functional modules can be partially powered off, while maintaining very low power consumption to complete fast multi-core system startup.

[0030] In order to describe the solution clearly, before introducing the embodiments of the present invention, the technical terms involved in the embodiments of the present invention are first explained.

[0031] 1. A multi-core system refers to a system that contains multiple CPU cores. For example, the current wireless connection chip WCN system contains multiple cortex m33 cores.

[0032] 2. USB communication, whose full English name is Universal Serial Bus, is a serial bus standard and also a technical specification of input and output interface.

[0033] 3. RAM (Random Access Memory) is a type of memory used to store temporary data, allowing random reading and writing of data. Data in RAM is lost when power is removed.

[0034] 4. RAM retention means that the data in certain RAM areas can be retained and not initialized after a software reset. This feature is very useful in embedded systems, especially when critical data or status information needs to be saved.

[0035] 5. Firmware is the program running on chips and other devices.

[0036] After introducing the above technical terms, a low-power hot start method for a multi-core system and a multi-core system provided by an embodiment of the present invention will be described in detail below.

[0037] An embodiment of the present invention provides a low-power hot start method for a multi-core system. The multi-core system is connected to a host (HOST). The multi-core system includes multiple processing cores (also referred to as CPU cores). Each processing core is configured to implement a functional module, wherein the functional module can be a wireless communication module, which mainly includes a Wi-Fi module and a Bluetooth module.

[0038] like Figure 1 As shown, the method may include the following steps: S110, when any target functional module among multiple functional modules needs to enter a low power consumption state, the first random storage area corresponding to the target functional module is controlled to enter a low power consumption data retention state, the second random storage area corresponding to the target functional module is controlled to be powered off, and the target processing core implementing the target functional module is controlled to enter a sleep state.

[0039] The first random storage area is used for storing a secondary boot program and a communication interface maintenance program, and the capacity of the first random storage area is less than the capacity of the second random storage area.

[0040] As an implementation manner of the embodiment, the first random storage area and the second random storage area can be two logical areas divided by a memory controller in a same physical RAM of a target processing core, or the first random storage area and the second random storage area can be two independent physical RAMs. The capacity of the first random storage area is much less than the capacity of the second random storage area, and the capacity of the first random storage area can be pre-configured according to the communication interface type and the wake-up delay requirement of the target function module, and only needs to store the most basic boot and communication programs, thereby minimizing the area of the normal power supply area and reducing the overall power consumption. The capacity of the first random storage area is not specifically limited in the embodiment, and can be determined according to actual conditions.

[0041] For example, for the communication interface type, the capacity of the first random storage area required by a function module for processing a gigabit Ethernet is usually greater than the capacity of the first random storage area required by a function module for processing a low-speed serial port.

[0042] For the wake-up delay requirement, a function module with extremely high real-time requirement (such as voice wake-up) usually needs a slightly larger capacity of the first random storage area to save more context states, so as to realize instant recovery; and a function module not sensitive to delay can use a very small first random storage area to save area and power consumption.

[0043] The above examples are for illustrating that the capacity of the first random storage area can be determined according to actual conditions for different function modules, but for the same function module, the capacity of the first random storage area is much less than the capacity of the second random storage area.

[0044] Specifically, when any target function module (for example, a Wi-Fi module or a Bluetooth module) in the multi-core system completes current service processing, in order to save power consumption, the target function module needs to enter a low-power consumption state, at this time, the power management circuit of the multi-core system can receive a sleep instruction sent by a host (HOST), and perform corresponding control on the first random storage area, the second random storage area, and a target processing core for implementing the target function module. The control operations of the first random storage area, the second random storage area, and the target processing core will be introduced in detail below.

[0045] First, the first random storage area is controlled to enter an ultra-low power consumption data retention state by the power management circuit, wherein in the ultra-low power consumption data retention state, the power supply voltage of the first random storage area is reduced to a data retention voltage capable of maintaining data without loss; and the first random storage area cannot respond to normal read-write access operations.

[0046] Specifically, the process of controlling the first random storage area to enter the low-power consumption data retention state can be that a voltage regulator inside the power management circuit reduces the voltage supplied to the first random storage area to a data retention voltage capable of maintaining internal data without loss, while cutting off the clock signal. At this time, the first random storage area cannot respond to any external read-write access operations, but the key data such as the secondary boot program and the communication interface maintenance program stored therein are completely retained, thereby laying a foundation for subsequent fast hot start.

[0047] Second, the specific process of controlling the second random storage area corresponding to the target function module to be powered off can be that the power management circuit controls the second random storage area corresponding to the target function module to be completely powered off. Thus, all static power consumption and dynamic power consumption of the second random storage area can be eliminated, which is a key step to achieve ultra-low standby power consumption. Moreover, since the second random storage area is mainly used to store the main business firmware and runtime data of the target function module, these data do not need to be maintained after entering the low-power consumption state, and thus the power-off operation of the second random storage area will not affect the functional integrity of the multi-core system. When the power supply is cut off, all data in the second random storage area are lost.

[0048] Third, the process of controlling the target processing core implementing the target function module to enter a sleep state can be that the power management circuit cuts off the clock signal input to the target processing core by clock gating technology, and can reduce the power supply voltage thereof by power gating technology. Thus, the dynamic power consumption and static power consumption of the target processing core can be significantly reduced, so that it is in a non-active state that can be quickly awakened.

[0049] It should be noted that the control operations of the first random storage area, the second random storage area and the target processing core do not have a strict sequence, and can be executed in parallel or in any order by the power management circuit. The purpose is to make the target function module as a whole enter a standby state with extremely low power consumption but fast recovery.

[0050] S120, in the case where the start instruction is received, running the secondary boot program in the first random storage area, and calling the communication interface maintenance program by the secondary boot program to establish a communication connection with the host.

[0051] Specifically, when a multi-core system needs to recover from a low-power state, upon receiving a startup instruction, a hot boot process is triggered for the target functional module. This startup instruction can be a specific wake-up command proactively sent by the host via a communication interface (such as USB), or a wake-up signal triggered by an external interrupt signal (such as a GPIO level change, sensor trigger, or timer timeout). This embodiment of the present invention does not specifically limit the source of the startup instruction.

[0052] Once the power management circuitry of a multi-core system detects a start instruction, it performs the following operations: First, the power supply and boot environment are restored. Specifically, the power management circuit restores the normal operating voltage of the first random access memory area, causing it to exit the low-power data retention state. Simultaneously, the sleep control of the target processing core is released, providing it with a clock signal, waking it from sleep and preparing it to execute instructions.

[0053] Next, it jumps to the secondary bootloader. After the target processing core wakes up, its program counter is directed by hardware or firmware logic to a specific address in the first random access memory area, and begins executing the secondary bootloader stored in the first random access memory area. This process completely skips the primary bootloader code stored in ROM that must be executed when the multi-core system is powered on, thus saving a significant amount of initialization time.

[0054] Again, the secondary bootloader acts as the overall coordinator of the hot boot process and performs the following key tasks in sequence: The first key task is to perform minimal hardware initialization. Specifically, the second-level bootloader first executes a lightweight initialization code that configures the target processing core's basic working environment (for example, initializing the stack pointer and disabling interrupts). This process takes very little time.

[0055] The second key task is to call and run the communication interface maintenance program. Specifically, the secondary boot program searches, calls and jumps to the communication interface maintenance program that is also stored in the first random storage area. The communication interface maintenance program is a dedicated code optimized for low-power wake-up scenarios. It is configured to initialize the interface controller (such as a USB device controller) required to communicate with the host and execute the necessary protocol processes required to re-establish a complete communication link with the host. For example, if the communication interface is USB, a fast USB device enumeration process is performed to restore the high-speed data transmission channel with the host.

[0056] Once the communication interface maintenance program is successfully completed, a stable and reliable communication connection is established between the multi-core system and the host, preparing for the subsequent download of business firmware.

[0057] At this point, the most time-consuming phase of the warm boot process, reestablishing the communication link, has been completed. Because the secondary bootloader and communication interface maintenance program are both permanently resident in the first random access memory area and their states are preserved, the system does not need to reload them from slow non-volatile memory (such as Flash) or perform a complete hardware initialization, thus achieving extremely fast recovery from a low-power state to a communication-ready state.

[0058] S130 , downloading the service firmware of the target functional module to the second random storage area through the secondary boot program.

[0059] Specifically, after the secondary bootloader successfully invokes the communication interface maintenance program and establishes a stable communication connection with the host, the multi-core system enters the service firmware loading phase. The core of this step is to efficiently and reliably load the complete service function firmware into the de-energized secondary random access memory area via the restored high-speed communication channel and resume its execution.

[0060] The specific process may include the following steps: The first step is to initiate a firmware transfer request. Specifically, the secondary bootloader sends a request message to the host via an established communication interface. This request message requests the latest service firmware image for the target functional module. This request message may include information such as the identifier of the target functional module and the required firmware version number to ensure that the host sends the correct firmware package.

[0061] The second step is to receive and verify the firmware data. Specifically, after receiving the request message, the host retrieves the corresponding service firmware data from its own storage system and transmits the firmware data stream to the multi-core system at high speed through a communication interface (such as USB bulk transfer or PCIe memory write operation). The secondary boot program can open a temporary buffer in the first random storage area to receive these data packets and can perform the following operations: As an implementation of the embodiment of the present invention, before the step of downloading the service firmware of the target functional module to the second random storage area through the secondary boot program, the service firmware of the target functional module is security verified by the secondary boot program to obtain a verification result; If the verification result is that the service firmware security verification passes, the step of downloading the service firmware of the target functional module to the second random storage area through the secondary boot program is executed.

[0062] Specifically, the cyclic redundancy check code (CRC) of the received data can be calculated or its digital signature can be verified to ensure that no errors or tampering occurred in the firmware during transmission, thereby achieving security verification of the business firmware.

[0063] As another implementation manner of the embodiment of the present application, the service firmware can also be re-sequenced. Specifically, if the data transmission adopts a packet mechanism, the secondary boot program is responsible for sequencing and re-sequencing the data packets to reconstruct the complete firmware image.

[0064] In the third step, the firmware data obtained in the second step is written into the second random storage area. Specifically, after the firmware data is verified to be correct, the secondary boot program controls the reconstructed complete service firmware image to be written into the predetermined address of the second random storage area which has been restored to normal power supply. During this period, the power management circuit has restored the normal power supply for the second random storage area in advance in response to the instruction of the secondary boot program or according to the preset timing. The process of writing the firmware data obtained in the second step into the second random storage area can be block-by-block writing or direct DMA transmission to achieve the highest efficiency.

[0065] In the S140, the service firmware in the second random storage area is run to restore the operation of the target function module.

[0066] Specifically, when the entire service firmware is successfully downloaded and written into the second random storage area, the secondary boot program executes the final jump instruction to jump the program execution flow from itself (located in the first random storage area) to the entry address of the service firmware in the second random storage area. At this time, the target processing core starts to execute the main service code of the target function module, and the function of the target function module is completely restored to normally respond to the service instruction of the host.

[0067] The low-power hot start method provided by the embodiment of the present application has the following significant differences and advantages compared with the cold start flow of the prior art: the secondary boot program and the communication interface maintenance program which are already resident in the first storage area do not need to be re-downloaded, and only the volatile service firmware needs to be downloaded, which greatly reduces the data transmission amount and shortens the recovery time.

[0068] The technical solution provided by the embodiments of the present invention achieves both partial system state retention and partial power down through an innovative RAM partitioning design and refined power control. The ultimate technical effect is: standby power consumption approaches the ultra-low level of a "completely powered-off" solution, while startup speed approaches the instantaneous response capability of a "completely powered-on" solution, thus resolving the technical challenge of traditional solutions in achieving both low power consumption and fast startup. Furthermore, by completely powering down the second random access memory area, which occupies the majority of the memory, and placing the processing core into hibernation, the static leakage current and dynamic power consumption of these two major power sources are fundamentally eliminated. Meanwhile, only the extremely small first random access memory area is maintained in a nanoampere-level data retention state, minimizing the overall system standby power consumption. Furthermore, because the first random access memory area remains powered at all times, the secondary bootloader and communication interface maintenance program stored therein are immediately available. Upon system wakeup, the system can directly jump to execution without executing time-consuming processes such as ROM code initialization, communication interface enumeration, and basic driver loading, significantly shortening the recovery time from command reception to full readiness.

[0069] Furthermore, the rapid responsiveness brought by fast hot boot significantly reduces the user-perceived delay in function activation. Furthermore, frequent switching between active and sleep states without incurring significant power consumption overhead provides greater flexibility in system design and contributes to improved overall energy efficiency.

[0070] Furthermore, compared to solutions using two independent physical RAMs, the present invention prioritizes partition management through logical partitioning, eliminating the need for additional physical memory resources, saving chip area and reducing manufacturing costs. Furthermore, the secondary bootloader verifies the downloaded service firmware, ensuring its integrity and reliability. This avoids multi-core system startup failures or security risks caused by firmware errors or tampering, ensuring the reliability and security of the multi-core system.

[0071] After a detailed introduction to the low-power hot start method for a multi-core system provided by an embodiment of the present invention, the system architecture of the embodiment of the present invention will be described below with reference to specific examples. Figure 2 As shown in FIG, it is a block diagram of the entire multi-core system. The multi-core system may include multiple CPU cores, such as Figure 2 Core 1, core 2, ..., core n, each core is configured to implement a functional module (corresponding to Figure 2 Each core has corresponding ROM (read-only memory) and RAM resources, such as service 1, service 2, ..., service n. Alternatively, some cores may not have ROM resources, but each core has RAM resources. The RAM capacity of each core can be determined based on service requirements.

[0072] In the prior art, each core corresponds to a RAM resource. The present invention divides RAM resources into two parts, which can be referred to as RAM0 (the second random access memory area described in the above embodiment) and RAM1 (the first random access memory area described in the above embodiment). RAM1 has a relatively small capacity and is only needed to maintain interface communication (wherein the communication interface controller refers to the digital logic unit responsible for protocol processing and data scheduling, and is a chip-level component. The communication interface PHY is the physical layer chip responsible for signal conversion and electrical connections, and is a board-level component. The two work together but are at different levels), secondary boot, and other minor system overhead, such as USB enumeration and related event processing, as well as implementing service boot functions. RAM0, on the other hand, has a larger capacity and is used to meet the service requirements itself. In this embodiment, RAM0 and RAM1 can be controlled independently. That is, in a low-power state, RAM1 can be controlled to enter a low-power data retention state, while RAM0 can be powered off. The specific control process has been detailed in the above embodiment and will not be repeated here.

[0073] The overall technical solution of the embodiment of the present invention will be further described in detail below with reference to examples.

[0074] like Figure 3 As shown, this embodiment divides the storage space into 6 parts as shown in the figure. Among them, area ① is the ROM code (ROMCODE) of service 1, and areas ② and ③ correspond to Figure 2 The RAM1 area in the embodiment shown is the RAM0 area. The specific size of the RAM1 area can be flexibly configured according to actual application requirements. Its main function is to maintain the system communication interface and implement the secondary boot function. It is worth noting that the capacity of RAM1 is much smaller than the total amount of RAM required to run the complete business functions. Figure 3 Business 1, Business 2 and Business 3 in Figure 2 has the same meaning as in and can be a functional module.

[0075] The workflow of a multi-core system is as follows: A. The processing core of Service 1 first executes its ROM code to complete initialization. This ROM code includes basic system bootstrap functionality, enabling the multi-core system to be correctly identified after establishing communication with the host and receiving firmware downloads through the communication interface. It should be noted that a single copy of the ROM code can exist throughout the entire multi-core system, eliminating the need for separate configuration for each processing core.

[0076] The main function of the B.ROM code is to download the firmware to the RAM1 area. After the download is complete, the system switches to running the code in RAM1, which ensures that the system can maintain normal communication with external devices. The RAM1 mentioned here can be the RAM1 area corresponding to any processing core in the system.

[0077] C. When at least one service in the system is in operation, if any of the services enters idle state and needs to switch to low-power state, the RAM1 area corresponding to the service will enter the data retention state, the corresponding processing core will suspend execution, the RAM0 area will be powered off, and the entire system will enter low-power standby mode, waiting to resume operation quickly after the next wake-up.

[0078] D. If all services in the system enter a stopped state, all processing cores switch to their corresponding RAM1s for operation. Subsequently, all RAM0 areas are powered off, and all processing cores enter a dormant state. All RAM1 areas enter a data retention state. At this point, the system maintains operation with minimal RAM1 resource consumption, awaiting a service wake-up signal to trigger a fast hot boot. The specific hot boot process has been detailed in the previous embodiments and will not be repeated here.

[0079] The embodiment of the present invention further provides a multi-core system 40 connected to a host 41, such as Figure 4 Shown, including: Multiple processing cores 401, namely processing core 1, processing core 2, ..., processing core n, each processing core is configured to implement a functional module; a power management circuit 402 coupled to the plurality of processing cores; Wherein, the power management circuit is configured as follows: When any target functional module among the multiple functional modules needs to enter a low-power state, controlling a first random access memory area corresponding to the target functional module to enter a low-power data retention state, controlling a second random access memory area corresponding to the target functional module to be powered off, and controlling a target processing core implementing the target functional module to enter a dormant state; wherein the first random access memory area is used to store a secondary boot program and a communication interface maintenance program, and the capacity of the first random access memory area is smaller than the capacity of the second random access memory area; When receiving a startup instruction, running the secondary boot program in the first random access memory area, and having the secondary boot program call the communication interface maintenance program to establish a communication connection with the host; Downloading the service firmware of the target functional module to the second random storage area through the secondary boot program; Run the service firmware in the second random storage area to restore the operation of the target functional module.

[0080] Optionally, the first random storage area and the second random storage area are logical areas divided in the same physical RAM of the target processing core; the second random storage area is used to store the main business firmware and data of the target functional module.

[0081] And for any functional module, the capacity of the first random storage area corresponding to the functional module is independently configured according to the communication interface type and / or wake-up delay requirement of the functional module.

[0082] Optionally, controlling the first random access storage area corresponding to the target functional module to enter a low-power data retention state includes: The first random storage area is controlled by a power management circuit to enter an ultra-low power data retention state, wherein, in the ultra-low power data retention state, the power supply voltage of the first random storage area is reduced to a data retention voltage that can maintain data without loss; and the first random storage area cannot respond to normal read and write access operations.

[0083] Optionally, the startup instruction is: A wake-up command sent by the host through the communication interface; Alternatively, the wake-up signal is triggered by an external interrupt signal, wherein the external interrupt signal includes an interrupt signal triggered by a general input / output pin level change, a real-time timer timeout, or sensor data reaching a threshold.

[0084] Optionally, the method further includes: Before the step of downloading the service firmware of the target functional module to the second random storage area through the secondary boot program, performing security verification on the service firmware of the target functional module through the secondary boot program to obtain a verification result; If the verification result is that the service firmware security verification passes, the step of downloading the service firmware of the target functional module to the second random storage area through the secondary boot program is executed.

[0085] Optionally, the target functional module is a wireless communication module, and the wireless communication module includes a Wi-Fi module and a Bluetooth module.

[0086] An embodiment of the present invention further provides a computer-readable storage medium. When instructions in the computer-readable storage medium are executed by a multi-core system, the multi-core system is enabled to execute the method described in the first aspect.

[0087] An embodiment of the present invention further provides a computer program product, including a computer program, which implements the method described in the first aspect when executed by a multi-core system.

[0088] The technical solution provided by the embodiments of the present invention achieves both partial system state retention and partial power down through an innovative RAM partitioning design and refined power control. The ultimate technical effect is: standby power consumption approaches the ultra-low level of a "completely powered-off" solution, while startup speed approaches the instantaneous response capability of a "completely powered-on" solution, thus resolving the technical challenge of traditional solutions in achieving both low power consumption and fast startup. Furthermore, by completely powering down the second random access memory area, which occupies the majority of the memory, and placing the processing core into hibernation, the static leakage current and dynamic power consumption of these two major power sources are fundamentally eliminated. Meanwhile, only the extremely small first random access memory area is maintained in a nanoampere-level data retention state, minimizing the overall system standby power consumption. Furthermore, because the first random access memory area remains powered at all times, the secondary bootloader and communication interface maintenance program stored therein are immediately available. Upon system wakeup, the system can directly jump to execution without executing time-consuming processes such as ROM code initialization, communication interface enumeration, and basic driver loading, significantly shortening the recovery time from command reception to full readiness.

[0089] Furthermore, the rapid responsiveness brought by fast hot boot significantly reduces the user-perceived delay in function activation. Furthermore, frequent switching between active and sleep states without incurring significant power consumption overhead provides greater flexibility in system design and contributes to improved overall energy efficiency.

[0090] Furthermore, compared to solutions using two independent physical RAMs, the present invention prioritizes partition management through logical partitioning, eliminating the need for additional physical memory resources, saving chip area and reducing manufacturing costs. Furthermore, the secondary bootloader verifies the downloaded service firmware, ensuring its integrity and reliability. This avoids multi-core system startup failures or security risks caused by firmware errors or tampering, ensuring the reliability and security of the multi-core system.

[0091] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention without departing from the principles and purpose of the present invention.

Claims

1. A low-power hot start method for a multi-core system, characterized in that: The multi-core system is connected to a host, the multi-core system includes multiple processing cores, each processing core is configured to implement a functional module, and the method includes: When any target functional module among the multiple functional modules needs to enter a low-power state, controlling a first random access memory area corresponding to the target functional module to enter a low-power data retention state, controlling a second random access memory area corresponding to the target functional module to be powered off, and controlling a target processing core implementing the target functional module to enter a dormant state; wherein the first random access memory area is used to store a secondary boot program and a communication interface maintenance program, and the capacity of the first random access memory area is smaller than the capacity of the second random access memory area; When receiving a startup instruction, running the secondary boot program in the first random access memory area, and having the secondary boot program call the communication interface maintenance program to establish a communication connection with the host; Downloading the service firmware of the target functional module to the second random storage area through the secondary boot program; Run the service firmware in the second random storage area to restore the operation of the target functional module.

2. The method according to claim 1, characterized in that The first random access memory area and the second random access memory area are logical areas divided in the same physical RAM of the target processing core; the second random access memory area is used to store the main business firmware and data of the target functional module; And for any functional module, the capacity of the first random storage area corresponding to the functional module is independently configured according to the communication interface type and / or wake-up delay requirement of the functional module.

3. The method according to claim 1, characterized in that The controlling the first random access storage area corresponding to the target functional module to enter a low-power data retention state includes: The first random storage area is controlled by a power management circuit to enter an ultra-low power data retention state, wherein, in the ultra-low power data retention state, the power supply voltage of the first random storage area is reduced to a data retention voltage that can maintain data without loss; and the first random storage area cannot respond to normal read and write access operations.

4. The method according to claim 1, wherein The startup instruction is: A wake-up command sent by the host through the communication interface; Alternatively, the wake-up signal is triggered by an external interrupt signal, wherein the external interrupt signal includes an interrupt signal triggered by a general-purpose input / output pin level change, a real-time timer timeout, or sensor data reaching a threshold.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: Before the step of downloading the service firmware of the target functional module to the second random storage area through the secondary boot program, performing security verification on the service firmware of the target functional module through the secondary boot program to obtain a verification result; If the verification result is that the service firmware security verification passes, the step of downloading the service firmware of the target functional module to the second random storage area through the secondary boot program is executed.

6. The method according to any one of claims 1 to 4, characterized in that The target functional module is a wireless communication module, which includes a Wi-Fi module and a Bluetooth module.

7. A multi-core system connected to a host, characterized in that: include: a plurality of processing cores, each processing core being configured to implement a functional module; a power management circuit coupled to the plurality of processing cores; Wherein, the power management circuit is configured as follows: When any target functional module among the multiple functional modules needs to enter a low-power state, controlling a first random access memory area corresponding to the target functional module to enter a low-power data retention state, controlling a second random access memory area corresponding to the target functional module to be powered off, and controlling a target processing core implementing the target functional module to enter a dormant state; wherein the first random access memory area is used to store a secondary boot program and a communication interface maintenance program, and the capacity of the first random access memory area is smaller than the capacity of the second random access memory area; When receiving a startup instruction, running the secondary boot program in the first random access memory area, and having the secondary boot program call the communication interface maintenance program to establish a communication connection with the host; Downloading the service firmware of the target functional module to the second random storage area through the secondary boot program; Run the service firmware in the second random storage area to restore the operation of the target functional module.

8. The system according to claim 7, characterized in that The first random access memory area and the second random access memory area are logical areas divided in the same physical RAM of the target processing core; the second random access memory area is used to store the main business firmware and data of the target functional module; And for any functional module, the capacity of the first random storage area corresponding to the functional module is independently configured according to the communication interface type and / or wake-up delay requirement of the functional module.

9. A computer-readable storage medium, characterized in that When the instructions in the computer-readable storage medium are executed by a multi-core system, the multi-core system is enabled to execute the method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises a computer program, which implements the method according to any one of claims 1 to 6 when executed by a multi-core system.

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