A storage device and a data processing method thereof

Abstract

The application provides a storage device and a data processing method thereof. The storage device comprises: a buffer for buffering multiple frames of original data transmitted by a host in succession, each frame of original data comprising valid data, and all the frames of original data comprising an authentication code; a central processing module for sending control instructions to a hardware acceleration module in sequence according to a buffering order when the buffer exceeds a preset number of frames of original data, and sending an end instruction to the hardware acceleration module when the buffer buffers the last frame of original data transmitted by the host; and the hardware acceleration module for responding to each control instruction to sequentially calculate the valid data in each frame of original data in the buffer, and for responding to the end instruction to generate a check code of all the frames of original data based on the calculation results of the valid data in all the frames of original data. The application improves the calculation efficiency of the hardware acceleration module, thereby enhancing the use performance of the storage device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of static storage, in particular to a storage device and a data processing method thereof. BACKGROUND

[0002] In a non-volatile storage device, a replay protected memory block (RPMB) is used to store data that needs to be protected. For the existing RPMB protocol, the HMAC (Hash-based Message Authentication Code) algorithm under the RPMB protocol needs to be implemented through hardware acceleration.

[0003] In the prior art, when multiple frames of original data are written under the RPMB protocol, the HMAC calculation is started only after the multiple frames of original data are all transmitted to the cache, thereby consuming a large amount of time. Therefore, there is room for improvement. SUMMARY

[0004] The present application provides a storage device and a data processing method thereof, to solve the technical problem that the hardware acceleration module is always idle in the process of writing multiple frames of data into a replay protected memory block in the prior art.

[0005] The present application provides a storage device, comprising:

[0006] a buffer, configured to cache multiple frames of original data transmitted by a host in succession, each frame of the original data comprising valid data, and all frames of the original data comprising an authentication code;

[0007] a central processing module, configured to send control instructions to a hardware acceleration module in sequence according to a caching order when the buffer caches original data of a preset number of frames, and send an end instruction to the hardware acceleration module when the buffer caches the last frame of original data transmitted by the host;

[0008] the hardware acceleration module, configured to respond to each control instruction to calculate the valid data in each frame of original data in the buffer in sequence, and further configured to generate a check code of all frames of original data based on the calculation results of the valid data in all frames of original data in response to the end instruction;

[0009] the central processing module is further configured to compare the check code with the authentication code, and complete authentication verification of all frames of original data transmitted by the host in succession based on a comparison result.

[0010] In one embodiment of the present application, the central processing module is further configured to monitor the working state of the hardware acceleration module in real time, and send a control instruction to the hardware acceleration module when the hardware acceleration module is in an idle state.

[0011] In one embodiment of the present application, the hardware acceleration module is further configured to divide the valid data in each frame of raw data into a plurality of block data of the same size, and perform the following processing on the block data in each frame of raw data:

[0012] sequentially read a plurality of block data of a frame of raw data from the buffer, and perform calculation on the previous block data while reading the current block data.

[0013] In one embodiment of the present application, a read storage area is provided in the hardware acceleration module, and the hardware acceleration module is further configured to read the block data from the buffer and cache it into the read storage area.

[0014] In one embodiment of the present application, the hardware acceleration module is further configured to perform the following processing on the block data of each frame of raw data:

[0015] parse the storage address of a frame of raw data in the control instruction, and obtain the storage address of one block data in the frame of raw data each time;

[0016] read the block data from the buffer according to the storage address of the block data obtained each time and cache it into the read storage area.

[0017] In one embodiment of the present application, the time from parsing the storage address in the control instruction to caching one block data into the read storage area of the hardware acceleration module is T1, and the time for the hardware acceleration module to call one block data from the read storage area is T2, which satisfy T1=3T2.

[0018] In one embodiment of the present application, the hardware acceleration module is further configured to perform a clearing process on the read storage area after reading the current block data from the read storage area, and cache the next block data in the buffer into the read storage area.

[0019] In one embodiment of the present application, the central processing module is further configured to count the number of frames corresponding to all frames of raw data, and generate error information of all frames of raw data when the counted number of frames is not the number of frames specified by the replay-protected block protocol.

[0020] In one embodiment of the present application, the central processing module is further configured to count the number of frames corresponding to all frames of raw data, and generate error information of all frames of raw data when the counted number of frames is not the number of frames specified by the replay-protected block protocol.

[0021] determining whether the check code is identical to the authentication code:

[0022] when the comparison result is that the check code is identical to the authentication code, sequentially writing all the frame original data into the replay protection storage area;

[0023] when the comparison result is that the check code is not identical to the authentication code, generating error information of all the frame original data.

[0024] The application further provides a data processing method of a storage device, comprising:

[0025] caching multiple frames of original data transmitted by a host in sequence, each frame of the original data comprising valid data, and all the frames of the original data comprising an authentication code;

[0026] when the cached original data exceeds a preset frame number, calculating the valid data in each frame of the original data according to the caching sequence, and generating a check code of all the frames of the original data based on the calculation result of the valid data in all the frames of the original data when the last frame of the original data transmitted by the host is cached;

[0027] comparing the check code with the authentication code, and completing authentication verification of all the frames of the original data transmitted by the host in sequence based on the comparison result.

[0028] The application has the following beneficial effects: the storage device and the data processing method thereof provided by the application cache multiple frames of original data transmitted by a host in sequence in a buffer area, and when the buffer area exceeds a preset frame number of original data, send control instructions to a hardware acceleration module in sequence according to the caching sequence. The hardware acceleration module calculates the valid data in each frame of the original data in the buffer area based on each control instruction. Since the hardware acceleration module starts to calculate the valid data in each frame of the original data in the buffer area when the buffer area exceeds the preset frame number of original data, and does not need to wait until all the frames of the original data are transmitted to the buffer area before starting to calculate, the calculation efficiency of the hardware acceleration module is directly improved, thereby enhancing the use performance of the storage device. BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles behind the application. It is apparent that the accompanying drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0030] In the drawings:

[0031] Figure 1 The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles behind the application. It is apparent that the accompanying drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0032] Figure 2 A schematic diagram of a frame of raw data provided in an embodiment of the present application.

[0033] Figure 3 A schematic diagram of the steps of a data processing method for a storage device provided in an embodiment of the present application.

[0034] Reference signs are as follows:

[0035] 10, host; 20, storage device; 30, main controller; 31, central processing module; 32, buffer; 33, hardware acceleration module; 40, flash memory; 41, playback protection storage area. DETAILED DESCRIPTION

[0036] The above embodiments of the present application are described with reference to specific examples. However, a person skilled in the art will readily understand that the above embodiments of the present application are merely illustrative and that other advantages and effects of the present application can be readily understood from the above description. The present application can be implemented or applied in other different embodiments, and the details in the above description can be modified or changed based on different views and applications without departing from the spirit of the present application. The above embodiments and features in the embodiments can be combined with each other in the case of no conflict.

[0037] It should be noted that the diagrams provided in the following embodiments merely schematically illustrate the basic concept of the present application, and the figures in the drawings only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation. The type, number and ratio of the components in actual implementation can be arbitrarily changed, and the layout type of the components can be more complex.

[0038] In the following description, a large number of details are discussed to provide a more thorough explanation of the embodiments of the present application. However, it is obvious to a person skilled in the art that the embodiments of the present application can be implemented without these specific details, and in other embodiments, the well-known structures and devices are shown in the form of block diagrams instead of details to avoid making the embodiments of the present application difficult to understand.

[0039] Please refer to Figures 1 to 3The application provides a storage device and a data processing method thereof, which can be applied to a storage device 20 such as an embedded multimedia card (EMMC), a solid state disk (SSD), a universal flash storage (UFS) and the like. When the raw data exceeding a preset frame number is buffered in a buffer area 32, the application can calculate the effective data in the raw data through a hardware acceleration module 33, so that the calculation efficiency of the hardware acceleration module 33 is improved, and the use performance of the storage device 20 is enhanced. The application is described in detail through specific embodiments.

[0040] Referring to Figure 1 In an embodiment of the application, a storage device 20 is provided, and the storage device 20 is provided with a bus interface. The storage device 20 is electrically connected with a host 10 through the bus interface. The host 10 can write raw data and send instructions to the storage device 20, or the host 10 can read the raw data and receive instructions from the storage device 20. The host 10 can be a personal computer (PC), a tablet computer (Pad), a mobile phone (Cell Phone) or the like.

[0041] Referring to Figure 1 The storage device 20 can include a main controller 30 and a flash memory 40. The flash memory 40 is a non-volatile memory, and is usually used to store raw data and system programs and the like. Inside the storage device 20, the main controller 30 is provided with a flash memory interface. The main controller 30 is electrically connected with the flash memory 40 through the flash memory interface. The main controller 30 is mainly used to operate and manage the flash memory 40. The main controller 30 is electrically connected with the flash memory 40. The main controller 30 can control many functions of the flash memory 40, and can greatly improve the read-write and moving operation performance of the raw data in the flash memory 40.

[0042] Referring to Figure 1 The main controller 30 can include a central processing module (CPU) 31, a buffer area 32 and a hardware acceleration module 33. The central processing module 31 is the operation core and control core of the storage device 20. The buffer area 32 is an internal memory directly exchanging data with the central processing module 31, and is also called a main memory (internal memory). In the storage device 20, the flash memory 40 is not a memory directly exchanging data with the central processing module 31, and thus the flash memory 40 is an auxiliary memory (external memory).

[0043] Specifically, the buffer area 32 can be used to buffer multiple frames of raw data transmitted by the host 10 successively. For example, the buffer area 32 can be used to buffer 16 frames of raw data.Figure 2 As shown, each frame of raw data can include padding data and valid data, and all frames of raw data can include an authentication code, which is calculated by the host 10 before transmission to the buffer 32. The data size of a frame of raw data is 512 bytes, of which only 284 bytes are valid data.

[0044] Specifically, the padding data is located in the high address region of a frame of data, specifically occupying the 511th byte to the 316th byte, a total of 196 bytes. The content of the padding data generally has no specific meaning in the protocol, and its value can be fixed (such as all 0s), random, or generated by a specific rule, but its core characteristic is not to participate in the calculation of the subsequent security verification algorithm (such as HMAC). Its role is similar to that of a placeholder, ensuring the integrity of the data frame structure and compatibility with the underlying storage hardware.

[0045] Specifically, the authentication code is located immediately after the padding data, from the 315th byte to the 284th byte, a total of 32 bytes. This part of data is the core of the security verification of all frames of data, and when performing a write operation, these 32 bytes are the HMAC value calculated by the host 10 side using the shared key on the valid data part of all frames of data for this transaction. After calculating its own verification code, the storage device 20 compares the verification code with the authentication code from the host 10, and if they are consistent, it proves that the data is legitimate and has not been tampered with.

[0046] Specifically, the valid data is located in the lowest address region of a frame of data, i.e., from the 283rd byte to the 0th byte, a total of 284 bytes. This is the user data or protocol command data that needs to be securely stored to or read from the replay protection storage area 41, and by performing HMAC (Hash-based Message Authentication Code) calculation on the valid data, the corresponding verification code can be obtained.

[0047] Specifically, the central processing module 31 can be configured to send control instructions to the hardware acceleration module 33 in sequence according to the cache order when the buffer 32 exceeds the preset number of frames of raw data, and send an end instruction to the hardware acceleration module 33 when the buffer 32 caches the last frame of raw data transmitted by the host 10. The central processing module 31 is also configured to monitor the working state of the hardware acceleration module 33 in real time, and send a control instruction to the hardware acceleration module 33 when the hardware acceleration module 33 is in an idle state.

[0048] Specifically, the hardware acceleration module 33 can be configured to respond to each control instruction to sequentially calculate the valid data in each frame of raw data in the buffer 32, and also configured to respond to the end instruction to generate a verification code for all frames of raw data based on the calculation results of the valid data in all frames of raw data.

[0049] Specifically, the central processing module 31 is further configured to compare the check code with the authentication code of all the frame original data, and based on the comparison result, complete the authentication check of all the frame original data transmitted by the host 10 successively.

[0050] Specifically, the judgment result of the check code and the authentication code of all the frame original data can include the following two cases.

[0051] When the comparison result is that the check code is the same as the authentication code of all the frame original data, that is, the check code corresponding to the valid data in all the frame original data is the same as the authentication code, it indicates that the data source of all the frame original data is legal and has not been tampered with, at this time, all the frame original data transmitted by the host 10 successively can be considered normal, and all the frame original data is written into the replay protection storage area 41 successively.

[0052] When the comparison result is that the check code is not the same as the authentication code of all the frame original data, it indicates that some of the frame original data of all the frame original data may be tampered with. Under the condition that there may be data security risks in some frame original data, at this time, all the frame original data transmitted by the host 10 successively can be considered abnormal, and error information of all the frame original data is generated.

[0053] For the above-mentioned central processing module 31, buffer area 32 and hardware acceleration module 33, the following processing process can be had.

[0054] First, the host 10 successively sends multiple frame original data, for example, 32 frame original data, and also successively stores the 32 frame original data one frame by one frame into the internal buffer area 32, while issuing an interrupt command (CMD, command) to notify the central processing module 31 that the frame original data is ready.

[0055] Second, the central processing module 31 configures the storage address of one frame original data on the buffer area 32, and issues a control instruction to require the hardware acceleration module 33 to read out the frame original data from the specified storage address, and calculate the valid data of the frame original data. When the hardware acceleration module 33 starts to calculate, the busy signal is set to 1 and the finish signal is set to 0, indicating that the hardware acceleration module 33 is currently starting to work, and when the hardware acceleration module 33 completes the calculation, the busy signal is set to 0 and the finish signal remains 0, indicating that the hardware acceleration module 33 is in a waiting state.

[0056] Meanwhile, the original data frames from the host 10 are continuously written into the internal buffer 32, and the central processing module 31 continuously reads the state of the busy signal of the hardware acceleration module 33. When the busy signal is read as 0, if one or more frames of original data are received again, the storage address corresponding to the one or more frames of original data is configured again, and a control instruction is issued. The hardware acceleration module 33 reads the one or more frames of original data based on the storage address, and calculates the valid data in the one or more frames of original data.

[0057] Then, when the last frame of the 32 frames of original data from the host 10 is stored in the internal buffer 32, the central processing module 31 configures the corresponding storage address for the last time, issues a control instruction and an end instruction, and the end instruction tells the hardware acceleration module 33 that this is the last time of calculation. After the hardware acceleration module 33 completes the calculation of the valid data in all frames of original data, the results of the calculation of the valid data corresponding to all frames of original data are retained, that is, the check codes corresponding to all frames of original data are retained, and the finish signal is set to 1, indicating that the calculation of the multiple frames of original data transmitted by the host 10 in succession has been completed.

[0058] The central processing module 31 can read the check codes corresponding to all frames of original data from the hardware acceleration module 33, and compare the check codes corresponding to all frames of original data with the authentication codes of all frames of original data.

[0059] Please refer to Figure 1 In an embodiment of the present application, the hardware acceleration module 33 is further configured to divide the valid data in each frame of original data into multiple block data of the same size, and perform the following processing on the block data in each frame of original data:

[0060] The multiple block data of one frame of original data are sequentially read from the buffer 32, and the last block data is calculated while the current block data is being read.

[0061] Specifically, since the hardware acceleration module 33 corresponding to the SHA256 algorithm is operated on a 512-bit message block, the valid data in each frame of original data can be processed in blocks of 512 bits, that is, the valid data in each frame of original data is divided into multiple block data of 512 bits.

[0062] And, in order to improve the processing efficiency of the hardware acceleration module 33 on the block data in each frame of raw data, a plurality of block data of a frame of raw data can be sequentially read from the buffer 32, and the previous block data is calculated while the current block data is read. When the current block data is read, the previous block data is also calculated, so that the reading of the current block data and the calculation of the previous block data are overlapped, thereby improving the processing efficiency of the hardware acceleration module 33.

[0063] Referring to Figure 1 In an embodiment of the present application, a read storage area is arranged in the hardware acceleration module 33, and the hardware acceleration module 33 is further configured to read the block data from the buffer 32 and cache it in the read storage area.

[0064] Specifically, a dedicated read storage area is integrated in the hardware acceleration module 33, which is composed of 16 32-bit registers with a total capacity of 512 bits, and is used to temporarily cache the block data read from the buffer 32. When the hardware acceleration module 33 is working, it will first read a complete block of data from the specified address of the buffer 32 and store it in the registers of the read storage area in order. Then, the hardware acceleration module 33 directly reads the fast data from this local read storage area for processing.

[0065] Referring to Figure 1 In an embodiment of the present application, the hardware acceleration module 33 is further configured to perform the following processing on the block data of each frame of raw data:

[0066] The storage address of a frame of raw data in the control instruction is parsed, and the storage address of a block data in the frame of raw data is obtained each time, and the block data is read from the buffer 32 and cached in the read storage area according to the storage address of the block data obtained each time.

[0067] Specifically, since the hardware acceleration module 33 reads the block data from the internal buffer 32, a block data is 512 bits, 16 double bytes (DW, Double Word), and uses AHB bus. Since the address of the read data is decreasing, it cannot use the address increment mode of AHB bus to save time. Therefore, it cannot use the address increment corresponding to one-time addressing and multiple transmission mode, but only can use the address decrement corresponding to multiple addressing and multiple transmission mode, that is, using multiple addressing and multiple transmission mode for 16 DW. The theoretical clock period of reading one DW is 1 clock period of address sending + 1 clock period of address analysis + 1 clock period of data return, which corresponds to three clock periods of time.

[0068] Specifically, in the theoretical clock cycle of reading one DW, the address sending can be understood as the hardware acceleration module 33 obtaining the storage address of one block data in the frame raw data each time, the address analysis can be understood as the hardware acceleration module 33 requesting the data transmission of the block data from the buffer 32 according to the storage address of one block data obtained each time, and the data return can be understood as the buffer 32 transmitting the block data to the hardware acceleration module 33.

[0069] Therefore, the time from the address analysis in the control instruction to the caching of one block data to the read storage area of the hardware acceleration module 33 is T1, and the time from the calling of one block data from the read storage area of the hardware acceleration module 33 is T2, and T1 = 3T2 is satisfied.

[0070] Specifically, the hardware acceleration module 33 only needs 1 clock cycle to call one block data from the read storage area, that is, T2 represents only 1 clock cycle, so that T1 = 3T2 is satisfied.

[0071] Specifically, the hardware acceleration module 33 is further configured to clear the read storage area after reading the current block data from the read storage area, and cache the next block data in the buffer 32 to the read storage area.

[0072] Please refer to Figure 1 In an embodiment of the present application, the host 10 successively sends 32 frames of raw data, for example, successively stores the 32 frames of raw data frame by frame into the internal buffer 32, and issues an interrupt command (CMD, command) to notify the central processing module 31 that the frame of raw data is ready.

[0073] Then, the central processing module 31 is further configured to count the frame number corresponding to all frames of raw data, and determine whether the counted frame number conforms to the frame number specified by the replay protected storage block protocol, and perform the following processing according to the determination result.

[0074] The central processing module 31 is further configured to generate error information of all frames of raw data when the counted frame number is not the frame number specified by the replay protected storage block protocol.

[0075] The central processing module 31 is further configured to determine the authentication code of all frames of raw data when the counted frame number is the frame number specified by the replay protected storage block protocol.

[0076] When the comparison result is that the authentication code of all frames of raw data is the same as the authentication code, all frames of raw data are successively written into the replay protected storage area 41.

[0077] When the comparison result is that the authentication code of all frames of raw data is not the same as the authentication code, error information of all frames of raw data is generated.

[0078] Referring to Figure 3 In one embodiment of the present application, a data processing method of a storage device can include the following steps.

[0079] Step S10, cache the multiple frames of raw data transmitted by the host one by one, each frame of the raw data includes valid data, and all frames of the raw data include an authentication code.

[0080] Step S20, when the cached raw data exceeds a preset frame number, calculate the valid data in each frame of raw data according to the cache order, and generate a check code of all frames of raw data based on the calculation results of the valid data in all frames of raw data when the last frame of raw data transmitted by the cache host.

[0081] Step S30, compare the check code with the authentication code, and complete the authentication check of all frames of raw data transmitted by the host one by one based on the comparison result.

[0082] Therefore, when the raw data buffered in the buffer area 32 exceeds the preset frame number, the hardware acceleration module 33 is used to calculate the valid data in the raw data, thereby improving the calculation efficiency of the hardware acceleration module 33 and enhancing the use performance of the storage device 20.

[0083] In summary, the present application provides a storage device and a data processing method thereof. The multiple frames of raw data transmitted by the host one by one are cached in the buffer area, and when the raw data buffered in the buffer area exceeds the preset frame number, control instructions are sent to the hardware acceleration module one by one according to the cache order. The hardware acceleration module calculates the valid data in each frame of raw data in the buffer area based on each control instruction. Since the hardware acceleration module starts to calculate the valid data in each frame of raw data in the buffer area when the raw data buffered in the buffer area exceeds the preset frame number, and does not need to wait until all frames of raw data are transmitted to the buffer area before starting to calculate, the calculation efficiency of the hardware acceleration module is directly improved, thereby enhancing the use performance of the storage device.

[0084] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A storage device, characterized in that, include: The buffer is used to cache multiple frames of raw data transmitted by the host in succession. Each frame of raw data includes valid data, and all frames of raw data include an authentication code. The central processing module is used to send control commands to the hardware acceleration module in sequence according to the caching order when the buffer exceeds the preset number of original data frames, and to send an end command to the hardware acceleration module when the buffer caches the last frame of original data transmitted by the host. The hardware acceleration module is used to respond to each of the control commands by sequentially calculating the valid data in each frame of raw data in the buffer; it is also used to respond to the end command by generating a checksum for all frames of raw data based on the calculation results of the valid data in all frames of raw data. The central processing module is also used to compare the verification code with the authentication code, and based on the comparison result, complete the authentication and verification of all frame raw data transmitted by the host in succession. The hardware acceleration module is also used to divide the effective data in each frame of raw data into multiple blocks of data of the same size, and to process the blocks of data in each frame of raw data as follows: read multiple blocks of data of a frame of raw data sequentially from the buffer, and calculate the previous block of data while reading the current block of data; The hardware acceleration module is also used to process the block data of each frame of raw data as follows: parse the storage address of a frame of raw data in the control instruction, and obtain the storage address of a block of data in the frame of raw data each time; according to the storage address of a block of data obtained each time, read the block of data from the buffer and cache it in the read storage area of ​​the hardware acceleration module.

2. The storage device according to claim 1, characterized in that, The central processing module is also used to monitor the working status of the hardware acceleration module in real time, and send control commands to the hardware acceleration module when the hardware acceleration module is idle.

3. The storage device according to claim 1, characterized in that, The hardware acceleration module is equipped with a read storage area, and the hardware acceleration module is also used to read block data from the buffer and cache it in the read storage area.

4. The storage device according to claim 1, characterized in that, The time from parsing the storage address in the control instruction to caching a block of data in the read storage area by the hardware acceleration module is T1, and the time from the hardware acceleration module to calling a block of data from the read storage area is T2, satisfying: T1=3T2.

5. The storage device according to claim 3, characterized in that, The hardware acceleration module is also used to clear the read storage area after reading the current block of data from the read storage area, and cache the next block of data in the buffer into the read storage area.

6. The storage device according to claim 1, characterized in that, The central processing module is also used to count the number of frames corresponding to all raw frame data. When the counted number of frames is not the number of frames specified by the replay protection storage block protocol, error information for all raw frame data is generated.

7. The storage device according to claim 1, characterized in that, The central processing module is also used to count the number of frames corresponding to all raw frame data. When the counted number of frames is the number of frames specified by the replay protection storage block protocol, Determine whether the verification code matches the authentication code: When the comparison result shows that the verification code is the same as the authentication code, all frame original data are successively written into the replay protection storage area; When the comparison result shows that the check code and the authentication code are different, error information is generated for all frame raw data.

8. A data processing method for a storage device, characterized in that, include: The cache host transmits multiple frames of raw data in succession. Each frame of raw data includes valid data, and all frames of raw data include an authentication code. When the cached raw data exceeds the preset number of frames, the valid data in each frame of raw data is calculated according to the cache order. When the last frame of raw data transmitted by the cache host is cached, a check code for all frames of raw data is generated based on the calculation results of the valid data in all frames of raw data. The verification code is compared with the authentication code, and based on the comparison result, the authentication and verification of all frame raw data transmitted by the host is completed. The steps for calculating the valid data within each frame of raw data include: The effective data within each frame of raw data is divided into multiple blocks of data of the same size, and the blocks of data within each frame of raw data are processed as follows: multiple blocks of data of a frame of raw data are read sequentially from the buffer, and the previous block of data is calculated while reading the current block of data; The block data of each frame of raw data is processed as follows: the storage address of a frame of raw data in the control instruction is parsed, and the storage address of a block of data in the frame of raw data is obtained each time; according to the storage address of a block of data obtained each time, the block of data is read from the buffer and cached in the read storage area of ​​the hardware acceleration module.

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