A general PMU structure supporting RISC-V instruction set

Abstract

The application discloses a general PMU structure supporting a RISC-V instruction set, belongs to the chip design technical field, and is arranged in the chip interior and comprises a PMU special register, an SRAM control module, an instruction fetching module, a RSICV instruction set decoding and executing module and a general register module; the PMU special register control module is used for controlling the starting address of the instruction fetching module and a decoding mode; the application supports the architecture of the PMU of the RSICV instruction set, can solve the problem that the ASIC circuit is not flexible, and compared with the chip core directly using the RISC-V, the architecture deletes unnecessary logic and functions, and the area and power consumption overhead are reduced to the maximum extent; and the PMU module of the structure can be reused in multiple different projects as an IP.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip design, and particularly relates to a general PMU structure supporting a RISC-V instruction set. BACKGROUND

[0002] At present, in the implementation process of a PMU (Power Management Unit) in a chip, a special ASIC design or a low-power Core (core) is mainly used to build a SOC (System on chip) system environment to perform chip power management. Both the above two implementation methods have limitations. For example, the special ASIC design can realize lower power consumption and area, but has the disadvantage of being not flexible, and the startup process is relatively fixed, and power management cannot be realized by software flexible configuration. The system built by the low-power Core (core) can flexibly configure the startup sequence of each module in the chip, but the area and power consumption are relatively large, and it cannot be used in a system with relatively strict power consumption requirements. SUMMARY

[0003] The purpose of the application is to provide a general PMU structure supporting a RISC-V instruction set. By using the structure, the flexibility of the PMU (Power Management Unit) can be maintained, the area increase and power consumption waste caused by the structure can be reduced as much as possible, and the problems in the background technology can be solved.

[0004] To achieve the above purpose, the application provides the following technical scheme: a general PMU structure supporting a RISC-V instruction set, which is configured in a chip and includes a PMU special register, an SRAM control module, an instruction fetching module, a RISC-V instruction set decoding and executing module, and a general register module.

[0005] The PMU special register control module is used to control the starting address and decoding mode of the instruction fetching module. The PMU special register control module is also used to trigger the wake-up source. When the wake-up source arrives, it will be converted into a corresponding starting signal to control the whole PMU to enter the power-on program.

[0006] The SRAM control module is used to transfer the reset content of the PMU special register module and the general register module to the SRAM in the SRAM control module when the chip is initially powered on, for the first startup of the PMU. After the transfer is completed, the registers of the PMU special register module and the general register module are released. When the chip startup is completed, the SRAM control module is used to store the corresponding instructions of the RISC-V instruction set. Before the chip is in the sleep state, the instructions required for wake-up are placed in the SRAM inside the SRAM control module. When the wake-up source arrives, the instruction fetching module will fetch the instructions from the specified address to enter the wake-up program.

[0007] The RSICV instruction set decoding execution module is used for decoding of the RSIC-V instruction set; meanwhile, corresponding operations are performed, including data fetching from the general register module and jump command fetching; for part of the jump commands, the pipeline will be flushed; after the corresponding operations are performed, if there is a corresponding instruction, the RSICV instruction set decoding execution module will perform input and output of the power management control signal;

[0008] The general register module sends reset values and default values to the SRAM control module when the chip is in an initial start stage; in a normal working stage of the chip, the general register module is used for buffering intermediate variables of RSIC-V instruction set running.

[0009] Preferably, in the initialization process, part of the registers that do not affect functions are used for storing start control instructions of the PMU; and when the chip is started, the part of the registers are released and continue to be used as function registers.

[0010] Preferably, the working stages of the chip include an initial start stage and a stage of preparing to enter sleep;

[0011] When the chip is in the initial start stage:

[0012] The SRAM control module carries the reset values of the general register module and the PMU special register to the SRAM, and releases the registers to enter a normal mode; then, the SRAM control module controls the instruction fetching module to fetch instructions; then, the instruction fetching module receives data and sends the data to the RSICV instruction set decoding execution module for instruction decoding and execution; finally, the RSICV instruction set decoding execution module outputs the power management control signal, and the power-on work of the chip is completed;

[0013] When the chip is in the stage of preparing to enter sleep:

[0014] The chip core writes sleep and wake-up related instructions into the PMU special register, and synchronizes them to the SRAM through the SRAM control module; the chip core writes a sleep start signal and an instruction fetching address, the PMU enters instruction decoding and execution, and makes the chip enter a sleep state through the power management control signal; if there is no wake-up source operation, the chip is in a complete power-off state thereafter;

[0015] If there is a wake-up source operation, the PMU special register accepts the wake-up source and configures the instruction fetching module to start fetching instructions from a wake-up start address; the instruction fetching module receives data and sends the data to the RSICV instruction set decoding execution module for instruction decoding and execution; the chip enters a normal working state, and the chip works normally thereafter.

[0016] Compared with the prior art, the beneficial effects of the present invention are:

[0017] This invention supports a PMU (Power Management Unit) architecture based on the RISC-V instruction set. This architecture solves the problem of insufficient flexibility in ASIC circuits. Compared to directly using the RISC-V core, this architecture eliminates unnecessary logic and functions, minimizing area and power consumption. Furthermore, the PMU module of this structure can be reused as IP in multiple different projects. Attached Figure Description

[0018] Figure 1 This is a general PMU architecture diagram supporting the RISC-V instruction set in this invention.

[0019] Figure 2 This is a flowchart illustrating the specific implementation steps of the general PMU architecture supporting the RISC-V instruction set of this invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0021] like Figure 1 As shown, the PMU (Power Management Unit) supported by this invention includes the following modules:

[0022] 1. PMU dedicated register control module, which includes the following functions:

[0023] a. The dedicated registers inside the PMU (Power Management Unit) are used to control the starting address of the instruction fetch module and the decoding method, among other functions.

[0024] b. During the initialization process, some registers that do not affect functionality will be used to store the startup control instructions for the PMU (Power Management Unit). Once startup is complete, these registers will be released and reused as function registers.

[0025] c. Used for triggering the wake-up source. When the wake-up source arrives, it will be converted into a corresponding start signal to control the entire PMU (Power Management Unit) to enter the power-on procedure.

[0026] d. This module has an interface for directly writing to the memory in the static random access memory control module. Data can be written to the memory by continuously writing to a certain address within the module.

[0027] 2. SRAM static random access memory control:

[0028] a. In the initial power-on, the module will carry the reset content of the PMU special register module and the general register module to the internal memory for the first start of the PMU (power management module). After the carrying is completed, the above two module registers are released.

[0029] b. After the start is completed, the module is mainly used for storing the instructions corresponding to the RISC-V instruction set. Before the chip system is in the sleep state, the instructions required for waking up are placed in the memory. When the wake-up source comes, the instruction fetching module will fetch instructions from the specified address to enter the wake-up program.

[0030] 3. Instruction fetching module: mainly used for fetching corresponding instructions from the SRAM static random access memory and sending them to the RSICV decoding and executing module for decoding and executing operation. The start signal and the start address of the module are generated by the PMU special register module.

[0031] 4. RSICV instruction set decoding and executing module:

[0032] a. The module is used for decoding the RSICV instruction set. Considering the power consumption area, the design only supports the most basic I instruction set.

[0033] b. At the same time, the module executes corresponding operations, including fetching data from the general register module and fetching instructions and jumping commands.

[0034] c. For part of the jump command, the pipeline will be flushed.

[0035] d. After the corresponding operation is executed, if there is a corresponding instruction, the module will control the input and output of the power management signal.

[0036] 5. General register module:

[0037] a. At the start, the module will send the reset value default value to the SRAM (static random access memory) control module.

[0038] b. In normal operation, the module is mainly used for buffering the intermediate variables of the RSICV instruction operation.

[0039] Further, as shown in Figure 2 , the embodiment of the present application also provides a specific implementation step of the general PMU structure supporting the RISC-V instruction set, as follows:

[0040] Power-on:

[0041] a. SRAM (static random access memory) control module carries the reset value of general registers and PMU (power management unit) dedicated registers into SRAM, and releases the registers to enter normal mode.

[0042] b. SRAM (static random access memory) control module controls the instruction fetch module to start fetching instructions.

[0043] c. The instruction fetch module receives data and sends it to the RSIC V instruction set decoding and execution module for instruction decoding and execution.

[0044] d. Control the power management signal to complete the power-on work of the chip.

[0045] The chip is ready to enter the sleep state:

[0046] a. The core of the chip writes the sleep and wake-up related instructions into the PMU (power management unit) dedicated register, and synchronizes it to the SRAM (static random access memory) through the module.

[0047] b. The core of the chip writes the sleep start signal and instruction fetch address, and the PMU (power management unit) enters the instruction decoding and execution, and makes the chip enter the sleep state through the power management control signal.

[0048] Note: After this step is completed, the power can be completely turned off.

[0049] c. Trigger the wake-up source, and the PMU (power management unit) dedicated register accepts the wake-up source and configures the instruction fetch module to start fetching instructions from the wake-up start address.

[0050] d. After instruction fetching, decoding and execution, the chip enters the normal working state.

[0051] e. The chip is working normally.

[0052] The application supports the architecture of the PMU (power management unit) of the RSIC V instruction set, which can solve the problem of insufficient flexibility of ASIC circuits, and compared with directly using the core of RISC-V, the architecture deletes unnecessary logic and functions, and maximally reduces the area and power consumption overhead. The PMU (power management unit) module of the structure can be reused as an IP in multiple different projects.

[0053] Although the preferred embodiments of the application have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the application.

[0054] Obviously, many modifications and variations of the present application are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A general purpose PMU architecture supporting RISC-V instruction set, characterized in that, The general PMU structure is configured in the chip, and includes a PMU special register, an SRAM control module, a fetch module, an RSICV instruction set decoding and executing module, and a general register module; The PMU special register control module is used for controlling the starting address and decoding mode of the fetch module; the PMU special register control module is also used for triggering the wake-up source; when the wake-up source arrives, the PMU special register control module is converted into a corresponding starting signal to control the whole PMU to enter a power-on program; The SRAM control module is used for carrying the reset contents of the PMU special register module and the general register module to the SRAM in the SRAM control module when the chip is in an initial power-on state, and is used for the first start of the PMU; after the carrying is completed, the registers of the PMU special register module and the general register module are released; when the chip is started completely, the SRAM control module is used for storing the corresponding instructions of the RISC-V instruction set; before the chip is in a sleep state, the instructions required for wake-up are placed in the SRAM in the SRAM control module; when the wake-up source arrives, the fetch module fetches the instructions from the specified address to enter the wake-up program; The RSICV instruction set decoding and executing module is used for decoding the RSIC-V instruction set; meanwhile, corresponding operations are performed, including fetching data from the general register module and fetching jump commands; for part of the jump commands, the pipeline is flushed; after the corresponding operations are performed, if there is a corresponding instruction, the RSICV instruction set decoding and executing module inputs and outputs the power management control signal; The general register module sends the reset value and the default value to the SRAM control module when the chip is in an initial start stage; when the chip is in a normal working stage, the general register module is used for buffering the intermediate variables of the RSIC-V instruction set.

2. The general purpose PMU architecture supporting RISC-V instruction set according to claim 1, wherein, In the initialization process, part of the registers that do not affect the function are used for storing the start control instructions of the PMU; after the chip is started completely, the part of the registers are released to continue to be used as the function registers.

3. The general purpose PMU architecture supporting RISC-V instruction set according to claim 1, wherein, The working stages of the chip include an initial start stage and a sleep preparation stage; When the chip is in the initial start stage: The SRAM control module carries the reset value of the general register module and the PMU special register to the SRAM, and releases the registers to enter the normal mode; then, the SRAM control module controls the fetch module to fetch; then, the fetch module receives the data and sends the data to the RSICV instruction set decoding and executing module to decode and execute the instructions; finally, the RSICV instruction set decoding and executing module outputs the power management control signal to complete the power-on work of the chip; When the chip is in the sleep preparation stage: The chip core writes the sleep and wake-up related instructions into the PMU special register, and synchronizes the instructions to the SRAM through the SRAM control module; the chip core writes the sleep starting signal and the fetch address, the PMU enters the fetch decoding and executing, and the chip enters the sleep state through the power management control signal; if there is no wake-up source operation, the chip is in a complete power-off state. If there is a trigger wake-up source operation, the PMU special register accepts the wake-up source and configures the instruction fetch module to start fetching instructions from the wake-up start address; the instruction fetch module receives the data and sends it to the RSIC V instruction set decoding and execution module for instruction decoding and execution; the chip enters the normal working state, and thereafter the chip works normally.

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