Chip-to-chip interconnect, chip-to-chip interconnect method and device

Abstract

This application proposes a chip interconnect, a chip interconnect method, and an apparatus to address the technical problem of low yield and reliability caused by PHY interface failures in chips employing the chip interconnect protocol. This application improves the MAC layer of the UCIe protocol in the chip interconnect. In the MAC layer, faulty PHY interfaces are detected during the PHY interface negotiation process, and available and unavailable PHY interfaces are marked using a PHY bitmap. The MAC layer selects an available PHY interface based on the PHY bitmap, splits and maps the interconnect data to the available PHY interface for transmission to the peer, or receives data from the peer from the available PHY and reassembles it. This application proposes an adaptive detection and adaptation design for the UCIe PHY layer interface of the interconnect chip, which can improve the yield and interconnect failure recovery rate of chips implementing the UCIe protocol for chip interconnect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, and in particular to a chiplet interconnection chip, a chiplet interconnection method and equipment. BACKGROUND

[0002] Chiplet interconnection technology of a semiconductor chip is mainly used to realize high-speed and low-delay communication between chiplets with different functions. Based on the chiplet interconnection technology, a large system chip can be divided into chiplets with different functions, each small chiplet can be independently manufactured according to a suitable process, and then different chiplets are assembled into a system chip through advanced packaging. For example, a system chip can include a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit) with a 5nm process, an NPU (Network Processing Unit) with a 7nm process, a VPU (Vector Processing Unit) with a 12nm process and a display control chiplet, an ISP (Image Signal Processor) with a 12nm process, a main memory and an I / O chiplet with a 22nm process, etc. These chiplets are connected through a chiplet interconnection IP to form a complete functional system-level chip.

[0003] There are different interconnection technologies for the physical connection between chiplets. The UCIe (Universal Chiplet Interconnect Express) protocol is a protocol specially designed for chiplet interconnection, and is an open, multi-protocol compatible and customizable technology standard that can meet the interconnection requirements of different customers between multiple DIEs (independent small chips cut from a silicon wafer) in a custom package.

[0004] Suppose that chiplet A and chiplet B are interconnected through the UCIe protocol. Each UCIe of each chiplet is composed of multiple PHYs. According to the UCIe protocol (see ucie spec), each UCIe PHY provides a redundant design inside to ensure reliable transmission and fault transmission inside the PHY to the greatest extent.

[0005] However, when one of the multiple UCIe PHYs of a chiplet fails due to chip generation yield problems or chip operation damage, it will directly affect the function of the chip, causing the chiplets to be unable to intercommunicate, thereby causing the chip to fail. SUMMARY

[0006] This application provides a chip interconnect chip, chip interconnect method, and device to solve the technical problem of low yield and reliability of chip interconnect chips using the chip interconnect protocol due to physical PHY interface failure.

[0007] Based on one aspect of the embodiments of this application, this application provides an interconnect chip, the chip interconnect chip including a plurality of chips interconnected via a chip interconnect protocol, wherein the MAC layer in the chip interconnect protocol module of the chip includes:

[0008] The PHY bitmap is used to identify the availability status of a PHY interface by using the values ​​of binary bits that correspond one-to-one with the physical PHY interface.

[0009] The PHY negotiation module is used to negotiate the PHY interface with the PHY negotiation module of the peer chip, determine the available PHY interface, and maintain the PHY bitmap.

[0010] The transceiver module is used to transmit data between cores based on the PHY bitmap through the available PHY interface when transmitting and receiving data through the PHY layer.

[0011] Furthermore, during the initialization process after the chip is powered on, the PHY negotiation module executes the detection and negotiation process of the PHY interface, or when the chip receives an interrupt indicating a hardware fault of the PHY interface during operation, the PHY negotiation module is triggered to execute the detection and negotiation process of the PHY interface.

[0012] Furthermore, the PHY negotiation module includes:

[0013] The polling detection unit is used to control the PHY interface under test to send detection frames to the peer and receive response frames sent by the peer in a polling manner during the detection negotiation process of the PHY interface. Before sending the detection frame, the instruction bitmap maintenance unit sets the binary bit of the PHY bitmap corresponding to the PHY interface under test to 1. If the detection frame fails to be sent or the response frame is received and the timeout occurs, the instruction bitmap maintenance unit sets the binary bit of the PHY bitmap corresponding to the PHY interface under test to 0.

[0014] The bitmap maintenance unit is used to maintain the PHY bitmap according to the instructions of the polling detection unit.

[0015] Furthermore, when the transceiver module sends a data frame to the peer, it selects an available PHY interface based on the PHY bitmap and sends the data to the peer through the available PHY interface.

[0016] When the size of the data frame encapsulated by the MAC layer does not exceed the transmission bit width provided by the available PHY interface of the PHY layer, the data frame is directly mapped to the available PHY interface according to the PHY bitmap and transmitted to the other end.

[0017] When the size of the data frame encapsulated by the MAC layer exceeds the transmission bit width provided by the available PHY interface, the data frame is divided into multiple data blocks suitable for the parallel transmission bit width of the available PHY interface according to the PHY bitmap, and the data blocks are marked with sequence numbers. The divided data blocks are sent to the peer in sequence to instruct the peer to reassemble and recover the original data frame according to the sequence numbers.

[0018] Based on another aspect of this application, this application also provides a chip interconnect method, which is applied to a chip in a chip interconnect chip, the method comprising:

[0019] The process involves detecting and negotiating the PHY interface with the peer chip to determine the available PHY interface and maintain a PHY bitmap. The PHY bitmap is used to identify the available status of the PHY interface through the values ​​of binary bits that correspond one-to-one with the physical PHY interface.

[0020] When the MAC layer sends and receives data through the PHY layer, it uses the available PHY interfaces to transmit data between chips based on the PHY bitmap.

[0021] Furthermore, during the initialization process after the chip is powered on, the detection and negotiation process of the PHY interface is executed, or when an interrupt indicating a hardware fault of the PHY interface is received during the operation of the chip, the PHY negotiation module is triggered to execute the detection and negotiation process of the PHY interface.

[0022] Furthermore, during the PHY interface detection negotiation process, a polling method is used to control the PHY interface being detected to send detection frames to the peer and receive response frames sent by the peer.

[0023] Before sending the detection frame, the binary bit in the PHY bitmap corresponding to the PHY interface to be detected is set to 1; if the detection frame fails to be sent or the response frame times out, the binary bit in the PHY bitmap corresponding to the PHY interface to be detected is set to 0.

[0024] Furthermore, when sending a data frame to the other end, the available PHY interface is selected based on the PHY bitmap and the data is sent to the other end through the available PHY interface;

[0025] When the size of the data frame encapsulated by the MAC layer does not exceed the transmission bit width provided by the available PHY interface of the PHY layer, the data frame is directly mapped to the available PHY interface according to the PHY bitmap and transmitted to the other end.

[0026] When the size of the data frame encapsulated by the MAC layer exceeds the transmission bit width provided by the available PHY interface, the data frame is divided into multiple data blocks suitable for the parallel transmission bit width of the available PHY interface according to the PHY bitmap, and the data blocks are marked with sequence numbers. The divided data blocks are sent to the peer in sequence to instruct the peer to reassemble and recover the original data frame according to the sequence numbers.

[0027] Furthermore, the chip interconnect protocol is the Universal Chip Interconnect Bus (UCIe) protocol.

[0028] Based on another aspect of the embodiments of this application, this application also provides a device that uses a system chip based on the aforementioned chips.

[0029] The technical solutions provided in this application embodiment may include the following beneficial effects:

[0030] This application improves the UCIe protocol MAC layer of interconnect chips. In the MAC layer, faulty PHY interfaces are detected during the negotiation process via the PHY interface, and available and unavailable PHY interfaces are marked using a PHY bitmap. The MAC layer selects an available PHY interface based on the PHY bitmap, splits and maps the interconnect data to the available PHY interface for transmission to the peer, or receives data from the peer from the available PHY and reassembles it. This application proposes an adaptive detection and adaptation design for the UCIe PHY layer interface of interconnect chips, which can improve the yield and interconnect fault recovery rate of chips implementing the UCIe protocol.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0032] Figure 1 A schematic diagram of a 6-PHY structure is provided for the single-sided UCIe protocol of core A in one embodiment of the invention;

[0033] Figure 2 A schematic diagram of a structure in one embodiment of the invention, showing that core B provides six PHY interfaces for the dual-sided UCIe protocol.

[0034] Figure 3 This is a schematic diagram of a chip interconnect chip structure composed of one chip B and two chips A in one embodiment of the present invention;

[0035] Figure 4 This is a schematic flowchart of the chip interconnection method provided in an embodiment of the present invention;

[0036] Figure 5 This is a flowchart illustrating the PHY detection and negotiation process of the interconnect chip in one embodiment of the present invention. Detailed Implementation

[0037] The exemplary embodiments will now be described in detail. When the description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification; they are merely exemplary embodiments of apparatuses and methods consistent with some aspects of this specification.

[0038] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “described,” and “the” as used herein are also intended to include the plural forms unless the context clearly indicates otherwise.

[0039] It should be understood that the terms "first," "second," "third," etc., may be used in this specification to describe various information or structural modules for the purpose of more clearly describing the solution. These terms should not be construed as indicating or implying relative importance or implicitly specifying the number, order, or position of the indicated technical features. Therefore, a feature defined with "first," "second," "third," etc., may explicitly or implicitly include one or more of that feature. In the description of this specification, unless otherwise stated, "a plurality of" means two or more; "if" can be interpreted as "when," "when," or "in response to determination."

[0040] In this specification, unless otherwise expressly specified and limited, the term "connection" shall be interpreted broadly. For example, "connection" may be a fixed connection, a detachable connection, or an integral part; it may be a direct connection or an indirect connection through an intermediate medium.

[0041] In this specification, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects are in an "or" relationship.

[0042] Figure 1 This is a schematic diagram illustrating the structure of a single-sided UCIe protocol providing six PHY interfaces in one embodiment of the invention. In this embodiment, the UCIe protocol module of chip A in the chip interconnect chip provides six physical layer PHY interfaces, namely PHY1, PHY2, PHY3, PHY4, PHY5, and PHY6. Each PHY interface adopts the X16 Standard package mode, providing 16 lanes (physical transmission channels), and each channel supports 16Gbps. Therefore, chip A can provide a total interconnect bandwidth of 1.5Tbps (6*16*16).

[0043] It should be noted that the chip A mentioned in the embodiments of the present invention and the subsequent chip B can both adopt the standard X16 Standard packaging mode (16 lanes per PHY) or the advanced X64 Advanced Package (64 lanes per PHY). The transmission rate supported by a single lane can be 4Gbps, 8Gbps, 12Gbps, 16Gbps, 24Gbps, 32Gbps, etc., and a single chip can also have fewer or more than 6 PHY interfaces to meet the bandwidth requirements of different applications. The present invention does not limit the specific packaging mode, the rate supported by the lane, or the number of PHYs in the chip.

[0044] Figure 2 The diagram illustrates the structure of a chip B with six PHYs on each side of the UCIe protocol in one embodiment of the invention. In this embodiment, the UCIe protocol module of chip B in the chip interconnect chip provides six PHY physical layer interfaces on each side. Each PHY interface adopts the X16 Standard package mode, providing 16 lanes, and each channel supports 16Gbps. Therefore, chip B can provide a total interconnect bandwidth of 3Tbps (2*6*16*16).

[0045] Figure 3 This is a schematic diagram of a chip interconnect chip structure composed of one chip B and two chips A in one embodiment of the present invention. In this chip interconnect chip, chip A and chip B communicate via the UCIe protocol. Each UCIe consists of 6 PHYs, and each PHY provides 256G bandwidth.

[0046] According to the current UCIe protocol version (see ucie spec), although each UCIe PHY provides a redundant channel design, such as redundant lanes for both the main band and sideband, it can maximize the reliability and stability of communication when the PHY fails through fault detection and repair mechanisms, meeting the needs of demanding application scenarios such as high-performance computing and data centers. However, when a certain UCIE PHY interface in the chip fails and becomes unusable due to chip production yield issues or chip malfunction, it will directly affect the chip's functionality, causing the chips to be unable to communicate with each other, thus rendering the chip unusable.

[0047] To address the aforementioned technical issues, this invention proposes an adaptive detection and adaptation design for the UCIe PHY layer interface of interconnect chips. It improves the UCIe protocol MAC layer of the chip by detecting faulty PHY interfaces during the negotiation process and marking available and unavailable PHY interfaces using a PHY bitmap. The MAC layer selects available PHY interfaces based on the PHY bitmap, splits and maps interconnect data to available PHY interfaces for transmission to the peer, or receives data from the peer from available PHY interfaces and reassembles it. This invention can improve the yield and interconnect fault recovery rate of chips using the UCIe protocol for interconnect implementation. For example, for an interconnect chip with n PHY interfaces, the interconnect yield can be improved by (nm) / n, where m is the minimum number of interconnect PHY interfaces. For system chips with multiple interconnect chips, it can significantly improve the overall yield, reliability, and availability of the system chip.

[0048] Based on the above ideas, such as Figure 1 and Figure 2 For example, in one embodiment of the present invention, the MAC layer in the interconnect protocol module of the interconnect chip includes:

[0049] The PHY bitmap is used to identify the availability status of a PHY interface by using the values ​​of binary bits that correspond one-to-one with the physical PHY interface.

[0050] The PHY negotiation module is used to negotiate the PHY interface with the PHY negotiation module of the peer chip, determine the available PHY interface, and maintain the PHY bitmap.

[0051] The transceiver module is used to transmit data between cores based on the PHY bitmap through the available PHY interface when transmitting and receiving data through the PHY layer.

[0052] After completing the PHY interface detection and negotiation process and determining the available PHY interface on the local end, the transceiver module in the MAC layer of the chip selects an available PHY interface based on the PHY bitmap when sending a data frame to the peer end, and sends the data through the available PHY interface. If the size of the data frame does not exceed the transmission bit width provided by the available PHY interface in the PHY layer, the MAC layer can directly map the data frame to the available PHY interface according to the PHY bitmap and transmit it to the peer end's PHY receiving interface.

[0053] If the size of the data frame encapsulated by the MAC layer exceeds the transmission bit width provided by the available PHY interface, the MAC layer can divide the data frame into multiple data blocks suitable for the parallel transmission bit width of the available PHY interface according to the PHY bitmap, mark the sequence number of the data blocks, and send the divided data blocks to the peer in sequence. After receiving the data blocks, the peer can reassemble them according to the sequence number to obtain the original data frame.

[0054] Similarly, the MAC of the UCIe protocol in the receiving chip also uses the same detection and negotiation process to determine the available PHY interface and update the local PHY bitmap. Based on the PHY bitmap, it receives the data transmitted from the peer through the available PHY interface.

[0055] Figure 4 This is a schematic flowchart of a chip interconnect method provided in an embodiment of the present invention. The method is applied to a chip in a chip interconnect chip and includes:

[0056] Step 401. Perform PHY interface detection negotiation with the peer chip to determine the available PHY interface and maintain the PHY bitmap;

[0057] In this embodiment, a PHY bitmap is implemented in the protocol layer (MAC layer) above the UCIE PHY layer. Each bit in the bitmap represents the availability status of a PHY interface in a PHY layer, with 1 indicating availability and 0 indicating unavailability. The size of the PHY bitmap is determined by the number of PHY interfaces in the chip.

[0058] In this embodiment, during the initialization process after the chip is powered on, the above-mentioned PHY detection negotiation process is executed. The detection negotiation process detects all available PHY interfaces in normal state and sets the bit position corresponding to the PHY interface in the PHY bitmap to 1.

[0059] If the UCIE PHY is damaged during chip operation, such as by static electricity, lightning strikes, or other abnormal conditions that cause damage to the PHY interface, the communication connection between chips will be broken. At this time, the chip's fault detection mechanism may be interrupted. After receiving the interrupt signal or information, the PHY negotiation module in the UCIe protocol MAC layer will re-trigger the detection and negotiation process of the PHY interface to update the PHY bitmap.

[0060] Step 402. When the MAC layer sends and receives data through the PHY layer, it performs data transmission between chips based on the PHY bitmap through the available PHY interface.

[0061] Figure 5 This is a flowchart illustrating the PHY detection and negotiation process of an interconnect chip in one embodiment of the present invention. This example uses the case where both chip A and chip B have six PHY interfaces to describe the process by which the PHY negotiation module performs a PHY interface detection and negotiation process to detect available PHY interfaces and update the PHY bitmap. Chip A initiates the PHY detection and negotiation process, detecting each of the six PHY interfaces one by one, and updating the PHY bitmap based on the detection results. The specific steps are as follows:

[0062] S501. The PHY negotiation module of chip A sets the corresponding bit of PHY1 in the PHY bitmap to 1 (that is, the PHY bitmap of A is 0x1=000001), and sends a detection frame to chip B through the PHY1 interface.

[0063] Chip A sequentially checks available PHY interfaces, starting with the first one, according to the number of PHY interfaces. The six bits of the PHY bitmap correspond to the six PHY interfaces, and the initial state value of the PHY bitmap is set to 0. In some cases, due to hardware failure, the PHY interface may be in a hardware failure state upon startup. In this situation, the PHY negotiation module can directly mark the corresponding bit in the PHY bitmap as 0, and during subsequent polling checks, only PHY interfaces in the UP state will be checked.

[0064] The PHY interfaces at both ends of the chip can notify the other party that a PHY interface detection and negotiation process is currently being performed through a special mode frame or through a control channel. After receiving the detection frame, the other end needs to send a response frame back to the sending end so that the sending end can confirm that the sending end's PHY interface is a usable interface.

[0065] S502. After receiving the detection frame sent by core A from the PHY1 interface, the PHY1 interface of core B notifies the PHY negotiation module in the MAC layer. The PHY negotiation module sets the corresponding bit of the PHY1 interface in the PHY bitmap of core B to 1 (i.e., the PHY bitmap of B is 0x1=000001), and then sends back a response frame through the PHY1 interface.

[0066] When chip B receives the detection frame through the B-end PHY1 interface corresponding to the A-end PHY1 interface and successfully sends it to the PHY negotiation module of the MAC layer, chip B can confirm that its local PHY interface is in an available state. Then, it sets the corresponding binary bit of the local PHY bitmap PHY1 interface to 1 and sends a response frame back through the PHY1 interface to inform the other end in a timely manner that the detection of the current PHY interface is complete and the detection of the next PHY interface can begin.

[0067] S503. After receiving the response frame from the PHY1 interface, Chip A confirms that the PHY1 interface is an available PHY interface, and then starts the availability detection of the PHY2 interface; Chip A's PHY negotiation module sets the corresponding bit of PHY2 in the PHY bitmap to 1 (that is, the PHY bitmap of A is 0x3=000011), and sends a detection frame to Chip B through the PHY2 interface.

[0068] In this embodiment, although the PHY2 interface at end A is in the UP state, the detection frame is not successfully sent to the PHY2 interface at end B due to some fault. This situation may be due to a fault in the PHY2 interface at end A or a fault in the PHY2 interface at end B. Regardless of which side has the problem, the detection frame will not be successfully sent to the chip B.

[0069] S504. Chip B waits to receive the detection frame of the PHY2 interface. If no detection frame is received after the timeout, the PHY negotiation module of chip B will not set the bit corresponding to the PHY2 interface in the PHY bitmap. Therefore, the PHY bitmap of B remains unchanged (i.e., the PHY bitmap of B is still 0x1=000001).

[0070] S505. After the PHY negotiation module of chip A fails to send a detection frame through the PHY2 interface or the timeout occurs while waiting for the response frame from the PHY2 interface, it sets the corresponding bit of the PHY2 interface in the PHY bitmap to 0 (i.e., the PHY bitmap of the A end becomes 0x1=000001 again, which is equivalent to marking the PHY2 interface as unavailable); then, it performs the detection of the PHY3 interface, sets the corresponding bit of PHY3 in the PHY bitmap to 1 (i.e., the PHY bitmap of the A end is 0x5=000101), and sends a detection frame to chip B through the PHY3 interface.

[0071] S506. Core B receives the detection frame received through the PHY3 interface. The PHY negotiation module sets the corresponding bit of PHY3 in the PHY bitmap to 1 (i.e., the PHY bitmap at end A is 0x5=000101). This step is similar to S502 and will not be described again.

[0072] S507. After receiving the response frame from the PHY3 interface, chip A confirms that the PHY3 interface is an available PHY interface, and then starts the availability detection of the PHY4 interface. It sets the corresponding bit of PHY4 in the PHY bitmap to 1 (that is, the PHY bitmap on the A side is 0xD=001101) and sends a detection frame to chip B through the PHY4 interface.

[0073] For the sake of simplicity, the availability testing process for the PHY4, PHY5, and PHY6 interfaces is omitted below. For details, please refer to the steps described above.

[0074] according to Figure 5 Example of steps, Figure 1 and Figure 2 The example PHY negotiation module may further include:

[0075] The polling detection unit is used to control the PHY interface under test to send detection frames to the peer and receive detection frames sent by the peer in a polling manner during the detection negotiation process of the PHY interface. Before sending the detection frame, the instruction bitmap maintenance unit sets the binary bit of the PHY bitmap corresponding to the PHY interface under test to 1. If the detection frame fails to be sent or the response frame is received and timed out, the instruction bitmap maintenance unit sets the binary bit of the PHY bitmap corresponding to the PHY interface under test to 0.

[0076] The bitmap maintenance unit is used to maintain the PHY bitmap according to the instructions of the polling detection unit.

[0077] It should be noted that the embodiments of the present invention are described using the UCIe protocol as an example, and do not mean that the technical solutions provided by the present invention are only applicable to the UCIe application scenario or environment. Based on the content disclosed in the present invention, the present invention can also be applied to the chip interconnect protocol with a layered architecture of MAC layer and PHY layer.

[0078] The chip and chip interconnection methods disclosed in this specification can be applied to terminal devices, servers, or network devices.

[0079] The foregoing has described exemplary embodiments of this specification. It should be understood that in some cases, the modules described in this specification may be divided in a manner different from that in the embodiments, and the described actions or steps may be performed in a different order than that in the embodiments, while still achieving the desired result. Furthermore, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0080] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not illustrated herein.

[0081] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A chiplet interconnect chip, comprising: The chiplet interconnect chip comprises a plurality of chiplets interconnected through a chiplet interconnect protocol, a MAC layer in a chiplet interconnect protocol module of the chiplets comprises: a PHY bitmap for identifying available states of PHY interfaces through values of binary bits corresponding to the PHY interfaces one by one; a PHY negotiation module for performing detection negotiation of the PHY interfaces with a PHY negotiation module of a peer chiplet, determining available PHY interfaces and maintaining the PHY bitmap; a transceiving module for performing data transmission between the chiplets through the available PHY interfaces based on the PHY bitmap when data is transmitted through the PHY layer; the PHY negotiation module comprises: a polling detection unit for controlling a PHY interface to be detected to send a detection frame to the peer in a polling manner in the detection negotiation process of the PHY interfaces, and receiving a response frame sent by the peer; before the detection frame is sent, an instruction bitmap maintenance unit sets a binary bit corresponding to the PHY interface to be detected in the PHY bitmap to 1; in a case where the detection frame is not sent successfully or the response frame is not received in time, the instruction bitmap maintenance unit sets the binary bit corresponding to the PHY interface to be detected in the PHY bitmap to 0; a bitmap maintenance unit for maintaining the PHY bitmap according to instructions of the polling detection unit.

2. The chiplet interconnect chip according to claim 1, wherein the PHY negotiation module performs the detection negotiation process of the PHY interfaces in an initialization process after the chiplet is powered on, or triggers the PHY negotiation module to perform the detection negotiation process of the PHY interfaces when an interrupt indicating a hardware fault of the PHY interface is received in a running process of the chiplet.

3. The chiplet interconnect chip according to claim 1, wherein the transceiving module selects an available PHY interface to send data to the peer through the available PHY interface based on the PHY bitmap when a data frame is sent to the peer; when a size of the data frame encapsulated by the MAC layer does not exceed a transmission bit width provided by the available PHY interface of the PHY layer, the data frame is directly mapped to the available PHY interface for transmission to the peer according to the PHY bitmap; when the size of the data frame encapsulated by the MAC layer exceeds the transmission bit width provided by the available PHY interface of the PHY layer, the data frame is divided into a plurality of data blocks suitable for parallel transmission bit width of the available PHY interface and marked with serial numbers, and the divided data blocks are sent to the peer in sequence to instruct the peer to recover the original data frame according to the serial numbers.

4. A method of interconnecting core particles, characterized by, The method is applied to a chiplet in a chiplet interconnect chip, and the method comprises: performing a detection negotiation process of PHY interfaces with a peer chiplet, determining available PHY interfaces and maintaining a PHY bitmap; the PHY bitmap is used to identify available states of the PHY interfaces through values of binary bits corresponding to the PHY interfaces one by one; the MAC layer performs data transmission between the chiplets through the available PHY interfaces based on the PHY bitmap when data is transmitted through the PHY layer; a polling manner is adopted to control a PHY interface to be detected to send a detection frame to the peer in a detection negotiation process of the PHY interfaces, and a response frame sent by the peer is received; Before sending the detection frame, the binary position 1 in the PHY bitmap corresponding to the PHY interface to be detected is set; in the case of failure of sending the detection frame or timeout of receiving the response frame, the binary position 0 in the PHY bitmap corresponding to the PHY interface to be detected is set.

5. The method of claim 4, wherein, In the initialization process after the power-on of the corelet, the detection negotiation process of the PHY interface is executed, or when an interrupt indicating a hardware failure of the PHY interface is received during the operation of the corelet, the detection negotiation process of the PHY interface is triggered to be executed.

6. The method of claim 4, wherein, When sending a data frame to the opposite end, the available PHY interface is selected based on the PHY bitmap to send the data to the opposite end through the available PHY interface; When the size of the data frame encapsulated by the MAC layer does not exceed the transmission bit width provided by the available PHY interface of the PHY layer, the data frame is directly mapped to the available PHY interface according to the PHY bitmap to transmit to the opposite end; When the size of the data frame encapsulated by the MAC layer exceeds the transmission bit width provided by the available PHY interface of the PHY layer, the data frame is divided into multiple data blocks suitable for the parallel transmission bit width of the available PHY interface and the data blocks are marked with serial numbers, and the divided data blocks are sequentially sent to the opposite end to instruct the opposite end to recover the original data frame according to the serial numbers.

7. The method of claim 4, wherein, The protocol of the corelet interconnection is a universal corelet interconnection bus (UCIe) protocol.

8. An apparatus, comprising: The device uses a corelet interconnection chip according to any one of claims 1 to 3.

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