Method and system for verifying physical memory protection function and storage medium

Abstract

The application is suitable for the technical field of processors, and particularly relates to a physical memory protection function verification method and system and a storage medium. The method comprises the following steps: obtaining a plurality of physical address segments to be used by a processor architecture during a verification process; establishing a mapping relationship between each physical address segment and a randomly selected physical memory protection region in the processor architecture, and taking a start address and an end address of the physical address segment as a start address and an end address of the corresponding physical memory protection region; randomly selecting a preset number of mapping regions for abnormality injection; and verifying a physical memory protection function of the processor architecture based on the mapping regions to be verified. The application can quickly generate physical memory protection mapping region configurations meeting verification requirements, randomly inject abnormalities into the mapping regions through mechanisms such as permission cancellation, address range reduction and boundary value replacement, and effectively verify the behavior correctness of the processor architecture under different physical memory protection mapping region configurations.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a method, system, and storage medium for verifying physical memory protection functions. Background Technology

[0002] With the continuous improvement of the RISC-V instruction set architecture and the ongoing expansion of its application areas, the RISC-V architecture is increasingly supporting physical memory management in various scenarios, from embedded systems to high-performance computing. Among these features, the Physical Memory Protection (PMP) design employed by RISC-V demonstrates significant flexibility, supporting precise control over various access permissions, including read, write, and execute. By configuring specific address ranges and corresponding access attributes, the PMP mechanism achieves fine-grained protection of physical memory, which is crucial for ensuring system security and stability.

[0003] However, in practical applications, correctly configuring PMP address ranges and effectively verifying their correctness has gradually become a significant challenge that needs to be addressed. Currently, the industry has not yet developed a mature PMP address range allocation method that can be used to perform complete and comprehensive verification of RISC-V PMP functionality at the module level.

[0004] Currently, the mainstream PMP configuration methods in the industry are mainly divided into two types: manual configuration and simple random generation. However, both of these methods have obvious problems:

[0005] Firstly, manual configuration is prone to errors, especially when configuring multiple overlapping or adjacent PMP intervals. Due to the complexity and negligence of human operation, the probability of error increases significantly.

[0006] Secondly, the simple random generation method cannot meet the precise control of whether PMP exceptions are generated in module-level verification. It may cause a large number of physical addresses used by test cases to hit exceptions, which in turn causes a large number of unexpected scenarios to be generated in the test cases, affecting the accuracy of verification.

[0007] Third, both of these methods lack systematic coverage of misconfiguration scenarios, making it difficult to fully verify the boundary conditions and exception handling rules of PMP configuration, which is not conducive to ensuring the reliability of PMP functions.

[0008] Therefore, there is an urgent need for a new method, system, and storage medium for verifying physical memory protection functions to solve the above-mentioned technical problems. Summary of the Invention

[0009] This invention provides a method, system, and storage medium for verifying physical memory protection functions, aiming to solve the problem that existing physical memory protection address segment configurations cannot meet the verification requirements of physical memory protection functions for complex processor architectures.

[0010] In a first aspect, the present invention provides a method for verifying physical memory protection functions, the verification method comprising the following steps:

[0011] S1. Obtain the multiple physical address ranges that the processor architecture will use during the verification process;

[0012] S2. Establish a mapping relationship between each physical address segment and a randomly selected physical memory protection region in the processor architecture. Use the start address and end address of the physical address segment as the start address and end address of the corresponding physical memory protection region, and grant the physical memory protection region access permissions under the current verification scenario of the processor architecture to obtain multiple mapped regions. Configure the physical memory protection regions in the processor architecture that have not established a mapping relationship as invalid regions.

[0013] S3. Randomly select a preset number of the mapped regions for anomaly injection to obtain the mapped regions to be verified;

[0014] S4. Verify the physical memory protection function of the processor architecture based on the mapping region to be verified, and obtain the verification result.

[0015] Preferably, in step S3, when the abnormal injection into the mapped region is a permission violation, the preset number of the mapped regions are randomly selected, and the access permissions of the randomly selected mapped regions are cancelled.

[0016] Preferably, in step S3, when the abnormal injection of the mapped region is an address mismatch abnormality, a preset number of the mapped regions are randomly selected, and the starting address of the randomly selected preset number of the mapped regions is moved a random distance toward the ending address of the mapped region, or the ending address of the randomly selected preset number of the mapped regions is moved a random distance toward the starting address of the mapped region.

[0017] Preferably, in step S3, when the abnormal injection of the mapping region is an address overlap abnormality, the preset number of the mapping regions are randomly selected, and the start address or end address of the selected mapping region is randomly replaced with another mapping region.

[0018] Preferably, step S1 further includes the following sub-steps:

[0019] S11. Determine whether the number of multiple physical address segments exceeds a preset value: if so, randomly select multiple consecutive adjacent physical address segments for merging.

[0020] Preferably, the access permissions include one or more of read permissions, write permissions, and execute permissions.

[0021] Secondly, the present invention also provides a verification system for physical memory protection functions, the verification system comprising:

[0022] The address range acquisition module is used to acquire multiple physical address ranges that the processor architecture will use during the verification process;

[0023] A mapping establishment module is used to establish a mapping relationship between each physical address segment and a randomly selected physical memory protection region in the processor architecture, using the start and end addresses of the physical address segment as the start and end addresses of the corresponding physical memory protection region, and granting the physical memory protection region access permissions under the current verification scenario of the processor architecture, thereby obtaining multiple mapped regions; and configuring physical memory protection regions in the processor architecture that do not have an established mapping relationship as invalid regions;

[0024] Anomaly injection module is used to randomly select a preset number of the mapping regions for anomaly injection to obtain the mapping regions to be verified.

[0025] The verification module is used to verify the physical memory protection function of the processor architecture based on the mapping region to be verified, and obtain the verification result.

[0026] Thirdly, the present invention also provides a computer device, including: a memory, a processor, and a verification program for physical memory protection function stored in the memory and executable on the processor, wherein when the processor executes the verification program for physical memory protection function, it implements the steps in the verification method for physical memory protection function as described in any of the above embodiments.

[0027] Fourthly, the present invention also provides a computer-readable storage medium storing a verification program for physical memory protection functions, wherein when the verification program for physical memory protection functions is executed by a processor, it implements the steps in the verification method for physical memory protection functions as described in any of the above embodiments.

[0028] Compared with existing technologies, this invention obtains multiple physical address segments used by the processor architecture during the verification process; it randomly selects a physical memory protection region from the processor architecture to establish a mapping relationship for each physical address segment, using the start and end addresses of the physical address segments as the start and end addresses of the corresponding physical memory protection regions, and granting the physical memory protection regions access permissions under the current verification scenario of the processor architecture, thus obtaining multiple mapped regions; it configures physical memory protection regions in the processor architecture that do not have established mapping relationships as invalid regions; it randomly selects a preset number of mapped regions for anomaly injection to obtain the mapped regions to be verified; and it verifies the physical memory protection function of the processor architecture based on the mapped regions to be verified to obtain the verification results. This invention can quickly generate physical memory protection mapping region configurations that meet verification requirements, and can effectively verify the correctness of the processor architecture's behavior under different physical memory protection mapping region configurations by randomly injecting anomalies into the mapped regions through mechanisms such as permission cancellation, address range reduction, and boundary value replacement. At the same time, it can automatically handle the mapping relationship between any number of physical address segments and limited physical memory protection regions. By randomly merging physical address segments, it ensures that effective physical memory protection configurations can be generated under different processor specification limitations, meeting the complex RISC-V physical memory protection function verification requirements. Attached Figure Description

[0029] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0030] Figure 1 This is a flowchart of the verification method for physical memory protection function provided in the embodiments of the present invention;

[0031] Figure 2 This is a schematic diagram of the physical memory protection area in the verification method for physical memory protection function provided in this embodiment of the invention;

[0032] Figure 3 This is a schematic diagram of multiple physical address segments in the verification method for physical memory protection function provided in this embodiment of the invention;

[0033] Figure 4 This is a flowchart illustrating the physical address segment merging process of the verification method for physical memory protection function provided in this embodiment of the invention.

[0034] Figure 5 This is a schematic diagram illustrating the process of mapping physical address segments to physical memory protection regions in the verification method for physical memory protection function provided in this embodiment of the invention.

[0035] Figure 6This is a flowchart illustrating the process of injecting address mismatch anomalies into the mapped region in the verification method for physical memory protection function provided in this embodiment of the invention.

[0036] Figure 7 This is a flowchart illustrating the process of injecting address overlap anomalies into the mapped region in the verification method for physical memory protection function provided in this embodiment of the invention.

[0037] Figure 8 This is a schematic diagram of the structure of the verification system for physical memory protection function provided in an embodiment of the present invention;

[0038] Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0040] Example 1

[0041] Please refer to Figure 1 This invention provides a method for verifying physical memory protection functionality, the verification method comprising the following steps:

[0042] S1. Obtain the multiple physical address ranges that the processor architecture will use during the verification process.

[0043] In this embodiment of the invention, the processor architecture is a RISC-V architecture, which includes multiple physical memory protection regions. Each physical memory protection region may include the start and end addresses of the physical address space, access permissions of the space, and valid bits, etc., which can be referred to... Figure 2 , Figure 2 This is a schematic diagram of the physical memory protection area of ​​the verification method for physical memory protection function provided in this embodiment of the invention.

[0044] The physical memory protection features defined by RISC-V are typically used in multiple different modules within a RISC-V CPU core. The verification process for different modules may result in one or more contiguous or non-contiguous physical address segments during simulation due to different privilege levels and paging modes. (See reference...) Figure 3 , Figure 3This is a schematic diagram illustrating multiple physical address segments in the verification method for physical memory protection provided in this embodiment of the invention. This step records the information of each physical address segment using a data structure. Each physical address segment consists of a start address and an end address. If address segments overlap, the overlapping parts are merged. After all address segment information is recorded, each address segment is sorted in descending order of address value to form multiple physical address segments.

[0045] In this embodiment of the invention, since the upper limit of the number of usable physical address segments supported by different CPU products (assuming a maximum of N pairs of physical memory protection regions) is inconsistent, and the number of physical address segments used in the simulation can be arbitrarily set according to verification requirements, when the number of physical address segments used in the simulation is greater than N, it is necessary to merge the recorded physical address segments to reduce them to within N. When merging, step S1 further includes the following sub-steps:

[0046] S11. Determine whether the number of multiple physical address segments exceeds a preset value: if so, randomly select multiple consecutive adjacent physical address segments for merging.

[0047] Specifically, by calculating the number of recorded physical address segments, assuming the number of physical address segments is P, randomly select (P-N+1) consecutive adjacent physical address segments. Adjacent means that no physical address segment is allocated between two adjacent physical address segments, which is considered to be adjacent.

[0048] Please refer to Figure 4 , Figure 4 This is a flowchart illustrating the physical address segment merging process of the physical memory protection function verification method provided in this embodiment of the invention. The (P-N+1) physical address segments are merged into one. Specifically, the starting address of the lowest physical address segment is set as the starting address of the merged segment, and the ending address of the highest physical address segment is set. To merge physical address segment 3 and address segment 2 into one, the starting address of physical address segment 2 is set as the starting address of the merged segment, and the ending address of physical address segment 3 is set as the ending address of the merged segment. If the number of physical address segments used by the processor architecture during verification is less than or equal to N, then merging is not required.

[0049] S2. Establish a mapping relationship between each physical address segment and a randomly selected physical memory protection region in the processor architecture. Use the start address and end address of the physical address segment as the start address and end address of the corresponding physical memory protection region, and grant the physical memory protection region access permissions under the current verification scenario of the processor architecture to obtain multiple mapped regions. Configure the physical memory protection regions in the processor architecture that have not established a mapping relationship as invalid regions.

[0050] In the embodiments of the present invention, please refer to Figure 5 , Figure 5 This is a flowchart illustrating the mapping process between physical address segments and physical memory protection regions in the verification method for physical memory protection function provided in this embodiment of the invention. A physical memory protection region is randomly selected for mapping; unmapped physical memory protection regions are considered invalid. For mapped physical memory protection regions, the start and end addresses of the corresponding physical address segments to be used are used as the start and end addresses of the physical memory protection region, and this physical memory protection region is given the correct access permissions in the current verification scenario. This ensures that all used physical address segments have been assigned the correct access permissions to the physical memory protection region.

[0051] The access permissions include one or more of the following: read permission, write permission, and execute permission.

[0052] S3. Randomly select a preset number of the mapped regions for anomaly injection to obtain the mapped regions to be verified.

[0053] In this embodiment of the invention, anomaly injection in the mapped region refers to actively modifying the configuration of physical memory protection mechanisms (such as RISC-V's PMP, ARM's MPU, x86's memory protection, etc.) or triggering specific access scenarios to artificially create access behaviors that do not conform to memory protection rules, thereby triggering processor-preset anomalies (such as permission violations, address overwrite, etc.). The purpose is to verify the processor architecture's ability to detect, respond to, and process anomalies in the physical memory protection mechanism, and to ensure the reliability of the memory protection function.

[0054] When the abnormal injection into the mapped region is a permission violation, the preset number of the mapped regions are randomly selected, and the access permissions of the randomly selected mapped regions are revoked.

[0055] Please refer to Figure 6 , Figure 6This is a flowchart illustrating the address mismatch exception injection process for the mapping region in the verification method for physical memory protection provided in this embodiment of the invention. When the exception injection for the mapping region is an address mismatch exception, a preset number of the mapping regions are randomly selected, and the starting address of the randomly selected preset number of the mapping regions is moved a random distance towards the ending address of the mapping region (the maximum random distance is equal to the ending address), or the ending address of the randomly selected preset number of the mapping regions is moved a random distance towards the starting address of the mapping region (the maximum random distance is equal to the starting address). The minimum granularity of the movement can be flexibly set according to the specifications of the processor architecture being verified.

[0056] Please refer to Figure 7 , Figure 7 This is a flowchart illustrating the process of injecting address overlap anomalies into a mapped region using the verification method for physical memory protection provided in this embodiment of the invention. When the anomaly injection into the mapped region is an address overlap anomaly, a preset number of the mapped regions are randomly selected, and the start address or end address of the selected mapped region is randomly replaced with another mapped region. For example... Figure 7 In the process, the starting address of mapping region 2 is randomly selected for replacement, and the starting address of mapping region 1 is randomly selected to replace the old starting address of mapping region 2. After the replacement, an anomaly can be formed that the address ranges of mapping region 2 and mapping region 1 overlap.

[0057] S4. Verify the physical memory protection function of the processor architecture based on the mapping region to be verified, and obtain the verification result.

[0058] In this embodiment of the invention, by generating a mapping region with various anomalies in step S3, the correctness of the physical memory protection function of the processor architecture under different PMP configurations is effectively verified, and the physical memory protection region of the processor architecture is adjusted according to the verification results.

[0059] Compared with existing technologies, this invention obtains multiple physical address segments used by the processor architecture during the verification process; it randomly selects a physical memory protection region from the processor architecture to establish a mapping relationship for each physical address segment, using the start and end addresses of the physical address segments as the start and end addresses of the corresponding physical memory protection regions, and granting the physical memory protection regions access permissions under the current verification scenario of the processor architecture, thus obtaining multiple mapped regions; it configures physical memory protection regions in the processor architecture that do not have established mapping relationships as invalid regions; it randomly selects a preset number of mapped regions for anomaly injection to obtain the mapped regions to be verified; and it verifies the physical memory protection function of the processor architecture based on the mapped regions to be verified to obtain the verification results. This invention can quickly generate physical memory protection mapping region configurations that meet verification requirements, and can effectively verify the correctness of the processor architecture's behavior under different physical memory protection mapping region configurations by randomly injecting anomalies into the mapped regions through mechanisms such as permission cancellation, address range reduction, and boundary value replacement. At the same time, it can automatically handle the mapping relationship between any number of physical address segments and limited physical memory protection regions. By randomly merging physical address segments, it ensures that effective physical memory protection configurations can be generated under different processor specification limitations, meeting the complex RISC-V physical memory protection function verification requirements.

[0060] Example 2

[0061] This invention also provides a verification system for physical memory protection functions; please refer to [link / reference]. Figure 8 , Figure 8 This is a schematic diagram of the structure of a physical memory protection function verification system 200 provided in an embodiment of the present invention, which includes:

[0062] The address range acquisition module is used to acquire multiple physical address ranges that the processor architecture will use during the verification process;

[0063] A mapping establishment module is used to establish a mapping relationship between each physical address segment and a randomly selected physical memory protection region in the processor architecture, using the start and end addresses of the physical address segment as the start and end addresses of the corresponding physical memory protection region, and granting the physical memory protection region access permissions under the current verification scenario of the processor architecture, thereby obtaining multiple mapped regions; and configuring physical memory protection regions in the processor architecture that do not have an established mapping relationship as invalid regions;

[0064] An anomaly injection module is used to randomly select a preset number of the mapped regions for anomaly injection to obtain the mapped regions to be verified.

[0065] In this embodiment of the invention, when the abnormal injection into the mapped region is a permission violation, the corresponding access permissions of the preset number of the mapped regions are randomly selected and cancelled.

[0066] When the abnormal injection of the mapped region is an address mismatch abnormality, the preset number of the mapped regions are randomly selected, and the starting address of the mapped region is moved a random distance toward the ending address of the mapped region, or the ending address of the mapped region is moved a random distance toward the starting address of the mapped region.

[0067] When the abnormal injection into the mapped region is an address overlap anomaly, the preset number of the mapped regions are randomly selected, and the start address or end address of the mapped region is randomly replaced with another mapped region.

[0068] The verification module is used to verify the physical memory protection function of the processor architecture based on the mapping region to be verified, and obtain the verification result.

[0069] The physical memory protection function verification system 200 can implement the steps in the physical memory protection function verification method in the above embodiments and achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0070] Example 3

[0071] This invention also provides a computer device, please refer to... Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a verification program for physical memory protection function stored in the memory 302 and capable of running on the processor 301.

[0072] The processor 301 calls the verification program for the physical memory protection function stored in the memory 302, and executes the steps in the verification method for the physical memory protection function provided in this embodiment of the invention. Please refer to... Figure 1 Specifically, it includes the following steps:

[0073] S1. Obtain the multiple physical address ranges that the processor architecture will use during the verification process.

[0074] In this embodiment of the invention, the processor architecture is a RISC-V architecture, which includes multiple physical memory protection regions. The physical memory protection regions may include the start and end addresses of the physical address space, the access permissions of the space, and the valid bits, etc.

[0075] The physical memory protection features defined by RISC-V are typically used in multiple different modules within a RISC-V CPU core. The verification process of different modules may involve different privilege levels and paging modes, ultimately resulting in one or more contiguous or non-contiguous physical address segments in the simulation. This step records the information of each physical address segment using data structures. Each physical address segment consists of a start address and an end address pair. If address segments overlap, the overlapping parts are merged. After recording all address segment information, each address segment is sorted in descending order of address, forming multiple physical address segments.

[0076] In this embodiment of the invention, since the upper limit of the number of usable physical address segments supported by different CPU products (assuming a maximum of N pairs of physical memory protection regions) is inconsistent, and the number of physical address segments used in the simulation can be arbitrarily set according to verification requirements, when the number of physical address segments used in the simulation is greater than N, it is necessary to merge the recorded physical address segments to reduce them to within N. When merging, step S1 further includes the following sub-steps:

[0077] S11. Determine whether the number of multiple physical address segments exceeds a preset value: if so, randomly select multiple consecutive adjacent physical address segments for merging.

[0078] Specifically, by calculating the number of recorded physical address segments, assuming the number of physical address segments is P, randomly select (P-N+1) consecutive adjacent physical address segments. Adjacent means that no physical address segment is allocated between two adjacent physical address segments, which is considered to be adjacent.

[0079] These (P-N+1) physical address segments are merged into one. This involves setting the start address of the lowest physical address segment to the start address of the merged segment, and setting the end address of the highest physical address segment to the end address. To merge physical address segments 3 and 2 into one, the start address of physical address segment 2 is set to the start address of the merged segment, and the end address of physical address segment 3 is set to the end address of the merged segment. If the number of physical address segments used by the processor architecture during verification is less than or equal to N, then no merging is required.

[0080] S2. Establish a mapping relationship between each physical address segment and a randomly selected physical memory protection region in the processor architecture. Use the start address and end address of the physical address segment as the start address and end address of the corresponding physical memory protection region, and grant the physical memory protection region access permissions under the current verification scenario of the processor architecture to obtain multiple mapped regions. Configure the physical memory protection regions in the processor architecture that have not established a mapping relationship as invalid regions.

[0081] In this embodiment of the invention, a physical memory protection region is randomly selected for mapping. Unmapped physical memory protection regions are considered to be configured as invalid regions. For mapped physical memory protection regions, the start and end addresses of the corresponding physical address segments to be used are used as the start and end addresses of the physical memory protection region, and the physical memory protection region is given the correct access permissions in the current verification scenario. This ensures that all physical address segments to be used have been assigned the correct access permissions to the physical memory protection region.

[0082] The access permissions include one or more of the following: read permission, write permission, and execute permission.

[0083] S3. Randomly select a preset number of the mapped regions for anomaly injection to obtain the mapped regions to be verified.

[0084] In this embodiment of the invention, when the abnormal injection into the mapped region is a permission violation, the preset number of the mapped regions are randomly selected, and the access permissions of the randomly selected mapped regions are cancelled.

[0085] When the anomaly injection into the mapped region is an address mismatch anomaly, a preset number of the mapped regions are randomly selected, and the starting address of the randomly selected preset number of the mapped regions is moved a random distance towards the ending address of the mapped region (the maximum random distance is equal to the ending address), or the ending address of the randomly selected preset number of the mapped regions is moved a random distance towards the starting address of the mapped region (the maximum random distance is equal to the starting address). The minimum granularity of the movement can be flexibly set according to the specifications of the verified processor architecture.

[0086] When the abnormal injection of the mapped region is an address overlap abnormality, the preset number of the mapped regions are randomly selected, and the start address or end address of the selected mapped region is randomly replaced with another mapped region.

[0087] S4. Verify the physical memory protection function of the processor architecture based on the mapping region to be verified, and obtain the verification result.

[0088] In this embodiment of the invention, by generating a mapping region with various anomalies in step S3, the correctness of the physical memory protection function of the processor architecture under different PMP configurations is effectively verified, and the physical memory protection region of the processor architecture is adjusted according to the verification results.

[0089] The computer device 300 provided in this embodiment of the invention can implement the steps in the verification method of physical memory protection function as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0090] Example 4

[0091] This invention also provides a computer-readable storage medium storing a verification program for physical memory protection function. When the verification program for physical memory protection function is executed by a processor, it implements the various processes and steps in the verification method for physical memory protection function provided in this invention and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0092] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to computer programs or instructions. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0093] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0094] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0095] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A method for verifying physical memory protection function, characterized in that, The verification method includes the following steps: S1. Obtain the multiple physical address ranges that the processor architecture will use during the verification process; S2. Establish a mapping relationship between each physical address segment and a randomly selected physical memory protection region in the processor architecture. Use the start address and end address of the physical address segment as the start address and end address of the corresponding physical memory protection region, and grant the physical memory protection region access permissions under the current verification scenario of the processor architecture to obtain multiple mapped regions. Configure the physical memory protection regions in the processor architecture that have not established a mapping relationship as invalid regions. S3. Randomly select a preset number of the mapped regions for anomaly injection to obtain the mapped regions to be verified; S4. Verify the physical memory protection function of the processor architecture based on the mapping region to be verified, and obtain the verification result; In step S3, when the abnormal injection into the mapped region is a permission violation, the preset number of the mapped regions are randomly selected, and the access permissions of the randomly selected mapped regions are cancelled. In step S3, when the abnormal injection of the mapping region is an address mismatch abnormality, the preset number of the mapping regions are randomly selected, and the starting address of the preset number of the randomly selected mapping regions is moved a random distance toward the ending address of the mapping region, or the ending address of the preset number of the randomly selected mapping regions is moved a random distance toward the starting address of the mapping region. In step S3, when the abnormal injection of the mapping region is an address overlap abnormality, the preset number of the mapping regions are randomly selected, and the start address or end address of the selected mapping region is randomly replaced with another mapping region.

2. The verification method for physical memory protection function as described in claim 1, characterized in that, Step S1 also includes the following sub-steps: S11. Determine whether the number of multiple physical address segments exceeds a preset value: if so, randomly select multiple consecutive adjacent physical address segments for merging.

3. The verification method for physical memory protection function as described in claim 1, characterized in that, The access permissions include one or more of the following: read permission, write permission, and execute permission.

4. A verification system for physical memory protection function, characterized in that, The verification system includes: The address range acquisition module is used to acquire multiple physical address ranges that the processor architecture will use during the verification process; A mapping establishment module is used to establish a mapping relationship between each physical address segment and a randomly selected physical memory protection region in the processor architecture, using the start and end addresses of the physical address segment as the start and end addresses of the corresponding physical memory protection region, and granting the physical memory protection region access permissions under the current verification scenario of the processor architecture, thereby obtaining multiple mapped regions; and configuring physical memory protection regions in the processor architecture that do not have an established mapping relationship as invalid regions; Anomaly injection module is used to randomly select a preset number of the mapping regions for anomaly injection to obtain the mapping regions to be verified. When the abnormal injection into the mapped region is a permission violation, the preset number of the mapped regions are randomly selected, and the access permissions of the randomly selected mapped regions are revoked. When the abnormal injection of the mapped region is an address mismatch abnormality, the preset number of the mapped regions are randomly selected, and the starting address of the preset number of randomly selected mapped regions is moved a random distance toward the ending address of the mapped region, or the ending address of the preset number of randomly selected mapped regions is moved a random distance toward the starting address of the mapped region. When the abnormal injection into the mapped region is an address overlap anomaly, the preset number of the mapped regions are randomly selected, and the start address or end address of the selected mapped region is randomly replaced with another mapped region. The verification module is used to verify the physical memory protection function of the processor architecture based on the mapping region to be verified, and obtain the verification result.

5. A computer device, characterized in that, include: The device includes a memory, a processor, and a verification program for physical memory protection functions stored on the memory and executable on the processor. When the processor executes the verification program for physical memory protection functions, it implements the steps in the verification method for physical memory protection functions as described in any one of claims 1-3.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a verification program for physical memory protection functions, which, when executed by a processor, implements the steps of the verification method for physical memory protection functions as described in any one of claims 1-3.

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